L8229 [STMICROELECTRONICS]
Dual DMOS full bridge stepper/DC motor driver; 双DMOS全桥步进/ DC电机驱动器
| 型号： | L8229 |
| 厂家： | 
ST |
| 描述： | Dual DMOS full bridge stepper/DC motor driver |
| 文件： | 总42页 (文件大小：863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L8229
Dual DMOS full bridge stepper/DC motor driver
Preliminary Data
Features
■ Flexible Motor Driver configurations:
Dual Full Bridge for one bipolar Stepping motor.
–
– Dual or single DC motor driver.
■ Programmable by two input pins to achieve
PwSSO24
one of the following functionalities:
– Pin to pin compatible with ST L6219 or
levels to perform a more accurate stepping
functionality. This is achieved by multiplexing
the input pins dedicated to set the level of the
current. Additionally the user can set the
mixed mode decay for current recirculation.
– Stepping motor direct control with 8 current
levels or
– Driver parameters control by means of
Serial Port.
■ Mixed Decay.
3,4. The third and fourth conurations are
intended to provide a ery flexible
■ Micro stepping function.
programming fseveral parameters useful
to drive different kind of Stepping and DC
motors. Ths is achieved by means of a serial
port inerface that allows the user to
■ BCD5 technology (No Charge Pump required).
■ Supply Range from 8V to 38V.
■ IOUT up to 1.2A (1.5A peak).
■ RDSon= 0.85Ω (typ) for each switch.
configure the following parameters:
a) Current levels (32 values for each
bridge).
■ Input logic level compatible with 3.3V or 5V
control signals.
b) Current direction.
■ Package: PwSSO24.
c) Type of decay for Stepping motors
(Mix/Slow) or for DC motors (Fast/Slow).
d) Vref input (Ext/Int).
e) Vref divider (:5/:10).
Description
This IC is designed to be very flexible in driving
Stepping or DC motors.
f)
Blanking time (4 values).
By connecting to Vcc or to nd two program pins
(pin 7 and 18) the uhas the possibility to set
up the device in different configurations.
g) Oscillator freq divider (4 values).
h) Off time (32 values).
i)
j)
Fast decay time (16 values).
Syncronous rectification.
1. The first configuration is an identical
appliction of ST L6219 but with increased
cuent. In this configuration L8229 provides
a continuous current of the output stage up
to 1.2A (1.5A peak).
The functionalities of the two configurations are
identical except that the internal bit address (first
bit of SPI words) can be programmed to be 1 or 0:
this enables two different L8229 to share a
common serial bus.
2. The second configuration allows a
functionality similar to previous one but with
the possibility of choosing 8 different current
Order code
Part number
Package
PwSSO24
Packing
L8229
Tube
September 2006
Rev 5
1/42
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
1
Contents
L8229
Contents
1
2
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.1
3.3.2
3.3.3
3.3.4
Output Drivers (OUTA or OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Control Logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
5
L6219_HI and L6219_8 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
L6219_HI and L6219_8 Electrical characteristics . . . . . . . . . . . . . . . . . 14
5.1
5.2
DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC/transient specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
L6219_HI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
6.2
6.3
6.4
6.5
6.6
Input Logic (I0 and I1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Single-pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Vs, Vcc, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
L6219_8 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1
7.2
8 Level Current Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mixed Decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
L8229_0 and L8229_1 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.1
Serial interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/42
L8229
Contents
8.2
SPI Bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.2.1
8.2.2
Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
W0 (OPERATIVE: Bit 2=0, Bit 1=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.3
8.4
W1 (PARAMETERS: Bit 2=0, Bit 1=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
W2 (FUNCTIONAL: Bit 2=1, Bit 1=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.4.1
Reading back SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9
SPI programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1
9.2
9.3
9.4
Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timings Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Decay Modes and Synchronous Rectification . . . . . . . . . . . . . . . . . . . . . 33
Mixed Decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1) ACTIVE SYNC recirculation could be divided in following cases. . . . . . . . . . . . 35
2) - PASSIVE SYNC recirculation could be divided in following cases:. . . . . . . . . 36
3) - SYNC OFF recirculation has only one case: . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4) LOW SIDE recirculation has only one case: . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.5
Slow Decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1) ACTIVE SYNC recirculation is not allowed.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2) PASSIVE SYNC recirculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3) SYNC OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4) LOW SIDE is identical to PASSIVE SYNC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10
11
12
DC Motor Driver operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3/42
List of tables
L8229
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programmable modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating ratings (0°C £ Tj £ 125°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Drivers (OUTA or OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Control Logic pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC/transient specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Logic (I0 and I1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC/Transient Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AC/Transient Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Word Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
W0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Motor mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Nsleep mode selected by W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Brake mode selected by W1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Vref mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Range mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current direction selected by W0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current levels selected by W0 for DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Oscillator frequency selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Blanking time selected by W2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Fast decay time selected by W1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Toff time selected by W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Stepping decay mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC decay mode selected by W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Sync rectification selected by W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Motor Drivers - DC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC Motor Drivers - AC/Transient Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC Motor Drivers Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
4/42
L8229
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ton and Toff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Half and Full Step Drive with Imax=1.2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Normal conduction and slow recirculation current paths. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
L6219_8 mode Stepping Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
L6219_8 mode Fast and Slow Decay current paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Active and Passive synchronous rectification during Mixed Decay. . . . . . . . . . . . . . . . . . . 34
Figure 10. PowerSSO24 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5/42
Block diagram
L8229
1
Block diagram
Figure 1.
Block Diagram
Analog Toff
VREFDEC
RC1
VS
VS
VH
VL
M
VREF1
2 / 7.5
U
DAC5
-
Pre
Driver
OUT1A
OUT1B
X
S
R
Q
+
2V
COMPIN1
SENSE1
Digital Control
Digital Prog Toff
PROG1
PROG2
COMPIN1
Osc Freq Select
Stepper/DC Select
Decay Ctrl
00
01
10
11
I01
I11
I02
Serial Port
Toff Select
I01
I11
I02
I12
I01
I11
PWM1 PWM1
PWM2 PWM2
Tfastdec Select
Synch Rect Select
Test Mode
STB STB SCLK
II2 II2 SDI
I12
PHA1 PHA1 PHA1 OSC
PHA2 PHA2 PHA2 nCS
DAC Select
VS
Digital Prog`
Toff
Pre
Driver
ADDR
4MHz
OUT2A
OUT2B
COMPIN2
R
2V
+
-
M
U
X
S
Q
DAC5
VREF2
RC2
2 / 7.5
SENSE2
VL
Test Mux
VH
VREFDEC
COMPIN2
GND
4MHz
Int Osc
Bandgap
Temp Mon
2V
VREFDEC
Analog Toff
Tshut
GND
VCC
UV
UVLO
Note:
The sensing resistors used for the stepping motor configurations must be not inductive.
6/42
L8229
Pin description
2
Pin description
Figure 2.
Pin Connection (Top view)
1
2
3
4
24
23
22
21
OUT1A
OUT2A
VS (Load Supply)
SENSE1
SENSE2
COMPIN1
OUT1B
COMPIN2
5
6
7
8
20
19
18
17
OUT2B
GND
I01/I01/PWM1
GND
PROG1
PROG2
I11/I11/PWM2
IO2/STB/SCLK
9
I12 /I12/SDI
PHASE2 /PHASE2/nCS
VREF2/VREFDEC/VREF2
16
15
14
13
PHASE1/PHASE1 /OSC
VREF1/VREFCOM/VREF1
RC1/RC1/nRESET
10
11
12
VCC (Logic Supply)
RC2/RC2/FAULT
Note:
The pin functionality is different according to different configurations, so the relative pin
function and name are different: the first name is relative to first configuration (L6219_HI),
the second name is relative to second configuration (L6219_8), and the third name is
relative to third and fourth configuration (L8229_0 and L8229_1).
Table 1.
Pin N#
Pin Description
L8229_x
L6219_HI
L6219_8
Function
(Pin7&18=10
or 11)
(Pin7&18=00) (Pin7&18=01)
1
2
3
4
5
6
OUT1A
OUT2A
SENSE2
COMPIN2
OUT2B
GND
Motor Driver Bridge 1 Output A.
Motor Driver Bridge 2 Output A.
Motor Driver Bridge 2 Sense Resistor.
Current Comparator input for Bridge2.
Motor Driver Bridge 2 Output B.
Ground.
Configuration Program pin. When used together with pin
18, it programs device into one of the four configurations
(see following Programmable Modes table)
7
PROG1
I02: Current level control bit for Bridge 2.
STB: Strobe input pin for current setting.
SCLK: Clock input pin for serial protocol.
8
9
IO2
I12
STB
I12
SCLK
SDI
I12: Current level control bit for Bridge 2.
SDI: Data input pin for serial protocol.
7/42
Pin description
L8229
Table 1.
Pin N#
Pin Description (continued)
L8229_x
L6219_HI
L6219_8
Function
(Pin7&18=10
or 11)
(Pin7&18=00) (Pin7&18=01)
PHASE2: Direction input control pin for Bridge 2.
nCS: Chip Select input pin for serial protocol.
10
11
PHASE2
VREF2
RC2
PHASE2
nCS
VREF2: Reference voltage input for Bridge 2.
VREFDEC
VREF2
FAULT
VREFDEC: Mixed Decay Reference voltage for both
Bridges 1 and 2.
RC2: Toff input pin for Bridge 2.
12
13
14
RC2
VCC
RC1
FAULT: This pin is high when a generic fault is present.
Logic and Low voltage analog Supply.
RC1: Toff input pin for Bridge 1.
RC1
VREF1
PHASE1
I11
nRESET
VREF1
OSC
nRESET: Input pin for reset of serial port.
VREF1: Reference voltage input for Bridge 1.
15
16
17
VREFCOM
PHASE1
I11
VREFCOM: Common Reference voltage input for both
Bridges 1 and 2.
PHASE1: Direction input control pin for Bridge 1.
OSC: Input for external oscillator used for timings.
I11: Current level control bit for Bridge 1.
PWM2
PWM2: PWM input control pin for Bridge 2 when used as
a DC motor driver.
Configuration Program pin. When used together with pin
7, it programs device into one of the four configurations
(see following Programmable Modes table).
18
19
20
PROG2
GND
I01
Ground.
I01: Current level control bit for Bridge 1.
I01
PWM1
PWM1: PWM input control pin for bridge 1 when used as
a DC motor driver
21
22
23
24
OUT1B
COMPIN1
SENSE1
VS
Motor Driver Bridge 1 Output B.
Current Comparator input for Bridge1.
Motor Driver Bridge 1 Sense Resistor.
Supply voltage for output stages.
Note:
ESD on pin PROG1 vs. V is guaranteed up to +2KV/-1.75KV (Human Body Model,
S
1500Ohm, 100pF)
8/42
L8229
Pin description
Table 2.
Programmable modes
Pin # 18
Pin #7
PROG1
Description
Mode name Drive Configurations
PROG2
L6219 compatible
(up to 1.2A Iout)
1 x Stepping
L6219_HI
0
0
0
MotorDriver.
L6219 like with 8 current levels
1 x Stepping
L6219_8
1
0
1
(up to 1.2A Iout) and Mixed
Decay.
MotorDriver.
1 x Stepping
1
1
SPI operation, Chip Address = 0
SPI operation, Chip Address = 1
L8229_0
L8229_1
MotorDriver or 2 x DC
Motor Driver.
1 x Stepping
MotorDriver or 2 x DC
Motor Driver.
9/42
Electrical Characteristics
L8229
3
Electrical Characteristics
Independently from the selected configurations, L8229 has some electrical characteristics
that are common for all modes. These are listed below while specific characteristics are
listed in their respective functionality descriptions.
In all modes L8229 is powered by Vs supply voltage. The anti cross-conduction delay is
controlled to provide sufficient time for cross-conduction suppression so that at no time both
the upper and lower output devices (on the same side of the H bridge) are allowed to
conduct simultaneously.
During an over-temperature event, when the device Tj is above Tj(shutdown), the internal
thermal protection circuit disables the drive outputs until the device temperature drops below
the lower thermal threshold temperature.
Note:
The programming pins, PROG1 and PROG2, must be soldered to Vcc or to GND and must
not be driven when supplies are on.
3.1
Absolute maximum ratings
Table 3.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Vs
Vcc
Supply voltage (including ripple).
40
V
V
Logic and Low voltage analog supply voltage
Motor Driver Output Peak Current (see Note (1)).
Vref input voltage.
7
1.5
Ipeak
Vref
A
7.5
V
Vsense Vsense output voltage.
2
V
Vin
Tj
Logic input voltage.
Junction Temperature.
Storage Temperature.
-0.3 to +7
170
V
°C
°C
Tstg
-25 to 150
1. This peak current is intended as start up current for max 1 second with D.C. ≤10%
3.2
Operating ratings
Table 4.
Operating ratings (0°C ≤ Tj ≤ 125°C)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vs
Supply voltage (including ripple).
8.5
32
38
V
Logic and Low voltage analog
supply voltage.
Vcc
3.135
5
5.25
V
L8229_0/1 configuration
Sleep mode:
I_Vs
Vs Standby Current
3
6
mA
NSLEEP (W1, bit3) = 0
10/42
L8229
Electrical Characteristics
Table 4.
Operating ratings (0°C ≤ Tj ≤ 125°C) (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vcc total supply current
I_VccL6219
Vcc=5.25V
7
7
mA
mA
mA
V
(L6219_HI and L6219_8 modes)
Vcc=5.25V
Vcc total supply current
I_VccL8229_0/1
Vcc=5.25V,
(L8229_0 or L8229_1 mode)
3
NSLEEP (W1, bit3) = 0
Vin
Logic input voltage
0
Vcc
1.2
Motor Driver Output Current
(continuous)
Iout
A
3.3
General electrical characteristics
(0°C ≤ Tj ≤ 125°C, VS = 32V, unless otherwise specified)
3.3.1
Output Drivers (OUTA or OUTB)
Table 5.
Symbol
Output Drivers (OUTA or OUTB)
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Source Driver, ILOAD =-1.2A
Sink Driver, ILOAD =+1.2A
Vout = Vs or Gnd
1.3
1.3
Ω
Ω
Output ON Resistance
(Tj = 70 °C)
RDSON
Icex
Output leakage current
50
1
µA
V
Sink Diode, IF = 1.2A
Source Diode, IF = 1.2A
1.5
1.5
VF
Body Diode Forward Voltage
1
V
Vs=12V, RL=12Ω connected to
Vs or Gnd
Vs=24V, RL=38Ω connected to
Vs or Gnd
tr
tf
Output rising time
Output falling time
100
350
300
ns
Vs=36V, RL=58Ω connected to
Vs or Gnd
Vs=12V, RL=12Ω connected to
Vs or Gnd
Vs=24V, RL=38Ω connected to
Vs or Gnd
75
ns
Vs=36V, RL=58Ω connected to
Vs or Gnd
Tdead Shoot through delay
1
µA
11/42
Electrical Characteristics
L8229
3.3.2
Control Logic pins
Table 6.
Symbol
Control Logic pins
Parameter
Test Condition
All logic input for
Min.
Typ.
Max.
Unit
VIN (H) Input Voltage
2
V
Vcc = 3.3V or 5V.
All logic input for
Vcc = 3.3V or 5V.
VIN (L) Input Voltage
IIN (H) Input Current
0.8
V
VIN = 2.0V
VIN = 0.8V
-20
-20
20
20
50
µA
µA
µA
IIN (L)
Isdi
Input Current
SDI Input Current
-200
3.3.3
Analog Input Pins
Table 7.
Symbol
Analog Input Pins
Description
Condition
Min.
1.5
Typ.
Max.
Unit
Vref
IVref
Vref Input Voltage
7.5
200
0.75
20
V
µA
V
Vref Input Current
Vref = 5.0V
Vcompin
Icompin
Vsense
Isense
Vcompin Input Voltage
Vcompin Input Current
Vsense Input Voltage
Vsense Output Current
1
µA
V
0.75
100
50
µA
3.3.4
General
Table 8.
General
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vsc_off
Vs_UV
Sense comparator offset
Vs undervoltage threshold
Vs undervoltage hysteresis
Vcc undervoltage threshold
10
7.5
mV
V
Vs_UVhys
Vcc_UV
300
2.9
mV
V
Vcc_UVhys Vcc undervoltage hysteresis
150
mV
Thermal shutdown junction
Tj(shutdown)
160
25
°C
°C
temperature
Tj(enable_
hysteresis)
Thermal enable junction temperature
hysteresis
12/42
L8229
L6219_HI and L6219_8 modes
4
L6219_HI and L6219_8 modes
When configured in one of these modes the device has a functionality similar to ST L6219
with some improvements. The output stage is made by LDMOS devices instead of the BJT
present in ST L6219. This allows a reduced saturation drop and an higher current handling
with similar power dissipation. Additionally the recirculation diodes are internally available as
a part of the LDMOS structure.
In case of:
a) Undervoltage detection (UVD) or
b) Thermal shutdown (TSD),
the outputs will be in Hi-Z mode (all outputs off) respectively until the supplies voltage goes
over the UV threshold plus hysteresis or the themperature decreases below TSD threshold
minus hysteresis.
In case of:
c) Overcurrent detection (OCD)
the outputs will be in Hi-Z mode (all outputs off) and will remain in this condition until the
device is reset by turning off and on VCC supply voltage.
Common electrical characteristics of both L6219_HI and L6219_8 modes are listed below,
while specific characteristics are listed in their respective functionality descriptions.
13/42
L6219_HI and L6219_8 Electrical characteristics
L8229
5
L6219_HI and L6219_8 Electrical characteristics
(0°C ≤ Tj ≤ 125°C, VS = 32 V, unless otherwise specified)
5.1
DC specifications
Table 9.
DC specifications
Symbol
Description
Condition
Min
Typ
Max
Unit
I0 ≤ 0.8V, I1 ≤ 0.8V
I0 ≥ 2.0V, I1 ≤ 0.8V
I0 ≤ 0.8V, I1 ≥ 2.0V
9.25
13.5
25.5
10
15
30
10.5
16.5
34.5
Current Limit Threshold (at trip
point ) for Vref = 5V and Tj ≤ 70°C
Vref/Vsense
5.2
AC/transient specifications
Table 10. AC/transient specifications
Symbol
Parameter
Cut off time
Test Condition
Min.
Typ.
Max.
Unit
Toff
Rt=56Kohm, Ct =820pF
50
1
µA
µA
Tdelay Turn Off Delay for comparator
Blanking time for Sense
Tblank
1
µA
comparator
14/42
L8229
L6219_HI mode
6
L6219_HI mode
The device will be set into the L6219_HI mode by asserting PROG1 and PROG2 pins (pin 7
and 18) to 00.
In the L6219_HI mode, the device is pin and function compatible with the ST L6219 device.
Please note that while ST L6219 allows good power dissipation by simply connecting to gnd
the center pins because of the batwing frame, the L8229 power dissipation will be good only
by connecting the exposed pad to a proper heat sink.
The circuit is intended to drive both windings of a bipolar stepping motor. The peak current
control is made through switch mode regulation. There is a choice of three different current
levels with the two logic inputs I01 and I11 for winding 1 and I02 and I12 for winding 2. The
current can also be completely switched off.
6.1
Input Logic (I0 and I1)
The current level in the motor winding is selected with these inputs (see Figure 1). If any of
the logic inputs is left open, the circuit will treat it as a high level input.
Table 11. Input Logic (I0 and I1)
I0X
I1X
Current Level
H
L
H
H
L
No Current
Low Current:
1/3 Io max
H
L
Medium Current: 2/3 Io max
Maximum Current: Io max
L
6.2
6.3
Phase
This input pin determines the direction of current flow in the windings, depending on the
motor connections. The signal is fed through a Schmitt trigger for noise immunity, and
through a time delay in order to guarantee that no cross conduction occurs in the output
stage during phase-shift. High level on the PHASE input causes the motor current to flow
from OutA through the motor winding to OutB.
Current Sensing
This part contains a low pass filter for the external current sensing resistor (Rs) and three
comparators. Only one comparator is active at a time: it is activated by the input logic
according to the current level chosen with signals I0 and I1.
The motor current flows through the sensing resistor Rs and when the current has increased
so that the voltage across Rs becomes higher than the reference voltage on the other
comparator input, the comparator output goes high, triggering the pulse generator.
The max peak current Imax can be defined by:
Imax = Vref / 10 Rs
15/42
L6219_HI mode
L8229
Note that Iout max is 1.2A and the wide range allowed for Vref requires the choice of a
suitable sense resistor to prevent current range over the maximum.
6.4
Single-pulse Generator
The pulse generator is a monostable circuit triggered on the positive going edge of the
comparator output. The circuit output is high during the pulse time Toff that is determined by
the time components Rt and Ct.
Toff =~ 1.1 x RtCt
(including switching dead time)
The single pulse turns off the power switch connected to the motor winding, causing the
winding current to decrease during Toff. If a new trigger signal should occur during Toff it will
be ignored.
6.5
6.6
Output Stage
Each of the two outputs stage contains four LDMOS transistors (P and N channel)
connected in two H Bridges. The intrinsic body diode of the LDMOS serve as recirculation
diode for flyback current.
The LDMOS are used to switch the power supply to the motor winding, thus driving a
constant current through the winding. It should be noted however, that is not permitted to
short-circuit the outputs. Internal circuitry is added in order to increase the accuracy of the
motor current particularly with low current levels.
Vs, Vcc, Vref
The circuit will stand any order of turn-on or turn-off of the supply voltages Vs and Vcc.
Normal dV/dt values are then assumed.
Preferably, Vref should be tracking Vcc during power-on and power-off if Vs is established.
Figure 3.
Ton and Toff
Normalized
output current
1.0
Tdelay
Ton
0.5
Toff
0
VSense
Vref
VRC
16/42
L8229
L6219_HI mode
Figure 4.
Half and Full Step Drive with Imax=1.2A
Hold
Half Step Drive
Full Step Drive
1
2
3
4
5
6
7
8
I01
I11
PHASE 1
I02
I12
PHASE 2
Motor Current Phase 1 A to B
Motor Current Phase 2 A to B
1.2A
0.8A
0 A
-0.8A
-1.2A
1.2A
0.8A
0 A
-0.8A
-1.2A
Figure 5.
Normal conduction and slow recirculation current paths.
Toff
Vcc
RC
Ton
Ton
T2
T3
T1
OUTA1
Slow Decay
L6219_HI Mode
OUTB1
VS
HA
HB
Ton Current
Toff Current
LB
LA
Slow Decay
17/42
L6219_8 mode
L8229
7
L6219_8 mode
A second configuration of the device is achieved when PROG1 and PROG2 pins (pin 7 and
18) are asserted to 01. The device is now configured into the L6219_8 configuration. This
device mode function is similar to L6219_HI, but with the possibility of using 8 current levels
instead of 4, to implement a more accurate microstepping function and with the possibility to
set a mixed decay for recirculation current. The remaining functionalities are identical to
L6219_HI mode.
7.1
8 Level Current Setting
This setting is achieved by using pin 8 (STB) as a strobe for latching the current setting
control inputs. The rising edge of STB will latch the I01, I11 and I12 inputs for decoding
current levels settings for Bridge 1. Similarly the falling edge will latch the I01, I11 and I12
inputs for decoding current levels settings for Bridge 2.
In order to allow a good similitude to sine drive, the levels set by the input pins are not
equally spaced but are choosen to approximate a sinusoidal wave.
On power up, the device is by default into a no current drive state for both H Bridges and will
start driving only upon the rising or falling edges of STB.
7.2
Mixed Decay
VREFCOM input (pin 15) is the reference voltage for both bridges while VREFDEC input
(pin 11) is a voltage reference for decay control. When the current setting is set from an
higher level to a lower level, the device can be set to perform:
1.
Slow decay (current is recirculated throught the low side drivers) when VREFDEC > 0.94Vcc.
2. A mix of Fast followed by Slow decay when 0.33Vcc < VREFDEC < 0.94Vcc.
3. Fast decay (current is recirculated from Sense to Vs) when VREFDEC < 0.33Vcc.
In case 2, VREFDEC voltage is compared with the RC discharging voltage during the Toff
duration. Until the RC voltage is above VREFDEC there will be fast decay: the bridge
outputs will be driven to enable recirculation from Rsense to VS. For RC voltages below
VREFDEC, the bridges will be driven to recirculate through the low side drivers. (see
Figure 8)
Table 12. Current levels
STB
I01
I11
I12
Current level
Bridge1
No current
Bridge 2
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
-
-
-
-
-
-
I
OUT / Imax=0.22
IOUT / Imax=0.42
IOUT / Imax=0.61
I
OUT / Imax=0.77
IOUT / Imax=0.87
18/42
L8229
L6219_8 mode
Table 12. Current levels (continued)
STB
I01
I11
I12
Current level
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
IOUT / Imax=0.93
-
IOUT / Imax=1
-
-
-
-
-
-
-
-
-
IOUT / Imax=1
IOUT / Imax=0.93
I
OUT / Imax=0.87
IOUT / Imax=0.77
IOUT / Imax=0.61
I
OUT / Imax=0.42
IOUT / Imax=0.22
No current
Table 13. AC/Transient Specification
Symbol
Description
Min
Typ
Max
MD_h
MD_l
Mixed decay trip point high
Mixed decay trip point low
0.93Vcc 75mV
0.33Vcc 50mV
Table 14. Timing specifications
(0°C ≤ T ≤ 125°C, V = 32 V, unless otherwise specified)
j
S
Name
Description
MIN
TYP
MAX
Units
Fstb
Strobe frequency
Strobe high width
Strobe low width
STB rise time
6
MHz
ns
Thstb
20
20
0
Tlstb
ns
Trd_stb
Tfd_stb
Trd_Ixx
Tfd_Ixx
Tsu_Ixx
Thd_Ixx
10
10
10
10
ns
STB fall time
0
ns
I01,I11,I12 rise time
I01,I11,I12 fall time
I01,I11,I12 setup time
I01,I11,I12 hold time
0
ns
0
ns
15
15
ns
ns
19/42
L6219_8 mode
Figure 6. L6219_8 mode Stepping Driving
L8229
Bridge2
Bridge1
PHASE2
PHASE1
I12
I11
I01
STB
Figure 7.
L6219_8 mode Fast and Slow Decay current paths
Toff
Vcc
RC
SLOW DECAY
0.94Vcc
VREFDEC
OUTA
Toff= 1.1RC inclusive of
Tdeadtime T1 and T3
MIXED DECAY
FAST DECAY
0.33Vcc
T1 T2 T3
T4
T5
T1, T3 and T5 are
dead times
to ensure no cross
conduction
L6219_8 Mode
OUTB
Slow
Fast
Decay
Decay
VS
HA
LA
Ton Current
HB
Toff Fast Decay
Current
Toff Slow Decay
Current
LB
20/42
L8229
L8229_0 and L8229_1 modes
8
L8229_0 and L8229_1 modes
When in these modes, the device can be programmed via a serial interface. This allows a
very precise microstepping functionality as well as the control of several parameters related
to the motor functionality.
In this configuration there is also the possibilty of driving two DC motors by means of two
pulse width modulated (PWM) control signals.
The parameters that can be set are the following:
1. Current levels (32 values for each bridge).
2. Current direction.
3. Type of decay for stepping motor (Mix/Slow).
4. Vref input (Ext/Int)
5. Vref divider (:5/:10).
6. Blanking time (4 values).
7. Oscillator freq divider (4 values).
8. Off time (32 values).
9. Fast decay time (16 values).
10. Synchronous rectification (Active/Passive/LowSide/Off).
11. Choose of driving a Stepping or DC motor.
12. Possibility of paralleling bridges (in DC motor drive).
13. Slow or fast decay (in DC motor drive).
14. Possibility of setting outputs in brake mode.
15. Possibility of asserting Sleep mode to reduce current consumption and put outputs in
HI-Z.
When in L8229 modes, pin 12 (FAULT) is used to provide a "Generic Fault" signal that is
intended as a warning for the user. In case of:
a) Undervoltage detection (UVD): no action is taken on output bridges and the device
will be working, leaving to the user the action of stopping the output bridges
functionality.
During UVD event, the Generic Fault signal is pulled high.
b) Thermal shutdown (TSD): output bridges will be in Hi-Z mode (all outputs off) until
the temperature decreases below TSD threshold minus hysteresis.
During TSD event, the Generic Fault signal is pulled high.
c) Over current detection (OCD): output bridges will be in Hi-Z mode. Depending on
the motor (Stepping or DC according to W2 bit 14), the OCD status will be latched
as follows:
– for stepping motor driving the OCD status will be latched until SPI is reset by
means of nRESET pin.
– for DC motor driving the OCD status will be latched until next positive PWM
edge occurs.
For both above cases, the Generic Fault signal is pulled high until the OCD
status persists.
21/42
L8229_0 and L8229_1 modes
Table 15. DC Specifications
L8229
(0°C ≤ T ≤ 125°C, V = 32 V, unless otherwise specified)
j
S
Name
Description
Conditions
Min
Typ
Max
Units
Vref voltage Internal reference voltage
1.94
2
2.06
V
Reverse current detection offset
Ioff-rev
50
mA
(in Active Sync recirculation)
Table 16. AC/Transient Specifications
(0°C ≤ T ≤ 125°C, V = 32 V, unless otherwise specified)
j
S
Name
Description
Conditions
Min
Typ
Max
Units
Osc
Oscillator frequency
4
MHz
8.1
Serial interface specification
This device, when in L8229_0 or L8229_1 configuration, is managed via a Serial Interface
Port for a total of 16 bits with 4 different words. This port provides an interface between the
chip and external digital ASIC. For the user this port is write-only: assigned read registers
are for test mode purposes only.
The interface consists of 3 signal lines: chip select (nCS, active low), serial clock (SCLK)
and serial data input (SDI).
The digital ASIC initiates a serial transfer by pulling low the chip select line, nCS. Then it
generates 16 clock pulses on SCLK while presenting the serial data on input SDI. The data
is shifted into the L8229 on the rising edge of SCLK. The digital ASIC presents the data on
SDI one setup time (Tdsu) before the rising edge of SCLK. The data is held constant for the
data hold time (Tdhd) beyond the SCLK rising edge. The less significant bit, or LSB, is the
first to be shifted out of the digital ASIC and into the chip, followed by the remaining bits. The
last of the 16 bits is the most significant bit or MSB. SDI will remain at the value presented
with the last bit of data. The nCS line is then returned to a high state. The low to high
transition of nCS loads the data into the internal L8229 input register where all the inputs are
presented to their appropriate functions in a parallel mode.
In the event that there are less or more than 16 SCLK rising edges during nCS=0, the device
will interprete the packet as invalid. This enables the SPI bus to be shared with others
devices with similar packet skipping functionality (and with programming word length
different from 16 bits), without the use of nCS.
The outputs of the serial input port shall not "glitch" during any operation.
The serial interface is cleared by nRESET signal applied to pin 14. When nRESET=0,
output stages are in Hi-Z mode (all outputs off). Please note that neither TSD nor OCD reset
the SPI.
22/42
L8229
L8229_0 and L8229_1 modes
Figure 8.
SPI Operations
Data latched on rising edge of SCLK
TCS-SCLK
TSCLK-CS
nCS
SCLK
SDI
TDSU
Bit1
TDHD
Bit3
Bit0
Bit4
Bit7
Bit14 Bit15
MSB
Bit2
Bit5
Bit6
LSB
Table 17. SPI Timing specifications
(0°C ≤ T ≤ 125°C, V = 32 V, unless otherwise specified)
j
S
Name
Description
MIN
TYP
MAX
Units
Fclk
Tclh
Serial clock frequency
SCLK high width
8
12
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
10
10
10
10
10
0
Tcll
SCLK low width
Tcs-sclk
Tsclk-cs
Tdsu
Tdhd
Tcs-cs
Trd
Delay nCS falling to first SCLK rising
Delay last SCLK rising edge to nCS rising
Data valid to SCLK set up time
Data hold time
Delay required from (n-1)CS to nCS
SDI rise time
20
20
20
Tfd
SDI fall time
0
Trfc
SCLK rise/fall time
0
23/42
L8229_0 and L8229_1 modes
L8229
8.2
SPI Bit definition
8.2.1
Word Description
Each of the 3 words used to program the chip when in L8229_0 or L8229_1 mode has the 3
LSB used to address the word as follows:
Table 18. Word Description
BIT #
NAME
Value
DESCRIPTION
This value addresses the word to chip #0 (if two L8229 are
present on the same board and a single nCS line is used).
0
Chip address is assigned by configuring the PROG bit
according to Table 2.
0
CHIP ADDRESS
This value addresses the word to chip #1 (if two L8229 are
present on the same board and a single nCS line is used).
1
Chip address is assigned by configuring the PROG bit
according to Table 2.
Bit 2
Bit 1
0
0
1
1
0
1
0
1
W0: OPERATIVE register
W1: PARAMETERS register
W2 : FUNCTIONAL register
Not allowed
WORD ADDRESS 1,
WORD ADDRESS 2
1 and 2
8.2.2
W0 (OPERATIVE: Bit 2=0, Bit 1=0)
This word is mainly used to fix the current level and direction in the bridge.
Table 19. W0
RESET
VALUE
BIT #
NAME
DESCRIPTION
This bit is used to select if the informations provided by bits 1 to 15 are
referred to chip 0 or chip 1. This is useful in the case that two L8229 are
present on the same board and a single nCS line is used.
0
CHIP ADDRESS
0
1
2
3
4
5
6
7
WORD ADDRESS 1
WORD ADDRESS 2
DAC1 BIT 1 (LSB)
DAC1 BIT 2
0
0
0
0
0
0
0
This is the LSB of the two bits used to address the word
This is the MSB of the two bits used to address the word
LSB for DAC intended to regulate the current of Bridge 1
BIT2 for DAC intended to regulate the current of Bridge 1
BIT3 for DAC intended to regulate the current of Bridge 1
BIT4 for DAC intended to regulate the current of Bridge 1
MSB for DAC intended to regulate the current of Bridge 1
DAC1 BIT 3
DAC1 BIT 4
DAC1 BIT 5 (MSB)
Controls the direction of current flow for Bridge1.
8
9
PHASE 1
0
0
A logic 0 level causes current flow from A (source) to B (sink).
DAC2 BIT1 (LSB)
LSB for DAC intended to regulate the current of Bridge 2
24/42
L8229
L8229_0 and L8229_1 modes
Table 19. W0 (continued)
RESET
VALUE
BIT #
NAME
DESCRIPTION
10
11
12
13
DAC2 BIT 2
0
0
0
0
BIT2 for DAC intended to regulate the current of Bridge 2
BIT3 for DAC intended to regulate the current of Bridge 2
BIT4 for DAC intended to regulate the current of Bridge 2
MSB for DAC intended to regulate the current of Bridge 2
DAC2 BIT 3
DAC2 BIT 4
DAC2 BIT 5 (MSB)
Controls the direction of current flow Bridge 2.
14
15
PHASE 2
0
0
A logic HIGH level causes current flow from A (source) to B (sink).
This bit must be set to 1 when otputs are paralled to drive a single DC
motor
PARALLEL OUTPUT
8.3
W1 (PARAMETERS: Bit 2=0, Bit 1=1)
This word is mainly used to set motor related parameters.
Table 20. W1
RESET
VALUE
BIT #
NAME
DESCRIPTION
This bit is used to select if the informations provided by bits 1 to 15 are
referred to chip 0 or chip 1. This is useful in the case that two L8229 are
present on the same board and a single nCS line is used.
0
CHIP ADDRESS
0
1
2
WORD ADDRESS 1
WORD ADDRESS 2
NSLEEP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This is the LSB of the two bits used to address the word.
This is the MSB of the two bits used to address the word.
This bit is used to decide if the device should exit sleep mode.
LSB for fixing the Toff time (see following Table 32).
BIT 2 for fixing the Toff time (see following Table 32).
BIT 3 for fixing the Toff time (see following Table 32).
BIT 4 for fixing the Toff time (see following Table 32).
MSB for fixing the Toff time (see following Table 32).
LSB for fixing the Fast Decay time (see followingTable 31).
BIT 2 for fixing the Fast Decay time (see following Table 31).
BIT 3 for fixing the Fast Decay time (see following Table 31).
MSB for fixing the Fast Decay time (see following Table 31).
LSB to decide the rectification mode (see following Table 35).
MSB to decide the rectification mode (see following Table 35).
This bit is used to put outputs in brake mode
3
4
OFF1
5
OFF2
6
OFF3
7
OFF4
8
OFF5
9
FASTDEC1
FASTDEC2
FASTDEC3
FASTDEC4
SYNCRECT1
SYNCRECT2
Brake
10
11
12
13
14
15
25/42
L8229_0 and L8229_1 modes
L8229
8.4
W2 (FUNCTIONAL: Bit 2=1, Bit 1=0)
This word is mainly used to set the functional mode
Table 21. W2
RESET
VALUE
BIT #
NAME
DESCRIPTION
This bit is used to select if the informations provided by bits 1 to 15 are
referred to chip 0 or chip 1. This is useful in the case that two L8229 are
present on the same board and a single nCS line is used.
0
CHIP ADDRESS
0
1
2
WORD ADDRESS 1
WORD ADDRESS 2
0
0
This is the LSB of the two bits used to address the word.
This is the MSB of the two bits used to address the word.
This bit is to decide if Slow or Mixed Decay is applied to Bridge 1
(Stepping motor).
3
4
5
6
7
8
9
MIX/SLOW 1 (St. mot)
MIX/SLOW 2 (St. mot)
REFERENCE INT/EXT
RANGE
0
0
0
0
0
0
0
0
This bit is to decide if Slow or Mixed Decay is applied to Bridge 2
(Stepping motor).
This bit is used to decide if the reference voltage will be internal (0) or
external (1)
This bit is to decide if the reference voltage will be divided by 10 (0) or
by 5 (1).
This is the LSB bit used to fix the Blanking time (see following
Table 30).
BLANK LSB
This is the MSB bit used to fix the Blanking time (see following
Table 30).
BLANK MSB
This is the LSB bit used to fix the Oscillator values (see following
Table 29).
OSC LSB
This is the MSB bit used to fix the Oscillator values (see following
Table 29).
10 OSC MSB
11 TEST 1
12 TEST 2
13 TEST 3
0
0
0
This bit is used for trim mode.
This bit is used for trim mode.
This bit is used for trim mode.
This bit is used to set the drive of a Stepping Motor (0) or a DC Motor
(1).
14 STEP/DC
0
0
This bit is used to decide if Slow (0) or Fast (1) decay is applied to DC
Motor configuration
15 SLOW/FAST (DC mot)
26/42
L8229
L8229_0 and L8229_1 modes
8.4.1
Reading back SPI.
When W2 bit 11 to 13 are to 111, read back from SPI is enabled. This function is to check
the actual data in W0 and W1; W2 can’t be read back.
To read back the following procedure is requested:
1. Set PROG1=1, PROG2=0
2. Write W0 and W1 to SDI
3. Write W2 (with bits 11, 12, 13 set to 111) to SDI. This enables read back mode from
SPI.
4. Write 0001 1111 1111 1111 to SDI (the first three bits mean that W0 is requested to be
read out, the other bits have no sense just to fill the blank bits). This allows to check if
the SDI output is W0 bit3~15.
5. Write W2 (with bits 11, 12, 13 set to 111) to SDI. This enables read back mode from
SPI.
6. Write 0101 1111 1111 1111 to SDI (the first three bits mean that W1 is requested to be
read out, the other bits have no sense just to fill the blank bits). This allows to check if
the SDI output is W1 bit3~15.
If the data to be read out are the same as the data write in, it means write function of SPI is
right.
27/42
SPI programming
L8229
9
SPI programming
On power up, the device is by default in sleep mode. Before coming out from sleep, the
device needs to be programmed to drive either Stepping or DC motor. This is controlled by
W2 bit 14. Default is stepping motor drive.
Table 22. Motor mode selected by W2
Bit 14
Mode
0
1
Stepping motor
DC motor
The device can be awoken from the sleep mode by means of the bit 3 of W1.
Table 23. Nsleep mode selected by W1
Bit 3
Mode
0
1
Sleep
Normal
The device can be set in brake mode ( both outputs are LL) by means of W1 bit 15. Please
note that Brake mode overcomes Nsleep mode.
Table 24. Brake mode selected by W1
Bit 15
Mode
0
1
Normal
Brake
9.1
Current Control
Current level in the motor is set by means of a combination of Vref (ext or int), Rsense and
DAC control bits.
The max current is set as follows:
Imax = Vref / (Range x Rsense)
Vref can be set to be internal at 2V or externally applied to VREF1 and VREF2 pins. On
power up, the default is the internal 2V.
Table 25. Vref mode selected by W2
Bit 5
Mode
0
1
Internal ref. 2V
External ref. (7.5V max)
Vref voltage is divided according to Range value that is defined by W2 bit 6 to be either 10
or 5.
28/42
L8229
SPI programming
Table 26. Range mode selected by W2
Bit 6
Mode
0
1
Range = 10
Range = 5
The direction of current is determined by W0 bits 8 and 14. During Ton, outputs will be
according to following table:
Table 27. Current direction selected by W0
Bit 8 (14)
OUT A
OUT B
0
1
L
H
L
H
The 5 bit DACs for each Bridge enable an accurate resolution control defined by Current
levels table below. The current level Iset is then defined as:
Iset = Vdac / (Range x Rsense)
where:
Vdac = (DAC/31) x Vref
where DAC is defined from 0 to 31, so the current level is fixed by W0 bits 7 (MSB) to 3
(LSB) (13 to 9) as in following table.
Table 28. Current levels selected by W0 for DAC
Bit 7 (13)
Bit 6 (12)
Bit 5 (11)
Bit 4 (10)
Bit 3 (9)
IPH_A (B)/Imax
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
16/31
29/42
SPI programming
Table 28. Current levels selected by W0 for DAC (continued)
L8229
Bit 7 (13)
Bit 6 (12)
Bit 5 (11)
Bit 4 (10)
Bit 3 (9)
IPH_A (B)/Imax
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
9.2
Timings Control
All timings are controlled by a master oscillator that can be internal or externally provided. At
power up, OSC will default to the internal 4MHz oscillator. Setting W2 bits 9 and 10 will
select the external oscillator frequency or it's dividing by either 2 or 4.
Table 29. Oscillator frequency selected by W2
Bit 10
Bit 9
Freq
0
0
1
1
0
1
0
1
Internal (4MHz)
Ext
Ext/2
Ext/4
The switching blanking time for masking transient can be selected by W2 bits 7 and 8.
Table 30. Blanking time selected by W2
Bit 8
Bit 7
Time
0
0
1
1
0
1
0
1
2/fosc
4/fosc
8/fosc
12/fosc
30/42
L8229
SPI programming
Fast decay timing is set by W1 bits 9 (LSB) to 12 (MSB).
Tfast = (N+1) x 8/Fosc
Where N = 0 to 15 and Fosc is either the internal 4 MHz or the external oscillator frequency
with selected division.
Setting Toff to be smaller than Tfast will result in fast decay only.
Table 31. Fast decay time selected by W1
Bit 12
Bit 11
Bit10
Bit9
Fast decay
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1x8/fosc
2x8/fosc
3x8/fosc
4x8/fosc
5x8/fosc
6x8/fosc
7x8/fosc
8x8/fosc
9x8/fosc
10x8/fosc
11x8/fosc
12x8/fosc
13x8/fosc
14x8/fosc
15x8/fosc
16x8/fosc
The Toff timing is controlled by bits 4 (LSB) to 8 (MSB) of W1 and is based on the oscillator
frequency.
Toff = (N+1) x 8/Fosc
Where N = 0 to 31 and Fosc is either the internal 4 MHz or the external oscillator frequency
with selected division.
Table 32. Toff time selected by W1
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Toff
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1x8/fosc
2x8/fosc
3x8/fosc
4x8/fosc
5x8/fosc
6x8/fosc
31/42
SPI programming
Table 32. Toff time selected by W1 (continued)
L8229
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Toff
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
7x8/fosc
8x8/fosc
9x8/fosc
10x8/fosc
11x8/fosc
12x8/fosc
13x8/fosc
14x8/fosc
15x8/fosc
16x8/fosc
17x8/fosc
18x8/fosc
19x8/fosc
20x8/fosc
21x8/fosc
22x8/fosc
23x8/fosc
24x8/fosc
25x8/fosc
26x8/fosc
27x8/fosc
28x8/fosc
29x8/fosc
30x8/fosc
31x8/fosc
32x8/fosc
32/42
L8229
SPI programming
9.3
Decay Modes and Synchronous Rectification
For stepping motor drive, the recirculation mode during Toff could be slow, fast or mixed
(that is fast followed by slow decay): W2, by means of bit 3 (for Out1) and bit 4 (for Out2),
allows to select MIXED or SLOW decay for bridge 1 and bridge 2 respectively; by selecting
(with W1, bits 9 to 12) Tfast longer than Toff, it is possible to select FAST decay for all the
Toff duration.
Table 33. Stepping decay mode selected by W2
Bit 3 (4)
Mode
0
1
Mixed decay
Slow decay
For DC motor drive, W2 bit 15 allows to choose slow or fast decay.
Table 34. DC decay mode selected by W2
Bit 15
Mode
0
1
Slow
Fast
During the decay, it is possible for the current to flow through the intrinsic body diodes of the
LDMOS or through switched on LDMOS channel (in this case the current conduction will be
reversed from Source to Drain). This switching on of the active device in parallel with the
diode is called SYNCHRONOUS rectification and means that the recirculation path is not
obtained only through the internal diodes but also by turning on the DMOS in parallel with
the diode needed to recirculate current; because of the low RDSon of this LDMOS the
dissipation is reduced.
For stepping motors only with W1, by means of bits 13 and 14, it is possible to choose
several kinds of SYNCHRONOUS recirculation modes: ACTIVE recirculation, PASSIVE
recirculation, SYNC OFF recirculation, and LOW SIDE recirculation.
Table 35. Sync rectification selected by W1
Bit 14
Bit 13
Mode
0
0
1
0
1
Active(1)
Passive
Off
0
1
1
Low side
1. Only for Mixed Decay mode.
ACTIVE means that the current is monitored to avoid reverse current in the load: this could
happen because of FAST SYNC recirculation (that reverse the conduction of the bridge).
When a reverse current is detected, synchronous rectification is turned off, so the outputs
are placed in Hi-Z state until the end of Toff. Please note that Active Synchronous
rectification can't be used when in Slow Decay mode.
PASSIVE means that the current is not monitored to avoid a reverse current in the load. In
this case the current, during Toff, could be inverted and no action is taken until the current
reaches the current limit selected by the user by means of Vref and Rsense. When this
33/42
SPI programming
L8229
value is reached, synchronous rectification is turned off, so the outputs are placed in Hi-Z
state until the end of Toff. Please note that a typical 50mA reverse current could be present
during Active Sync rectification.
SYNC OFF means that the current will recirculate through the body diodes in parallel with
power DMOS. This is intended to allow the user to use external Schottky diodes to save the
internal dissipation.
LOW SIDE means that the synchronous recirculation is forced only through the low side
power DMOS.
Please note that while the current reversal is always sensed, if required, the current level is
sensed only by means of Rsense, so no current control is performed when current flows
away from Rsense, as in SLOW recirculation.
Active and passive synchronous rectification modes are illustrated in the following drawing:
Figure 9.
Active and Passive synchronous rectification during Mixed Decay.
VS
HA
I1
HB
-
-
ADgtS
BDgtS
I2
+
+
LA
LB
+
-
Ilimit
VDAC
Active Sync during Fast decay
Active Sync during Slow decay
Recirculation
Drive
Hi-Z
Drive
Hi-Z
Recirculat.
I1
I2
I1
I2
ADgtS
LA
ADgtS
LA
ON
ON
ON
ON
HB
LB
Passive Sync during Fast decay
Passive Sync during Slow decay
Drive
Recirculation
Hi-Z
Drive
Recirculation
Hi-Z
I1
I2
I1
I2
ADgtS
LA
ADgtS
LA
HB
ON
ON
ON
ON
LB
Ilimit
Remains ON till end of Toff
Remains ON till end of Toff or
Ilimit reached
34/42
L8229
SPI programming
The output states during these cases of recirculation could be summarized as below: (only
OUTA to OUTB current flowing is described)
9.4
Mixed Decay
1) ACTIVE SYNC recirculation could be divided in following cases.
1a) No reverse current detected during Toff
HA on HB off
LA off
LB on Current increasing in the load.
Anticross state (fast recirculation through LA and HB body
diodes).
All off
FAST SYNC recirculation through DMOS till end of fast decay
HA off HB on
LA on
LB off
time.
Anticross state (fast recirculation through LA DMOS and HB
body diode).
HA off HB off
HA off HB off
HA off HB off
HA on HB off
LA on
LA on
LA off
LA off
LB off
LB on SLOW SYNC recirculation till end of Toff.
Anticross state (slow recirculation through LA body diode and
LB DMOS).
LB on
LB on Current increasing in the load.
1b) Reverse current detected during Fast Recirculation of Toff
HA on HB off
LA off
LB on Current increasing in the load.
Anticross state (fast recirculation through LA and HB body
diodes).
All off
FAST SYNC recirculation through DMOS till reverse current is
detected.
HA off HB on
HA on HB off
LA on
LB off
All off
LA off
Hi-Z state till end of Toff.
LB on Current increasing in the load.
1c) Reverse current detected during Slow Recirculation of Toff
HA on HB off
LA off
LB on Current increasing in the load.
Anticross state (fast recirculation through LA and HB body
diodes).
All off
FAST SYNC recirculation through DMOS till end of fast
decay time.
HA off HB on
LA on
LB off
Anticross state (fast recirculation through LA DMOS and HB
body diode).
HA off HB off
HA off HB off
LA on
LA on
LB off
LB on SLOW SYNC recirculation till reverse current is detected.
Hi-Z state till end of Toff.
All off
HA on HB off
LA off
LB on Current increasing in the load.
35/42
SPI programming
L8229
2) - PASSIVE SYNC recirculation could be divided in following cases:
2a) The reverse current (if present) does not exceed the regulated value
(Note: this case is identical to ACTIVE SYNC case 1a)
HA on HB off
LA off
LB on Current increasing in the load.
Anticross state (fast recirculation through LA and HB body
diodes).
All off
FAST SYNC recirculation through DMOS till end of fast decay
time.
HA off HB on
LA on
LB off
LB off
Anticross state (fast recirculation through LA DMOS and HB
body diode).
HA off HB off
HA off HB off
HA off HB off
HA on HB off
LA on
LA on
LA off
LA off
LB on SLOW SYNC recirculation till end of Toff.
Anticross state (slow recirculation through LA body diode and
LB DMOS).
LB on
LB on Current increasing in the load.
2b) The reverse current exceeds the regulated value during FAST
recirculation.
(Note: if the current exceed the regulated value during SLOW recirculation, no
action is taken and the behaviour will be that of case 2a)
HA on HB off
LA off
LB on Current increasing in the load.
Anticross state (fast recirculation through LA and HB body
diodes).
All off
FAST SYNC recirculation through DMOS till reverse current
reaches the regulated value).
HA off HB on
HA on HB off
LA on
LB off
All off
LA off
Hi-Z state till end of Toff.
LB on Current increasing in the load.
3) - SYNC OFF recirculation has only one case:
HA on HB off
LA off
LB on Current increasing in the load.
Fast recirculation through LA and HB body diodes till end of
fast decay time.
All off
Slow recirculation through LA body diode and LB DMOS till
end of Toff.
HA off HB off
HA on HB off
LA off
LA off
LB on
LB on Current increasing in the load.
36/42
L8229
SPI programming
4) LOW SIDE recirculation has only one case:
HA on HB off
LA off
LB on Current increasing in the load.
Fast recirculation through LA and HB body diodes) till end of
fast decay time.
All off
HA off HB off
HA off HB off
HA on HB off
LA on
LA off
LA off
LB on SLOW SYNC recirculation till end of Toff.
Anticross state (slow recirculation through the LA body diode
and LB DMOS).
LB on
LB on Current increasing in the load.
9.5
Slow Decay
When in Slow Decay, Active Synchronous rectification can't be used since current is not
expected to be reversed because of BEMF. Therefore only Passive, Off or Low side
recirculation cases can be selected.
1) ACTIVE SYNC recirculation is not allowed.
2) PASSIVE SYNC recirculation
HA on HB off
HA off HB off
HA off HB off
HA off HB off
HA on HB off
LA off
LA off
LA on
LA off
LA off
LB on Current increasing in the load.
Anticross state (slow recirculation through LA body diode and
LB DMOS).
LB on
LB on SLOW SYNC recirculation till end of Toff.
Anticross state (slow recirculation through the LA body diode
and LB DMOS).
LB on
LB on Current increasing in the load.
3) SYNC OFF
HA on HB off
HA off HB off
HA on HB off
LA off
LA off
LA off
LB on Current increasing in the load.
Slow recirculation (through the LA body diode and LB DMOS)
till end of Toff
LB on
LB on Current increasing in the load.
4) LOW SIDE is identical to PASSIVE SYNC.
37/42
DC Motor Driver operation
L8229
10
DC Motor Driver operation
When in L8229_0 or L8229_1 configuration, the device could be configured to drive two
different DC motors. Each drive provides bi-directional drive to a DC motor via the serial
control and the PWM pins. The W0 bits 8 and 14 in the register will control the direction of
drive while the PWM input pin controls the switching of the drivers. According to above
description, the motor drive will be in voltage mode only.
The device could also drive a single DC motor with increased current by paralleling the two
bridges. If this is required, W0 bit 15 must be set to 1 and OUT1A must be shorted to
OUT2A while OUT1B must be shorted to OUT2B. In this case of two bridges paralled to
drive a single DC motor, the W0 bit 14 (PHASE2) will not be used as well as pin 17 (PWM2).
This means that the device will act as a single bridge with ouputs OUTA (OUT1A in parallel
with OUT2A), OUTB (OUT1B in parallel with OUT2B) and driven by PHASE1 (W0 bit 8) and
PWM1 (pin 20).
The drives are powered by VS.
The crossover delay is controlled to provide sufficient time for cross-conduction
suppression, so that at no time both the upper and lower output devices on the same side of
the H bridge are allowed to conduct simultaneously.
A blanking period following a current turn-on event is included to prevent false current
protection turnoffs due to the initial current spike resulting from circuit capacitance.
When OCD happens, outputs are placed in Hi_Z untill next PWM positive edge occurs.
During an over-temperature event, when the device junction temperature Tj is above
Tj(shutdown), the internal thermal protection circuit disables the drive outputs by driving all
outputs to the high impedance state until the device temperatures have dropped below the
lower thermal threshold temperature.
Table 36. DC Motor Drivers - DC Specifications
(0°C ≤ T ≤ 125°C, V = 32 V, unless otherwise specified)
j
S
Name
Description
Conditions
Min
Typ
Max
Units
DC Motor Over Current Threshold
(1)
IDCMOTOR OCT
1.5
A
1. The current limitation is applied to the bottom H bridge LDMOS only, therefore over current protection applies to motor
current, but no short circuit protection exists against shorts from the DC motor outputs to ground or to VS.
Table 37. DC Motor Drivers - AC/Transient Specifications
(0°C ≤ T ≤ 125°C, V = 32 V, unless otherwise specified)
j
S
Name
Description
PWM frequency
Blanking time (for OCD)
Conditions
Min
Typ
Max
Units
fPWM
10
30
KHz
Tblank
1
μs
Table 38. DC Motor Drivers Truth Table
W2 bit 15
(SLOW
/FAST)
W0 bit 8 Pin 20
or 14 or 17
(PHASE) (PWM)
Therm.
prot.
OUT A
OUT Al
OUT B
OUT B
OCD
Out State
high side ow side high side low side
0
0
0
0
0
0
0
0
0
1
Off
Off
On
On
Off
On
On
Off
L-L
L-H
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L8229
DC Motor Driver operation
Table 38. DC Motor Drivers Truth Table (continued)
W2 bit 15
(SLOW
/FAST)
W0 bit 8 Pin 20
or 14 or 17
(PHASE) (PWM)
Therm.
prot.
OUT A
OUT Al
OUT B
OUT B
OCD
Out State
high side ow side high side low side
0
0
0
0
0
0
x
1
0
0
0
0
0
0
1
x
0
0
1
1
1
1
X
X
1
1
0
0
1
1
X
X
0
1
0
1
0
1
X
X
Off
On
On
Off
Off
On
Off
Off
On
Off
Off
On
On
Off
Off
Off
Off
Off
Off
On
On
Off
Off
Off
On
On
On
Off
Off
On
Off
Off
L-L
H-L
H-L
L-H
L-H
H-L
Hi. Z
Hi. Z
39/42
Package Information
L8229
11
Package Information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 10. PowerSSO24 Mechanical Data & Package Dimensions
mm
inch
DIM.
OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A
A2
a1
b
2.15
2.15
0
2.47 0.084
2.40 0.084
0.097
0.094
0.003
0.020
0.012
0.413
0.075
0
0.33
0.23
10.10
0.51 0.013
0.32 0.009
10.50 0.398
c
D (1)
E (1)
e
7.4
7.6
0.291
0.299
0.8
8.8
0.031
0.346
e3
G
0.10
0.06
0.004
0.002
0.413
0.016
0.033
G1
H
10.10
0.55
10.50 0.398
0.40
h
L
0.85 0.022
10˚ (max)
N
X
4.10
6.50
4.70 0.161
7.10 0.256
0.185
0.279
Y
(1) “D and E1” do not include mold flash or protusions.
PowerSSO-24
(Exposed Pad)
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
(3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm
per side
7412818 A
40/42
L8229
Revision history
12
Revision history
Table 39. Document revision history
Date
Revision
Changes
17-Feb-2005
10-Aug-2005
1
2
Initial release.
Many modify of texts and table.
Corrected some errors/imprecisions in the whole document.
20-Feb- 2006
3
Cancelled the L8229S part number, and all information about
HSOP24 package.
30-May-2006
12-Sep- 2006
4
5
Added note at the table 2.
Applied new graphic design template.
Modified the tables 2, 5, 6, 7, 8. 10, 13, 14, 15, 16, 17, 23 and 24.
41/42
L8229
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