74VHC16373 [STMICROELECTRONICS]
16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING; 具有三态输出的非反相16位D型锁存器
| 型号： | 74VHC16373 |
| 厂家： | 
ST |
| 描述： | 16-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS NON INVERTING |
| 文件： | 总11页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VHC16373
16-BIT D-TYPE LATCH
WITH 3-STATE OUTPUTS NON INVERTING
■
■
■
HIGH SPEED:
= 5.0 ns (TYP.) at V = 5V
t
PD
CC
LOW POWER DISSIPATION:
= 4 µA (MAX.) at T =25°C
I
CC
A
HIGH NOISE IMMUNITY:
= V = 28% V (MIN.)
V
NIH
NIL
CC
TSSOP
TUBE
■
■
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I | = I = 8 mA (MIN)
OH
OL
■
■
■
BALANCED PROPAGATION DELAYS:
ORDER CODES
PACKAGE
t
t
PLH
PHL
T & R
OPERATING VOLTAGE RANGE:
(OPR) = 2V to 5.5V
TSSOP
74VHC16373TTR
V
CC
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
PIN CONNECTION
■
■
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
= 0.9V (MAX.)
OLP
DESCRIPTION
The 74VHC16373 is an advanced high-speed
CMOS 16 BIT D-TYPE LATCH with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
2
wiring C MOS technology.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(nOE).
While the nLE input is held at a high level, the nQ
outputs will follow the data (D) inputs.
When the nLE is taken LOW, the nQ outputs will
be latched at the logic level of D data inputs.
When the (nOE) input is low, the nQ outputs will
be in a normal logic state (high or low logic level);
when nOE is at high level ,the outputs will be in a
high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
February 2003
1/11
74VHC16373
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
IEC LOGIC SYMBOLS
PIN No
SYMBOL
NAME AND FUNCTION
1
1OE
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs
11, 12
13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs
19, 20, 22, 23
24
2OE
3 State Output Enable
Input (Active LOW)
25
2LE
Latch Enable Input
36, 35, 33, 32, 2D0 to 2D7 Data Inputs
30, 29, 27, 26
47, 46, 44, 43, 1D0 to 1D7 Data Inputs
41, 40, 38, 37
48
1LE
Latch Enable Input
Ground (0V)
4, 10, 15, 21,
28, 34, 39, 45
GND
7, 18, 31, 42
V
Positive Supply Voltage
CC
TRUTH TABLE
INPUTS
LE
OUTPUT
OE
D
Q
H
L
L
X
L
X
X
L
Z
NO CHANGE *
H
H
L
L
H
H
X : Don‘t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.
2/11
74VHC16373
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +7.0
-0.5 to +7.0
V
V
CC
V
DC Input Voltage
I
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
-0.5 to V + 0.5
V
O
CC
I
- 20
± 20
mA
mA
mA
mA
°C
IK
I
OK
I
± 25
O
I
or I
DC V or Ground Current
± 75
CC
GND
CC
T
Storage Temperature
-65 to +150
300
stg
T
Lead Temperature (10 sec)
°C
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
2 to 5.5
0 to 5.5
V
V
CC
V
Input Voltage
I
V
Output Voltage
0 to V
V
O
CC
T
Operating Temperature
-55 to 125
0 to 100
0 to 20
°C
op
Input Rise and Fall Time (note 1) (V = 3.3 ± 0.3V)
CC
dt/dv
ns/V
(V = 5.0 ± 0.5V)
CC
1) V from 30% to 70% of V
IN
CC
3/11
74VHC16373
DC SPECIFICATIONS
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
High Level Input
Voltage
2.0
1.5
1.5
1.5
IH
V
V
3.0 to
5.5
0.7VCC
0.7VCC
0.7VCC
V
Low Level Input
Voltage
2.0
0.5
0.5
0.5
IL
3.0 to
5.5
0.3VCC
0.3VCC
0.3VCC
V
High Level Output
Voltage
I =-50 µA
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
1.9
2.9
2.0
3.0
4.5
1.9
2.9
1.9
2.9
4.4
2.4
3.7
OH
O
I =-50 µA
O
I =-50 µA
4.4
4.4
V
O
I =-4 mA
2.58
3.94
2.48
3.8
O
I =-8 mA
O
V
Low Level Output
Voltage
I =50 µA
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
OL
O
I =50 µA
O
I =50 µA
0.1
0.1
0.1
V
O
I =4 mA
0.36
0.36
0.44
0.44
0.55
0.55
O
I =8 mA
O
I
High Impedance
Output Leakage
Current
OZ
V = V or V
IL
I
IH
5.5
±0.25
± 2.5
± 5
µA
V
= V or GND
CC
O
I
Input Leakage
Current
0 to
5.5
I
V = 5.5V or GND
± 0.1
± 1
± 1
µA
µA
I
I
Quiescent Supply
Current
CC
V = V or GND
5.5
4
40
40
I
CC
4/11
74VHC16373
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3ns)
r
f
Test Condition
Value
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
T
= 25°C
Symbol
Parameter
A
V
C
L
(V) (pF)
CC
(*)
t
t
Propagation Delay
Time
LE to Qn
15
50
15
50
15
50
15
50
15
50
15
50
50
50
5.5
7
13
14.5
8.5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
4
4
1
1
15
16.5
9.5
10.5
15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
4
4
1
1
15
16.5
9.5
10.5
15
PLH
3.3
PHL
(*)
3.3
ns
ns
(**)
(**)
(*)
3.6
5
5.0
5.0
9.5
t
t
Propagation Delay
Time
Dn to Qn
5.5
7.5
4
13
PLH
PHL
3.3
(*)
14
16
16
3.3
(**)
(**)
(*)
8.2
9.5
10.5
15
9.5
10.5
15
5.0
5.0
5
9.2
t
t
Output Enable
Time
5.2
7.6
4
13
PZL
3.3
3.3
ns
ns
ns
ns
ns
ns
ns
(*)
PZH
14.9
9.1
16
16
(**)
(**)
(*)
10
10
5.0
5.0
5
10.1
15.5
10.5
11.5
17
11.5
17
t
Output Disable
Time
9
PLZ
3.3
t
(**)
PHZ
6
11.5
11.5
5.0
3.3
(*)
t
Pulse Width (LE)
HIGH
5
5
4
4
1
1
w
(**)
(*)
5.0
t
Setup Time Dn to
LE HIGH or LOW
s
3.3
(**)
5.0
3.3
(*)
t
Hold Time Dn to LE
HIGH or LOW
h
(**)
5.0
(*)
t
t
50
50
1.5
1
1.5
1
1.5
1
OSLH
OSHL
3.3
Output to Output
Skew time (note 1)
(**)
5.0
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
Note 1 : Parameter guaranteed by design. t
= |t
- t
|, t
= |t
- t
|
soLH
pLHm pLHn soHL
pHLm pHLn
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
C
Input Capacitance
2.5
4
10
10
10
pF
pF
IN
Output
Capacitance
C
OUT
C
Power Dissipation
Capacitance
(note 1)
PD
f
= 10MHz
5.0
21
pF
IN
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= C x V x f + I /n (per Latch)
CC(opr)
PD CC IN CC
5/11
74VHC16373
DYNAMIC SWITCHING CHARACTERISTICS
Test Condition
Value
T
= 25°C
Symbol
Parameter
-40 to 85°C -55 to 125°C Unit
A
V
CC
(V)
Min. Typ. Max. Min. Max. Min. Max.
V
Dynamic Low
Voltage Quiet
Output (note 1, 2)
0.6
0.9
OLP
5.0
V
V
V
V
-0.9
3.5
-0.6
OLV
Dynamic High
Voltage Input
(note 1, 3)
V
C = 50 pF
L
5.0
5.0
IHD
Dynamic Low
Voltage Input
(note 1, 3)
V
1.5
ILD
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V ), 0V to threshold
ILD
(V ), f=1MHz.
IHD
TEST CIRCUIT
TEST
SWITCH
t
t
t
, t
Open
PLH PHL
, t
V
CC
PZL PLZ
, t
GND
PZH PHZ
C
R
R
= 15/50 pF or equivalent (includes jig and probe capacitance)
L
L
T
= R1 = 1KΩ or equivalent
= Z
of pulse generator (typically 50Ω)
OUT
6/11
74VHC16373
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
7/11
74VHC16373
WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
8/11
74VHC16373
TSSOP48 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
A
A1
A2
b
0.05
0.15
0.002
0.9
0.035
0.17
0.09
12.4
0.27
0.20
12.6
0.0067
0.0035
0.488
0.011
0.0079
0.496
c
D
E
8.1 BSC
0.5 BSC
0.318 BSC
E1
e
6.0
6.2
0.236
0.244
0.0197 BSC
K
0˚
8˚
0˚
8˚
L
0.50
0.75
0.020
0.030
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
7065588C
9/11
74VHC16373
Tape & Reel TSSOP48 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
30.4
8.9
1.197
0.350
0.524
0.067
0.161
0.476
Ao
Bo
Ko
Po
P
8.7
13.1
1.5
0.343
0.516
0.059
0.153
0.468
13.3
1.7
3.9
4.1
11.9
12.1
10/11
74VHC16373
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics - Printed in Italy - All Rights Reserved
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11/11
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