MQFP-D [STATSCHIP]
Heat Spreader Metric Quad Flat Pack; 散热器公制四方扁平封装
| 型号： | MQFP-D |
| 厂家： | 
STATS CHIPPAC, LTD. |
| 描述： | Heat Spreader Metric Quad Flat Pack |
| 文件： | 总2页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MQFP-d
Heat Spreader Metric Quad Flat Pack
• 14 x 14mm to 32 x 32mm
• 64 to 240 lead count
• Lead pitch range from 0.80mm
to 0.50mm
FEATURES
DESCRIPTION
• Body Sizes: 14 x 14mm to 32 x 32mm
• Package Height: 2.0mm to 3.4mm (same as QFP)
• Lead Counts: 64L to 240L
STATS ChipPAC’s Heat Spreader Metric Quad Flat Pack
(MQFP-d) is a thermally enhanced version of the QFP
package. Thermal enhancement is achieved by an embedded
anodized aluminum heat spreader which is dropped in
during the mold process. This process allows the use of
standard leadframe while offering an added margin of
thermal performance for high power applications. The
QFP-d package offers 30% improvement (typical) in thermal
performance over standard MQFP packages.
• Lead Pitch: 0.80mm to 0.50mm
• Moisture Sensitivity: JEDEC Level 3
• Wide range of open tool leadframe and die pad sizes
available
• JEDEC standard compliant
• Lead-free and Green material sets available
APPLICATIONS
• ASIC
• DSP
• FPGA
• PLD
• High speed logic, high power microprocessors /
controllers
• 3D graphics, telecom, wireless, audio, CPU / GUI
www.statschippac.com
MQFP-d
Heat Spreader Metric Quad Flat Pack
RELIABILITY
SPECIFICATIONS
Die Thickness
Gold Wire
380-560µm (15-22mils) range preferred
25/30µm (1.0/1.2mils) diameter, 99.999% Au
85/15 Sn/Pb or Matte Tin
Moisture Sensitivity Level
JEDEC Level 3
Temperature Cycling
-65°C/150°C, 1000 cycles
150°C, 500 hrs
Lead Finish
High Temperature Storage
Pressure Cooker Test
Marking
Laser / ink
121°C 100% RH,
2 atm, 168 hrs
Packing Options
JEDEC tray / tape and reel
Liquid Thermal Shock (opt)
-55°C/125°C, 1000 cycles
THERMAL PERFORMANCE, θja (°C/W)
Package
Body Size (mm)
Pad Size (mm)
Die Size (mm) Thermal Performance, θja (°C/W)
100L
14 x 20 x 2.7
9.0 x 9.0
7.8 x 7.8
26.6
208L
28 x 28 x 3.4
14.0 x 14.0
10.2 x 10.2
18.4
Note: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-7) under natural convection as defined in JESD51-2.
ELECTRICAL PERFORMANCE
Package
Body Size (mm)
Pad Size (mm)
Frequency
Self Inductance (nH) Self Capacitance(pF)
100L
208L
14 x 20 x 2.7
28 x 28 x 3.4
9.0 x 9.0
100MHz
100MHz
6.3~8.7
0.56~1.11
1.43~1.56
10.5 x 10.5
11.6~14.7
Notes: *Results are simulated. Data is available through 2.5GHz.
PACKAGE CONFIGURATIONS
CROSS-SECTION
Package Size (mm) Lead Count
14 x 14 x 2.0
14 x 14 x 2.7
14 x 20 x 2.7
28 x 28 x 3.4
32 x 32 x 3.4
64, 80
64, 80
80, 100, 128
120, 128, 144, 160, 208
240
Corporate Office 10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823
Global Offices USA 510-979-8000 JAPAN 81-43-351-3320 CHINA 86-21-5976-5858 MALAYSIA 603-4257-6222
KOREA 82-31-639-8911 TAIWAN 886-3-593-6565 UK 44-1483-413-700 NETHERLANDS 31-38-333-2023
The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks
of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information
will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document.
STATS ChipPAC reserves the right to change the information at any time and without notice.
©Copyright 2005. STATS ChipPAC Ltd. All rights reserved.
January 2005
相关型号：
©2020 ICPDF网 联系我们和版权申明