CY28330OCT [SPECTRALINEAR]
Clock Generator for AMD⑩ Hammer; 时钟发生器的AMD ™锤
| 型号： | CY28330OCT |
| 厂家： | 
SPECTRALINEAR INC |
| 描述： | Clock Generator for AMD⑩ Hammer |
| 文件： | 总14页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY28330
Clock Generator for AMD™ Hammer
Table 1. Frequency Table (MHz)[1]
Features
FS
(3:0)
PCI_HT
SEL
CPU PCI_H PCI
Div T Div Div
• Supports AMD¥ Hammer CPU
• 2 differential Pair of CPU Clocks
• 6 Low Skew/Jitter PCI Clocks
• 1 Free-running PCI Clock
CPU
PCI_HT
PCI
VC0
0000 Hi-Z
0001 XIN
0001 XIN
X
0
1
Hi-Z
Hi-Z
XIN/3 XIN/6
XIN/6 XIN/6
• 3 Low Skew/Jitter AGP/HT Clocks
• 148M Output for USB
0010 100.0 0/1 66.7/33.3 33.31 200
0011 100.0 0/1 66.7/33.3 33.31 200
0100 100.0 0/1 66.7/33.3 33.31 200
0101 133.3 0/1 66.7/33.3 33.31 266.6
0110 166.7 0/1 66.7/33.3 33.31 333.3
0111 200.0 0/1 66.7/33.3 33.31 400.0
1000 105.0 0/1 70.0/35.0 35.00 210.0
1001 110.0 0/1 73.3/36.7 36.67 220.0
1010 115.0 0/1 76.7/38.3 38.33 230.0
1011 120.0 0/1 60.0/30.0 30.00 240.0
1100 140.0 0/1 70.0/35.0 35.00 280.0
1101 150.0 0/1 60.0/30.0 30.00 300.0
1110 160.0 0/1 64.0/32.0 32.00 320.0
1111 180.0 0/1 60.0/30.0 30.00 360.0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3/6
3/6
3/6
4/8
6
6
6
8
• 1 programmable 24M or 48M for FDC
• 3 REF 14.318MHz Clocks
• Dial-a-Frequency¥ Programmability
• Cypress Spread Spectrum for Best EMI Reduction
• SMBus Register Programmable Options
• 5V Tolerance SCLK and SDATA Lines
• 3.3V Operation
5/10 10
6/12 12
3/6
3/6
3/6
4/8
4/8
6
6
6
8
8
• Power Management Control Pins
• 48 Pin SSOP Package
5/10 10
5/10 10
6/12 12
=
Pin Configuration
Block Diagram
XIN
14.31818MHz
XTAL
FS0/REF0
VDD
XIN
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
FS1/REF1
VSS
VDD
REF(0:2)
USB
XOUT
2
3
/4
/2
XOUT
VSS
4
FS2/REF2
*SPREAD
VDDA
VSSA
CPUT0
CPUC0
VSS
PLL1
5
*PCI33HT66SEL#
PCI33_HT66_0
PCI33_HT66_1
VDD
6
24_48MH
7
8
9
24_48MH/
24_48SEL#
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PCI33_HT66_2
*SRESET#/PD#
PCI33_0
PCI33_1
VSS
VDD
CPUT1
CPUC1
VDD
FS(0:3)
PCISTOP#
CPUT(0:1)
CPUC(0:1)
PLL2
VSS
VDD
VSSF
VDDF
USB
SPREAD
PCI33_2
PCI33_3
VDD
Control Logic
PCI33_F
/N
SRESET#/PD#
VSS
VDD
SCLK
VSS
STOP
CNTL
PCI33_(0:5)
PCI33_4
PCI33_5
FS3/PCI33_F
PCISTOP#
24_48MHz/SEL#
VSS
SDATA
SDATA
PCI33_HT66_(0:2)
SCLK
* = 150 K:Pull-up
Note:
1. All outputs except XOUT will be three-stated when FS(3:0) = 0000.
Rev 1.0, November 21, 2006
Page 1 of 14
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
CY28330
Pin Description
Pin
3
Name
XIN
PWR
VDD
VDD
I/O
I
Description
Oscillator Buffer Input. Connect to a crystal or to an external clock.
4
XOUT
O
Oscillator Buffer Output. Connect to a crystal. Do not connect when
an external clock is applied at XIN.
41, 37
40, 36
CPUT(0:1)
CPUC(0:1)
VDDC
VDDC
O
O
CPU clock outputs 0 and 1: push-pull “true” output of differential pair.
CPU clock outputs 0 and 1: push-pull “compliment” output of differ-
ential pair.
23
PCI33_F
VDD
VDD
O
O
3.3V free-running PCI clock output.
13, 14, 17, 18,
21, 22
PCI33(0:5)
3.3V PCI clock outputs controlled by PCISTOP#.
7, 8, 11
PCI33_HT66(0:2)
PCI33_HT66SEL#
VDD
VDD
O
3.3V PCI 33MHz or HyperTransport¥ꢀ66 clock outputs. This group
is selectable between 33 MHz and 66 MHz based upon the state of the
PCI33HT66SEL#.
6
I
PU
This input selects the output frequency of PCI33_HT66 outputs to
either 33 MHz or 66 MHz. There is an internal 150K ohm pull-up
resistor. This pin will be externally strapped low using a 10Kohm
resistor to VSS. 0 = 66 MHz, 1 = 33 MHz.
31
28
USB
VDDF
VDDF
O
3.3V USB clock output at 48 MHz.
24_48/SEL#
I/O
PU
3.3v Super I/O clock output. At power up this pin is sensed to
determine whether the output is 24 MHz or 48 MHz. There is an internal
150K ohmpull-up resistor. Thispin will be externally strapped lowusing
a 10K ohm resistor to VSS. 0 = 48 MHz, 1 = 24 MHz.
1, 48, 45
REF(0:2)/FS(0:2)
SPREAD
VDD
VDD
I/O
PU
3.3V Reference clock output. At power up this pin is sensed to
determine the CPU output frequency. There is an internal 150K ohm
pull-up resistor. These pins will be externally strapped low using a 10K
ohm resistor to VSS. See Table 1.
44
I
PU
Spread Spectrum clock enable. At power up this pin is sensed to
determine whether spread spectrum clocking in enabled on all output
except the USB and 24_48/SEL#. There is an internal 150K ohm
pull-up resistor. This pin will be externally strapped low using a 10K
ohm resistor to VSS. 0=disable, 1=enable.
24
12
PCISTOP#
VDD
I
PU
Control for PCI33(0:5) and PCI33_HT66(0:2) outputs. Active LOW
control input to halt all 33MHz PCI clocks except PCI33_F. Only the
PCI33_HT66 outputs that are running at 33MHz will be stopped. The
outputs will be glitch free when turning off and turning on. There is an
internal 150K ohm pull-up resistor.
SRESET#
PD#
VDD
VDD
O
SRESET output from Watchdog timer. Active low.
I
PU
Power-down input. 1 = running, 0 = Power Down. There is an internal
150K ohm pull-up resistor.
26
25
SDATA
SCLK
VDD
VDD
VDD
I/O
I
Data pin for SMBus (rev2.0).
Clock pin for SMBus (rev2.0).
2, 9,16,19,29,
35, 38, 46
PWR Power connection to 3.3V for the core.
5, 10, 15, 20,
27, 30, 34, 39,
47
VSS
GND Power connection to GROUND for the CORE section of the chip.
43
42
VDDA
VSSA
PWR Power connection to 3.3V for the ANALOG section of the chip.
GND Power connection to GROUND for the ANALOG section of the
chip.
32
33
VDDF
VSSF
PWR Power connection to 3.3V for the 48-MHz PLL section of the chip.
GND Power connection to GROUND for the 48-MHz PLL section of the
chip.
Rev 1.0,November 21, 2006
Page 2 of 14
CY28330
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc., can be individually enabled or
disabled.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation
1 = Byte read or byte write operation
Data Protocol
(6:0)
Byte offset for byte read or byte write operation.
For block read or block write operations, these bits
should be '0000000'
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operation from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
Table 3. Block Read and Block Write protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Start
Bit
1
2:8
9
Start
2:8
9
Slave address - 7 bits
Write = 0
Slave address - 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code - 8 Bit
'00000000' stands for block operation
11:18
Command Code - 8 Bit
'00000000' stands for block operation
19
20:27
28
Acknowledge from slave
Byte Count from master - 8 bits
Acknowledge from slave
Data byte 0 from master- 8 bits
Acknowledge from slave
Data byte 1 from master - 8 bits
Acknowledge from slave
Data bytes from master/Acknowledge
Data Byte N - 8 bits
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address - 7 bits
Read = 1
29:36
37
29
Acknowledge from slave
Byte count from slave - 8 bits
Acknowledge
38:45
46
30:37
38
....
39:46
47
Data byte 0 from slave - 8 bits
Acknowledge
....
....
Acknowledge from slave
Stop
48:55
56
Data byte 1 from slave - 8 bits
Acknowledge
....
....
Data bytes from slave/Acknowledge
Data byte N from slave - 8 bits
Not Acknowledge
....
....
....
Stop
Rev 1.0,November 21, 2006
Page 3 of 14
CY28330
Table 4. Byte Read and Byte Write protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Start
Bit
1
Start
2:8
9
Slave address - 7 bits
Write = 0
2:8
9
Slave address - 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
Command Code - 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
11:18
Command Code - 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
11:18
19
20:27
28
Acknowledge from slave
Data byte from master - 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address - 7 bits
Read = 1
29
29
Acknowledge from slave
Data byte from slave - 8 bits
Not Acknowledge
Stop
30:37
38
39
Serial Control Registers
Byte 0: Frequency and Spread Spectrum Control Register
Bit
@Pup
Description
7
Inactive = 0 Write Disable (write once). A 1 written to this bit after a 1 has been written to Byte0 bit0 will perma-
nently disable modification of all configuration registers until the part has been powered off. Once
the clock generator has been Write Disabled, the SMBus controller should still accept and
acknowledge subsequent write cycles but it should not modify any of the registers.
6
Inactive = 0 Spread Spectrum enable (0=disable, 1=enable). This bit provides a SW programmable control for
spread spectrum clocking. See Table 5. The readback version of this bit is the hardware strapped
value such that the SW has the ability to know each state, either by readback or by writing the SSE bit.
5
4
3
2
1
0
0
ATPG Mode. 0 = disable, 1 = enable. See Byte 8, bit 7.
FS(3) (corresponds to Frequency Selection. See Table 1.
FS(2) (corresponds to Frequency Selection. See Table 1.
FS(1) (corresponds to Frequency Selection. See Table 1.
FS(0) (corresponds to Frequency Selection. See Table 1.
FS3 pin
FS2 pin
FS1 pin
FS0 pin
Inactive = 0 Write Enable. A 1 written to this bit after power up will enable modification of all configuration registers
and subsequent 0's written to this bit will disable modification of all configuration except this single
bit. Note that block write transactions to the interface will complete, however unless the interface has
been previously un-locked, the writes will have no effect. The effect of writing this bit does not take
effect until the subsequent block write command.
Table 5. Spread Spectrum Enable
Pin 44
B0b6
Spread Enable
0
0
1
1
0
1
0
1
Off
On
On
On
Rev 1.0,November 21, 2006
Page 4 of 14
CY28330
Byte 1: PCI Clock Control Register
Bit
7
@Pup
Pin#
8
Name
Test Condition
1
1
1
1
1
1
1
1
PCI33_HT66_1 enable (1=Enabled, 0=Disabled)
PCI33_HT66_0 enable (1=Enabled, 0=Disabled)
6
7
5
22
21
18
17
14
13
PCI33_5
PCI33_4
PCI33_3
PCI33_2
PCI33_1
PCI33_0
enable (1=Enabled, 0=Disabled)
enable (1=Enabled, 0=Disabled)
enable (1=Enabled, 0=Disabled)
enable (1=Enabled, 0=Disabled)
enable (1=Enabled, 0=Disabled)
enable (1=Enabled, 0=Disabled)
4
3
2
1
0
Byte 2: PCI Clock, USB, 24_48MHz, REF(0:2) Control Register
Bit
@Pup
Test Condition
7
active = 1
CPUT/C(1) shutdown. This bit can be optionally used to disable the CPUT/C(1) clock pair.
During shutdown, CPUT=low and CPUC=high
6
active = 1
CPUT/C(0) shutdown. This bit can be optionally used to disable the CPUT/C(0) clock pair.
During shutdown, CPUT=low and CPUC=high
5
4
3
2
1
0
active = 1
active = 1
active = 1
active = 1
active = 1
active = 1
REF(2) enable (1=Enabled, 0=Disabled)
REF(1) enable (1=Enabled, 0=Disabled)
REF(0) enable (1=Enabled, 0=Disabled)
24_48MHz enable (1=Enabled, 0=Disabled)
USB enable (1=Enabled, 0=Disabled)
PCI33_HT66(2) enable (1=Enabled, 0=Disabled)
Byte 3: PCI Clock Free Running Select Control Register
Bit
7
@Pup
0
Description
PCI33 drive strength. 0 = normal, 1 = high.
6
0
PCI33_HT66 drive strength. 0 = normal, 1 = high.
5
Inactive = 0
Inactive = 0
Inactive = 0
Inactive = 0
Inactive = 0
Inactive = 0
PCI(5) free running enable (1=Free running, 0=Disabled)
PCI(4) free running enable (1=Free running, 0=Disabled)
PCI(3) free running enable (1=Free running, 0=Disabled)
PCI(2) free running enable (1=Free running, 0=Disabled)
PCI(1) free running enable (1=Free running, 0=Disabled)
PCI(0) free running enable (1=Free running, 0=Disabled)
4
3
2
1
0
Byte 4: Pin Latched/Real Time State (and one free running control)
Bit
7
@Pup
active = 1
Pin 44
Pin 28
Pin 6
Description
PCI33_F output enable. This bit can be optional used to disable the PCI33_F output.
SPREAD pin state, not latched
6
5
24_48SEL# pin power up latched state
PCI33_HT66SEL# pin statement latched
FS(2) power up latched state
4
3
Pin 45
Pin 48
Pin 1
2
FS(1) power up latched state
1
FS(0) power up latched state
0
Pin 23
FS(3) power up latched state
Rev 1.0,November 21, 2006
Page 5 of 14
CY28330
Byte 5: Clock Vendor ID
Bit
7
@Pup
Description
1
0
0
0
0
0
0
0
Vendor ID, Cypress = 100
Vendor ID
6
5
Vendor ID
4
Device Revision ID
Device Revision ID
Device Revision ID
Device Revision ID
Device Revision ID
3
2
1
0
Byte 6: SSCG, Dial-a-Skew™ and Dial-a-Ratio™ Register
Bit
7
@Pup
Description
SS_MODE; 0 = down spread, 1 = center spread See Table 6.
SST1 Select spread percentage. See Table 6.
SST0 Select spread percentage. See Table 6.
Reserved
0
0
0
1
0
6
5
4
3
DASAG1; Programming these b its allow shifting the skew of the HT66(0:2) signals relative
to their default value. See Table 7.
2
1
0
0
DASAG0; Programming these bits allow shifting the skew of the HT66(0:2) signals relative
to their default value. See Table 7.
DARAG1; Programming these bits allow shifting the ratio of the HT66(0:2) signals relative
to their default value. See Table 8.
DARAG0; Programming these bits allow shifting the ratio of the HT(0:2) signals relative to
their default value. See Table 8.
0
0
Table 6. Spread Spectrum Table
SS_Mode (B6b7)
SST1 (B6b6)
SST0 (B6b5)
% Spread
-1.5%
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-1.0%
-0.7%
-0.5%
r0.75%
r0.5
r0.35%
0.25%
Table 7. Dial-a-Skew CPU to HT66
Table 8. Dial-a-Ratio CPU to HT66
DASAG(1:0)
HT66 Skew Shift
Default
DASAG(1:0)
CPU/HT66 Ratio
00
01
10
11
00
01
10
11
Frequency selection default
-150 ps
2/1
2.5/1
3/1
+ 150ps
+ 300 ps
Rev 1.0,November 21, 2006
Page 6 of 14
CY28330
Byte 7: Watchdog Control Register
Bit
@Pup
Name
Description
7
0
Pin 12 Mode SRESET#; 1 = Pin 12 is the input pin which functions as a PD# signal. 0 = Pin 12 is the
output pin as SRESET# signal.
Select
6
0
Frequency
Reversion
This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog
time out only.
0 = selects frequency of existing H/W setting
1 = selects frequency of the second to last S/W setting. (the software setting prior to the
one that caused a system reboot).
5
4
0
0
For Test, ALWAYS program to ‘0’
WD Time-out This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system clears
the WD time stamps (WD3:0).
3
2
1
0
0
0
0
0
WD3
WD2
WD1
WD0
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
This bit allows the selection of the time stamp for the Watchdog timer. See Table 9.
Table 9. Watchdog Time Stamp
WD3
0
WD2
0
WD1
0
WD0
0
Function
Off
0
0
0
1
1 second
0
0
1
0
2 seconds
3 seconds
4 seconds
5 seconds
6 seconds
7 seconds
8 seconds
9 seconds
10 seconds
11 seconds
12 seconds
13 seconds
14 seconds
15 seconds
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Byte 8: Dial-a-Frequency™ Control Register N
Bit
@PUp
Description
7
0
ATPG Pulse. A 0 to 1 transition on this bit will trigger a differential pulse on the CPUT/C
lines whose pulse width is equal to the period of the currently latched frequency.
6
5
4
3
2
1
0
N6
N5
N4
N3
N2
N1
N0
These bits are for programming the PLL’s internal N register. This access allows the
user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks
that are generated from the same PLL, such as PCI, remain at their existing ratios relative
to the CPU clock.
Rev 1.0,November 21, 2006
Page 7 of 14
CY28330
Byte 9: Dial-a-Frequency™ Control Register M
Bit
7
@Pup
0
Description
CPU output skew; 0 = normal, 1 = -200ps Pin 41 to Pin 7
6
R5
R4
R3
R2
R1
R0
0
These bits are for programming the PLL’s internal R register. This access allows the user
to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that
are generated from the same PLL, such as PCI, remain at their existing ratios relative to
the CPU clock.
5
4
3
2
1
0
When this bit = 1, it enables the Dial-a-Frequency N and R bits to be multiplexed into the
internal N and R registers. When this bit = 0, the ROM based N and R values are loading
into the internal N and R registers.
ROM
N Register
SMBus
Latch
Byte8
Byte8 Write
R Register
SMBus
Byte9
Byte9 Write
DAFEN
Figure 1. Dial-a-Frequency Register Loading
output may not occur immediately after this time as the PLL
needs to be locked and will not output an invalid frequency.
The CPU frequencies are defined from the hardware-sampled
inputs. Additional frequencies and operating states can be
selected through the SMBus programmable interface.
Dial-a-Frequency Feature
Dial-a-Frequency gives the designer direct access to the
reference divider (M) and the feedback divider (N) of the
internal Phase Lock Loop (PLL). The algorithm is the same for
all P values, which is Fcpu = (P * N) / M with the following
conditions. M = (20..56), N = (21..127) and N > M > N/2. ‘P’ is
a large value constant that translates the output of the PLL into
the CPU frequency. The Value of ‘P’ is relative to the latest
frequency selected in the device prior to enabling the
Dial-a-Frequency feature. Furthermore, P is an indication that
the frequency ratios between the CPU, SDRAM, AGP (3V66),
and PCI clock outputs remains unchanged when the
Dial-a-Frequency feature is enabled.
Spread spectrum modulation is required for all outputs derived
from the internal CPU PLL2 (see Block Diagram). This include
the CPU(0:1), PCI33(0:5), PCI33_F and PCI33_HT66(0:2).
The REF (0:2), USB and 24_48 clocks are not affected by the
spread spectrum modulation. The spread spectrum
modulation is set for both center and down modes using linear
and Lexmark profiles for amounts of 0.5% and 1.0% at a
33KHz rate.
The CPU clock driver is of a push-pull type for the differential
outputs, instead of the AMD Athlon¥ open-drain style. The
CPU clock termination has been derived such that a 15-40
ohm, 3.3V output driver can be used for the CPU clock.
Table 10.
FS(3:0)
P
XXXX
95995000
The PCISTOP# signal provides for synchronous control over
the any output, except the PCI33_F, that is running at 33MHz.
If the PCI33_HT66 outputs are configured to run at 66MHz will
not be stopped by this signal. The PCISTOP# signal is
sampled by an internal PCI clock such that once it is sensed
low or active, the 33MHz signals are stopped on the next high
to low transition such that there is always a valid high signal.
Operation
Pin strapping on any configuration pin is based on a 10K ohm
resistor connected to either 3.3V (VDD) or ground (VSS).
When the VDD supply goes above 2.0V, the Power-On-Reset
circuitry latches all of the configuration bits into their respective
registers and then allows the outputs to be enabled. The
Rev 1.0,November 21, 2006
Page 8 of 14
CY28330
Absolute Maximum Rating
Parameter
Description
Supply voltage
Input voltage
Rating
–0.5 to 3.8
–0.5 to 3.8
–65 to +150
> 2,000
Unit
V
VDD, VDDA, VDDF
VIN1, VIN2
V
TSTG
Storage temperature
Input ESD (HBN)
°C
V
ESDprotection
Operating Condition[2]
Parameter
VDD, VDDA, VDDF
TA
Description
Min.
3.135
0
Typ.
Max.
Unit
V
Supply voltage
3.3
3.465
70
Operating temperature, Ambient
Input frequency (crystal or reference)
qC
Finput
10
14.318
16
MHz
SCLK and SDATA Input Electrical Characteristics (5V tolerant)
Parameter
VIL
Description
Supply voltage
Conditions
Min.
VSS-0.3
2.0
Typ.
Max.
0.8
Unit
V
VIH
Input voltage
VDD+0.3
µ5
V
IIL, IIH
VOL
IOL
Input high/low current
Output high voltage
Output low voltage
0<VIN<VDD
µA
V
IOL=1.75mA
VO=0.8V
VSS-0.3
2
0.4
6
mA
DC Parameters (All outputs loaded)
Parameter Description
VIL Input Low Voltage
Input High Voltage
Conditions
See Note 3
Min.
VSS-0.3
2.0
Typ.
Max.
0.8
Unit
V
VIH
IIL
VDD+0.3
-50
V
Input Low Current (@VIL = VSS) For internal Pull up resistors,
See Note 4
µA
IIH
Input High Current (@VIH =VDD)
Three-State leakage Current
50
10
µA
µA
mA
mA
pF
pF
nH
pF
V
Ioz
Idd3.3V
Ipd3.3V
Cin
Dynamic Supply Current
Power Down Supply Current
Input pin capacitance
Output pin capacitance
Pin inductance
CPU(0:1) @ 200MHz
250
2
5
6
Cout
Lpin
7
Cxtal
VBIAS
Txs
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
Measured from Pin to Ground.
From Stable 3.3V power supply.
27
36
45
0.3Vdd
Vdd/2
0.7Vdd
40
µs
Notes:
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Applicable to input signals: SPREAD, PCISTOP#, 24–48/Sel#.
4. Internal Pull-up and Pull-down resistors have a typical value of 250:ꢁ
Rev 1.0,November 21, 2006
Page 9 of 14
CY28330
AC Parameter
PCI133_HT66 = 66MHz
Parameter
Description
Test Condition
Min.
Typ. Max. Unit
TR
Output Rise Edge Rate
Output Fall Edge Rate
Differential Voltage
Measured @ the Hammer test load using
VOCM 400mV, 0.850V to 1.650V
2
7
V/ns
V/ns
V
TF
Measured @ the Hammer test load using
VOCM 400mV, 1.650V to 0.850V
2
7
VDIFF
DVDIFF
VCM
'VCM
Measured @ the Hammer test load (single
ended)
0.4
1.25
1.25
2.3
150
1.45
200
Change in VDIFF_DC Magnitude Measured @ the Hammer test load (single
ended)
-150
1.05
-200
mV
V
Common Mode Voltage
Measured @ the Hammer test load (single
ended)
Change in VCM
Measured @ the Hammer test load (single
ended)
mV
TD
Duty Cycle
Measured at VOX
Measured at VOX
Measured at VOX
45
0
50
53
%
ps
ps
dB
TJC
Jitter, Cycle to Cycle
Jitter, Accumulated
100
200
TJA
-1000
TBD
1000
TBD
TJSC_OP
Spectral Content Noise near
Hammer frequency
TJSC_DC
Spectral Content Noise from
0-200MHz
Noise floor measured with Spread Spectrum TBD
on between 0 MHz and 200 MHz. Measured
with a 3.3V PECL differential buffer in line
with CPU clock output
TBD
dB
TFS
Frequency Stabilization from
Power-up
Measure from full supply voltage
0
3
ms
W
RON
Output Impedance
Average value during switching transition.
15
35
55
Table 11.PCI/Hyper Transport Clock Outputs
PCI33, PCI33_HT = 33 MHz PCI33_HT = 66 MHz
Parameter
VOL
VOH
IOL
Description
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Frequency Actual
Conditions
IOL = 9.0mA
Min.
-
Typ.
Max.
Min.
Typ. Max. Unit
0.4
0.4
-
V
V
IOH =-12.0mA
VO = 0.8V
2.4
10
2.4
10
-
mA
mA
MHz
V/ns
V/ns
%
IOH
F
VO = 2.0V
-15
-15
33.33
66.67
TR
Output Rise Edge Rate Measured from 20% to 60%
Output Fall Edge Rate Measured from 60% to 20%
1
1
4
4
1
1
4
4
TF
TD
Duty Cycle
Measured at 1.5V
Measured at 1.5V
Measured at 1.5V
45
0
55
45
55
TJC
TJA
TFS
Jitter, Cycle-to-Cycle
Jitter Accumulated
250
1000
3
0
250
1000
3
ps
-1000
0
-1000
ps
Frequency Stabilization Measure from full supply
voltage
ms
from Power-up
RON
Output Impedance
Average value during
switching transition.
12
15
55
12
15
55
W
Rev 1.0,November 21, 2006
Page 10 of 14
CY28330
Table 12.REF(0:2) Clock Outputs
PCI133_HT66 = 66 MHz
Parameter
VOL
VOH
IOL
Description
Test Condition
IOL = 9.0 mA
Min.
Typ.
Max.
Unit
V
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.4
IOH = -12.0 mA
VO = 0.8V
2.4
16
V
mA
mA
MHz
V/ns
V/ns
%
IOH
F
VO = 2.0V
-22
14.318
TR
Measured from 20% to 60%
Measured from 60% to 20%
Measured at 1.5V
0.5
0.5
45
2
2
TF
TD
55
TJC
TJA
TFS
RON
Jitter, Cycle-to-Cycle
Jitter, Accumulated
Measured at 1.5V
0
500
24
1000
1000
3
ps
Measured at 1.5V
-1000
0
ps
Frequency Stabilization from Power-up Measure from full supply voltage
mS
W
Output Impedance
Average value during switching transition.
20
60
Table 13.USB, 24_24 Clock Outputs
PCI33, PCI33_HT =
33MHz
PCI33_HT = 66MHz
Parameter
Description
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Frequency Actual
Conditions
IOL = 9.0mA
Min.
Typ.
Max.
Min.
Typ.
Max. Unit
VOL
VOH
IOL
IOH
F
0.4
0.4
V
IOH =-12.0mA
VO = 0.8V
2.4
16
2.4
16
V
mA
mA
MHz
V/ns
VO = 2.0V
-22
-22
24.004
48.008
TR
Output Rise Edge Rate
Measured from 20% to
80%
0.5
0.5
2
2
0.5
0.5
2
2
TF
Output Fall Edge Rate
Measured from 80% to
20%
V/ns
TD
Duty Cycle
Measured at 1.5V
45
0
55
45
0
55
%
TJC
Jitter, Cycle-to-Cycle 24_48 Measured at 1.5V
MHz
250
500
250
500
ps
TJC
TJA
TFS
Jitter, Cycle-to-Cycle USB
Jitter Accumulated
Measured at 1.5V
Measured at 1.5V
0
100
1000
3
ps
ps
-1000
0
1000 -1000
Frequency Stabilization from Measurefromfullsupply
voltage
3
0
ms
Power-up
RON
Output Impedance
Average value during
switching transition.
20
24
60
20
24
60
W
[5]
Table 14.Skew
Parameter
Description
Conditions
Skew Window Unit
TSK_CPU_CPU
CPU to CPU skew, time Measured @ crossing points for CPUT rising edges1
independent
250
500
500
ps
ps
ps
TSK_CPU_PCI33 CPU to PCI33 skew, time Measured @ crossing points for CPUT rising edge and
1.5V PCI clocks
independent
TSK_PCI33_PCI33 PCI33 to PCI33 skew,
time independent
Measured between rising @ 1.5V
Note:
5. All skews in this skew budget are measured from the first referenced signal to the next. Therefore, this skew specifies the maximum SKEW WINDOW between
these two signals to be 500ps whether the CPU crossing leads or lags the PCI clock. This should NOT be interpreted to mean that the PCI33 edge could either
be 500ps before the CPU clock to 500ps after the clock, thus defining a 1000ps window in which the PCI33 clock edge could fall.
Rev 1.0,November 21, 2006
Page 11 of 14
CY28330
Table 14.Skew (continued)[5]
Parameter Description
Conditions
Skew Window Unit
TSK_PCI33_HT66 PCI33 to HT66 skew, time Measured between rising @ 1.5V
independent
500
500
500
200
200
200
200
200
200
ps
ps
ps
ps
ps
ps
ps
ps
ps
TSK_CPU_HT66 CPU to HT66 skew, time Measured @ crossing points for CPUT rising edge and
1.5V for HyperTransport clocks
independent
TSK_HT66_HT66 HT66 to HT66 skew, time Measured between rising @ 1.5V
independent
TSK_CPU_CPU CPU to CPU skew, time Measured @ crossing points for CPUT rising edges
variant
TSK_CPU_PCI33 CPU to PCI33 skew, time Measured @ crossing points for CPUT rising edge and
1.5V PCI clocks
variant
TSK_PCI33_PCI33 PCI33 to PCI33 skew,
time variant
Measured between rising @ 1.5V
TSK_PCI33_HT66 PCI33 to HT66 skew, time Measured between rising @ 1.5V
variant
TSK_CPU_HT66 CPU to HT66 skew, time Measured @ crossing points for CPUT rising edge and
1.5V for HyperTransport clocks
variant
TSK_HT66_HT66 HT66 to HT66 skew, time Measured between rising @ 1.5V
variant
Table 15.Loading Table
Clock Name
Max Load (in pF)[6]
CPU(0:1)
See Figure 2
USB 24_48, REF (0:2)
20
30
PC133(0:5), PC133_F, PCI33_HT66(0:2)
Vbias=1.25V
125 ohms
125 ohms
15 ohms
15 ohms
3900pF
3900pF
169 ohms
5pF
5pF
Figure 2. Test Load Configuration
Note:
6. The above loads are positioned near each output pin when tested.
Rev 1.0,November 21, 2006
Page 12 of 14
CY28330
SRESET#/PD#
CPUT(0:1)
CPUC(0:1)
PCI/PCI_HT
USB,24_48MHz
REF(0:2)
Figure 3. PD# Assertion Waveform
PD#
CPUT
CPUC
PCI 33MHz
3V66
USB 48MHz
REF 14.318MHz
Figure 4. PD# Deassertion Waveform
Rev 1.0,November 21, 2006
Page 13 of 14
CY28330
Ordering Information
Part Number
CY28330OC
CY28330OCT
Package Type
48-pin SSOP
48-pin SSOP–Tape and Reel
Product Flow
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Package Drawing and Dimensions
48-pin Shrunk Small Outline Package O48
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 21, 2006
Page 14 of 14
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