CY28331-2OC [CYPRESS]
Processor Specific Clock Generator, 300MHz, CMOS, PDSO48, SSOP-48;
| 型号： | CY28331-2OC |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 300MHz, CMOS, PDSO48, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总17页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY28331-2
Clock Generator for AMD™ Hammer
Features
Table 1. Frequency Table (MHz)
• Supports AMD Hammer CPU
FS
PCI_HT
SEL
• Two differential pair of CPU clocks
• Eight low-skew/-jitter PCI clocks
• One free-running PCI clock
(3:0)
CPU
HT66
PCI
0000
X
Hi-Z (All outputs except XOUT are
three-stated)
• Four low-skew/-jitter PCI/HyperTransport clocks
• One 48M output for USB
• One programmable 24M or 48M for FDC
• Three REF 14.318-MHz clocks
• Dial-a-Frequency programmability
0001
0010
0011
0100
0101
0110
0/1
0/1
0/1
0/1
0/1
0/1
133.9
166.9
200.9
100.0
133.3
166.7
67.0/33.5
66.8/33.4
67.0/33.5
66.7/33.3
66.7/33.3
66.7/33.3
33.5
33.4
33.5
33.3
33.3
33.3
• Lexmark Spread Spectrum for optimal electromag-
netic interference (EMI) reduction
• SMBus register programmable options
• 5V-tolerance SCLK and SDATA lines
• 3.3V operation
• Power management control pins
• 48-pin SSOP package
0111
(default)
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
200.0
105.0
110.0
210.0
240.0
270.0
233.3
266.7
300.0
66.7/33.3
70.0/35.0
73.3/36.7
70.0/35.0
60.0/30.0
67.5/33.8
58.3/29.2
66.7/33.3
75.0/37.5
33.3
35.0
36.7
35.0
30.0
33.8
29.2
33.3
37.5
1000
1001
1010
1011
1100
1101
1110
1111
HCLK, 66 MHz and 33 MHz are in phase and synchronous
upon power-up.
Block Diagram
Pin Configuration
XIN
14.31818MHz
REF(0:2)
USB
XTAL
XOUT
*FS0/REF0
1
2
3
4
5
6
7
8
9
48 *FS1/REF1
47 VSS
46 VDD
45 *FS2/REF2
44 SRESET#PD#
43 VDDA
42 VSSA
41 CPUT0
40 CPUC0
39 VSS
VDD
XIN
XOUT
VSS
/4
PLL1
PCI33_HT66_0/*PCI33HT66SEL0#
PCI33_HT66_1/*PCI33HT66SEL1#
PCI33_HT66_2
24_48MHz
/2
VDD
SEL#
VSS 10
PCI33_HT66_3 11
PCI33_7 12
38 VDD
37 CPUT1
36 CPUC1
35 VDD
SRESET#
PCI33_0 13
PCI33_1 14
VSS 15
VDD 16
PCI33_2 17
PCI33_3 18
VDD 19
VSS 20
PCI33_4 21
34 VSS
33 VSSF
32 VDDF
31 **USB/FS23
30 VSS
29 VDD
28 24_48MHz/**SEL#
27 VSS
26 SDATA
25 SCLK
FS(0:3)
CPUT(0:1)
CPUC(0:1)
PLL2
PCISTOP#
SPREAD
Control
PCI33_F
/N
Logic
PD#
*PCISel/PCI33_5 22
PCI33_F 23
*PCI33_6/PCISTOP# 24
SCLK
STOP
PCI33_(0:7)
PCI33_HT66_(0:3)
SDATA
* 100K Internal Pull-up
** 100K Internal Pull-down
CNTL
Cypress Semiconductor Corporation
Document #: 38-07545 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised May 19, 2003
CY28331-2
Pin Description
Pin
Name
PWR
VDD
VDD
I/O
I
Description
3
4
XIN
Oscillator Buffer Input. Connect to a crystal or to an external clock.
XOUT
O
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
41, 37
40, 36
CPUT(0:1)
CPUC(0:1)
VDDC
VDDC
O
O
CPU clock outputs 0 and 1: push-pull “true” output of differential pair.
CPU clock outputs 0 and 1: push-pull “compliment” output of differential
pair.
13, 14, 17,
18, 21
PCI33(0:5)
O
3.3V PCI clock outputs controlled by PCISTOP#.
22
PCISEL/PCI_5
I/O PCISEL is a strap option during power-up to select Pin 24 functionality:
0: Configure Pin 24 as PCI33_6
1: Configure Pin 24 as PCISTOP# (default 100k internal pull-up)
After power-up, this pin reverts to standard PCI33_5 output.
23
PCISEL /
PCI33_F
I/O Free-running 3.3V PCI clock output.
8, 11
PCI33_HT66(2:3)
VDDD
O
3.3V PCI 33 MHz or HyperTransport 66 clock outputs. This group is
selectable between 33MHz and 66MHz based upon the state of
PCI33HT66SEL[0:1]#.
6, 7
PCI33_HT66_[0:1]/
VDDD
I/O PCI33 or HT66 Select.
PCI33_HT66SEL[0:1]#
This input strap selects the output frequency of PCI33_HT66 outputs to
either 33 MHz or 66 MHz. There is an internal 100Kohm pull-up resistor.
After power-up, this pin becomes PCI33_HT66_[0:1] output.
SEL1 SEL0
PIN6
PIN7
PIN8
PIN11
0
0
1
1
0
1
0
1
HT66_0 HT66_1 HT66_2 HT66_3
HT66_0 HT66_1 HT66_2 PCI33_3
HT66_0 HT66_1 PCI33_2PCI33_3
HT66_0 PCI33_1 PCI33_2PCI33_3
31
28
USB/FS3
I/O 3.3V USB clock output at 48 MHz. At power-up this pin is sensed to
determine the CPU output frequency. There is an internal 100-Kohm
pull-down resistor.
24_48MHz/SEL#
I/O 3.3V Super I/O clock output. At power-up this pin is sensed to determine
whether the output is 24 MHz or 48 MHz. There is an internal 100-Kohm
pull-down resistor. This pin will be externally strapped high using a 10-Kohm
resistor to VSS. 0 = 48 MHz, 1 = 24 MHz.
1, 48, 45
REF(0:2)/FS(0:2)
SRESET#/PD#
I/O 3.3V Reference clock output. At power-up this pin is sensed to determine
the CPU output frequency. There is an internal 100K ohm pull-up resistor
for FS0, while FS(1:2) includes 100K ohm pull-up resistors.
44
24
I/O Watchdog Time-out Reset Output. Power-down input (100k internal
pull-up).
PCI33_6/
PCISTOP#
I/O When configured through Pin 23 as PCI_STOP#, this pin controls the
PCI33(0:5,7) and PCI33_HT66(1:3) outputs. Active LOW control input to
halt all 33MHz PCI clocks except PCI33_F. Only the PCI33_HT66 outputs
that are running at 33MHz will be stopped. The outputs will be glitch-free
when turning off and turning on (100k internal pull-up).
When configured through Pin 23 as PCI33_6, PCI_STOP# is unavailable.
12
26
PCI33_7
SDATA
O
3.3V PCI clock outputs controlled by PCISTOP#.
I/O Data pin for SMBus (rev 2.0). There is an internal 100 Kohm pull-up
resistor.
25
SCLK
VDD
I
Clock pin for SMBus (rev 2.0). There is an internal 100 Kohm pull-up
resistor.
2, 9, 16,
19, 29, 35,
38, 46
PWR Power connection to 3.3V for the core.
Document #: 38-07545 Rev. **
Page 2 of 17
CY28331-2
Pin Description (continued)
Pin
Name
PWR
I/O
Description
5, 10, 15,
20, 27, 30,
34, 39, 47
VSS
GND Power connection to GROUND for the CORE section of the chip.
43
42
32
VDDA
VSSA
VDDF
PWR Power connection to 3.3V for the ANALOG section of the chip.
GND Power connection to GROUND for the ANALOG section of the chip.
PWR Power connection to 3.3V for the 48-MHz phase-locked loop (PLL)
section of the chip.
33
VSSF
GND Power connection to GROUND for the 48-MHz PLL section of the chip.
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte
read or byte write operation
Data Protocol
(6:0)
Byte offset for byte read or byte write operation.
For block read or block write operations, these bits
should be ‘0000000’
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
Start
1
2:8
9
Start
2:8
9
Slave address – 7 bits
Write = 0
Slave address – 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
19
20:27
28
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
......................
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read = 1
29:36
37
29
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
38:45
46
30:37
38
....
39:46
47
Data byte from slave – 8 bits
Acknowledge
....
Data Byte (N–1) –8 bits
Acknowledge from slave
Data Byte N –8 bits
Acknowledge from slave
Stop
....
48:55
56
Data byte from slave – 8 bits
Acknowledge
....
....
....
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledged
Stop
....
....
....
....
Document #: 38-07545 Rev. **
Page 3 of 17
CY28331-2
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bits
Write = 0
2:8
9
Slave address – 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
Command Code – 8 bits
11:18
Command Code – 8 bits
11:18
‘1xxxxxxx’ stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
‘1xxxxxxx’ stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
19
20:27
28
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read = 1
29
29
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
30:37
38
39
Serial Control Registers
Byte 0: Frequency and Spread Spectrum Control Register
Bit
@Pup
Pin#
Name
Description
Write Disable (write once).
A 1 written to this bit after a 1 has been written to Byte0 bit0 will permanently
disable modification of all configuration registers until the part has been
powered off. Once the clock generator has been Write Disabled, the SMBus
controller should still accept and acknowledge subsequent write cycles but
it should not modify any of the registers.
7
Inactive = 0
6
5
4
3
2
1
0
For Test, ALWAYS program to ‘0’
1
12
31
45
48
1
PCI33_7
enable (1 = Enabled, 0 = Disabled)
FS3 pin
FS2 pin
FS1 pin
FS0 pin
FS3
FS2
FS1
FS0
corresponds to Frequency Selection. See Table 1.
corresponds to Frequency Selection. See Table 1.
corresponds to Frequency Selection. See Table 1.
corresponds to Frequency Selection. See Table 1.
Write Enable. A 1 written to this bit after power-up will enable modification
of all configuration registers and subsequent 0's written to this bit will disable
modification of all configuration except this single bit. Note that block write
transactions to the interface will complete, however unless the interface has
been previously unlocked, the writes will have no effect. The effect of writing
this bit does not take effect until the subsequent block write command.
0
Inactive = 0
Byte 1: PCI Clock Control Register
Bit
7
@Pup
Pin#
23
Name
Description
enable (1 = Enabled, 0 = Disabled)
enable (1 = Enabled, 0 = Disabled)
enable (1 = Enabled, 0 = Disabled)
enable (1 = Enabled, 0 = Disabled)
enable (1 = Enabled, 0 = Disabled)
enable (1 = Enabled, 0 = Disabled)
1
1
1
1
1
1
PCI33_F
PCI33_6
PCI33_5
PCI33_4
PCI33_3
PCI33_2
6
24
5
22
4
21
3
18
2
17
Document #: 38-07545 Rev. **
Page 4 of 17
CY28331-2
Byte 1: PCI Clock Control Register(continued)
Bit
1
@Pup
Pin#
14
Name
Description
enable (1 = Enabled, 0 = Disabled)
enable (1 = Enabled, 0 = Disabled)
1
1
PCI33_1
PCI33_0
0
13
Byte 2: USB, 24–48MHz, REF(0:2) Control Register
Bit
@Pup
Pin #
Name
Description
CPUT/C(1) CPUT/C(1) shutdown. This bit can be optionally used to disable the
CPUT/C(1) clock pair. During shutdown, CPUT = low and CPUC = high
7
active = 1
37, 36
CPUT/C(0) CPUT/C(0) shutdown. This bit can be optionally used to disable the
CPUT/C(0) clock pair. During shutdown, CPUT = low and CPUC = high
6
active = 1
41, 40
5
4
3
2
1
0
active = 1
active = 1
active = 1
active = 1
active = 1
0
45
48
1
REF2
REF1
REF0
enable (1 = Enabled, 0 = Disabled)
enable (1 = Enabled, 0 = Disabled)
enable (1 = Enabled, 0 = Disabled)
28
31
24_48MHz enable (1 = Enabled, 0 = Disabled)
USB
enable (1 = Enabled, 0 = Disabled)
For Test, ALWAYS program to ‘0’
Byte 3: PCI Clock Free-running Select Control Register
Bit
@Pup
Pin #
Name
Description
PCI_DRV
0 = Low Strength
1 = High Strength
7
Inactive = 0
PCI33_HT66 Drive Strength
0 = Low Strength
6
Inactive = 0
1 = High Strength
5
4
3
2
1
0
Inactive = 0
22
21
18
11
8
PCI5
PCI4
PCI3
free-running enable (10 = Free-running, 0 = Disabled)
free-running enable (1 = Free-running, 0 = Disabled)
free-running enable (1 = Free-running, 0 = Disabled)
Inactive = 0
Inactive = 0
1
1
1
PCI33_HT66_3 enable (1 = Enabled, 0 = Disabled)
PCI33_HT66_2 enable (1 = Enabled, 0 = Disabled)
PCI33_HT66_1 enable (1 = Enabled, 0 = Disabled)
7
Byte 4: Pin Latched/Real Time State
Bit
7
@Pup
Pin#
Name
Description
enable (1 = Enabled, 0 = Disabled)
1
HW
0
6
PCI33_HT66_0
6
24_48MHz/SEL# pin power-up latched state
5
Reserved
SSEN
for Test, ALWAYS program to ‘0’
Spread Spectrum enable (0 = disable, 1 = enable).
This bit provides a SW programmable control for spread spectrum
clocking.
4
1
3
2
1
0
FS3 pin
FS2 pin
FS1 pin
FS0 pin
31
45
48
1
FS3
FS2
FS1
FS0
power-up latched state
power-up latched state
power-up latched state
power-up latched state
Document #: 38-07545 Rev. **
Page 5 of 17
CY28331-2
Byte 5: SSCG, Dial-a-Skew™ and Dial-a-Ratio™ Register
Bit
7
@Pup
Description
0
1
1
Spread Spectrum Selection:
bit7
bit6
bit5
% Spread
6
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
–1.5
–1.0
5
–0.7
–0.5 (default)
±0.75
±0.50
±0.35
±0.25
4
3
2
1
0
0
0
0
0
0
HT66 Frequency Fractional Aligner: These bits determine the HT66 fixed frequency when the
HT66 Output Frequency Selection bit is set. It does not incorporate spread spectrum.
Fract_Align PCI_HT
PCI
(MHz)
Off
bit[4:0]
(MHz)
Off
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
(default)
66.5
67.5
68.5
69.5
70.6
71.6
72.6
73.6
74.7
75.7
76.7
77.7
78.7
79.8
80.8
81.8
82.8
83.9
84.9
85.9
86.9
88.0
89.0
90.0
91.0
92.0
93.1
94.1
95.1
96.1
97.2
33.2
33.7
34.3
34.8
35.3
35.8
36.3
36.8
37.3
37.8
38.4
38.9
39.4
39.9
40.4
40.9
41.4
41.9
42.4
43.0
43.5
44.0
44.5
45.0
45.5
46.0
46.5
47.0
47.6
48.1
48.6
Byte 6: Watchdog Control Register
Bit
@Pup
Name
Description
7
0
HT66 Output Frequency
Selection
HT66 Output Frequency Selection:
0: Set according to Frequency Selection Table
1: Set according to Fractional Aligner Table
6
5
0
0
Pin 44 Mode Select
Frequency Reversion
Pin 44 Mode Select:
0 = Pin 12 is the output pin as SRESET# signal.
1 = Pin 12 is the input pin which functions as a PD# signal.
Frequency Reversion:
This bit allows setting the Revert Frequency once the system is
rebooted due to Watchdog time out only.
0 = selects frequency of existing H/W setting
1 = selects frequency of the second to last S/W setting. (the
software setting prior to the one that caused a system reboot).
4
0
WD Time-out
WD Time-out:
This bit is set to “1” when the Watchdog times out. It is reset to “0”
when the system clears the WD time stamps (WD3:0).
Document #: 38-07545 Rev. **
Page 6 of 17
CY28331-2
Byte 6: Watchdog Control Register (continued)
Bit
3
@Pup
Name
Description
0
0
0
0
WD3
WD2
WD1
WD0
This bit allows the selection of the time stamp for the Watchdog
timer. After a Watchdog time-out, the frequency will revert to the
original frequency.
2
1
WD3 ..
.. WD0
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Off (default)
1 second
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2 seconds
3 seconds
4 seconds
5 seconds
6 seconds
7 seconds
8 seconds
9 seconds
10 seconds
11 seconds
12 seconds
13 seconds
14 seconds
15 seconds
Byte 7: Clock Vendor ID
Bit
7
@Pup
Description
0
1
0
1
1
0
0
0
Revision ID[1]
Revision ID[0]
Device ID[9]
Device ID[8]
Vendor ID[3]
Vendor ID[2]
Vendor ID[1]
Vendor ID[0]
6
5
4
3
2
1
0
Byte 8: Device ID
Bit
7
@Pup
Description
0
1
0
0
1
0
1
1
Device ID
Device ID
Device ID
Device ID
Device ID
Device ID
Device ID
Device ID
6
5
4
3
2
1
0
Byte 9: Dial-a-Frequency Control Register N
Bit
7
@PUp
0
Description
ATPG Pulse
6
N6
N5
N4
N3
N2
N1
N0
These bits are for programming the PLL’s internal N register. This access allows the user to
modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are
generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU
clock.
5
4
3
2
1
0
Document #: 38-07545 Rev. **
Page 7 of 17
CY28331-2
Byte 10: Dial-a-Frequency Control Register M
Bit
7
@Pup
0
Description
ATPG Mode (default = 0)
6
M5
M4
M3
M2
M1
M0
These bits are for programming the PLL’s internal M register. This access allows the user to
modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are
generated from the same PLL such as PCI) remain at their existing ratios relative to the CPU
clock.
5
4
3
2
1
When this bit = 1, it enables the Dial-a-Frequency N and M bits to be multiplexed into the
internal N and M registers. When this bit = 0, the ROM based N and M values are loading into
the internal N and M registers.
0
DAFEN
Byte 11:
Bit
@Pup
Pin #
Name
Description
For Test, ALWAYS program to ‘0’
PCI33/HT66 Mode Select 1
7
0
HW
7
6
5
PCI33HT66SEL1# Power-up Latched State of PCI33HT66SEL1# Mode Select 1.
(read only)
PCI33/HT66 Mode Select 0
PCI33HT66SEL0# Power-up Latched State of PCI33HT66SEL0# Mode Select 0.
(read only)
HW
6
4
3
2
1
0
0
0
0
0
0
Reserved Set = 0
Reserved Set = 0
Reserved Set = 0
Reserved Set = 0
Reserved Set = 0
Meanwhile, the system BIOS is running its operation with the
System Self-Recovery Clock Management
new frequency. If this device receives a new SMBus command
to clear the bits originally programmed in Watchdog Timer bits
(reprogram to 0000) before the Watchdog times out, then this
device will keep operating in its normal condition with the new
selected frequency.
This feature is designed to allow the system designer to
change frequency while the system is running, and reboot the
operation of the system in case of a hang up due to the
frequency change.
When the system sends an SMBus command requesting a
frequency change through the Dial-a-Frequency Control
Registers, it must have previously sent a command to the
Watchdog Timer to select which time out stamp the Watchdog
must perform, otherwise the System Self-Recovery feature will
not be applicable. Consequently, this device will change
frequency and then the Watchdog timer starts timing.
The Watchdog timer will also be triggered if you program the
software frequency select bits (FSEL) to a new frequency
selection. If the Watchdog times out before the new SMBus
reprograms the Watchdog Timer bits to (0000), then this
device will send a low system reset pulse, on SRESET#, and
changes WD Time-out bit to “1.”
Document #: 38-07545 Rev. **
Page 8 of 17
CY28331-2
RESET W ATCHDOG TIMER
Set WD(0:3) Bits = 0
INITIALIZE W ATCHDOG TIMER
Set Frequency Revert Bit
Set WD(0:3) = (# of Sec ) x2
SET SOFTW ARE FSEL
Set SW Freq_Sel = 1
Set FS(0:4)
SET DIAL-A-FREQUENCY
Load M and N Registers
Set Pro_Freq_EN = 1
Wait for 6msec For
ClockOutput to Ramp to
Target Frequency
N
CLEAR W D
Set WD(0:3) Bits = 0
Hang?
Exit
Y
W ATCHDOG TIMEOUT
FrequencyRevert Bit =
FrequencyRevert Bit =
0
1
Set Frequency to
FS_HW_Latched
Set Frequency to FS_SW
Set SRESET# = 0 for 6 msec
Reset
Figure 1. Watchdog Self-Recovery Sequence Flowchart
Document #: 38-07545 Rev. **
Page 9 of 17
CY28331-2
Dial-a-Frequency
ROM
M Register
SMBus
Control
Latch
Register N
Control Register N White
N Register
SMBus
Control
Register M
Control Register M White
DAFEN
Figure 2. Dial-a-Frequency Feature
The SMBus controlled Dial-a-Frequency feature is available in
Operation
this device via Dial-a-Frequency Control Register N and
Dial-a-Frequency Control Register M. P is a PLL constant that
depends on the frequency selection prior to accessing the
Dial-a-Frequency feature.
Pin strapping on any configuration pin is based on a 10-Kohm
resistor connected to either 3.3V (VDD) or ground (VSS).
When the VDD supply goes above 2.0V, the Power-on-Reset
circuitry latches all of the configuration bits into their respective
registers and then allows the outputs to be enabled. The
output may not occur immediately after this time as the PLL
needs to be locked and will not output an invalid frequency.
The CPU frequencies are defined from the hardware-sampled
inputs. Additional frequencies and operating states can be
selected through the SMBus programmable interface.
Table 5. Dial-A-Frequency Constants
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
P
127994667
191992000
191992000
95996000
Spread spectrum modulation is required for all outputs derived
from the internal CPU PLL2. This include the CPU(0:1),
PCI33(0:6), PCI33_F and PCI33_HT66(0:3). The REF (0:2),
USB and 24_48 clocks are not affected by the spread
spectrum modulation. The spread spectrum modulation is set
for both center and down modes using a Lexmark profiles for
amounts of 0.5% and 1.0% at a 33KHz rate.
127994667
191992000
191992000
95966000
The CPU clock driver is of a push-pull type for the differential
outputs, instead of the AMD Athlon open-drain style. The
CPU clock termination has been derived such that a
15–40-ohm 3.3V output driver can be used for the CPU clock.
95966000
191992000
191992000
191992000
191992000
191992000
191992000
The PCISTOP# signal provides for synchronous control over
the any output, except the PCI33_F, that is running at 33 MHz.
If the PCI33_HT66 outputs are configured to run at 66 MHz will
not be stopped by this signal. The PCISTOP# signal is
sampled by an internal PCI clock such that once it is sensed
low or active, the 33-MHz signals are stopped on the next high
to low transition and remains low.
The algorithm is the same for all P values, which is Fcpu =
(P*N)/M with the following conditions. M = (20..58), N =
(21..125) and N > M > N/2.
Document #: 38-07545 Rev. **
Page 10 of 17
CY28331-2
Absolute Maximum Conditions
Parameter
Description
Conditions
Non-functional
Min.
–0.5
–0.5
–65
Max
Unit
V
V
DD, VDDA, VDDF Supply voltage
5.0
VDD + 0.5
+150
VIN
TS
Input voltage
Functional
V
Storage temperature
Temperature, Junction
Dissipation, Junction to Case
Non-functional
Functional
°C
TJ
+150
°C
ØJC
Mil-Spec 883E Method
1012.1
45
°C/W
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
15
10
°C/W
V
ESDh
ESD Protection (Human Body Model) MIL-STD-883, Method
3015
>2,000
Ul-94
MSL
Flammability Rating
V-0 @1/8 in.
ppm
Moisture Sensitivity Level
1
Operating Condition
Parameter
Description
Min.
Typ.
Max.
3.465
70
Unit
V
VDD, VDDA, VDDF Supply voltage
3.135
0
3.3
TA
Operating temperature, Ambient
°C
FXIN
Input frequency (crystal or reference)
10
14.318
16
MHz
SCLK and SDATA Input Electrical Characteristics (5V-tolerant)
Parameter
Description
Input Low Voltage
Conditions
Min.
VSS – 0.3
2.0
Typ.
Max.
Unit
V
VIL
VIH
0.8
Input High Voltage
Input High/Low Current
Output High Voltage
Output Low Current
VDD + 0.3
V
IIL, IIH
VOL
IOL
0 < VIN < VDD
±5
0.4
6
µA
V
IOL = 1.75 mA
VO = 0.8V
VSS – 0.3
2
mA
DC Electrical Specifications (all outputs loaded)
Parameter
VIL
Description
Input Low Voltage
Conditions
Min.
VSS – 0.3
2.0
Typ.
Max.
Unit
V
0.8
VIH
Input High Voltage
VDD + 0.3
V
IIL
Input Low Current
@VIL = VSS, except PU and PD
@VIH =VDD, except PU and PD
-5
5
µA
µA
µA
mA
mA
pF
pF
nH
pF
V
IIH
Input High Current
IOZ
Three-state Leakage Current
Dynamic Supply Current
Power-down Supply Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
10
IDD3.3V
IPD3.3V
CIN
CPU(0:1) @ 200MHz
Except XIN and XOUT
250
2
5
COUT
LPIN
6
7
CXTAL
VBIAS
Crystal Pin Capacitance
Crystal DC Bias Voltage
Measured from Pin to Ground.
27
36
45
0.3VDD
VDD/2
0.7VDD
Document #: 38-07545 Rev. **
Page 11 of 17
CY28331-2
AC Electrical Specifications
PCI133_HT66 = 66MHz
Parameter
Hammer CPU
TR
Description
Test Condition
Min.
Typ.
Max. Unit
Output Rise Edge Rate
Output Fall Edge Rate
Differential Voltage
Measured @ the Hammer test load using
VOCM±400mV, 0.850V to 1.650V
2
7
V/ns
V/ns
V
TF
Measured @ the Hammer test load using
VOCM ±400mV, 1.650V to 0.850V
2
7
VDIFF
Measured @ the Hammer test load
(single-ended)
0.4
1.25
1.25
2.3
150
1.45
200
∆
Change in VDIFF_DC
Magnitude
Measured @ the Hammer test load
(single-ended)
DIFF
–150
1.05
–200
mV
V
VCM
Common Mode Voltage
Measured @ the Hammer test load
(single-ended)
∆VCM
Change in VCM
Measured @ the Hammer test load
(single-ended)
mV
TDC
Duty Cycle
Measured at Vox
Measured at Vox
Measured at Vox
45
0
50
53
%
ps
ps
TCYC
TACCUM
TFS
Jitter, Cycle to Cycle
Jitter, Accumulated
100
200
–1000
1000
Frequency Stabilizationfrom Measure from full supply voltage
Power-up
0
3
ms
ZOUT
Output Impedance
Average value during switching transition.
15
35
55
Ω
PCI/HyperTransport Clock Outputs
VOL
VOH
IOL
IOH
F33
F66
TR
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Frequency Actual
IOL = 9.0 mA
IOH = –12.0 mA
VO = 0.8V
0.4
V
V
2.4
10
mA
mA
MHz
MHz
V/ns
V/ns
%
VO = 2.0V
–15
33.33
66.67
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Measured from 20% to 60%
Measured from 60% to 20%
Measured at 1.5V
0.9
0.9
4
4
TF
TD
45
55
TJC
TJA
Jitter, Cycle-to-Cycle
Jitter Accumulated
Measured at 1.5V
0
400
1000
ps
Measured at 1.5V
–1000
ps
REF(0:2) Clock Outputs
VOL
VOH
IOL
Output Low Voltage
IOL = 9.0 mA
IOH = –12.0 mA
VO = 0.8V
0.4
V
V
Output High Voltage
Output Low Current
Output High Current
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
2.4
16
mA
mA
MHz
V/ns
V/ns
%
IOH
VO = 2.0V
–22
FA
14.318
TR
Measured from 20% to 60%
Measured from 60% to 20%
Measured at 1.5V
0.5
0.5
2
2
TF
TDC
TCCJ
TACCUM
TFS
45
55
Jitter, Cycle-to-Cycle
Jitter, Accumulated
Measured at 1.5V
0
500
24
1000
1000
ps
Measured at 1.5V
–1000
ps
Frequency Stabilizationfrom Measure from full supply voltage
Power-up
0
3
mS
IOZ
Output Impedance
Average value during switching transition.
20
60
Ω
Document #: 38-07545 Rev. **
Page 12 of 17
CY28331-2
AC Electrical Specifications
PCI133_HT66 = 66MHz
Parameter
Description
Test Condition
Min.
Typ.
Max. Unit
USB, 24_48 Clock Outputs
VOL
VOH
IOL
Output Low Voltage
IOL = 9.0 mA
0.4
V
Output High Voltage
Output Low Current
Output High Current
Frequency Actual
IOH = –12.0 mA
VO = 0.8V
2.4
16
V
mA
mA
MHz
MHz
V/ns
V/ns
%
IOH
F24
F48
TR
VO = 2.0V
–22
24.004
48.008
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Measured from 20% to 80%
Measured from 80% to 20%
Measured at 1.5V
0.5
0.5
45
2
2
TF
TDC
TCCJ
55
Jitter, Cycle-to-Cycle 24_48 Measured at 1.5V
MHz
0
250
24
500
ps
TJC
TJA
TFS
Jitter, Cycle-to-Cycle USB
Jitter Accumulated
Measured at 1.5V
Measured at 1.5V
0
100
ps
ps
–1000
1000
Frequency Stabilizationfrom Measure from full supply voltage
Power_up
0
3
ms
ZOUT
Output Impedance
Average value during switching transition.
20
60
Ω
Table 6. Skew [1]
Parameter
Description
Conditions
Skew Window
Unit
TSK_CPU_CPU
CPU to CPU skew,
time-independent
Measured @ crossing points for CPUT rising
edges1
250
ps
TSK_CPU_PCI33 CPU to PCI33 skew, Measured @ crossing points for CPUT rising
time-independent edge and 1.5V PCI clocks
500
500
500
500
500
200
200
200
200
200
200
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
TSK_PCI33_PCI33 PCI33 to PCI33 skew, Measured between rising @ 1.5V
time-independent
TSK_PCI33_HT66 PCI33 to HT66 skew, Measured between rising @ 1.5V
time-independent
TSK_CPU_HT66 CPU to HT66 skew,
time-independent
Measured @ crossing points for CPUT rising
edge and 1.5V for HyperTransport clocks
TSK_HT66_HT66 HT66 to HT66 skew, Measured between rising @ 1.5V
time-independent
TSK_CPU_CPU
CPU to CPU skew,
time-variant
Measured @ crossing points for CPUT rising
edges
TSK_CPU_PCI33 CPU to PCI33 skew, Measured @ crossing points for CPUT rising
time-variant edge and 1.5V PCI clocks
TSK_PCI33_PCI33 PCI33 to PCI33 skew, Measured between rising @ 1.5V
time-variant
TSK_PCI33_HT66 PCI33 to HT66 skew, Measured between rising @ 1.5V
time-variant
TSK_CPU_HT66 CPU to HT66 skew,
time-variant
Measured @ crossing points for CPUT rising
edge and 1.5V for HyperTransport clocks
TSK_HT66_HT66 HT66 to HT66 skew, Measured between rising @ 1.5V
time-variant
Note:
1. All skews in this skew budget are measured from the first referenced signal to the next. Therefore, this skew specifies the maximum SKEW WINDOW between
these two signals to be 500 ps whether the CPU crossing leads or lags the PCI clock. This should NOT be interpreted to mean that the PCI33 edge could either
be 500 ps before the CPU clock to 500 ps after the clock, thus defining a 1000-ps window in which the PCI33 clock edge could fall.
Document #: 38-07545 Rev. **
Page 13 of 17
CY28331-2
Table 7.
Clock Name
Max Load (in pF)[2]
CPU, USB, 24_48MHz, REF
20
30
PCI33, PCI33_F, PCI33_HT66
Tsu
PCI_STP#
PCI_F
PCI
Figure 3. PCISTOP# Assertion Waveform
Tsu
PCI_STP#
PCI_F
PCI
Figure 4. PCISTOP# Deassertion Waveform
Vbias=1.25V
125 ohms
169 ohms
5pF
125 ohms
15 ohms
3900pF
3900pF
15 ohms
5pF
Figure 5. Test Load Configuration
Note:
2. The above loads are positioned near each output pin when tested.
Document #: 38-07545 Rev. **
Page 14 of 17
CY28331-2
SRESET#/PD#
CPUT
CPUC
PCI/PCI_HT
USB,24_48MHz
REF
Figure 6. PD# Assertion Waveform
PD#
CPUT
CPUC
PCI 33MHz
3V66
USB 48MHz
REF 14.318MHz
Figure 7. PD# Deassertion Waveform
Ordering Information
Part Number
CY28331-2OC
CY28331-2OCT
Package Type
48-pin SSOP
Product Flow
Commercial, 0° to 70°C
Commercial, 0° to 70°C
48-pin SSOP – Tape and Reel
Document #: 38-07545 Rev. **
Page 15 of 17
CY28331-2
Package Drawing and Dimensions
48-lead Shrunk Small Outline Package O48
51-85061-*C
AMDAthlonandHyperTransportaretrademarksofAdvancedMicroDevices, Inc. LexmarkisatrademarkofLexmarkInternational,
Inc. Dial-a-Frequency is a registered trademark, and Dial-a-Skew and Dial-a-Ratio are trademarks, of Cypress Semiconductor.
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07545 Rev. **
Page 16 of 17
CY28331-2
Document History Page
Document Title: CY28331-2 Clock Generator for AMD™ Hammer
Document Number: 38-07545
Orig. of
Rev.
ECN No. Issue Date
126369 05/21/03
Description of Change
Change
**
RGL
New Data Sheet
Document #: 38-07545 Rev. **
Page 17 of 17
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