MB9AF144MB [SPANSION]
The MB9A140NB Series are highly integrated;
| 型号： | MB9AF144MB |
| 厂家： | 
SPANSION |
| 描述： | The MB9A140NB Series are highly integrated |
| 文件： | 总121页 (文件大小：4532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products. Although the document is marked
with the name “Spansion”, the company that originally developed the specification, Cypress will
continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Cypress product. Any
changes that have been made are the result of normal document improvements and are noted in the
document history page, where supported. Future revisions will occur when appropriate, and changes
will be noted in a document history page.
Continuity of Ordering Part Numbers
Cypress continues to support existing part numbers. To order these products, please use only the
Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Cypress products and solutions.
About Cypress
Cypress (NASDAQ: CY) delivers high-performance, high-quality solutions at the heart of today’s most
advanced embedded systems, from automotive, industrial and networking platforms to highly
interactive consumer and mobile devices. With a broad, differentiated product portfolio that includes
NOR flash memories, F-RAM™ and SRAM, Traveo™ microcontrollers, the industry’s only PSoC®
programmable system-on-chip solutions, analog and PMIC Power Management ICs, CapSense®
capacitive touch-sensing controllers, and Wireless BLE Bluetooth® Low-Energy and USB connectivity
solutions, Cypress is committed to providing its customers worldwide with consistent innovation, best-
in-class support and exceptional system value.
MB9A140NB Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF141LB/MB/NB, MB9AF142LB/MB/NB,
MB9AF144LB/MB/NB
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9A140NB_DS706-00040
Revision 4.0
Issue Date June 10, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
MB9A140NB Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF141LB/MB/NB, MB9AF142LB/MB/NB,
MB9AF144LB/MB/NB
Data Sheet (Full Production)
Description
The MB9A140NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have
peripheral functions such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I2C).
The products which are described in this data sheet are placed into TYPE6 product categories in FM3
Family Peripheral Manual.
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Publication Number MB9A140NB_DS706-00040
Revision 4.0
Issue Date June 10, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
D a t a S h e e t
Features
32-bit ARM Cortex-M3 Core
Processor version: r2p1
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
Dual operation Flash memory
Dual Operation Flash memory has the upper bank and the lower bank.
So, this series could implement erase, write and read operations
for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is
connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
External Bus Interface*
Supports SRAM, NOR Flash memory device
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size : Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
* : MB9AF141LB, F142LB and F144LB do not support External Bus Interface.
Multi-function Serial Interface (Max 8channels)
4 channels with 16 steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
Operation mode is selectable from the followings for each channel.
UART
CSIO
I2C
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4)
Various error detection functions available (parity errors, framing errors, and overrun errors)
* : MB9AF141LB, F142LB and F144LB do not support Hardware Flow control.
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[I2C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
DMA Controller (8 channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2 units
Conversion time: 2.0 μs @ 2.7 V to 3.6 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion:
4 steps)
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 83 fast general-purpose I/O Ports@100 pin Package
Some ports are 5V tolerant I/O.
See Pin Description to confirm the corresponding pins.
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down counters.
Operation mode is selectable from the followings for each channel.
Free-running
Periodic (=Reload)
One-shot
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
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D a t a S h e e t
HDMI-CEC/Remote Control Receiver (Up to 2 channels)
HDMI-CEC transmitter
Header block automatic transmission by judging Signal free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data
Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)
HDMI-CEC receiver
Automatic ACK reply function available
Line error detection function available
Remote control receiver
4 bytes reception buffer
Repeat code detection function available
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of
the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The Watch counter is used for wake up from sleep and timer mode.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
External Interrupt Controller Unit
Up to 16 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog.
The Hardware watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the Hardware
watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby RTC and Deep
Standby Stop modes.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Built-in high-speed CR Clock: 4 MHz
Built-in low-speed CR Clock:
Main PLL Clock
100 kHz
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
External clock failure (clock stop) is detected, reset is asserted.
External frequency anomaly is detected, interrupt or reset is asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage that has been set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes supported.
Sleep
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value of RAM and not)
Deep Standby Stop (selectable between keeping the value of RAM and not)
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM).*
*: MB9AF141LB/MB, F142LB/MB and F144LB/MB support only SWJ-DP.
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Wide range voltage:
VCC = 1.65 V to 3.6 V
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
5
D a t a S h e e t
Product Lineup
Memory size
Product name
MB9AF141LB/MB/NB MB9AF142LB/MB/NB MB9AF144LB/MB/NB
Main
On-chip
area
64 Kbytes
32 Kbytes
128 Kbytes
32 Kbytes
256 Kbytes
32 Kbytes
Flash
Work
memory
area
16 Kbytes
16 Kbytes
32 Kbytes
SRAM0
On-chip
8 Kbytes
8 Kbytes
16 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
SRAM1
SRAM
Total
Function
Product name
Pin count
MB9AF141LB
MB9AF141MB
MB9AF142MB
MB9AF144MB
80/96
MB9AF141NB
MB9AF142NB
MB9AF144NB
100/112
MB9AF142LB
MB9AF144LB
64
Cortex-M3
40 MHz
CPU
Freq.
Power supply voltage range
DMAC
1.65 V to 3.6 V
8ch.
Addr: 21-bit (Max)
Addr: 25-bit (Max)
R/W Data: 8-bit (Max) R/W Data: 8-/16-bit (Max)
External Bus Interface
-
CS: 4 (Max)
Support: SRAM,
NOR Flash memory
8ch. (Max)
CS: 8 (Max)
Support: SRAM,
NOR Flash memory
Multi-function Serial Interface
(UART/CSIO/I2C)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
Base Timer
(PWC/Reload timer/PWM/PPG)
8ch. (Max)
1 unit
Dual Timer
HDMI-CEC/ Remote Control
Receiver
2ch. (Max)
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
8 pins (Max) +
NMI × 1
51 pins (Max)
12ch. (2 units)
11 pins (Max) +
NMI × 1
66 pins (Max)
17ch. (2 units)
Yes
16 pins (Max) +
External Interrupts
NMI × 1
83 pins (Max)
24ch. (2 units)
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
2ch.
High-speed
Low-speed
4 MHz
100 kHz
Built-in
CR
Debug Function
Unique ID
SWJ-DP
SWJ-DP/ETM
Yes
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics for
accuracy of built-in CR.
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Packages
MB9AF141LB MB9AF141MB MB9AF141NB
MB9AF142LB MB9AF142MB MB9AF142NB
MB9AF144LB MB9AF144MB MB9AF144NB
Product name
Package
LQFP: FPT-64P-M38 (0.5mm pitch)
LQFP: FPT-64P-M39 (0.65mm pitch)
QFN: LCC-64P-M24 (0.5mm pitch)
LQFP: FPT-80P-M37 (0.5mm pitch)
LQFP: FPT-80P-M40 (0.65mm pitch)
BGA: BGA-96P-M07 (0.5mm pitch)
LQFP: FPT-100P-M23 (0.5mm pitch)
QFP: FPT-100P-M36 (0.65mm pitch)
BGA: BGA-112P-M04 (0.8mm pitch)
: Supported
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note: See Package Dimensions for detailed information on each package.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
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D a t a S h e e t
Pin Assignment
FPT-100P-M23
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
75 VSS
P50/INT00_0/SIN3_1/MADATA00_1
P51/INT01_0/SOT3_1/MADATA01_1
P52/INT02_0/SCK3_1/MADATA02_1
P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1
P54/SOT6_0/TIOB1_2/MADATA04_1
P55/SCK6_0/ADTG_1/MADATA05_1
P56/INT08_2/MADATA06_1
74 P20/AN19/INT05_0/CROUT_0/MAD24_1
73 P21/AN18/SIN0_0/INT06_1/WKUP2
72 P22/AN17/SOT0_0/TIOB7_1
71 P23/AN16/SCK0_0/TIOA7_1
70 P1F/AN15/ADTG_5/MAD23_1
69 P1E/AN14/RTS4_1/MAD22_1
68 P1D/AN13/CTS4_1/MAD21_1
67 P1C/AN12/SCK4_1/MAD20_1
66 P1B/AN11/SOT4_1/MAD19_1
65 P1A/AN10/SIN4_1/INT05_1/MAD18_1
64 P19/AN09/SCK2_2/MAD17_1
63 P18/AN08/SOT2_2/MAD16_1
62 AVSS
P30/TIOB0_1/INT03_2/MADATA07_1
P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10
P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12
P34/TIOB4_1/MADATA11_1 13
P35/TIOB5_1/INT08_1/MADATA12_1 14
P36/SIN5_2/INT09_1/MADATA13_1 15
P37/SOT5_2/INT10_1/MADATA14_1 16
P38/SCK5_2/INT11_1/MADATA15_1 17
P39/ADTG_2 18
LQFP - 100
61 AVRH
60 AVCC
59 P17/AN07/SIN2_2/INT04_1/MAD15_1
58 P16/AN06/SCK0_1/MAD14_1
57 P15/AN05/SOT0_1/MAD13_1
56 P14/AN04/SIN0_1/INT03_1/MAD12_1
55 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1
54 P12/AN02/SOT1_1/MAD10_1
53 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1
52 P10/AN00
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 19
P3B/TIOA1_1 20
P3C/TIOA2_1 21
P3D/TIOA3_1 22
P3E/TIOA4_1 23
P3F/TIOA5_1 24
VSS 25
51 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
FPT-100P-M36
(TOP VIEW)
P51/INT01_0/SOT3_1/MADATA01_1 81
50 P22/AN17/SOT0_0/TIOB7_1
49 P23/AN16/SCK0_0/TIOA7_1
48 P1F/AN15/ADTG_5/MAD23_1
47 P1E/AN14/RTS4_1/MAD22_1
46 P1D/AN13/CTS4_1/MAD21_1
45 P1C/AN12/SCK4_1/MAD20_1
44 P1B/AN11/SOT4_1/MAD19_1
43 P1A/AN10/SIN4_1/INT05_1/MAD18_1
42 P19/AN09/SCK2_2/MAD17_1
41 P18/AN08/SOT2_2/MAD16_1
40 AVSS
P52/INT02_0/SCK3_1/MADATA02_1 82
P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1 83
P54/SOT6_0/TIOB1_2/MADATA04_1 84
P55/SCK6_0/ADTG_1/MADATA05_1 85
P56/INT08_2/MADATA06_1 86
P30/TIOB0_1/INT03_2/MADATA07_1 87
P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 88
P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 89
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 90
P34/TIOB4_1/MADATA11_1 91
QFP - 100
P35/TIOB5_1/INT08_1/MADATA12_1 92
P36/SIN5_2/INT09_1/MADATA13_1 93
P37/SOT5_2/INT10_1/MADATA14_1 94
P38/SCK5_2/INT11_1/MADATA15_1 95
P39/ADTG_2 96
39 AVRH
38 AVCC
37 P17/AN07/SIN2_2/INT04_1/MAD15_1
36 P16/AN06/SCK0_1/MAD14_1
35 P15/AN05/SOT0_1/MAD13_1
34 P14/AN04/SIN0_1/INT03_1/MAD12_1
33 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1
32 P12/AN02/SOT1_1/MAD10_1
31 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 97
P3B/TIOA1_1 98
P3C/TIOA2_1 99
P3D/TIOA3_1 100
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
9
D a t a S h e e t
FPT-80P-M37/M40
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
60 P20/AN19/INT05_0/CROUT_0/MAD24_1
59 P21/AN18/SIN0_0/INT06_1/WKUP2
58 P22/AN17/SOT0_0/TIOB7_1
57 P23/AN16/SCK0_0/TIOA7_1
56 P1B/AN11/SOT4_1/MAD19_1
55 P1A/AN10/SIN4_1/INT05_1/MAD18_1
54 P19/AN09/SCK2_2/MAD17_1
53 P18/AN08/SOT2_2/MAD16_1
52 AVSS
P50/INT00_0/SIN3_1/MADATA00_1
P51/INT01_0/SOT3_1/MADATA01_1
P52/INT02_0/SCK3_1/MADATA02_1
P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1
P54/SOT6_0/TIOB1_2/MADATA04_1
P55/SCK6_0/ADTG_1/MADATA05_1
P56/INT08_2/MADATA06_1
P30/TIOB0_1/INT03_2/MADATA07_1
P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10
P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12
P39/ADTG_2 13
51 AVRH
LQFP - 80
50 AVCC
49 P17/AN07/SIN2_2/INT04_1/MAD15_1
48 P16/AN06/SCK0_1/MAD14_1
47 P15/AN05/SOT0_1/MAD13_1
46 P14/AN04/SIN0_1/INT03_1/MAD12_1
45 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1
44 P12/AN02/SOT1_1/MAD10_1
43 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1
42 P10/AN00
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 14
P3B/TIOA1_1 15
P3C/TIOA2_1 16
P3D/TIOA3_1 17
P3E/TIOA4_1 18
P3F/TIOA5_1 19
VSS 20
41 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
10
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
FPT-64P-M38/M39
(TOP VIEW)
VCC
1
48 P21/AN18/SIN0_0/INT06_1/WKUP2
47 P22/AN17/SOT0_0/TIOB7_1
46 P23/AN16/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVSS
P50/INT00_0/SIN3_1
P51/INT01_0/SOT3_1
2
3
4
5
6
7
8
9
P52/INT02_0/SCK3_1
P30/TIOB0_1/INT03_2
P31/TIOB1_1/SCK6_1/INT04_2
P32/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/ADTG_2
42 AVRH
LQFP - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 10
P3B/TIOA1_1 11
38 P14/AN04/INT03_1
37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1
36 P12/AN02/SOT1_1
35 P11/AN01/SIN1_1/INT02_1/WKUP1
34 P10/AN00
P3C/TIOA2_1 12
P3D/TIOA3_1 13
P3E/TIOA4_1 14
P3F/TIOA5_1 15
VSS 16
33 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
11
D a t a S h e e t
LCC-64P- M24
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
48 P21/AN18/SIN0_0/INT06_1/WKUP2
47 P22/AN17/SOT0_0/TIOB7_1
46 P23/AN16/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVSS
P50/INT00_0/SIN3_1
P51/INT01_0/SOT3_1
P52/INT02_0/SCK3_1
P30/TIOB0_1/INT03_2
P31/TIOB1_1/SCK6_1/INT04_2
P32/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/ADTG_2
42 AVRH
QFN - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 10
P3B/TIOA1_1 11
38 P14/AN04/INT03_1
37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1
36 P12/AN02/SOT1_1
35 P11/AN01/SIN1_1/INT02_1/WKUP1
34 P10/AN00
P3C/TIOA2_1 12
P3D/TIOA3_1 13
P3E/TIOA4_1 14
P3F/TIOA5_1 15
VSS 16
33 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
BGA-112P-M04
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
VSS
VCC
P50
P53
P30
P34
P37
P3B
VCC
VCC
VSS
P81
VSS
P51
P54
P31
P35
P38
P3C
P3F
VSS
C
P80
P52
VSS
P55
P32
P36
P3A
P3E
VSS
X1A
X0A
VCC
P61
P60
VSS
P33
P39
P3D
VSS
P40
INITX
VSS
P0E
P0F
P62
P0B
P0C
P0D
P63
AN22
AN23
P09
TRSTX
VCC
VSS
AN19
AN16
AN12
AN09
AN06
AN03
AN01
VSS
X1
VSS
TDI
TDO/
SWO
TCK/
SWCLK
AN20
VSS
VSS
AN21
AN14
AN10
AN07
AN04
VSS
MD1
X0
AN18
AN15
AN11
AVRH
AVSS
AVCC
AN00
VCC
P56
P0A
Index
AN17
AN13
AN08
VSS
G
H
J
P44
P43
P42
P41
P4C
P49
P48
P45
AN05
P4D
P4B
P4A
AN02
P4E
K
L
MD0
VSS
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
13
D a t a S h e e t
BGA-96P-M07
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
VSS
VCC
P50
P53
P56
VSS
P32
P3A
P3D
VCC
VSS
P81
VSS
P51
P54
P30
VSS
P33
P3B
P3E
VSS
C
P80
P52
VSS
P55
P31
VSS
P39
P3C
VSS
X1A
X0A
VCC
P61
VSS
P63
P62
P0F
P0D
P0E
VSS
P0C
P0B
AN22
TRSTX
VSS
VSS
TDI
TDO/
SWO
TCK/
SWCLK
P60
P0A
VSS
AN17
AN11
AN08
AN06
AN04
VSS
MD1
X0
AN19
AN16
AN10
AN07
AN05
AN03
AN01
VSS
AN18
VSS
Index
AN09
AVRH
AVSS
AVCC
AN00
VCC
G
H
J
P3F
INITX
VSS
P48
P45
P44
P4A
P49
VSS
P4D
P4C
P4B
AN02
P4E
K
L
MD0
X1
VSS
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
14
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
List of Pin Functions
List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
1
79
B1
1
B1
1
2
-
VCC
P50
-
INT00_0
SIN3_1
MADATA00_1
P51
2
80
C1
2
C1
E
E
L
L
INT01_0
3
-
3
4
5
6
81
82
83
84
C2
B3
D1
D2
3
4
5
6
C2
B3
D1
D2
SOT3_1
(SDA3_1)
MADATA01_1
P52
INT02_0
4
-
E
E
E
L
L
K
SCK3_1
(SCL3_1)
MADATA02_1
P53
SIN6_0
-
-
TIOA1_2
INT07_2
MADATA03_1
P54
SOT6_0
(SDA6_0)
TIOB1_2
MADATA04_1
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
15
D a t a S h e e t
Pin No
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
P55
SCK6_0
(SCL6_0)
7
85
D3
7
D3
-
-
E
K
ADTG_1
MADATA05_1
P56
8
9
86
87
D5
E1
8
9
E1
E2
INT08_2
MADATA06_1
P30
E
E
L
L
5
-
TIOB0_1
INT03_2
MADATA07_1
P31
TIOB1_1
6
-
SCK6_1
(SCL6_1)
10
11
12
88
89
90
E2
E3
E4
10
11
12
E3
G1
G2
E
E
E
L
L
L
INT04_2
MADATA08_1
P32
TIOB2_1
7
-
SOT6_1
(SDA6_1)
INT05_2
MADATA09_1
P33
INT04_0
TIOB3_1
SIN6_1
8
ADTG_6
MADATA10_1
P34
-
-
13
14
91
92
F1
F2
-
-
-
-
TIOB4_1
MADATA11_1
P35
E
E
K
L
TIOB5_1
INT08_1
MADATA12_1
-
16
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
I/O
Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
P36
SIN5_2
INT09_1
MADATA13_1
VSS
15
93
F3
-
-
-
E
L
-
-
-
-
-
-
-
-
-
-
-
-
F1
F2
F3
-
-
-
-
-
-
VSS
VSS
P37
SOT5_2
(SDA5_2)
16
17
94
95
G1
G2
-
-
-
-
-
-
E
E
L
L
INT10_1
MADATA14_1
P38
SCK5_2
(SCL5_2)
INT11_1
MADATA15_1
P39
18
19
96
97
F4
13
14
G3
H1
9
E
E
K
K
ADTG_2
P3A
TIOA0_1
RTCCO_2
SUBOUT_2
P3B
G3
10
20
21
98
99
H1
H2
15
16
H2
H3
11
12
E
E
E
K
K
K
TIOA1_1
P3C
TIOA2_1
P3D
22
-
100
G4
B2
H3
17
-
J1
B2
J2
13
-
TIOA3_1
VSS
-
-
P3E
23
1
18
14
E
E
K
K
TIOA4_1
P3F
24
2
J2
19
J4
15
TIOA5_1
VSS
25
26
3
4
L1
J1
20
-
L1
-
16
-
-
-
VCC
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
17
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
LQFP-64
QFN-64
Type
Type
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
P40
27
5
J4
-
-
-
TIOA0_0
INT12_1
P41
E
L
28
29
30
6
7
8
L5
K5
J5
-
-
-
-
-
-
-
-
-
TIOA1_0
INT13_1
P42
E
E
E
L
K
K
TIOA2_0
P43
TIOA3_0
ADTG_7
P44
31
32
9
H5
L6
21
22
L5
-
-
TIOA4_0
MAD00_1
P45
TIOA5_0
MAD01_1
VSS
E
E
K
K
10
K5
-
-
-
-
K2
J3
-
-
K2
J3
-
-
-
-
-
-
-
-
-
VSS
VSS
-
-
H4
-
-
-
-
-
-
-
L6
L2
L4
K1
-
VSS
33
34
35
11
12
13
L2
L4
K1
23
24
25
17
-
C
VSS
18
VCC
P46
36
14
L3
26
L3
19
D
F
X0A
P47
37
38
15
16
K3
K4
27
28
K3
K4
20
21
D
B
G
C
X1A
INITX
P48
INT14_1
SIN3_2
MAD02_1
P49
39
17
K6
29
J5
-
E
L
22
-
TIOB0_0
40
18
J6
30
K6
E
K
SOT3_2
(SDA3_2)
MAD03_1
18
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
LQFP-64
QFN-64
Type
Type
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
P4A
23
TIOB1_0
41
42
19
20
L7
31
32
J6
E
K
SCK3_2
(SCL3_2)
-
MAD04_1
P4B
24
-
K7
L7
TIOB2_0
MAD05_1
P4C
E
I
K
S
TIOB3_0
25
SCK7_1
(SCL7_1)
43
21
H6
33
K7
CEC0
MAD06_1
P4D
-
TIOB4_0
26
-
44
45
22
23
J7
34
35
J7
I
I
K
L
SOT7_1
(SDA7_1)
MAD07_1
P4E
TIOB5_0
INT06_2
SIN7_1
MAD08_1
MD1
27
K8
K8
-
46
47
48
24
25
26
K9
L8
L9
36
37
38
K9
L8
L9
28
29
30
C
G
A
E
D
A
PE0
MD0
X0
PE2
X1
49
27
L10
39
L10
31
A
F
F
B
M
R
PE3
50
51
28
29
L11
K11
40
41
L11
K11
32
33
VSS
-
-
VCC
P10
52
30
J11
42
J11
34
AN00
P11
AN01
SIN1_1
INT02_1
WKUP1
MAD09_1
35
-
53
31
J10
43
J10
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
19
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
LQFP-64
QFN-64
Type
Type
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
P12
AN02
36
54
32
J8
44
J8
F
M
SOT1_1
(SDA1_1)
-
-
-
MAD10_1
VSS
-
-
-
-
K10
J9
-
-
K10
J9
-
-
VSS
P13
AN03
SCK1_1
(SCL1_1)
37
55
33
H10
45
H10
F
M
RTCCO_1
SUBOUT_1
MAD11_1
P14
-
38
AN04
56
57
58
59
34
35
36
37
H9
H7
46
47
48
49
H9
G10
G9
INT03_1
SIN0_1
MAD12_1
P15
F
F
F
F
N
M
M
N
-
39
AN05
SOT0_1
(SDA0_1)
-
-
MAD13_1
P16
AN06
G10
G9
SCK0_1
(SCL0_1)
MAD14_1
P17
AN07
40
F10
SIN2_2
INT04_1
MAD15_1
AVCC
-
60
61
62
38
39
40
H11
F11
G11
50
51
52
H11
F11
G11
41
42
43
-
-
-
AVRH
AVSS
20
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
LQFP-64
QFN-64
Type
Type
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
P18
AN08
44
-
63
41
G8
53
F9
F
M
SOT2_2
(SDA2_2)
MAD16_1
P19
AN09
45
64
-
42
-
F10
H8
F9
54
-
E11
-
F
M
SCK2_2
(SCL2_2)
-
-
MAD17_1
VSS
-
P1A
AN10
65
43
55
E10
-
-
-
SIN4_1
INT05_1
MAD18_1
P1B
F
F
F
N
M
M
AN11
66
67
44
45
E11
E10
56
E9
SOT4_1
(SDA4_1)
MAD19_1
P1C
AN12
-
-
SCK4_1
(SCL4_1)
MAD20_1
P1D
AN13
68
69
70
46
47
48
F8
E9
-
-
-
-
-
-
-
-
-
F
F
F
M
M
M
CTS4_1
MAD21_1
P1E
AN14
RTS4_1
MAD22_1
P1F
AN15
D11
ADTG_5
MAD23_1
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
21
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
LQFP-64
QFN-64
Type
Type
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
-
-
-
-
-
-
B10
C9
-
-
-
-
B10
C9
-
-
-
VSS
VSS
VSS
P23
-
-
-
D11
AN16
71
72
73
49
50
51
D10
E8
57
58
59
D10
D9
46
47
48
F
F
F
M
M
R
SCK0_0
(SCL0_0)
TIOA7_1
P22
AN17
SOT0_0
(SDA0_0)
TIOB7_1
P21
AN18
C11
C11
SIN0_0
INT06_1
WKUP2
P20
AN19
74
52
C10
60
C10
-
INT05_0
CROUT_0
MAD24_1
VSS
F
N
75
76
53
54
A11
A10
-
-
A11
-
-
-
-
-
VCC
P00
49
-
77
78
79
80
81
55
56
57
58
59
A9
B9
61
62
63
64
65
A10
B9
TRSTX
MCSX7_1
P01
E
E
E
E
E
J
J
J
J
J
50
TCK
SWCLK
P02
51
-
B11
A8
B8
B11
A9
TDI
MCSX6_1
P03
52
53
TMS
SWDIO
P04
B8
TDO
SWO
22
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
LQFP-64
QFN-64
Type
Type
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
P05
AN20
TRACED0
TIOA5_2
SIN4_2
INT00_1
MCSX5_1
VSS
82
-
60
-
C8
D8
-
-
-
-
-
-
F
Q
-
P06
AN21
TRACED1
TIOB5_2
83
61
D9
-
-
-
F
F
F
Q
P
P
SOT4_2
(SDA4_2)
INT01_1
MCSX4_1
P07
AN22
66
A8
ADTG_0
MCLKOUT_1
TRACED2
84
62
A7
-
-
-
-
SCK4_2
(SCL4_2)
-
-
-
A7
-
-
VSS
P08
-
AN23
TRACED3
TIOA0_2
CTS4_2
MCSX3_1
P09
85
63
B7
-
-
TRACECLK
TIOB0_2
RTS4_2
MCSX2_1
P0A
86
87
64
65
C7
D7
-
-
-
E
I
O
L
54
-
SIN4_0
INT00_2
MCSX1_1
67
C8
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
23
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
LQFP-64
QFN-64
Type
Type
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
P0B
SOT4_0
(SDA4_0)
55
-
88
89
66
67
A6
B6
68
69
C7
B7
I
K
TIOB6_1
MCSX0_1
P0C
SCK4_0
(SCL4_0)
56
I
K
TIOA6_1
MALE_1
VSS
-
-
-
-
-
-
-
D4
C3
-
-
-
-
-
C3
VSS
P0D
RTS4_0
TIOA3_2
MDQM0_1
P0E
90
68
C6
70
B6
-
E
E
K
K
CTS4_0
TIOB3_2
MDQM1_1
VSS
91
-
69
-
A5
-
71
-
C6
A5
-
-
-
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
WKUP0
P63
92
70
B5
72
A6
57
E
I
93
94
71
72
D6
C5
73
74
B5
C5
-
INT03_0
MWEX_1
P62
E
E
L
SCK5_0
(SCL5_0)
58
-
K
ADTG_3
MOEX_1
P61
SOT5_0
(SDA5_0)
95
73
B4
75
B4
59
E
K
TIOB2_2
24
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
LQFP-64
QFN-64
Type
Type
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
P60
SIN5_0
TIOA2_2
INT15_1
WKUP3
CEC1
60
96
74
C4
76
C4
I
T
-
MRDY_1
VCC
97
98
75
76
77
78
A4
A3
A2
A1
77
78
79
80
A4
A3
A2
A1
61
62
63
64
-
-
P80
H
H
H
H
99
P81
100
VSS
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
25
D a t a S h e e t
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
LQFP- QFP- BGA- LQFP- BGA-
100
100
112
80
96
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
84
7
62
85
96
72
-
A7
D3
F4
66
7
A8
D3
G3
C5
-
-
-
18
94
-
13
74
-
9
C5
-
58
-
A/D converter external trigger
input pin
70
12
30
-
48
90
8
D11
E4
-
-
-
12
-
G2
-
8
J5
-
-
-
-
-
-
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
71
72
73
74
82
83
84
85
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
49
50
51
52
60
61
62
63
J11
J10
J8
42
43
44
45
46
47
48
49
53
54
55
56
-
J11
J10
J8
34
35
36
37
38
39
-
AN01
AN02
AN03
H10
H9
H7
G10
G9
G8
F10
F9
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
AN04
AN05
AN06
AN07
40
44
45
-
AN08
AN09
AN10
AN11
E11
E10
F8
-
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN12
-
AN13
-
-
-
AN14
E9
-
-
-
AN15
D11
D10
E8
-
-
-
AN16
57
58
59
60
-
D10
D9
C11
C10
-
46
47
48
-
AN17
AN18
C11
C10
C8
D9
A7
B7
AN19
AN20
-
AN21
-
-
-
AN22
66
-
A8
-
-
AN23
-
26
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
LQFP- QFP- BGA- LQFP- BGA-
100
100
112
80
96
Base
Timer
0
TIOA0_0
27
19
85
40
9
5
97
63
18
87
64
6
J4
G3
B7
J6
-
-
-
10
-
TIOA0_1 Base timer ch.0 TIOA pin
14
-
H1
-
TIOA0_2
TIOB0_0
30
9
K6
E2
-
22
5
TIOB0_1 Base timer ch.0 TIOB pin
E1
C7
L5
H1
D1
L7
E2
D2
K5
H2
C4
K7
E3
B4
J5
TIOB0_2
86
28
20
5
-
-
Base
Timer
1
TIOA1_0
-
-
-
TIOA1_1 Base timer ch.1 TIOA pin
98
83
19
88
84
7
15
5
H2
D1
J6
E3
D2
-
11
-
TIOA1_2
TIOB1_0
41
10
6
31
10
6
23
6
TIOB1_1 Base timer ch.1 TIOB pin
TIOB1_2
-
Base
Timer
2
TIOA2_0
29
21
96
42
11
95
30
22
90
43
12
91
31
23
-
-
-
TIOA2_1 Base timer ch.2 TIOA pin
99
74
20
89
73
8
16
76
32
11
75
-
H3
C4
L7
G1
B4
-
12
60
24
7
TIOA2_2
TIOB2_0
TIOB2_1 Base timer ch.2 TIOB pin
TIOB2_2
59
-
Base
Timer
3
TIOA3_0
TIOA3_1 Base timer ch.3 TIOA pin
100
68
21
90
69
9
G4
C6
H6
E4
A5
H5
H3
-
17
70
33
12
71
21
18
-
J1
B6
K7
G2
C6
L5
J2
-
13
-
TIOA3_2
TIOB3_0
25
8
TIOB3_1 Base timer ch.3 TIOB pin
TIOB3_2
-
Base
Timer
4
TIOA4_0
-
TIOA4_1 Base timer ch.4 TIOA pin
1
14
-
TIOA4_2
-
TIOB4_0
44
13
-
22
91
-
J7
34
-
J7
-
26
-
TIOB4_1 Base timer ch.4 TIOB pin
F1
-
TIOB4_2
-
-
-
Base
Timer
5
TIOA5_0
32
24
82
45
14
83
10
2
L6
J2
22
19
-
K5
J4
-
-
TIOA5_1 Base timer ch.5 TIOA pin
15
-
TIOA5_2
60
23
92
61
C8
K8
F2
D9
TIOB5_0
35
-
K8
-
27
-
TIOB5_1 Base timer ch.5 TIOB pin
TIOB5_2
-
-
-
Base
Timer
6
TIOA6_1 Base timer ch.6 TIOA pin
TIOB6_1 Base timer ch.6 TIOB pin
89
88
67
66
B6
A6
69
68
B7
C7
56
55
Base
Timer
7
TIOA7_0
-
71
-
-
49
-
-
D10
-
-
57
-
-
D10
-
-
46
-
TIOA7_1 Base timer ch.7 TIOA pin
TIOA7_2
TIOB7_0
-
-
-
-
-
-
TIOB7_1 Base timer ch.7 TIOB pin
TIOB7_2
72
-
50
-
E8
-
58
-
D9
-
47
-
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
27
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP- BGA-
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
100
100
112
80
62
64
96
B9
A9
Debugger
Serial wire debug interface
clock input pin
SWCLK
SWDIO
78
56
B9
50
52
Serial wire debug interface
data input / output pin
80
58
A8
SWO
TCK
TDI
Serial wire viewer output pin
J-TAG test clock input pin
J-TAG test data input pin
J-TAG debug data output pin
81
78
79
81
59
56
57
59
B8
B9
65
62
63
65
B8
B9
53
50
51
53
B11
B8
B11
B8
TDO
J-TAG test mode state
input/output pin
TMS
80
58
A8
64
A9
52
TRACECLK Trace CLK output pin of ETM
TRACED0
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
64
60
61
62
63
55
9
C7
C8
D9
A7
B7
A9
H5
L6
-
-
-
-
-
-
-
-
49
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACED1
-
-
Trace data output pins of ETM
TRACED2
-
-
TRACED3
-
-
TRSTX
J-TAG test reset input pin
61
21
22
29
30
31
32
33
34
35
43
44
45
46
47
48
49
53
54
55
56
-
A10
L5
K5
J5
External
Bus
MAD00_1
MAD01_1
MAD02_1
MAD03_1
MAD04_1
MAD05_1
MAD06_1
MAD07_1
MAD08_1
MAD09_1
MAD10_1
MAD11_1
MAD12_1
MAD13_1
MAD14_1
MAD15_1
MAD16_1
MAD17_1
MAD18_1
MAD19_1
MAD20_1
MAD21_1
MAD22_1
MAD23_1
MAD24_1
10
17
18
19
20
21
22
23
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
K6
J6
K6
J6
L7
K7
H6
J7
L7
K7
J7
K8
J10
J8
K8
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
External bus interface address
bus
E11
E10
F8
-
-
E9
-
-
D11
C10
-
-
60
C10
28
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
LQFP- QFP- BGA- LQFP- BGA-
100
100
112
80
96
External
Bus
MCSX0_1
MCSX1_1
MCSX2_1
MCSX3_1
MCSX4_1
MCSX5_1
MCSX6_1
MCSX7_1
MDQM0_1
MDQM1_1
88
87
86
85
83
82
79
77
90
91
66
65
64
63
61
60
57
55
68
69
A6
D7
C7
B7
D9
C8
B11
A9
C6
A5
68
67
-
C7
C8
-
-
-
-
-
-
-
-
-
-
-
-
-
External bus interface chip
select output pin
-
-
-
-
63
61
70
71
B11
A10
B6
C6
External bus interface byte
mask signal output pin
External bus interface read
enable signal for SRAM
MOEX_1
MWEX_1
94
93
72
71
C5
D6
74
73
C5
B5
-
-
External bus interface write
enable signal for SRAM
2
3
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
C1
C2
B3
D1
D2
D3
D5
E1
E2
E3
E4
F1
F2
F3
G1
G2
2
3
C1
C2
B3
D1
D2
D3
E1
E2
E3
G1
G2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MADATA00_1
MADATA01_1
MADATA02_1
MADATA03_1
MADATA04_1
MADATA05_1
MADATA06_1
MADATA07_1
MADATA08_1
MADATA09_1
MADATA10_1
MADATA11_1
MADATA12_1
MADATA13_1
MADATA14_1
MADATA15_1
4
4
5
5
6
6
7
7
8
8
9
9
External bus interface data bus
10
11
12
13
14
15
16
17
10
11
12
-
-
-
-
-
-
-
-
-
Address Latch enable signal
for multiplex
89
67
B6
69
B7
-
MALE_1
External RDY input signal
96
84
74
62
C4
A7
76
66
C4
A8
-
-
MRDY_1
External bus clock output pin
MCLKOUT_1
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
29
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP- BGA-
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
100
100
112
80
96
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
2
80
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
C1
C8
D7
C2
D9
B3
J10
D6
H9
E1
2
C1
-
2
-
External interrupt request 00
input pin
82
87
3
-
67
3
C8
C2
-
54
3
External interrupt request 01
input pin
83
4
-
-
4
B3
J10
B5
H9
E2
G2
F10
E3
C10
E10
G1
C11
K8
4
External interrupt request 02
input pin
53
93
56
9
43
73
46
9
35
-
External interrupt request 03
input pin
38
5
12
59
10
74
65
11
73
45
E4
12
49
10
60
55
11
59
35
8
External interrupt request 04
input pin
G9
E2
40
6
C10
F9
-
External interrupt request 05
input pin
-
E3
7
External interrupt request 06
input pin
C11
K8
48
27
External interrupt request 07
input pin
INT07_2
5
83
D1
5
D1
-
INT08_1
INT08_2
External interrupt request 08
input pin
14
8
92
86
F2
-
-
-
-
D5
8
E1
External interrupt request 09
input pin
INT09_1
INT10_1
INT11_1
INT12_1
INT13_1
INT14_1
INT15_1
NMIX
15
16
17
27
28
39
96
92
93
94
95
5
F3
G1
G2
J4
-
-
-
-
-
-
External interrupt request 10
input pin
External interrupt request 11
input pin
-
-
-
External interrupt request 12
input pin
-
-
-
External interrupt request 13
input pin
6
L5
K6
C4
B5
-
-
-
External interrupt request 14
input pin
17
74
70
29
76
72
J5
C4
A6
-
External interrupt request 15
input pin
60
57
Non-Maskable Interrupt input
pin
30
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
LQFP/
QFN-
64
49
50
51
52
53
-
-
-
-
-
54
55
56
-
Pin Name
Function Description
LQFP- QFP- BGA- LQFP- BGA-
100
100
112
80
96
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
A9
B9
B11
A8
B8
61
62
63
64
65
-
-
66
-
A10
B9
B11
A9
B8
-
-
A8
-
C8
D9
A7
B7
General-purpose I/O port 0
C7
-
-
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
-
C8
C7
B7
B6
C6
A6
J11
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
-
57
34
35
36
37
38
39
-
40
44
45
-
-
-
-
-
-
-
48
47
46
General-purpose I/O port 1
E11
E10
F8
-
-
-
60
59
58
57
-
-
-
E9
D11
C10
C11
E8
C10
C11
D9
D10
General-purpose I/O port 2
D10
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
31
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP- BGA-
Pin
Function
LQFP/
Pin Name
Function Description
QFN-
64
5
6
7
8
-
-
-
-
-
9
10
11
12
13
14
15
-
100
100
112
80
96
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
9
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
9
10
11
12
-
-
-
-
-
13
14
15
16
17
18
19
-
E2
E3
G1
G2
-
-
-
-
-
G3
H1
H2
H3
J1
J2
J4
-
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
96
95
94
93
98
99
46
48
49
General-purpose I/O port 3
2
5
6
7
8
9
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
C4
B4
C5
D6
A3
A2
K9
L9
L10
-
-
-
-
-
-
-
-
-
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
L5
K5
L3
K3
J5
K6
J6
L7
K7
J7
K8
C1
C2
B3
D1
D2
D3
E1
C4
B4
C5
B5
A3
A2
K9
L9
L10
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
74
73
72
71
76
77
24
26
27
-
19
20
-
22
23
24
25
26
27
2
3
4
-
-
-
-
60
59
58
-
62
63
28
30
31
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
32
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
LQFP- QFP- BGA- LQFP- BGA-
100
100
112
80
96
Multi-
function
Serial
0
SIN0_0
SIN0_1
73
56
51
34
C11
H9
59
46
C11
H9
48
Multi-function serial interface
ch.0 input pin
-
Multi-function serial interface
ch.0 output pin.
This pin operates as SOT0
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA0
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.0 clock I/O pin.
SOT0_0
(SDA0_0)
72
57
71
50
35
49
E8
H7
58
47
57
D9
47
SOT0_1
(SDA0_1)
G10
D10
-
SCK0_0
(SCL0_0)
D10
46
This pin operates as SCK0
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL0
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.1 input pin
SCK0_1
(SCL0_1)
58
53
36
31
G10
J10
48
43
G9
-
Multi-
function
Serial
1
SIN1_1
J10
35
Multi-function serial interface
ch.1 output pin.
This pin operates as SOT1
when it is used in a
(SDA1_1) UART/CSIO (operation
modes 0 to 2) and as SDA1
when it is used in an I2C
(operation mode 4).
SOT1_1
54
55
32
33
J8
44
45
J8
36
37
Multi-function serial interface
ch.1 clock I/O pin.
This pin operates as SCK1
SCK1_1
(SCL1_1)
when it is used in a
H10
H10
UART/CSIO (operation
modes 0 to 2) and as SCL1
when it is used in an I2C
(operation mode 4).
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
33
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP- BGA-
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
100
100
112
80
96
Multi-
function
Serial
2
Multi-function serial interface
ch.2 input pin
Multi-function serial interface
ch.2 output pin.
SIN2_2
59
37
G9
49
F10
40
This pin operates as SOT2
when it is used in a
(SDA2_2) UART/CSIO (operation
modes 0 to 2) and as SDA2
when it is used in an I2C
(operation mode 4).
SOT2_2
63
64
41
42
G8
53
54
F9
44
Multi-function serial interface
ch.2 clock I/O pin.
This pin operates as SCK2
SCK2_2
(SCL2_2)
when it is used in a
F10
E11
45
UART/CSIO (operation
modes 0 to 2) and as SCL2
when it is used in an I2C
(operation mode 4).
Multi-
function
Serial
3
SIN3_1
SIN3_2
2
80
17
C1
K6
2
C1
J5
2
-
Multi-function serial interface
ch.3 input pin
39
29
Multi-function serial interface
ch.3 output pin.
This pin operates as SOT3
when it is used in a
SOT3_1
(SDA3_1)
3
81
C2
3
C2
3
UART/CSIO (operation
modes 0 to 2) and as SDA3
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.3 clock I/O pin.
SOT3_2
(SDA3_2)
40
4
18
82
J6
30
4
K6
B3
-
SCK3_1
(SCL3_1)
B3
4
This pin operates as SCK3
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL3
when it is used in an I2C
(operation mode 4).
SCK3_2
(SCL3_2)
41
19
L7
31
J6
-
34
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
LQFP- QFP- BGA- LQFP- BGA-
100
100
112
80
96
Multi-
function
Serial
4
SIN4_0
SIN4_1
SIN4_2
87
65
82
65
43
60
D7
F9
C8
67
55
-
C8
E10
-
54
-
Multi-function serial interface
ch.4 input pin
-
Multi-function serial interface
ch.4 output pin.
This pin operates as SOT4
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA4
when it is used in an I2C
(operation mode 4).
SOT4_0
(SDA4_0)
88
66
83
66
44
61
A6
E11
D9
68
56
-
C7
E9
-
55
-
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
-
Multi-function serial interface
ch.4 clock I/O pin.
This pin operates as SCK4
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL4
when it is used in an I2C
(operation mode 4).
SCK4_0
(SCL4_0)
89
67
67
45
B6
69
-
B7
-
56
-
SCK4_1
(SCL4_1)
E10
SCK4_2
(SCL4_2)
84
62
A7
-
-
-
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_2
90
69
86
91
68
85
96
15
68
47
64
69
46
63
74
93
C6
E9
C7
A5
F8
B7
C4
F3
70
-
B6
-
-
-
Multi-function serial interface
ch.4 RTS output pin
-
-
-
71
-
C6
-
-
Multi-function serial interface
ch.4 CTS input pin
-
-
-
-
Multi-
function
Serial
5
76
-
C4
-
60
-
Multi-function serial interface
ch.5 input pin
Multi-function serial interface
ch.5 output pin.
This pin operates as SOT5
when it is used in a
SOT5_0
(SDA5_0)
95
73
B4
75
B4
59
UART/CSIO (operation
modes 0 to 2) and as SDA5
when it is used in an I2C
(operation mode 4).
SOT5_2
(SDA5_2)
16
94
94
72
G1
C5
-
-
-
Multi-function serial interface
ch.5 clock I/O pin.
This pin operates as SCK5
when it is used in a
SCK5_0
(SCL5_0)
74
C5
58
UART/CSIO (operation
modes 0 to 2) and as SCL5
when it is used in an I2C
(operation mode 4).
SCK5_2
(SCL5_2)
17
95
G2
-
-
-
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
35
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP- BGA-
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
100
100
112
80
96
Multi-
function
Serial
6
SIN6_0
SIN6_1
5
83
90
D1
E4
5
D1
G2
-
Multi-function serial interface
ch.6 input pin
12
12
8
Multi-function serial interface
ch.6 output pin.
This pin operates as SOT6
when it is used in a
SOT6_0
(SDA6_0)
6
84
D2
6
D2
-
UART/CSIO (operation
modes 0 to 2) and as SDA6
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.6 clock I/O pin.
SOT6_1
(SDA6_1)
11
7
89
85
E3
D3
11
7
G1
D3
7
-
SCK6_0
(SCL6_0)
This pin operates as SCK6
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL6
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.7 input pin
SCK6_1
(SCL6_1)
10
45
88
23
E2
K8
10
35
E3
K8
6
Multi-
function
Serial
7
SIN7_1
27
Multi-function serial interface
ch.7 output pin.
This pin operates as SOT7
when it is used in a
(SDA7_1) UART/CSIO (operation
modes 0 to 2) and as SDA7
when it is used in an I2C
(operation mode 4).
SOT7_1
44
43
22
21
J7
34
33
J7
26
25
Multi-function serial interface
ch.7 clock I/O pin.
This pin operates as SCK7
SCK7_1
(SCL7_1)
when it is used in a
H6
K7
UART/CSIO (operation
modes 0 to 2) and as SCL7
when it is used in an I2C
(operation mode 4).
36
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
LQFP- QFP- BGA- LQFP- BGA-
100
100
112
80
96
Real-time
clock
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
92
55
19
92
55
19
70
33
97
70
33
97
B5
H10
G3
72
45
14
72
45
14
A6
H10
H1
57
0.5 seconds pulse output pin
of Real-time clock
37
10
57
37
10
B5
A6
SUBOUT_1 Sub clock output pin
SUBOUT_2
H10
G3
H10
H1
Low-Power
Consumption
Mode
Deep standby mode return
WKUP0
92
53
73
96
70
31
51
74
B5
J10
C11
C4
72
43
59
76
A6
J10
C11
C4
57
35
48
60
signal input pin 0
Deep standby mode return
signal input pin 1
WKUP1
Deep standby mode return
signal input pin 2
WKUP2
Deep standby mode return
signal input pin 3
WKUP3
HDMI-
CEC/
Remote
Control
HDMI-CEC/RemoteControl
Reception ch.0 input/output
pin
HDMI-CEC/RemoteControl
Reception ch.1 input/output
pin
CEC0
CEC1
43
96
21
74
H6
C4
33
76
K7
C4
25
60
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
37
D a t a S h e e t
Pin No
LQFP- QFP- BGA- LQFP- BGA-
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
100
100
112
80
96
Reset
Mode
External Reset Input pin.
A reset is valid when
INITX=L.
INITX
38
16
K4
28
K4
21
Mode 0 pin.
During normal operation,
MD0=L must be input. During
serial programming to Flash
memory, MD0=H must be
input.
MD0
47
25
L8
37
36
L8
29
Mode 1 pin.
During serial programming to
Flash memory, MD1=L must
be input.
MD1
46
24
K9
K9
28
Power
GND
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
1
26
35
51
76
97
-
-
-
-
25
-
-
-
-
34
50
-
-
-
-
-
-
75
-
-
-
-
-
79
4
13
29
54
75
-
-
-
-
3
-
-
-
-
12
28
-
-
-
-
-
-
53
-
-
-
-
-
B1
J1
1
-
25
41
-
77
-
-
-
-
20
-
-
-
-
24
40
-
-
-
-
-
B1
-
K1
K11
-
A4
F1
F2
F3
B2
L1
K2
J3
1
-
18
33
-
61
-
-
-
-
16
-
-
-
-
-
32
-
-
-
-
-
K1
K11
A10
A4
-
-
-
B2
L1
K2
J3
H4
-
L4
L11
K10
J9
H8
B10
C9
-
A11
D8
-
D4
C3
-
-
L6
L4
L11
K10
J9
-
B10
C9
D11
A11
-
A7
-
C3
A5
A1
-
-
-
-
-
-
-
80
-
-
-
-
-
-
-
64
GND Pin
GND Pin
GND Pin
100
78
A1
38
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
LQFP/
QFN-
64
Pin Name
Function Description
LQFP- QFP- BGA- LQFP- BGA-
100
100
112
80
38
26
39
96
Clock
Main clock (oscillation) input
pin
Sub clock (oscillation) input
pin
Main clock (oscillation) I/O
pin
X0
X0A
X1
48
26
L9
L9
30
19
31
36
14
L3
L3
49
27
L10
L10
X1A
CROUT_0
CROUT_1
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc
clock output port
37
74
92
15
52
70
K3
C10
B5
27
60
72
K3
C10
A6
20
-
57
ADC
power
A/D converter analog power
supply pin
A/D converter analog reference
voltage input pin
AVCC
AVRH
AVSS
C
60
61
62
33
38
39
40
11
H11
F11
G11
L2
50
51
52
23
H11
F11
G11
L2
41
42
43
17
ADC
GND
C pin
A/D converter GND pin
Power stabilization capacity
pin
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
39
D a t a S h e e t
I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
When the main oscillation is
selected.
Oscillation feedback resistor
: Approximately 1 MΩ
With Standby mode control
Digital output
Digital output
P-ch
P-ch
X1
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
N-ch
R
: Approximately 33 kΩ
IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
B
CMOS level hysteresis input
Pull-up resistor
: Approximately 33 kΩ
Pull-up resistor
Digital input
40
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Type
Circuit
Remarks
C
Open drain output
CMOS level hysteresis input
Digital input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is
selected.
Oscillation feedback resistor
: Approximately 5 MΩ
With Standby mode control
P-ch
P-ch
Digital output
X1A
When the GPIO is selected.
CMOS level output.
N-ch
Digital output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
IOH= -4 mA, IOL= 4 mA
R
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
41
D a t a S h e e t
Type
Circuit
Remarks
E
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
: Approximately 33 kΩ
Digital output
Digital output
IOH= -4 mA, IOL= 4 mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
IOH= -4 mA, IOL= 4 mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital output
Digital output
P-ch
P-ch
N-ch
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
G
CMOS level hysteresis input
Mode input
42
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Type
Circuit
Remarks
H
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH = -12.0 mA, IOL= 10.5 mA
P-ch
Digital output
Digital output
N-ch
R
Digital input
Standby mode control
I
CMOS level output
CMOS level hysteresis input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
IOH= -4 mA, IOL= 4 mA
Available to control PZR
registers.
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
43
D a t a S h e e t
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
44
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and
has established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
45
D a t a S h e e t
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant
aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum
laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
46
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
47
D a t a S h e e t
Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply..
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize
the oscillation.
・Surface mount type
Size:
More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
・Lead type
Load capacitance: Approximately 6 pF to 7 pF
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock
input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
• Example of Using an External Clock
Device
X0(X0A)
Set as
Can be used as
general-purpose
I/O ports.
External clock
input
X1(PE3),
X1A (P47)
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a
capacitor.A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistor stays low, as well as the distance between the mode pins and VCC pins or VSS pins is
as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
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D a t a S h e e t
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC →AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash
memory products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash memory
products and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant
I/O.
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Block Diagram
TRSTX,TCK,
TDI,TMS
SWJ-DP
TPIU*1
ETM*1
SRAM0
8/16 Kbyte
TDO
ROM
Table
TRACEDx,
TRACECLK
I
SRAM1
8/16 Kbyte
D
NVIC
Sys
On-Chip Flash
64+32 Kbyte/
128+32 Kbyte/
256+32 Kbyte
Flash I/F
Security
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch.
CSV
CLK
X0
X1
Main
Source Clock
CR
PLL
CR
Osc
Sub
Osc
X0A
X1A
4 MHz 100 kHz
CROUT
MADx
External Bus I/F*2
MADATAx
MCSXx,
MOEX,
MWEX,
MALE,
MRDY,
MCLKOUT,
MDQMx
AVCC,
AVSS,
AVRH
12-bit A/D Converter
Unit 0
ANxx
Power-On
Reset
Unit 1
ADTGx
LVD
LVD Ctrl
Regulator
C
IRQ-Monitor
TIOAx
TIOBx
Base Timer
16-bit 8ch./
32-bit 4ch.
CRC
Accelerator
Watch Counter
External Interrupt
Controller
16-pin + NMI
INTx
NMIX
MD0,
MD1
MODE-Ctrl
GPIO
P0x,
P1x,
.
.
.
PIN-Function-Ctrl
HDMI-CEC/
Remote Reciver Control
PEx
CEC0,CEC1
SCKx
SINx
Multi-Function Serial I/F
8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)*2
RTCCO,
SUBOUT
Real-Time Clock
SOTx
CTS4
RTS4
WKUPx
Deep Standby Ctrl
*1: For the MB9AF141LB/MB, MB9AF142LB/MB, and MB9AF144LB/MB, ETM is not available.
*2: For the MB9AF141LB, MB9AF142LB and MB9AF144LB, the External Bus Interface is not available. And
the Multi-function Serial Interface does not support hardware flow control in these products.
Memory Size
See Memory size in Product Lineup to confirm the memory size.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
51
D a t a S h e e t
Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_F000
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
DMAC
Reserved
EXT-bus I/F
Reserved
RTC
Reserved
Watch Counter
CRC
0x7000_0000
0x6000_0000
External Device
Area
MFS
Reserved
Reserved
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
0x4400_0000
0x4200_0000
0x4000_0000
32Mbytes
Bit band alias
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
GPIO
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
Reserved
CR Trim
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Reserved
0x4002_8000
0x4002_7000
A/DC
Reserved
Reserved
Base Timer
0x4002_6000
0x4002_5000
0x2008_0000
0x2000_0000
0x1FFF_0000
0x0020_8000
0x0020_0000
0x0010_4000
0x0010_0000
SRAM1
SRAM0
Reserved
Flash(Work area)
Reserved
Reserved
See the next page
"Memory Map (2)"
for the memory size
details.
Security/CR Trim
0x4001_6000
0x4001_5000
Dual Timer
Reserved
Flash(Main area)
0x4001_3000
SW WDT
HW WDT
0x4001_2000
0x4001_1000
0x0000_0000
Clock/Reset
0x4001_0000
Reserved
Flash I/F
0x4000_1000
0x4000_0000
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Memory Map (2)
MB9AF144LB/MB/NB
MB9AF142LB/MB/NB
MB9AF141LB/MB/NB
0x2008_0000
0x2008_0000
0x2008_0000
Reserved
Reserved
Reserved
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_2000
0x2000_0000
0x1FFF_E000
0x2000_2000
0x2000_0000
0x1FFF_E000
SRAM1
16Kbytes
SRAM1
8Kbytes
SRAM1
8Kbytes
SRAM0
8Kbytes
SRAM0
8Kbytes
SRAM0
16Kbytes
Reserved
Reserved
Reserved
SA4-7 (8 KBx4)
Reserved
0x0020_8000
0x0020_0000
0x0020_8000
0x0020_0000
0x0020_8000
0x0020_0000
SA4-7 (8 KBx4)
Reserved
SA4-7 (8 KBx4)
Reserved
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
Reserved
Reserved
0x0004_0000
SA9-11 (64 KBx3)
0x0002_0000
0x0000_0000
SA9 (64 KB)
0x0001_0000
0x0000_0000
SA8 (48 KB)
SA8 (48 KB)
SA8 (48 KB)
SA2-3 (8 KBx2)
SA2-3 (8 KBx2)
SA2-3 (8 KBx2)
0x0000_0000
Refer to the programming manual for the detail of Flash main area.
・MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
53
D a t a S h e e t
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_F000
0x4004_0000
0x4006_0000
0x4006_1000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_EFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x41FF_FFFF
Flash memory I/F register
Reserved
AHB
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual Timer
Reserved
Reserved
Base Timer
Reserved
APB1 A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
HDMI-CEC/Remote control Receiver
Low-Voltage Detector
Deep standby mode Controller
Reserved
APB2
Multi-function serial
CRC
Watch Counter
Real-time clock
Reserved
External bus interface
Reserved
AHB
DMAC register
Reserved
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
55
D a t a S h e e t
List of Pin Status
Power-on
Return from
Deep
standby
reset or
low-voltage
detection
state
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
A
Main crystal
oscillator input
pin/
Input
Input
Input
Input
Input
Input
Input
Input
Input
External main
clock input
selected
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
External main
clock input
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
disabled
disabled
disabled
B
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Hi-Z /
Internal
input
state/When state/When state/When state/When state/When state/When
oscillation oscillation oscillation oscillation oscillation oscillation
Hi-Z /
Hi-Z /
Main crystal
oscillator output
pin
Internal
Internal
fixed at
0/
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
input fixed input fixed
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
at 0
at 0
or Input
enabled
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed
at 0
at 0
at 0
at 0
at 0
at 0
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
INITX
C
D
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
E
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
Hi-Z /
Input
GPIO
Setting
Setting
Setting
GPIO
GPIO
selected
disabled
disabled
disabled
selected
selected
enabled
enabled
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Return from
Deep
standby
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
F
Sub crystal
oscillator input
pin /
Input
Input
Input
Input
Input
Input
Input
Input
Input
External sub
clock input
selected
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z/
Internal
input fixed
at 0
External sub
clock input
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
disabled
disabled
disabled
G
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Hi-Z /
Internal
input
state/When state/When state/When state/When state/When
Maintain oscillation oscillation oscillation oscillation oscillation
Hi-Z /
Hi-Z /
Sub crystal
oscillator output
pin
Internal
Internal
fixed at
0 /
previous
state
stops*2,
stops*2,
stops*2,
stops*2,
stops*2,
input fixed input fixed
Hi-Z /
Hi-Z /
Hi-Z/
Hi-Z/
Hi-Z/
at 0
at 0
or Input
enable
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed
at 0
at 0
at 0
at 0
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Input
Hi-Z /
Input
Maintain
previous
state
Maintain
previous
state
GPIO
GPIO
H
Hi-Z
selected
selected
enabled
enabled
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
57
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Return from
Deep
standby
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Maintain
previous
state
Setting
Setting
Setting
NMIX selected
disabled
disabled
disabled
Hi-Z /
WKUP
input
Maintain
previous
state
Maintain
previous
state
WKUP
input
Resource other
than above
selected
GPIO
I
Hi-Z /
Internal
input fixed
at 0
selected
Hi-Z /
Input
Hi-Z /
Input
enabled
enabled
Hi-Z
Hi-Z
enabled
enabled
GPIO
selected
Pull-up /
Input
Pull-up /
Input
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
enabled
enabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Internal
input fixed
at 0
J
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
Setting
Setting
Setting
GPIO
selected
disabled
disabled
disabled
selected
GPIO
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Resource selected
Hi-Z /
Input
Hi-Z /
Input
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
GPIO
K
Hi-Z
selected
GPIO
enabled
enabled
selected
Maintain
previous
state
External interrupt
enabled selected
Setting
Setting
Setting
disabled
disabled
disabled
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
GPIO
L
Hi-Z /
Internal
input fixed
at 0
selected
Hi-Z /
Input
Hi-Z /
Input
Hi-Z
Hi-Z
enabled
enabled
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
M
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Resource other
than above
selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
GPIO
disabled
disabled
disabled
selected
GPIO
selected
58
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Return from
Deep
standby
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
N
Maintain
previous
state
External interrupt
enabled selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
Setting
Setting
Setting
GPIO
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Setting
Setting
Setting
Trace
Trace selected
disabled
disabled
disabled
output
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Resource other
than above
selected
Maintain
previous
state
Maintain
previous
state
GPIO
O
Hi-Z /
Internal
input fixed
at 0
selected
Hi-Z /
Input
Hi-Z /
Input
Hi-Z
enabled
enabled
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
P
Trace
Trace selected
output
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Resource other
than above
selected
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
GPIO
Hi-Z /
Internal
input fixed
at 0
disabled
disabled
disabled
selected
GPIO
selected
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
59
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Return from
Deep
standby
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Trace
output
Trace selected
Q
Maintain
previous
state
GPIO
selected
Internal
input fixed
at 0
External interrupt
enabled selected
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
GPIO
disabled
disabled
disabled
selected
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Hi-Z /
WKUP
input
enabled
WKUP
input
WKUP
enabled
Maintain
previous
state
R
enabled
enabled
External interrupt
enabled selected
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
GPIO
GPIO
selected
Internal
input fixed
at 0
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at 0
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
Setting
Setting
Setting
enabled
disabled
disabled
disabled
Resource other
than above
selected
GPIO
S
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Input
Hi-Z /
Input
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
GPIO
Hi-Z
selected
enabled
enabled
GPIO
selected
60
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Return from
Deep
standby
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby RTC
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
Maintain
previous
state
SPL = 0
SPL = 1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
Setting
Setting
Setting
enabled
disabled
disabled
disabled
Hi-Z /
WKUP
input
WKUP
enabled
WKUP
input
Maintain
previous
state
Setting
Setting
Setting
enabled
enabled
disabled
disabled
disabled
T
External interrupt
enabled selected
Maintain
previous
state
Maintain
previous
state
GPIO
GPIO
selected
Internal
input fixed
at 0
selected
Hi-Z /
Internal
input fixed
at 0
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Input
Hi-Z /
Input
Hi-Z
enabled
enabled
GPIO
selected
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep
Standby RTC mode, and Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
61
D a t a S h e e t
Electrical Characteristics
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage*1, *2
VCC
AVCC
AVRH
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 4.6
VSS + 4.6
VSS + 4.6
VCC + 0.5
(≤ 4.6 V)
VSS + 6.5
AVCC + 0.5
(≤ 4.6 V)
VCC + 0.5
(≤ 4.6 V)
V
V
V
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
Input voltage*1
VI
5 V tolerant
Analog pin input voltage*1
Output voltage*1
VIA
VO
VSS - 0.5
V
10
mA
L level maximum output current*4
L level average output current*5
IOL
-
39
4
10.5
100
50
- 10
- 39
- 4
- 12
- 100
- 50
300
+ 150
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
P80/P81 pins
P80/P81 pins
IOLAV
-
L level total maximum output current
L level total average output current*6
∑IOL
∑IOLAV
-
-
H level maximum output current*4
IOH
-
-
P80/P81 pins
P80/P81 pins
H level average output current*5
IOHAV
H level total maximum output current
H level total average output current*6
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that VSS = AVSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*6: The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100 ms.
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
62
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
2. Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Value
Parameter
Symbol Conditions
Unit
Remarks
Min
Max
3.6
Power supply voltage
Analog power supply voltage
VCC
AVCC
-
-
1.65*2
1.65
2.7
V
V
V
V
3.6
AVCC = VCC
AVCC ≥ 2.7 V
AVCC<2.7 V
AVCC
AVCC
10
Analog reference voltage
AVRH
-
AVCC
1
Smoothing capacitor
Operating temperature
CS
TA
--
-
µF For Regulator*1
°C
- 40
+ 85
*1 : See C Pin in Handling Devices for the connection of the smoothing capacitor.
*2 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this
data sheet. If you are considering application under any conditions other than listed herein, please contact
sales representatives beforehand.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
63
D a t a S h e e t
3. DC Characteristics
(1) Current rating
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter Symbol
Conditions
Unit Remarks
Typ*3 Max*4
CPU: 40 MHz,
Peripheral: 40 MHz
CPU: 40 MHz,
Peripheral: the clock stops
NOP operation
15.5
8.7
21
12
mA *1, *5
PLL
Rrun mode
mA *1, *5
High-speed
CR
Rrun mode
Sub
Rrun mode
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
ICC
CPU/ Peripheral: 4 MHz*2
CPU/ Peripheral: 32 kHz
CPU/ Peripheral: 100 kHz
Peripheral: 40 MHz
1.8
110
125
9
2.9
680
700
12.5
1.6
mA *1
μA *1, *6
μA *1
Power
supply
current
VCC
mA *1, *5
mA *1
Peripheral: 4 MHz*2
Peripheral: 32 kHz
0.8
96
ICCS
670
680
μA *1, *6
μA *1
Peripheral: 100 kHz
110
Sleep mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=3.6 V
*4: TA=+85°C, VCC=3.6 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
64
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
Value
Pin
name
Parameter Symbol
Conditions
Unit Remarks
mA *1, *3
mA *1, *3
μA *1, *4
μA *1, *4
μA *1, *4
μA *1, *4
μA *1
Typ*2 Max*2
TA = + 25°C,
2.1
2.5
3.4
35
When LVD is off
TA = + 85°C,
Main Timer
mode
-
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
ICCT
12
-
Sub Timer
mode
330
29
9.8
-
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
ICCR
RTC mode
Stop mode
280
28
9
ICCH
-
270
μA *1
When LVD is off
TA = + 25°C,
When LVD is off,
When RAM is off
1.25
5.3
7
18
70
100
9
μA *1, *4, *5
μA *1, *4, *5
μA *1, *4, *5
μA *1, *4, *5
μA *1, *5
Power
supply
current
ICCHD
TA = + 25°C,
When LVD is off,
When RAM is on
VCC
Deep Standby
Stop mode
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
When LVD is off,
When RAM is on
TA = + 25°C,
-
When LVD is off,
When RAM is off
1.9
5.9
TA = + 25°C,
When LVD is off,
When RAM is on
20
μA *1, *5
Deep Standby
RTC mode
ICCRD
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
When LVD is off,
When RAM is on
75
μA *1, *5
μA *1, *5
-
105
*1: When all ports are fixed.
*2: VCC=3.6 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
*5: RAM on/off setting is on-chip SRAM only.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
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D a t a S h e e t
· Low-Voltage Detection Current
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Max
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
At operation
for reset
VCC = 3.6 V
0.13
0.3
μA At not detect
μA At not detect
Low-voltage
detection circuit
(LVD) power
supply current
ICCLVD
VCC
At operation
for interrupt
VCC = 3.6 V
0.13
0.3
· Flash Memory Current
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Max
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
9.5
11.2
mA
*
*: The current at which to write or erase Flash memory, ICCFLASH is added to ICC.
· A/D Converter Current
(VCC = VCC28 = AVCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = AVSS = 0V, TA = - 40°C to +85°C)
Value
Max
Pin
name
Parameter
Symbol
Conditions
Unit
mA
μA
Remarks
Typ
At 1unit
operation
0.27
0.42
Power supply
current
ICCAD
AVCC
AVRH
At stop
0.03
0.72
0.02
10
At 1unit
operation
AVRH=3.6 V
1.29
2.6
mA
Reference power
supply current
ICCAVRH
At stop
μA
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(2) Pin Characteristics
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Parameter Symbol Pin name
Conditions
Unit Remarks
Min
Max
CMOS
hysteresis
input pin,
MD0, MD1
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC × 0.8
-
-
-
-
VCC + 0.3
V
H level input
voltage
(hysteresis
input)
VCC × 0.7
VCC × 0.8
VCC × 0.7
VIHS
5 V tolerant
input pin
VSS + 5.5
V
V
V
CMOS
hysteresis
input pin,
MD0, MD1
VCC × 0.2
VCC × 0.3
VCC × 0.2
VSS - 0.3
VSS - 0.3
L level input
voltage
(hysteresis
input)
VILS
5 V tolerant
input pin
VCC < 2.7 V
VCC × 0.3
VCC ≥ 2.7 V,
IOH = - 4 mA
VCC - 0.5
4 mA type
P80/P81
-
-
VCC
V
V
VCC < 2.7 V,
IOH = - 2 mA
VCC - 0.45
H level
output voltage
VOH
VCC ≥ 2.7 V,
IOH = - 12 mA
VCC - 0.4
VCC
0.4
0.4
VCC < 2.7 V,
IOH = - 6.5 mA
VCC ≥ 2.7 V,
IOL = 4 mA
4mA type
VSS
-
-
V
V
VCC < 2.7 V,
IOL = 2 mA
L level
output voltage
VOL
VCC ≥ 2.7 V,
IOL = 10.5 mA
P80/P81
-
VSS
VCC < 2.7 V,
IOL = 5 mA
-
- 5
-
-
-
+ 5
μA
μA
Input leak
current
VCC = AVCC
AVRH = VSS
=
=
IIL
CEC0,
CEC1
+1.8
AVSS = 0.0 V
VCC ≥ 2.7 V
21
-
33
-
66
Pull-up
resistor value
RPU Pull-up pin
kΩ
VCC < 2.7 V
134
Other than
VCC,
Input
capacitance
VSS,
AVCC,
CIN
-
-
5
15
pF
AVSS,
AVRH
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4. AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Input frequency
Input clock cycle
Symbol
Conditions
Unit
Remarks
Min
4
Max
48
VCC ≥ 2.7 V
VCC < 2.7 V
When crystal oscillator
is connected
When using external
clock
When using external
clock
When using external
clock
MHz
MHz
ns
4
20
fCH
-
-
4
48
250
55
X0,
X1
tCYLH
-
20.83
45
Input clock pulse
width
PWH/tCYLH,
PWL/tCYLH
%
Input clock rising
time and falling
time
tCF,
tCR
When using external
clock
-
-
5
ns
fCM
fCC
-
-
-
-
-
-
40
40
MHz Master clock
Base clock
(HCLK/FCLK)
MHz
Internal operating
clock*1 frequency
fCP0
fCP1
fCP2
-
-
-
-
-
-
-
-
-
40
40
40
MHz APB0 bus clock*2
MHz APB1 bus clock*2
MHz APB2 bus clock*2
Base clock
tCYCC
-
-
25
-
ns
(HCLK/FCLK)
Internal operating
clock*1 cycle time
tCYCP0
tCYCP1
tCYCP2
-
-
-
-
-
-
25
25
25
-
-
-
ns
ns
ns
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral
Manual.
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data
sheet.
X0
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(2) Sub Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal
-
-
32.768
-
kHz oscillator is
connected
Input frequency
fCL
When using
external clock
When using
external clock
When using
external clock
-
-
32
10
45
-
-
-
100
31.25
55
kHz
X0A,
X1A
Input clock cycle
tCYLL
-
μs
Input clock pulse
width
PWH/tCYLL,
PWL/tCYLL
%
X0A
(3) Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
Remarks
Min
TA = + 25°C
VCC ≥ 2.7 V
3.96
4
4
4
4.04
TA = + 25°C
VCC < 2.7 V
When trimming*1
3.9
4.1
Clock frequency
fCRH
MHz
TA =
- 40°C to + 85°C
3.84
4.16
TA =
- 40°C to + 85°C
2.8
-
-
-
5.2
30
When not trimming
Frequency
stabilization time
2
tCRWT
-
μs
*
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature
trimming.
*2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value.
This period is able to use High-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
Remarks
Min
Clock frequency
fCRL
-
50
100
150
kHz
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(4-1) Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Parameter
PLL oscillation stabilization wait time*1
(LOCK UP time)
Symbol
Unit
Remarks
Min
Max
-
tLOCK
100
-
μs
PLL input clock frequency
PLL multiple rate
fPLLI
-
fPLLO
fCLKPLL
4
5
75
-
-
-
-
-
16
MHz
37 multiple
150
40
PLL macro oscillation clock frequency
MHz
MHz
Main PLL clock frequency*2
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family
Peripheral Manual.
(4-2) Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input
clock of the Main PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
fPLLI
-
fPLLO
fCLKPLL
3.8
19
72
-
4
-
-
4.2
MHz
35 multiple
150
40
PLL macro oscillation clock frequency
MHz
MHz
Main PLL clock frequency*2
-
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family
Peripheral Manual.
Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the
frequency/temperature has been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
Main PLL
clock
(CLKPLL)
PLL input
clock
PLL macro
oscillation clock
Main clock (CLKMO)
K
M
divider
Main
PLL
divider
High-speed CR clock (CLKHC)
N
divider
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D a t a S h e e t
(5) Reset Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
(6) Power-on Reset Timing
Parameter
(VCC= 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Symbol
Unit
Remarks
Min
0
Max
Power supply rising time
tVCCR
tOFF
-
-
ms
ms
Power supply shut down time
1
VCC
Time until releasing
Power-on reset
tPRT
1.34
16.09
ms
VCC_minimum
VDH_minimum
VCC
0.2V
tVCCR
0.2V
0.2V
tPRT
tOFF
Internal reset
Reset active
Release
start
CPU Operation
Glossary
・VCC_minimum: Minimum VCC of recommended operating conditions
・VDH_minimum: Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset
See 6. Low-Voltage Detection Characteristics
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D a t a S h e e t
(7) External Bus Timing
External bus clock output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
40
VCC ≥ 2.7 V
VCC < 2.7 V
-
-
MHz
MHz
Output frequency
tCYCLE
MCLKOUT*
20
*: The external bus clock output (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family
Peripheral Manual.
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
MCLKOUT
External bus signal input/output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol Conditions
Value
Unit
Remarks
VIH
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
V
V
V
V
Signal input characteristics
VIL
-
VOH
Signal output characteristics
VOL
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
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D a t a S h e e t
Separate Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tOEW
Pin name
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
MOEX
MOEX
MCLK×n-3
-
Min pulse width
MCSX ↓ → Address
output delay time
MOEX ↑ →
Address hold time
MCSX ↓ →
MOEX ↓ delay time
MOEX ↑ →
MCSX ↑ time
MCSX[7:0],
MAD[24:0]
MOEX,
-9
-12
+9
+12
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
MCLK×m+9
MCLK×m+12
MCLK×m-9 MCLK×m+9
0
MAD[24:0]
VCC < 2.7 V MCLK×m-12 MCLK×m+12
MOEX,
MCSX[7:0]
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
MCLK×m+9
MCLK×m+12
MCLK×m-9 MCLK×m+9
0
MCSX ↓ →
MCSX,
MDQM[1:0]
MOEX,
MADATA[15:0]
MOEX,
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MOEX ↑ →
Data hold time
MWEX
Min pulse width
MWEX ↑ → Address
output delay time
MCSX ↓ →
MWEX ↓ delay time
MWEX ↑ →
MCSX ↑ delay time
MCSX ↓→
MDQM ↓ delay time
MWEX ↓→
Data output time
MWEX ↑ →
VCC < 2.7 V MCLK×m-12 MCLK×m+12
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
30
38
-
-
tDH - OE
0
-
-
MADATA[15:0]
tWEW
MWEX
MCLK×n-3
MWEX,
MAD[24:0]
MCLK×m+9
MCLK×m+12
MCLK×n+9
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL - DV
tWEH - DX
0
MCLK×n-9
VCC < 2.7 V MCLK×n-12 MCLK×n+12
MWEX,
MCSX[7:0]
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
MCLK×m+9
MCLK×m+12
MCLK×n+9
0
MCSX,
MDQM[1:0]
MCSX,
MADATA[15:0]
MWEX,
MADATA[15:0]
MCLK×n-9
VCC < 2.7 V MCLK×n-12 MCLK×n+12
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MCLK-9
MCLK-12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
0
Data hold time
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
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D a t a S h e e t
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
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D a t a S h e e t
Separate Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tAV
Pin name
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
12
13
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC <2.7 V
VCC ≥ 2.7 V
VCC <2.7 V
MCLK,
MAD[24:0]
Address delay time
1
tCSL
1
1
1
1
12
12
MCLK,
MCSX[7:0]
MCSX delay time
MOEX delay time
tCSH
9
12
9
tREL
MCLK,
MOEX
tREH
tDS
12
24
37
Data set up →
MCLK ↑ time
MCLK ↑ →
MCLK,
MADATA[15:0]
MCLK,
-
tDH
0
-
Data hold time
MADATA[15:0]
9
12
9
12
9
12
9
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
1
MCLK,
MWEX
MWEX delay time
1
1
MDQM[1:0]
delay time
MCLK,
MDQM[1:0]
1
12
MCLK + 18
MCLK + 24
18
MCLK ↑ →
Data output time
MCLK ↑ →
MCLK,
MADATA[15:0]
MCLK,
MCLK + 1
1
Data hold time
MADATA[15:0]
24
Note: When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
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Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tALE-CHMADV
tCHMADH
Pin name
Conditions
Unit
ns
Min
Max
+10
+20
VCC ≥ 2.7 V
VCC < 2.7 V
Multiplexed
address delay time
Multiplexed
-2
MALE,
MADATA[15:0]
VCC ≥ 2.7 V MCLK×n+0 MCLK×n+10
VCC < 2.7 V MCLK×n+0 MCLK×n+20
ns
address hold time
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
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Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tCHAL
Pin name
Conditions
Unit Remarks
Min
Max
9
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
ns
ns
ns
ns
1
12
9
12
MCLK,
ALE
MALE delay time
tCHAH
1
1
MCLK ↑ →
Multiplexed
Address delay time
MCLK ↑ →
Multiplexed
Data output time
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
tCHMADV
tOD
ns
ns
MCLK,
MADATA[15:0]
tCHMADX
1
tOD
Note: When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
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External Ready Input Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol Pin name Conditions
Unit Remarks
Min
Max
MCLK ↑
MRDY input
setup time
VCC ≥ 2.7 V
23
MCLK,
MRDY
tRDYI
-
ns
VCC < 2.7 V
37
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
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(8) Base Timer Input Timing
Timer input timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
Parameter
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Symbol Pin name Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
TGIN)
tTRGH
tTRGL
,
Input pulse width
-
2tCYCP
-
ns
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see Block Diagram in this data
sheet.
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(9) CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Pin
VCC ≥ 2.7 V
Parameter
Serial clock cycle time
SCK ↓ → SOT delay time
Symbol
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx
Min
Max
Min
Max
tSCYC
4tCYCP
-
4tCYCP
-
tSLOVI
- 30
50
0
+ 30
- 20
36
0
+ 20
ns
Master mode
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock L pulse width
Serial clock H pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
tSHIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx,
SINx
2tCYCP
10
-
2tCYCP
10
-
SCKx
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
33
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in
this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
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tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
81
D a t a S h e e t
CSIO (SPI = 0, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Pin
VCC ≥ 2.7 V
Parameter
Serial clock cycle time
SCK ↑ → SOT delay time
Symbol
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx
Min
Max
Min
Max
tSCYC
4tCYCP
-
4tCYCP
-
tSHOVI
- 30
50
0
+ 30
- 20
36
0
+ 20
ns
Master mode
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
Serial clock L pulse width
Serial clock H pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
tSLIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx,
SINx
2tCYCP
10
-
2tCYCP
10
-
SCKx
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
33
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in
this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
82
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
83
D a t a S h e e t
CSIO (SPI = 1, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Pin
VCC ≥ 2.7 V
Parameter
Serial clock cycle time
SCK ↑ → SOT delay time
Symbol
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx Master mode
SCKx,
SINx
Min
Max
Min
Max
tSCYC
4tCYCP
-
4tCYCP
-
tSHOVI
- 30
50
0
+ 30
- 20
36
0
+ 20
ns
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
Serial clock L pulse width
Serial clock H pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tIVSLI
tSLIXI
tSOVLI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
SCKx,
SOTx
2tCYCP
34
-
2tCYCP
34
-
-
-
2tCYCP
10
-
2tCYCP
10
-
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
-
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
33
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in
this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
tF
VIH
VIH
SCK
SOT
SIN
VIL
VIL
tR
tSHOVE
VOH
VOL
*
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
85
D a t a S h e e t
CSIO (SPI = 1, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Pin
name
SCKx
VCC ≥ 2.7 V
Parameter
Symbol
Conditions
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYC
4tCYCP
-
4tCYCP
-
ns
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
Serial clock L pulse width
Serial clock H pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
tSHIXI
tSOVHI
tSLSH
50
0
-
-
36
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Master mode
2tCYCP
34
2tCYCP
10
tCYCP
10
-
2tCYCP
34
2tCYCP
10
tCYCP
10
-
-
-
-
-
SCKx
SCKx
-
-
+
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
33
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in
this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
86
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol Conditions
Unit Remarks
Min
Max
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
tSLSH
tSHSL
tF
tCYCP + 10
tCYCP + 10
-
-
5
5
ns
ns
ns
ns
CL = 30 pF
-
-
SCK rising time
tR
tF
tR
t
t
SLSH
SHSL
SCK
V
V
V
IH
IH
IH
VIL
VIL
V
IL
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
87
D a t a S h e e t
(10) External Input Timing
Parameter Symbol
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin name
Conditions
Unit
Remarks
Min
Max
A/D converter
trigger input
1
ADTG
-
2tCYCP
*
-
ns
tINH,
Input pulse width
tINL
*2
*3
2tCYCP + 100*1
500
-
-
ns
ns
INTxx,
NMIX
External interrupt
NMI
Deep standby
wake up
WKUPx
*4
600
-
ns
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Multi-function Timer is connected to, see Block Diagram in this
data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in Timer mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
(11) I2C Timing
Parameter
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Standard-mode Fast-mode
Symbol Conditions
Unit Remarks
Min
Max
Min
Max
SCL clock frequency
(Repeated) START
condition hold time
SDA ↓ → SCL ↓
FSCL
0
100
0
400 kHz
tHDSTA
4.0
-
0.6
-
μs
SCL clock L width
SCL clock H width
(Repeated) START
condition setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
CL = 30 pF,
R = (Vp/IOL)*1
tHDDAT
0
3.45*2
0
0.9*3 μs
tSUDAT
tSUSTO
250
4.0
-
-
100
0.6
-
-
ns
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
μs
Bus free time between
STOP condition and
START condition
Noise filter
tBUF
4.7
-
-
1.3
-
-
μs
4
4
tSP
-
2 tCYCP
*
2 tCYCP
*
ns
*1: R and C represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies
the requirement of tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
89
D a t a S h e e t
(12) ETM Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Min Max
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
2
11
TRACECLK,
TRACED[3:0]
Data hold
tETMH
ns
2
15
-
40 MHz
20 MHz
TRACECLK
frequency
1/ tTRACE
-
TRACECLK
25
50
-
-
ns
ns
TRACECLK
clock cycle
tTRACE
Note: When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
(13) JTAG Timing
Parameter
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Symbol Pin name Conditions
Unit
ns
Remarks
Min
Max
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
TMS, TDI setup
time
TCK,
TMS, TDI
tJTAGS
15
-
TCK,
TMS, TDI
TMS, TDI hold time tJTAGH
TDO delay time tJTAGD
15
-
ns
-
-
25
45
TCK,
TDO
ns
VCC < 2.7 V
Note: When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
91
D a t a S h e e t
5. 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
-
Pin
name
Parameter
Symbol
Unit
Remarks
Min
-
-
Max
12
± 4.5
Resolution
Integral Nonlinearity
Differential
-
-
-
-
bit
LSB
± 2
-
-
-
-
-
± 2.2
± 6
± 2.5
± 15
LSB
mV
Nonlinearity
Zero transition voltage
Full-scale transition
voltage
VZT
VFST
ANxx
ANxx
AVRH ± 6 AVRH ± 15 mV
2.0*1
4.0*1
10*1
0.6
1.2
3.0
100
200
500
-
-
-
-
-
-
-
-
-
AVCC ≥ 2.7 V
Conversion time
Sampling time*2
-
-
-
-
μs
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
tS
10
us
Compare clock
cycle*3
tCCK
-
1000
1.0
ns
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
State transition time to
operation permission
Power supply current
(analog + digital)
Reference power
supply current
(between AVRH to
AVSS)
Analog input capacity
tSTT
-
-
-
-
μs
-
-
0.27
0.03
0.42
10
mA
μA
A/D 1unit operation
When A/D stops
A/D 1unit operation
AVRH=3.6 V
AVCC
-
0.72
1.29
2.6
mA
-
AVRH
-
-
0.02
-
μA
When A/D stops
CAIN
RAIN
-
-
9.4
2.2
5.5
10.5
4
pF
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
Analog input resistor
-
-
kΩ
Interchannel disparity
Analog port input
current
-
-
-
-
-
-
-
-
-
-
-
LSB
μA
V
ANxx
ANxx
AVRH
5
Analog input voltage
AVSS
2.7
AVCC
AVRH
AVCC
AVCC ≥ 2.7 V
AVCC < 2.7 V
Reference voltage
V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 2.7 V, HCLK=40 MHz
1.8 V < AVCC < 2.7 V, HCLK=40 MHz
sampling time: 0.6 μs, compare time: 1.4 μs
sampling time: 1.2 μs, compare time: 2.8 μs
1.65 V < AVCC < 1.8 V, HCLK=40 MHz sampling time: 3 μs, compare time: 7 μs
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and the compare clock cycle, see Chapter 1-1: A/D Converter in FM3
Family Peripheral Manual Analog Macro Port.
The register setting of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see Block Diagram in this data
sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
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D a t a S h e e t
Comparator
ANxx
Analog input pin
REXT
RAIN
Analog
signal source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
Sampling time[ns]
RAIN
:
input resistor of A/D[kΩ] = 2.2 kΩ at 2.7 V < AVCC < 3.6 V
input resistor of A/D[kΩ] = 5.5 kΩ at 1.8 V < AVCC < 2.7 V
input resistor of A/D[kΩ] = 10.5 kΩ at 1.65 V < AVCC < 1.8 V
input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V
Output impedance of external circuit[kΩ]
CAIN
REXT
:
:
(Equation 2) tC = tCCK × 14
tC:
tCCK
Compare time
Compare clock cycle
:
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
93
D a t a S h e e t
Definition of 12-bit A/D Converter Terms
Resolution:
Integral Nonlinearity:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition
point (0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to
change the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
characteristics
0xFFE
0x(N+1)
0xN
{1 LSB(N-1) + VZT}
0xFFD
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
VZT
Actual conversion characteristics
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Linearity error of digital output N =
[LSB]
V(N + 1) T - VNT
Differential linearity error of digital output N =
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT: Voltage at which the digital output changes from 0x000 to 0x001.
VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.
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MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
6. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Value
Typ
1.50
1.55
1.55
Parameter
Symbol
Conditions
SVHR*1 = 00000
SVHR*1 = 00001
SVHR*1 = 00010
SVHR*1 = 00011
SVHR*1 = 00100
SVHR*1 = 00101
SVHR*1 = 00110
SVHR*1 = 00111
SVHR*1 = 01000
SVHR*1 = 01001
SVHR*1 = 01010
SVHR*1 = 01011
SVHR*1 = 01100
SVHR*1 = 01101
SVHR*1 = 01110
SVHR*1 = 01111
SVHR*1 = 10000
SVHR*1 = 10001
SVHR*1 = 10010
SVHR*1 = 10011
-
Unit
Remarks
Min
1.38
1.43
1.43
Max
1.60
1.65
1.65
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
LVD stabilization
wait time
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
Same as SVHR = 00000 value
1.47 1.60 1.73
Same as SVHR = 00000 value
1.52 1.65 1.78
Same as SVHR = 00000 value
1.56 1.70 1.84
Same as SVHR = 00000 value
1.61 1.75 1.89
Same as SVHR = 00000 value
1.66 1.80 1.94
Same as SVHR = 00000 value
1.70 1.85 2.00
Same as SVHR = 00000 value
1.75 1.90 2.05
Same as SVHR = 00000 value
1.79 1.95 2.11
Same as SVHR = 00000 value
1.84 2.00 2.16
Same as SVHR = 00000 value
1.89 2.05 2.21
Same as SVHR = 00000 value
2.30 2.50 2.70
Same as SVHR = 00000 value
2.39 2.60 2.81
Same as SVHR = 00000 value
2.48 2.70 2.92
Same as SVHR = 00000 value
2.58 2.80 3.02
Same as SVHR = 00000 value
2.67 2.90 3.13
Same as SVHR = 00000 value
2.76 3.00 3.24
Same as SVHR = 00000 value
2.85 3.10 3.35
Same as SVHR = 00000 value
2.94 3.20 3.46
Same as SVHR = 00000 value
5200 ×
tLVDW
-
-
μs
μs
2
tCYCP
*
LVD detection
delay time
tLVDDL
-
-
-
200
*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to 00000 by
Low-Voltage Detection Reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
95
D a t a S h e e t
(2) Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Value
Min Typ Max
Parameter
Symbol Conditions
Unit
Remarks
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
LVD stabilization
wait time
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
1.56
1.61
1.61
1.66
1.66
1.70
1.70
1.75
1.75
1.79
1.79
1.84
1.84
1.89
1.89
1.93
2.30
2.39
2.39
2.48
2.48
2.58
2.58
2.67
2.67
2.76
2.76
2.85
2.85
2.94
2.94
3.04
1.70
1.75
1.75
1.80
1.80
1.85
1.85
1.90
1.90
1.95
1.95
2.00
2.00
2.05
2.05
2.10
2.50
2.60
2.60
2.70
2.70
2.80
2.80
2.90
2.90
3.00
3.00
3.10
3.10
3.20
3.20
3.30
1.84
1.89
1.89
1.94
1.94
2.00
2.00
2.05
2.05
2.11
2.11
2.16
2.16
2.21
2.21
2.27
2.70
2.81
2.81
2.92
2.92
3.02
3.02
3.13
3.13
3.24
3.24
3.35
3.35
3.46
3.46
3.56
5200 ×
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
SVHI = 01011
SVHI = 01100
SVHI = 01101
SVHI = 01110
SVHI = 01111
SVHI = 10000
SVHI = 10001
SVHI = 10010
SVHI = 10011
-
tLVDW
-
-
-
-
μs
μs
tCYCP
*
LVD detection delay
time
tLVDDL
-
200
*: tCYCP indicates the APB2 bus clock cycle time.
96
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
7. Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(VCC = 1.65V to 3.6V, TA = - 40°C to + 85°C)
Value
Parameter
Unit
Remarks
Typ*
Max*
Large Sector
Small Sector
1.1
2.7
Sector erase
time
Includes write time prior to internal
erase
s
0.3
30
0.9
Half word (16-bit)
write time
Not including system-level overhead
time
Includes write time prior to internal
erase
528
18
μs
Chip erase time
6.8
s
*: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle
of erase/write.
(2) Write cycles and data hold time
Erase/write cycles (cycle) Data hold time (year)
Remarks
1,000
10,000
20*
10*
*: At average + 85C
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
97
D a t a S h e e t
8. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
・Return Count Time
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
tCYCC
Sleep mode
μs
High-speed CR Timer mode,
Main Timer mode,
40
80
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
350
690
700
880
μs
μs
tICNT
RTC mode,
Stop mode
278
523
μs
318
278
603
523
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
*: The maximum value depends on the accuracy of built-in CR.
・Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
98
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
・Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
・When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3
Family Peripheral Manual.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
99
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
・Return Count Time
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
148
263
μs
High-speed CR Timer mode,
Main Timer mode,
148
263
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
258
322
278
483
516
523
μs
μs
μs
tRCNT
RTC/Stop mode
318
278
603
523
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
*: The maximum value depends on the accuracy of built-in CR.
・Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
100
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
・Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
・When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3
Family Peripheral Manual.
・The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on
Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time
during the power-on reset/low-voltage detection reset.
・When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait
time or the Main PLL clock stabilization wait time.
・The internal resource reset means the watchdog reset and the CSV reset.
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
101
D a t a S h e e t
Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Main: 64 Kbyte
Work: 32 Kbyte
MB9AF141LBPMC1-G-JNE2
MB9AF142LBPMC1-G-JNE2
MB9AF144LBPMC1-G-JNE2
MB9AF141LBPMC-G-JNE2
MB9AF142LBPMC-G-JNE2
MB9AF144LBPMC-G-JNE2
MB9AF141LBQN-G-AVE2
MB9AF142LBQN-G-AVE2
MB9AF144LBQN-G-AVE2
MB9AF141MBPMC-G-JNE2
MB9AF142MBPMC-G-JNE2
MB9AF144MBPMC-G-JNE2
MB9AF141MBPMC1-G-JNE2
MB9AF142MBPMC1-G-JNE2
MB9AF144MBPMC1-G-JNE2
MB9AF141MBBGL-GE1
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
Plastic LQFP 64-pin
(0.5mm pitch),
Main: 128 Kbyte
Work: 32 Kbyte
(FPT-64P-M38)
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic LQFP 64-pin
(0.65mm pitch),
Main: 128 Kbyte
Work: 32 Kbyte
(FPT-64P-M39)
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic QFN 64-pin
(0.5mm pitch),
(LCC-64P-M24)
Main: 128 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic LQFP 80-pin
(0.5mm pitch),
Main: 128 Kbyte
Work: 32 Kbyte
Tray
(FPT-80P-M37)
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic LQFP 80-pin
(0.65mm pitch),
Main: 128 Kbyte
Work: 32 Kbyte
(FPT-80P-M40)
Main: 256 Kbyte
Work: 32 Kbyte
Main: 64 Kbyte
Work: 32 Kbyte
Plastic PFBGA 96-pin
(0.5mm pitch),
Main: 128 Kbyte
Work: 32 Kbyte
MB9AF142MBBGL-GE1
(BGA-96P-M07)
Main: 256 Kbyte
Work: 32 Kbyte
MB9AF144MBBGL-GE1
Main: 64 Kbyte
Work: 32 Kbyte
MB9AF141NBPMC-G-JNE2
MB9AF142NBPMC-G-JNE2
MB9AF144NBPMC-G-JNE2
Plastic LQFP 100-pin
(0.5mm pitch),
Main: 128 Kbyte
Work: 32 Kbyte
(FPT-100P-M23)
Main: 256 Kbyte
Work: 32 Kbyte
102
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Main: 64 Kbyte
Work: 32 Kbyte
MB9AF141NBPQC-G-JNE2
MB9AF142NBPQC-G-JNE2
MB9AF144NBPQC-G-JNE2
MB9AF141NBBGL-GE1
MB9AF142NBBGL-GE1
MB9AF144NBBGL-GE1
16 Kbyte
16 Kbyte
32 Kbyte
16 Kbyte
16 Kbyte
32 Kbyte
Plastic QFP 100-pin
(0.65mm pitch),
(FPT-100P-M36)
Main: 128 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Tray
Main: 64 Kbyte
Work: 32 Kbyte
Plastic PFBGA 112-pin
(0.8mm pitch),
Main: 128 Kbyte
Work: 32 Kbyte
(BGA-112P-M04)
Main: 256 Kbyte
Work: 32 Kbyte
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
103
D a t a S h e e t
Package Dimensions
100-pin plastic LQFP
Lead pitch
0.50 mm
14.00 mm × 14.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.65 g
Sealing method
Mounting height
Weight
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
1.50
-0.10
+.008
.059
-.004
(
)
(Mounting height)
INDEX
0°~8°
0.10±0.10
(.004±.004)
(Stand off)
100
26
0.50±0.20
(.020±.008)
"A"
0.25(.010)
0.60±0.15
1
25
(.024±.006)
0.50(.020)
0.22±0.05
(.009±.002)
0.145±0.055
(.006±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note:The values in parenthesesare reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
104
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
100-pin plastic QFP
Lead pitch
0.65 mm
14.00 mm × 20.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
3.35 mm MAX
Code
(Reference)
P-QFP100-14 × 20-0.65
(FPT-100P-M36)
100-pin plastic QFP
(FPT-100P-M36)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
*
80
51
81
50
0.10(.004)
17.90± 0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
31
0.25(.010)
3.00+–00.3250
.118+–..001048
(Mounting height)
0~8°
1
30
0.65(.026)
0.32 ± 0.05
(.013±.002)
0.17 ± 0.06
(.007 ±. 002)
M
0.13(.005)
0.25 ± 0.20
(.010 ±. 008)
(Stand off)
0.80 ± 0.20
(.031 ±. 008)
0.88 ± 0.15
"A"
(.035 ±. 006)
Dimensions in mm (inches).
Note: The valuesin parentheses are referencevalues.
C
2011 FUJITSU SEMICONDUCTOR LIMITED HMbF100-36Sc-1-1
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
105
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.50 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.47 g
Sealing method
Mounting height
Weight
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551± .008)SQ
*12.00± 0.10(.472± .004)SQ
0.145± 0.055
(.006± .002)
60
41
Details of "A" part
61
40
1.50–+00..1200
(Mounting height)
.059+–..000048
0.25(.010)
0~8°
0.08(.003)
0.50± 0.20
(.020± .008)
0.60± 0.15
0.10± 0.05
(.004± .002)
(Stand off)
(.024± .006)
INDEX
80
21
"A"
1
20
0.50(.020)
0.22± 0.05
M
0.08(.003)
(.009± .002)
Dimensions in mm (inches).
C
Note: The values in parentheses are reference values.
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
106
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.65 mm
14.00 mm × 14.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Plastic mold
1.60 mm Max.
Code
(Reference)
P-LQFP80-14 × 14-0.65
(FPT-80P-M40)
80-pin plastic LQFP
(FPT-80P-M40)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
0.145±0.055
(.006±.002)
60
41
Details of "A" part
61
40
1.50±0.10
(.059±.004)
0.25(.010)
0.10(.004)
0˚~7˚
INDEX
0.50±0.20
(.020±.008)
0.10±0.05
80
21
(.004±.002)
0.60±0.15
(.024±.006)
20
1
0.65(.026)
0.32±0.06
M
0.13(.005)
(.013±.002)
Dimensions in mm (inches).
Note: The values in parentheses are referencevalues.
C
2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
107
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.50 mm
10.00 mm × 10.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.32 g
Sealing method
Mounting height
Weight
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
0.145 ± 0.055
(.006 ± .002)
48
33
Details of "A" part
49
32
1.50–+00..1200
0.08(.003)
(Mounting height)
.059+–..000084
0.25(.010)
0~8°
INDEX
0.50±0.20
(.020±.008)
0.60 ± 0.15
(.024±.006)
0.10 ± 0.10
(.004±.004)
(Stand off)
64
17
"A"
1
16
0.50(.020)
0.22±0.05
M
0.08(.003)
(.009±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
108
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.65 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm MAX
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
48
33
Details of "A" part
49
32
1.50–+00..1200
.059–+..000048
0~8˚
0.10(.004)
0.10±0.10
(.004±.004)
INDEX
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)BSC
64
17
1
16
"A"
0.65(.026)
0.32±0.05
(.013±.002)
M
0.13(.005)
C
Dimensions in mm (inches).
Note: The values in parentheses are referencevalues.
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
June 10, 2015, MB9A140NB_DS706-00040-4v0-E
109
D a t a S h e e t
64-pin plastic QFN
Lead pitch
0.50 mm
9.00 mm × 9.00 mm
Plastic mold
0.90 mm MAX
-
Package width ×
package length
Sealing method
Mounting height
Weight
(LCC-64P-M24)
64-pin plastic QFN
(LCC-64P-M24)
9.00±0.10
(.354±.004)
6.00±0.10
(.236±.004)
0.25±0.05
(.010±.002)
6.00±0.10
(.236±.004)
9.00±0.10
(.354±.004)
INDEX AREA
0.45 (.018)
1PIN ID
(0.20R (.008R))
0.50 (.020)
(TYP)
0.40±0.05
(.016±.002)
0.85±0.05
(.033±.002)
0.05 (.002) MAX
(0.20 (.008))
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1
110
MB9A140NB_DS706-00040-4v0-E, June 10, 2015
D a t a S h e e t
112-ball plastic PFBGA
Ball pitch
0.80 mm
10.00 × 10.00 mm
Soldering ball
Plastic mold
Ф 0.45 mm
Package width ×
package length
Lead shape
Sealing method
Ball size
Mounting height
Weight
1.45 mm Max.
0.22 g
(BGA-112P-M04)
112-ball plastic PFBGA
(BGA-112P-M04)
10.00±0.10(.394±.004)
0.20(.008) S
B
0.80(.031)
REF
B
11
10
9
0.80(.031)
REF
8
A
7
10.00±0.10
(.394±.004)
6
5
4
3
2
1
L
K
J
H
G
F
E D
C
B
A
(INDEX AREA)
0.20(.008) S
1.25±0.20
(.049±.008)
(Seated height)
INDEX
0.35±0.10
(.014±.004)
(Stand off)
A
112-Ф0.45±010
(112-Ф0.18±.004)
M
Ф0.08(.003) S A B
S
0.10(.004) S
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3
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96-pin plastic FBGA
Lead pitch
0.5 mm
6.00 mm × 6.00 mm
Ball
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.30 mm MAX
0.08 g
(BGA-96P-M07)
96-pin plastic FBGA
(BGA-96P-M07)
5.00(.197)
REF
B
6.00±0.10(.236±.004)
0.50
(.020)
TYP
0.20(.008) S
B
11
10
9
8
A
7
5.00(.197)
REF
6.00±0.10
(.236±.004)
6
5
0.50(.020)
TYP
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
(INDEX AREA)
0.20(.008) S
INDEX
A
96-ø0.30±0.10
(96-ø.012±.004)
M
ø0.05(.002)
S A B
S
1.15±0.15
(.045±.006)
(Seated height)
0.08(.003) S
0.25±0.10
(.010±.004)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2012 FUJITSU SEMICONDUCTOR LIMITED B96007S-c-1-1
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Major Changes
Page
Section
Change Results
Revision 2.0
FEATURE
On-chip Memories
Unique ID
PRODUCT LINEUP
Function
Revised the descriptions of [Flash memory].
Added the descriptions of "Unique ID".
2
5
6
Added the descriptions.
48
53
HANDLING DEVICES
MEMORY MAP
Memory Map (2)
PIN STATUS IN EACH CPU STATE
List of Pin Status
ELECTRICAL CHARACTERISTICS
3.DC Characteristics
Revised the Pin status type of "I".
58
65
Revised the descriptions of Power supply current.
Added the "Flash memory write/erase current".
Added the footnote.
(1) Current rating
4.AC Characteristics
Revised the table and the footnote.
69
(3) Built-in CR Oscillation Characteristics
Built-in high-speed CR
(7) External Bus Timing
Separate Bus Access Asynchronous
SRAM Mode
Revised the table and the figure.
73, 74
75
Separate Bus Access Synchronous SRAM Mode
80, 82,
84, 86
89
Revised the title to "CSIO Timing".
Revised the note.
Revised the footnote.
(9) CSIO Timing
(11) I2C Timing
• Revised the parameter.
• Revised the symbol.
• Corrected the value.
5. 12-bit A/D Converter
• Electrical Characteristics for the A/D Converter
92
• Revised the parameter.
• Revised the symbol.
94
• Definition of 12-bit A/D Converter Terms
• Corrected "Conditions" and "Value" in the table.
• Added the Item.
• Added the footnote.
6. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
95
96
Added the Item.
(2) Interrupt of Low-Voltage Detection
Revision 2.1
-
-
Company name and layout design change
Revision 3.0
Corrected the Series name.
-
-
-
-
MB9A140NA Series → MB9A140NB Series
Corrected the Product name as follows.
MB9AF144LB, MB9AF142LB, MB9AF141LB
MB9AF144MB, MB9AF142MB, MB9AF141MB
MB9AF144NB, MB9AF142NB, MB9AF141NB
Added the Item.
FEATURES
2
3
•External Bus Interface
•Multi-function Serial Interface
PRODUCT LINEUP
•Function
• Maximum area size : Up to 256 Mbytes
Corrected the description of "I2C"
6
Added the footnote
51
52
BLOCK DIAGRAM
MEMORY MAP
•Memory Map (1)
Corrected the figure
Corrected the address "External Device Area"
ELECTRICAL CHARACTERISTICS
2.Recommended Operating Conditions
3.DC Characteristics
63
Add the footnote
•Corrected the Condition
•Delete the minmun value
•Corrected the remarks
•Add the footnote
(1)Current rating
64,65
(9)CSIO Timing
•Synchronous serial (SPI=1, SCINV=1)
(9) CSIO Timing
• External clock(EXT=1):asyntironous only
(12)I2C Timing
Corrected the figure of "MS bit=1"
Corrected the figure
86
88
Corrected the description as follows.
•Typical mode → Standard-mode
•High-speed mode→ Fast-mode
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D a t a S h e e t
Page
Section
5.12-bit A/D Converter
•Electrical Characteristics for
the A/D Converter
Change Results
•Corrected the terminal name
AN00 ~ AN23 → ANxx
•Corrected the minmum value of "Sampling time"
•Corrected the max and min value of "State transition time to
oprerationpermission"
91
•Corrected the footnote
ORDERING INFORMATON
98
Corrected the "Part number"
Revision 4.0
Memory Map
· Memory map(2)
53
Added the summary of Flash memory sector and the note
Electrical Characteristics
3. DC Characteristics
(1) Current rating
· Changed the table format
· Added Main Timer mode current
· Moved A/D Converter Current
64 - 66
Electrical Characteristics
3. DC Characteristics
(2) Pin Characteristics
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
4. AC Characteristics
67
70
Added input leak current of CEC pin at power off.
Added the figure of Main PLL connection
· Added Time until releasing Power-on reset
· Changed the figure of timing
71
80 - 87
92
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition voltage
· Added Conversion time at AVcc < 2.7V
(9) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Electrical Characteristics
8. Return Time from Low-Power Consumption
Mode
98 - 101
102, 103
Added Return Time from Low-Power Consumption Mode
Changed notation of part number
Ordering Information
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
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The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2013-2015 Cypress All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM
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,
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
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118
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