MB9AF144NBPMC-G-JNE2 [CYPRESS]
32-bit ARM® Cortex®-M3 FM3 Microcontroller;
| 型号： | MB9AF144NBPMC-G-JNE2 |
| 厂家： | 
CYPRESS |
| 描述： | 32-bit ARM® Cortex®-M3 FM3 Microcontroller 微控制器 |
| 文件： | 总118页 (文件大小：2168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MB9A140NB Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9A140NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I2C).
The products which are described in this datasheet are placed into TYPE6 product categories in FM3 Family Peripheral Manual.
Features
32-bit ARM® Cortex®-M3 Core
Processor version: r2p1
External Bus Interface*
Supports SRAM, NOR Flash memory device
Up to 8 chip selects
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC):
1 NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size: Up to 256 MB
Supports Address/Data multiplex
24-bit System timer (Sys Tick): System timer for OS task
management
Supports external RDY function
*: MB9AF141LB, F142LB and F144LB do not support
External Bus Interface.
On-chip Memories
[Flash memory]
Dual operation Flash memory
Multi-function Serial Interface (Max 8 channels)
Dual Operation Flash memory has the upper bank and the
lower bank.
4 channels with 16 steps×9-bit FIFO (ch.4 to ch.7), 4
channels without FIFO (ch.0 to ch.3)
So, this series could implement erase, write and read
operations
for each bank simultaneously.
Operation mode is selectable from the followings for each
channel.
UART
CSIO
I2C
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank
+ 16 Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
[UART]
Security function for code protection
Full-duplex double buffer
[SRAM]
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
*
Hardware Flow control : Automatically control the
SRAM0: Up to 16 KB
SRAM1: Up to 16 KB
transmission by CTS/RTS (only ch.4)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
*: MB9AF141LB, F142LB and F144LB do not support
Hardware Flow control.
Cypress Semiconductor Corporation
Document Number: 002-05637 Rev.*B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 1, 2017
MB9A140NB Series
[CSIO]
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
Capable of pull-up control per pin
[I2C]
Capable of reading pin level directly
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
Built-in the port relocate function
Up to 83 fast general-purpose I/O Ports@100 pin Package
DMA Controller (8 channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
Some ports are 5 V tolerant I/O.
See Pin Description to confirm the corresponding pins.
8 independently configured and operated channels
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Transfer can be started by software or request from the
built-in peripherals
Operation mode is selectable from the followings for each
channel.
Transfer address area: 32-bit (4 GB)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Free-running
Periodic (=Reload)
One-shot
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
HDMI-CEC/Remote Control Receiver (Up to 2
channels)
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
HDMI-CEC transmitter
Header block automatic transmission by judging Signal
free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output
CEC transmission by setting 1 byte data
Successive Approximation type
Built-in 2 units
Conversion time: 2.0 μs @ 2.7 V to 3.6 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Generating transmission status interrupt when transmitting
1 block (1 byte data and EOM/ACK)
HDMI-CEC receiver
Automatic ACK reply function available
Line error detection function available
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
Remote control receiver
4 bytes reception buffer
Repeat code detection function available
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Document Number: 002-05637 Rev.*B
Page 2 of 118
MB9A140NB Series
Real-time clock (RTC)
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Built-in high-speed CR Clock: 4 MHz
Built-in low-speed CR Clock: 100 kHz
Main PLL Clock
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
[Resets]
Watch Counter
The Watch counter is used for wake up from sleep and timer
mode.
Reset requests from INITX pin
Power on reset
Software reset
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
External Interrupt Controller Unit
Up to 16 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
External clock failure (clock stop) is detected, reset is
asserted.
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
External frequency anomaly is detected, interrupt or reset is
asserted.
The Hardware watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the Hardware watchdog is
active in any low-power consumption modes except RTC, Stop,
Deep Standby RTC and Deep Standby Stop modes.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Document Number: 002-05637 Rev.*B
Page 3 of 118
MB9A140NB Series
Low-Power Consumption Mode
Six low-power consumption modes supported.
Debug
Sleep
Timer
RTC
Stop
Serial Wire JTAG Debug Port (SWJ-DP)
*
Embedded Trace Macrocells (ETM)
*: MB9AF141LB/MB, F142LB/MB and F144LB/MB support
only SWJ-DP.
Unique ID
Unique value of the device (41-bit) is set.
Deep Standby RTC (selectable between keeping the value of
RAM and not)
Deep Standby Stop (selectable between keeping the value of
RAM and not)
Power Supply
Wide range voltage: VCC = 1.65 V to 3.6 V
Document Number: 002-05637 Rev.*B
Page 4 of 118
MB9A140NB Series
Contents
1. Product Lineup.................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 16
5. I/O Circuit Type................................................................................................................................................................ 39
6. Handling Precaution ....................................................................................................................................................... 44
7. Handling Devices ............................................................................................................................................................ 47
8. Block Diagram................................................................................................................................................................. 49
9. Memory Size .................................................................................................................................................................... 50
10. Memory Map .................................................................................................................................................................... 50
11. Pin Status in Each CPU State ........................................................................................................................................ 53
12. Electrical Characteristics ............................................................................................................................................... 60
12.1 Absolute Maximum Ratings......................................................................................................................................... 60
12.2 Recommended Operating Conditions.......................................................................................................................... 61
12.3 DC Characteristics....................................................................................................................................................... 62
12.3.1 Current Rating.............................................................................................................................................................. 62
12.3.2 Pin Characteristics ....................................................................................................................................................... 65
12.4 AC Characteristics....................................................................................................................................................... 66
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 66
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 67
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 67
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL).................................................. 68
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock
of the Main PLL)........................................................................................................................................................... 68
12.4.6 Reset Input Characteristics .......................................................................................................................................... 69
12.4.7 Power-on Reset Timing................................................................................................................................................ 69
12.4.8 External Bus Timing..................................................................................................................................................... 70
12.4.9 Base Timer Input Timing.............................................................................................................................................. 77
12.4.10 CSIO/UART Timing .................................................................................................................................................. 78
12.4.11 External Input Timing................................................................................................................................................ 86
12.4.12 I2C Timing................................................................................................................................................................. 87
12.4.13 ETM Timing .............................................................................................................................................................. 88
12.4.14 JTAG Timing............................................................................................................................................................. 89
12.5 12-bit A/D Converter.................................................................................................................................................... 90
12.6 Low-Voltage Detection Characteristics........................................................................................................................ 93
12.6.1 Low-Voltage Detection Reset....................................................................................................................................... 93
12.6.2 Interrupt of Low-Voltage Detection............................................................................................................................... 94
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 95
12.7.1 Write / Erase time......................................................................................................................................................... 95
12.7.2 Erase/write cycles and data hold time.......................................................................................................................... 95
12.8 Return Time from Low-Power Consumption Mode...................................................................................................... 96
12.8.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 96
12.8.2 Return Factor: Reset.................................................................................................................................................... 98
13. Ordering Information .................................................................................................................................................... 100
14. Package Dimensions .................................................................................................................................................... 102
15. Errata.............................................................................................................................................................................. 111
16. Major Changes .............................................................................................................................................................. 115
Document Number: 002-05637 Rev.*B
Page 5 of 118
MB9A140NB Series
Document History............................................................................................................................................................... 117
Sales, Solutions, and Legal Information........................................................................................................................... 118
Document Number: 002-05637 Rev.*B
Page 6 of 118
MB9A140NB Series
1. Product Lineup
Memory Size
Product name
MB9AF141LB/MB/NB
MB9AF142LB/MB/NB
MB9AF144LB/MB/NB
On-chip
Flash
memory
Main area
64 KB
128 KB
256 KB
Work area
32 KB
32 KB
32 KB
SRAM0
8 KB
8 KB
16 KB
On-chip
SRAM
SRAM1
Total
8 KB
16 KB
8 KB
16 KB
16 KB
32 KB
Function
MB9AF141LB
MB9AF142LB
MB9AF144LB
MB9AF141MB
MB9AF142MB
MB9AF144MB
MB9AF141NB
MB9AF142NB
MB9AF144NB
Product name
Pin count
CPU
64
80/96
Cortex-M3
40 MHz
100/112
Freq.
Power supply voltage range
DMAC
1.65 V to 3.6 V
8 ch.
Addr: 21-bit (Max)
R/W Data: 8-bit (Max)
CS: 4 (Max)
Addr: 25-bit (Max)
R/W Data: 8-/16-bit (Max)
CS: 8 (Max)
External Bus Interface
-
Support: SRAM, NOR Flash
memory
Support: SRAM,
NOR Flash memory
8 ch. (Max)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
Multi-function Serial Interface
(UART/CSIO/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
8 ch. (Max)
Dual Timer
1 unit
HDMI-CEC/ Remote Control Receiver
Real-Time Clock
2 ch. (Max)
1 unit
Watch Counter
1 unit
CRC Accelerator
Yes
Watchdog timer
1ch. (SW) + 1ch. (HW)
11 pins (Max) +
NMI × 1
8 pins (Max) +
NMI × 1
16 pins (Max) +
NMI × 1
External Interrupts
I/O ports
51 pins (Max)
12 ch. (2 units)
66 pins (Max)
17 ch. (2 units)
Yes
83 pins (Max)
24 ch. (2 units)
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
2 ch.
High-speed
Low-speed
4 MHz
100 kHz
Built-in CR
Debug Function
Unique ID
SWJ-DP
SWJ-DP/ETM
Yes
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See 12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Built-in CR Oscillation Characteristics for accuracy of built-in
CR.
Document Number: 002-05637 Rev.*B
Page 7 of 118
MB9A140NB Series
2. Packages
MB9AF141LB
MB9AF142LB
MB9AF144LB
MB9AF141MB
MB9AF142MB
MB9AF144MB
MB9AF141NB
MB9AF142NB
MB9AF144NB
Product name
Package
LQFP: LQD064 (0.5 mm pitch)
LQFP: LQG064 (0.65 mm pitch)
QFN: VNC064 (0.5 mm pitch)
LQFP: LQH080 (0.5 mm pitch)
LQFP: LQJ080 (0.65 mm pitch)
BGA: FDG096 (0.5 mm pitch)
LQFP: LQI100 (0.5 mm pitch)
QFP: PQH100 (0.65 mm pitch)
BGA: LBC112 (0.8 mm pitch)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
: Supported
Note:
−
See “14. Package Dimensions” for detailed information on each package.
Document Number: 002-05637 Rev.*B
Page 8 of 118
MB9A140NB Series
3. Pin Assignment
LQI100
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
75 VSS
P50/INT00_0/SIN3_1/MADATA00_1
P51/INT01_0/SOT3_1/MADATA01_1
P52/INT02_0/SCK3_1/MADATA02_1
P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1
P54/SOT6_0/TIOB1_2/MADATA04_1
P55/SCK6_0/ADTG_1/MADATA05_1
P56/INT08_2/MADATA06_1
74 P20/AN19/INT05_0/CROUT_0/MAD24_1
73 P21/AN18/SIN0_0/INT06_1/WKUP2
72 P22/AN17/SOT0_0/TIOB7_1
71 P23/AN16/SCK0_0/TIOA7_1
70 P1F/AN15/ADTG_5/MAD23_1
69 P1E/AN14/RTS4_1/MAD22_1
68 P1D/AN13/CTS4_1/MAD21_1
67 P1C/AN12/SCK4_1/MAD20_1
66 P1B/AN11/SOT4_1/MAD19_1
65 P1A/AN10/SIN4_1/INT05_1/MAD18_1
64 P19/AN09/SCK2_2/MAD17_1
63 P18/AN08/SOT2_2/MAD16_1
62 AVSS
P30/TIOB0_1/INT03_2/MADATA07_1
P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10
P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12
P34/TIOB4_1/MADATA11_1 13
P35/TIOB5_1/INT08_1/MADATA12_1 14
P36/SIN5_2/INT09_1/MADATA13_1 15
P37/SOT5_2/INT10_1/MADATA14_1 16
P38/SCK5_2/INT11_1/MADATA15_1 17
P39/ADTG_2 18
LQFP - 100
61 AVRH
60 AVCC
59 P17/AN07/SIN2_2/INT04_1/MAD15_1
58 P16/AN06/SCK0_1/MAD14_1
57 P15/AN05/SOT0_1/MAD13_1
56 P14/AN04/SIN0_1/INT03_1/MAD12_1
55 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1
54 P12/AN02/SOT1_1/MAD10_1
53 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1
52 P10/AN00
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 19
P3B/TIOA1_1 20
P3C/TIOA2_1 21
P3D/TIOA3_1 22
P3E/TIOA4_1 23
P3F/TIOA5_1 24
VSS 25
51 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05637 Rev.*B
Page 9 of 118
MB9A140NB Series
PQH100
(TOP VIEW)
P51/INT01_0/SOT3_1/MADATA01_1 81
P52/INT02_0/SCK3_1/MADATA02_1 82
P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1 83
P54/SOT6_0/TIOB1_2/MADATA04_1 84
P55/SCK6_0/ADTG_1/MADATA05_1 85
P56/INT08_2/MADATA06_1 86
50 P22/AN17/SOT0_0/TIOB7_1
49 P23/AN16/SCK0_0/TIOA7_1
48 P1F/AN15/ADTG_5/MAD23_1
47 P1E/AN14/RTS4_1/MAD22_1
46 P1D/AN13/CTS4_1/MAD21_1
45 P1C/AN12/SCK4_1/MAD20_1
44 P1B/AN11/SOT4_1/MAD19_1
43 P1A/AN10/SIN4_1/INT05_1/MAD18_1
42 P19/AN09/SCK2_2/MAD17_1
41 P18/AN08/SOT2_2/MAD16_1
40 AVSS
P30/TIOB0_1/INT03_2/MADATA07_1 87
P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 88
P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 89
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 90
P34/TIOB4_1/MADATA11_1 91
QFP - 100
P35/TIOB5_1/INT08_1/MADATA12_1 92
P36/SIN5_2/INT09_1/MADATA13_1 93
P37/SOT5_2/INT10_1/MADATA14_1 94
P38/SCK5_2/INT11_1/MADATA15_1 95
P39/ADTG_2 96
39 AVRH
38 AVCC
37 P17/AN07/SIN2_2/INT04_1/MAD15_1
36 P16/AN06/SCK0_1/MAD14_1
35 P15/AN05/SOT0_1/MAD13_1
34 P14/AN04/SIN0_1/INT03_1/MAD12_1
33 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1
32 P12/AN02/SOT1_1/MAD10_1
31 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 97
P3B/TIOA1_1 98
P3C/TIOA2_1 99
P3D/TIOA3_1 100
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05637 Rev.*B
Page 10 of 118
MB9A140NB Series
LQH080/ LQJ080
(TOP VIEW)
VCC
P50/INT00_0/SIN3_1/MADATA00_1
P51/INT01_0/SOT3_1/MADATA01_1
P52/INT02_0/SCK3_1/MADATA02_1
P53/SIN6_0/TIOA1_2/INT07_2/MADATA03_1
P54/SOT6_0/TIOB1_2/MADATA04_1
P55/SCK6_0/ADTG_1/MADATA05_1
P56/INT08_2/MADATA06_1
1
2
3
4
5
6
7
8
9
60 P20/AN19/INT05_0/CROUT_0/MAD24_1
59 P21/AN18/SIN0_0/INT06_1/WKUP2
58 P22/AN17/SOT0_0/TIOB7_1
57 P23/AN16/SCK0_0/TIOA7_1
56 P1B/AN11/SOT4_1/MAD19_1
55 P1A/AN10/SIN4_1/INT05_1/MAD18_1
54 P19/AN09/SCK2_2/MAD17_1
53 P18/AN08/SOT2_2/MAD16_1
52 AVSS
P30/TIOB0_1/INT03_2/MADATA07_1
P31/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 10
P32/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 11
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 12
P39/ADTG_2 13
51 AVRH
LQFP - 80
50 AVCC
49 P17/AN07/SIN2_2/INT04_1/MAD15_1
48 P16/AN06/SCK0_1/MAD14_1
47 P15/AN05/SOT0_1/MAD13_1
46 P14/AN04/SIN0_1/INT03_1/MAD12_1
45 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/MAD11_1
44 P12/AN02/SOT1_1/MAD10_1
43 P11/AN01/SIN1_1/INT02_1/WKUP1/MAD09_1
42 P10/AN00
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 14
P3B/TIOA1_1 15
P3C/TIOA2_1 16
P3D/TIOA3_1 17
P3E/TIOA4_1 18
P3F/TIOA5_1 19
VSS 20
41 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05637 Rev.*B
Page 11 of 118
MB9A140NB Series
LQD064/ LQG064
(TOP VIEW)
VCC
P50/INT00_0/SIN3_1
1
2
3
4
5
6
7
8
9
48 P21/AN18/SIN0_0/INT06_1/WKUP2
47 P22/AN17/SOT0_0/TIOB7_1
46 P23/AN16/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVSS
P51/INT01_0/SOT3_1
P52/INT02_0/SCK3_1
P30/TIOB0_1/INT03_2
P31/TIOB1_1/SCK6_1/INT04_2
P32/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/ADTG_2
42 AVRH
LQFP - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 10
P3B/TIOA1_1 11
38 P14/AN04/INT03_1
37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1
36 P12/AN02/SOT1_1
35 P11/AN01/SIN1_1/INT02_1/WKUP1
34 P10/AN00
P3C/TIOA2_1 12
P3D/TIOA3_1 13
P3E/TIOA4_1 14
P3F/TIOA5_1 15
VSS 16
33 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05637 Rev.*B
Page 12 of 118
MB9A140NB Series
VNC064
(TOP VIEW)
VCC
P50/INT00_0/SIN3_1
1
2
3
4
5
6
7
8
9
48 P21/AN18/SIN0_0/INT06_1/WKUP2
47 P22/AN17/SOT0_0/TIOB7_1
46 P23/AN16/SCK0_0/TIOA7_1
45 P19/AN09/SCK2_2
44 P18/AN08/SOT2_2
43 AVSS
P51/INT01_0/SOT3_1
P52/INT02_0/SCK3_1
P30/TIOB0_1/INT03_2
P31/TIOB1_1/SCK6_1/INT04_2
P32/TIOB2_1/SOT6_1/INT05_2
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6
P39/ADTG_2
42 AVRH
QFN - 64
41 AVCC
40 P17/AN07/SIN2_2/INT04_1
39 P15/AN05
P3A/TIOA0_1/RTCCO_2/SUBOUT_2 10
P3B/TIOA1_1 11
38 P14/AN04/INT03_1
37 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1
36 P12/AN02/SOT1_1
35 P11/AN01/SIN1_1/INT02_1/WKUP1
34 P10/AN00
P3C/TIOA2_1 12
P3D/TIOA3_1 13
P3E/TIOA4_1 14
P3F/TIOA5_1 15
VSS 16
33 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05637 Rev.*B
Page 13 of 118
MB9A140NB Series
LBC112
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
VSS
VCC
P50
P53
P30
P34
P37
P3B
VCC
VCC
VSS
P81
VSS
P51
P54
P31
P35
P38
P3C
P3F
VSS
C
P80
P52
VSS
P55
P32
P36
P3A
P3E
VSS
X1A
X0A
VCC
P61
P60
VSS
P33
P39
P3D
VSS
P40
INITX
VSS
P0E
P0F
P62
P0B
P0C
P0D
P63
AN22
AN23
P09
TRSTX
VCC
VSS
AN19
AN16
AN12
AN09
AN06
AN03
AN01
VSS
X1
VSS
TDI
TDO/
SWO
TCK/
SWCLK
AN20
VSS
VSS
AN21
AN14
AN10
AN07
AN04
VSS
MD1
X0
AN18
AN15
AN11
AVRH
AVSS
AVCC
AN00
VCC
P56
P0A
Index
AN17
AN13
AN08
VSS
G
H
J
P44
P43
P42
P41
P4C
P49
P48
P45
AN05
P4D
P4B
P4A
AN02
P4E
K
L
MD0
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05637 Rev.*B
Page 14 of 118
MB9A140NB Series
FDG096
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
VSS
VCC
P50
P53
P56
VSS
P32
P3A
P3D
VCC
VSS
P81
VSS
P51
P54
P30
VSS
P33
P3B
P3E
VSS
C
P80
P52
VSS
P55
P31
VSS
P39
P3C
VSS
X1A
X0A
VCC
P61
VSS
P63
P62
P0F
P0D
P0E
VSS
P0C
P0B
AN22
TRSTX
VSS
VSS
TDI
TDO/
SWO
TCK/
SWCLK
P60
P0A
VSS
AN17
AN11
AN08
AN06
AN04
VSS
MD1
X0
AN19
AN16
AN10
AN07
AN05
AN03
AN01
VSS
AN18
VSS
Index
AN09
AVRH
AVSS
AVCC
AN00
VCC
G
H
J
P3F
INITX
VSS
P48
P45
P44
P4A
P49
VSS
P4D
P4C
P4B
AN02
P4E
K
L
MD0
X1
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05637 Rev.*B
Page 15 of 118
MB9A140NB Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
I/O Circuit
Type
Pin State
Type
Pin Name
VCC
LQFP-64
QFN-64
LQFP-100
QFP-100
79
BGA-112
B1
LQFP-80
BGA-96
B1
1
1
1
-
P50
2
-
INT00_0
SIN3_1
MADATA00_1
P51
2
3
80
C1
2
3
C1
E
E
L
INT01_0
3
-
81
C2
C2
L
L
L
K
K
SOT3_1
(SDA3_1)
MADATA01_1
P52
INT02_0
4
-
4
5
6
7
82
83
84
85
B3
D1
D2
D3
4
5
6
7
B3
D1
D2
D3
E
E
E
E
SCK3_1
(SCL3_1)
MADATA02_1
P53
SIN6_0
-
-
TIOA1_2
INT07_2
MADATA03_1
P54
SOT6_0
(SDA6_0)
TIOB1_2
MADATA04_1
P55
SCK6_0
(SCL6_0)
-
-
ADTG_1
MADATA05_1
P56
8
9
86
87
D5
E1
8
9
E1
E2
INT08_2
MADATA06_1
P30
E
E
L
L
5
-
TIOB0_1
INT03_2
MADATA07_1
Document Number: 002-05637 Rev.*B
Page 16 of 118
MB9A140NB Series
Pin No
BGA-112 LQFP-80
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-96
P31
TIOB1_1
6
SCK6_1
(SCL6_1)
10
88
E2
10
E3
E
L
L
L
INT04_2
MADATA08_1
P32
-
TIOB2_1
7
-
SOT6_1
(SDA6_1)
11
12
89
90
E3
E4
11
12
G1
G2
E
E
INT05_2
MADATA09_1
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
MADATA10_1
P34
8
-
-
13
14
91
92
F1
F2
-
-
-
-
TIOB4_1
MADATA11_1
P35
E
E
K
L
TIOB5_1
INT08_1
MADATA12_1
P36
-
-
SIN5_2
INT09_1
MADATA13_1
VSS
15
93
F3
-
-
E
L
-
-
-
-
-
-
-
-
-
-
-
-
F1
F2
F3
-
-
-
-
-
-
VSS
VSS
P37
SOT5_2
(SDA5_2)
16
94
G1
-
-
-
E
L
INT10_1
MADATA14_1
P38
SCK5_2
(SCL5_2)
17
18
95
96
G2
F4
-
-
-
E
E
L
INT11_1
MADATA15_1
P39
13
G3
9
K
ADTG_2
Document Number: 002-05637 Rev.*B
Page 17 of 118
MB9A140NB Series
Pin No
BGA-112 LQFP-80
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-96
P3A
TIOA0_1
RTCCO_2
SUBOUT_2
P3B
19
97
G3
14
H1
10
E
K
20
21
98
99
H1
H2
15
16
H2
H3
11
12
E
E
K
K
K
TIOA1_1
P3C
TIOA2_1
P3D
22
-
100
G4
B2
H3
17
-
J1
B2
J2
13
-
E
-
TIOA3_1
VSS
-
P3E
23
1
18
14
E
K
TIOA4_1
P3F
24
2
J2
19
J4
15
E
K
TIOA5_1
VSS
25
26
3
4
L1
J1
20
-
L1
-
16
-
-
-
VCC
P40
27
5
J4
-
-
-
TIOA0_0
INT12_1
P41
E
L
28
29
30
6
7
8
L5
K5
J5
-
-
-
-
-
-
-
-
-
TIOA1_0
INT13_1
P42
E
E
E
L
K
K
TIOA2_0
P43
TIOA3_0
ADTG_7
P44
31
32
9
H5
L6
21
22
L5
-
-
TIOA4_0
MAD00_1
P45
TIOA5_0
MAD01_1
VSS
E
E
K
K
10
K5
-
-
K2
J3
H4
-
-
K2
J3
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS
VSS
VSS
C
-
-
-
-
-
-
-
L6
L2
L4
K1
-
33
34
35
11
12
13
L2
L4
K1
23
24
25
17
-
VSS
VCC
P46
X0A
P47
X1A
18
36
37
14
15
L3
26
27
L3
19
20
D
D
F
K3
K3
G
Document Number: 002-05637 Rev.*B
Page 18 of 118
MB9A140NB Series
Pin No
BGA-112 LQFP-80
K4 28
I/O Circuit
Type
Pin State
Type
Pin Name
INITX
LQFP-64
QFN-64
LQFP-100
QFP-100
16
BGA-96
K4
38
21
B
C
P48
INT14_1
SIN3_2
MAD02_1
P49
39
40
17
K6
29
J5
-
E
E
L
22
-
TIOB0_0
18
J6
30
K6
K
SOT3_2
(SDA3_2)
MAD03_1
P4A
23
-
TIOB1_0
41
42
19
20
L7
31
32
J6
L7
E
E
K
K
SCK3_2
(SCL3_2)
MAD04_1
P4B
24
-
K7
TIOB2_0
MAD05_1
P4C
TIOB3_0
25
SCK7_1
(SCL7_1)
43
21
H6
33
K7
I
S
CEC0
-
MAD06_1
P4D
TIOB4_0
26
-
44
45
22
23
J7
34
35
J7
I
I
K
L
SOT7_1
(SDA7_1)
MAD07_1
P4E
TIOB5_0
INT06_2
SIN7_1
MAD08_1
MD1
27
K8
K8
-
46
47
48
24
25
26
K9
L8
L9
36
37
38
K9
L8
L9
28
29
30
C
G
A
E
D
A
PE0
MD0
X0
PE2
X1
49
27
L10
39
L10
31
A
B
PE3
50
51
28
29
L11
K11
40
41
L11
K11
32
33
VSS
-
-
VCC
P10
52
30
J11
42
J11
34
F
M
AN00
Document Number: 002-05637 Rev.*B
Page 19 of 118
MB9A140NB Series
Pin No
BGA-112 LQFP-80
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-96
P11
AN01
35
SIN1_1
INT02_1
WKUP1
MAD09_1
P12
53
31
J10
43
J10
F
R
-
AN02
36
54
32
J8
44
J8
F
M
SOT1_1
(SDA1_1)
-
-
-
MAD10_1
VSS
-
-
-
-
K10
J9
-
-
K10
J9
-
-
VSS
P13
AN03
SCK1_1
(SCL1_1)
37
55
33
H10
45
H10
F
M
RTCCO_1
SUBOUT_1
MAD11_1
P14
-
38
AN04
56
57
58
59
34
35
36
37
H9
46
47
48
49
H9
INT03_1
SIN0_1
MAD12_1
P15
F
F
F
F
N
M
M
N
-
39
AN05
H7
G10
G9
SOT0_1
(SDA0_1)
-
-
MAD13_1
P16
AN06
G10
G9
SCK0_1
(SCL0_1)
MAD14_1
P17
AN07
40
F10
SIN2_2
INT04_1
MAD15_1
AVCC
-
60
61
62
38
39
40
H11
F11
G11
50
51
52
H11
F11
G11
41
42
43
-
-
-
AVRH
AVSS
Document Number: 002-05637 Rev.*B
Page 20 of 118
MB9A140NB Series
Pin No
BGA-112 LQFP-80
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-96
P18
AN08
44
63
41
G8
53
F9
F
M
M
SOT2_2
(SDA2_2)
-
MAD16_1
P19
AN09
45
64
-
42
-
F10
H8
F9
54
-
E11
-
F
-
SCK2_2
(SCL2_2)
-
-
MAD17_1
VSS
P1A
AN10
65
43
55
E10
-
-
-
SIN4_1
INT05_1
MAD18_1
P1B
F
N
AN11
66
67
44
45
E11
E10
56
E9
F
F
M
M
SOT4_1
(SDA4_1)
MAD19_1
P1C
AN12
-
-
SCK4_1
(SCL4_1)
MAD20_1
P1D
AN13
68
69
70
46
47
48
F8
-
-
-
-
-
-
-
-
-
F
F
F
M
M
M
CTS4_1
MAD21_1
P1E
AN14
E9
RTS4_1
MAD22_1
P1F
AN15
D11
ADTG_5
MAD23_1
VSS
-
-
-
-
-
-
B10
C9
-
-
-
-
B10
C9
-
-
-
-
-
-
VSS
D11
VSS
Document Number: 002-05637 Rev.*B
Page 21 of 118
MB9A140NB Series
Pin No
BGA-112 LQFP-80
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-96
P23
AN16
71
49
D10
E8
57
D10
46
F
M
M
R
SCK0_0
(SCL0_0)
TIOA7_1
P22
AN17
72
73
74
50
51
52
58
59
60
D9
47
48
-
F
F
F
SOT0_0
(SDA0_0)
TIOB7_1
P21
AN18
C11
C11
C10
SIN0_0
INT06_1
WKUP2
P20
AN19
C10
INT05_0
CROUT_0
MAD24_1
VSS
N
75
76
53
54
A11
A10
-
-
A11
-
-
-
-
-
VCC
P00
49
-
77
78
79
80
81
55
56
57
58
59
A9
B9
B11
A8
B8
61
62
63
64
65
A10
B9
TRSTX
MCSX7_1
P01
E
E
E
E
E
J
J
J
J
J
50
TCK
SWCLK
P02
51
-
B11
A9
TDI
MCSX6_1
P03
52
53
TMS
SWDIO
P04
B8
TDO
SWO
P05
AN20
TRACED0
TIOA5_2
SIN4_2
INT00_1
MCSX5_1
82
60
C8
-
-
-
F
Q
Document Number: 002-05637 Rev.*B
Page 22 of 118
MB9A140NB Series
Pin No
BGA-112 LQFP-80
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-96
-
-
D8
-
-
-
-
-
VSS
P06
-
AN21
TRACED1
TIOB5_2
83
61
D9
-
F
Q
P
P
SOT4_2
(SDA4_2)
INT01_1
MCSX4_1
P07
AN22
66
A8
ADTG_0
MCLKOUT_1
TRACED2
84
62
A7
-
F
-
-
-
SCK4_2
(SCL4_2)
-
-
-
A7
-
-
VSS
-
P08
AN23
TRACED3
TIOA0_2
CTS4_2
MCSX3_1
P09
85
63
B7
-
-
F
TRACECLK
TIOB0_2
RTS4_2
MCSX2_1
P0A
86
87
88
64
65
66
C7
D7
A6
-
-
-
E
O
L
54
-
SIN4_0
INT00_2
MCSX1_1
P0B
67
68
C8
C7
I
SOT4_0
(SDA4_0)
55
-
I
K
TIOB6_1
MCSX0_1
P0C
SCK4_0
(SCL4_0)
56
89
-
67
-
B6
D4
69
-
B7
-
I
K
TIOA6_1
MALE_1
VSS
-
-
-
Document Number: 002-05637 Rev.*B
Page 23 of 118
MB9A140NB Series
Pin No
BGA-112 LQFP-80
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP-64
QFN-64
LQFP-100
QFP-100
BGA-96
C3
-
-
C3
-
-
-
VSS
P0D
-
RTS4_0
TIOA3_2
MDQM0_1
P0E
90
68
C6
70
B6
E
K
K
CTS4_0
TIOB3_2
MDQM1_1
VSS
91
-
69
-
A5
-
71
-
C6
A5
-
-
E
-
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
WKUP0
P63
92
70
B5
72
A6
57
E
I
93
94
71
72
D6
C5
73
74
B5
C5
-
INT03_0
MWEX_1
P62
E
E
L
SCK5_0
(SCL5_0)
58
-
K
ADTG_3
MOEX_1
P61
SOT5_0
(SDA5_0)
95
96
73
74
B4
C4
75
76
B4
C4
59
E
K
T
TIOB2_2
P60
SIN5_0
TIOA2_2
INT15_1
WKUP3
CEC1
MRDY_1
VCC
60
I
-
97
75
76
77
78
A4
A3
A2
A1
77
78
79
80
A4
A3
A2
A1
61
62
63
64
-
98
P80
H
H
-
H
H
99
P81
100
VSS
Document Number: 002-05637 Rev.*B
Page 24 of 118
MB9A140NB Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
84
7
62
85
96
72
-
A7
66
7
A8
D3
G3
C5
-
-
D3
F4
-
18
94
-
13
74
-
9
C5
-
58
-
A/D converter external trigger
input pin
70
12
30
-
48
90
8
D11
E4
-
-
-
12
-
G2
-
8
J5
-
-
-
-
-
-
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
71
72
73
74
82
83
84
85
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
49
50
51
52
60
61
62
63
J11
J10
J8
42
43
44
45
46
47
48
49
53
54
55
56
-
J11
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
34
35
36
37
38
39
-
AN01
AN02
AN03
H10
H9
H7
G10
G9
G8
F10
F9
AN04
AN05
AN06
AN07
40
44
45
-
AN08
AN09
AN10
AN11
E11
E10
F8
-
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN12
-
AN13
-
-
-
AN14
E9
-
-
-
AN15
D11
D10
E8
-
-
-
AN16
57
58
59
60
-
D10
D9
C11
C10
-
46
47
48
-
AN17
AN18
C11
C10
C8
D9
A7
AN19
AN20
-
AN21
-
-
-
AN22
66
-
A8
-
-
AN23
B7
-
Document Number: 002-05637 Rev.*B
Page 25 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Pin Name
Function Description
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
LQFP/
QFN-64
Function
Base Timer
0
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
27
19
85
40
9
5
J4
G3
B7
J6
E1
C7
L5
H1
D1
L7
E2
D2
K5
H2
C4
K7
E3
B4
J5
G4
C6
H6
E4
A5
H5
H3
-
-
-
-
97
63
18
87
64
6
14
-
H1
-
10
-
30
9
K6
E2
-
22
5
86
28
20
5
-
-
Base Timer
1
-
-
-
98
83
19
88
84
7
15
5
H2
D1
J6
E3
D2
-
11
-
41
10
6
31
10
6
23
6
-
Base Timer
2
29
21
96
42
11
95
30
22
90
43
12
91
31
23
-
-
-
99
74
20
89
73
8
16
76
32
11
75
-
H3
C4
L7
G1
B4
-
12
60
24
7
59
-
Base Timer
3
100
68
21
90
69
9
17
70
33
12
71
21
18
-
J1
B6
K7
G2
C6
L5
J2
-
13
-
25
8
-
Base Timer
4
-
1
14
-
-
44
13
-
22
91
-
J7
F1
-
34
-
J7
-
26
-
-
-
-
Base Timer
5
32
24
82
45
14
83
10
2
L6
J2
C8
K8
F2
D9
22
19
-
K5
J4
-
-
15
-
60
23
92
61
35
-
K8
-
27
-
-
-
-
Base Timer
6
TIOA6_1
TIOB6_1
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
89
88
67
66
B6
A6
69
68
B7
C7
56
55
Base Timer
7
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
-
-
-
-
-
-
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
71
-
49
-
D10
57
-
D10
46
-
-
-
-
-
-
-
-
-
72
-
50
-
E8
-
58
-
D9
-
47
-
Document Number: 002-05637 Rev.*B
Page 26 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
Debugger
Serial wire debug interface
clock input pin
SWCLK
SWDIO
78
80
56
58
B9
A8
62
64
B9
A9
50
Serial wire debug interface
data input / output pin
52
SWO
TCK
TDI
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
81
78
79
81
59
56
57
59
B8
B9
B11
B8
65
62
63
65
B8
B9
B11
B8
53
50
51
53
TDO
JTAG test mode state
input/output pin
TMS
80
58
A8
64
A9
52
TRACECLK Trace CLK output pin of ETM
TRACED0
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
64
60
61
62
63
55
9
C7
C8
D9
A7
-
-
-
-
-
-
-
49
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TRACED1
-
-
Trace data output pins of ETM
TRACED2
-
-
TRACED3
B7
-
-
TRSTX
JTAG test reset input pin
A9
61
21
22
29
30
31
32
33
34
35
43
44
45
46
47
48
49
53
54
55
56
-
A10
L5
K5
J5
K6
J6
L7
K7
J7
K8
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
External
Bus
MAD00_1
MAD01_1
MAD02_1
MAD03_1
MAD04_1
MAD05_1
MAD06_1
MAD07_1
MAD08_1
MAD09_1
MAD10_1
MAD11_1
MAD12_1
MAD13_1
MAD14_1
MAD15_1
MAD16_1
MAD17_1
MAD18_1
MAD19_1
MAD20_1
MAD21_1
MAD22_1
MAD23_1
MAD24_1
H5
L6
10
17
18
19
20
21
22
23
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
K6
J6
L7
K7
H6
J7
K8
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
External bus interface address
bus
E11
E10
F8
-
-
E9
-
-
D11
C10
-
-
60
C10
Document Number: 002-05637 Rev.*B
Page 27 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
External
Bus
MCSX0_1
MCSX1_1
MCSX2_1
MCSX3_1
MCSX4_1
MCSX5_1
MCSX6_1
MCSX7_1
MDQM0_1
MDQM1_1
88
87
86
85
83
82
79
77
90
91
66
65
64
63
61
60
57
55
68
69
A6
D7
C7
B7
D9
C8
B11
A9
C6
A5
68
67
-
C7
C8
-
-
-
-
-
-
-
-
-
-
-
-
-
External bus interface chip
select output pin
-
-
-
-
63
61
70
71
B11
A10
B6
C6
External bus interface byte
mask signal output pin
External bus interface read
enable signal for SRAM
MOEX_1
MWEX_1
94
93
2
72
71
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
C5
D6
C1
C2
B3
D1
D2
D3
D5
E1
E2
E3
E4
F1
F2
F3
G1
G2
74
73
2
C5
B5
C1
C2
B3
D1
D2
D3
E1
E2
E3
G1
G2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
External bus interface write
enable signal for SRAM
MADATA00
_1
MADATA01
_1
3
3
MADATA02
_1
4
4
MADATA03
_1
5
5
MADATA04
_1
6
6
MADATA05
_1
7
7
MADATA06
_1
8
8
MADATA07
_1
9
9
External bus interface data bus
MADATA08
_1
10
11
12
13
14
15
16
17
10
11
12
-
MADATA09
_1
MADATA10
_1
MADATA11_
1
MADATA12
_1
-
-
MADATA13
_1
-
-
MADATA14
_1
-
-
MADATA15
_1
-
-
Address Latch enable signal
for multiplex
MALE_1
MRDY_1
89
96
84
67
74
62
B6
C4
A7
69
76
66
B7
C4
A8
-
-
-
External RDY input signal
MCLKOUT
_1
External bus clock output pin
Document Number: 002-05637 Rev.*B
Page 28 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
2
80
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
C1
C8
D7
C2
D9
B3
J10
D6
H9
E1
E4
G9
E2
C10
F9
2
C1
-
2
External interrupt request 00
input pin
82
87
3
-
-
67
3
C8
C2
-
54
3
External interrupt request 01
input pin
83
4
-
-
4
B3
J10
B5
H9
E2
G2
F10
E3
C10
E10
G1
C11
K8
4
External interrupt request 02
input pin
53
93
56
9
43
73
46
9
35
-
External interrupt request 03
input pin
38
5
12
59
10
74
65
11
73
45
12
49
10
60
55
11
59
35
8
External interrupt request 04
input pin
40
6
-
External interrupt request 05
input pin
-
E3
C11
K8
7
External interrupt request 06
input pin
48
27
External interrupt request 07
input pin
INT07_2
5
83
D1
5
D1
-
INT08_1
INT08_2
External interrupt request 08
input pin
14
8
92
86
F2
D5
-
-
-
-
8
E1
External interrupt request 09
input pin
INT09_1
INT10_1
INT11_1
INT12_1
INT13_1
INT14_1
INT15_1
NMIX
15
16
17
27
28
39
96
92
93
94
95
5
F3
G1
G2
J4
-
-
-
External interrupt request 10
input pin
-
-
-
External interrupt request 11
input pin
-
-
-
External interrupt request 12
input pin
-
-
-
External interrupt request 13
input pin
6
L5
K6
C4
B5
-
-
-
External interrupt request 14
input pin
17
74
70
29
76
72
J5
C4
A6
-
External interrupt request 15
input pin
60
57
Non-Maskable Interrupt input
pin
Document Number: 002-05637 Rev.*B
Page 29 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
A9
B9
B11
A8
B8
C8
D9
A7
B7
C7
D7
A6
B6
C6
A5
B5
61
62
63
64
65
-
-
66
-
A10
B9
B11
A9
B8
-
-
A8
-
49
50
51
52
53
-
-
-
-
-
General-purpose I/O port 0
-
-
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
-
C8
C7
B7
B6
C6
A6
J11
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
54
55
56
-
-
57
34
35
36
37
38
39
-
40
44
45
-
-
-
-
-
-
-
48
47
46
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
General-purpose I/O port 1
-
-
-
60
59
58
57
-
-
-
E9
D11
C10
C11
E8
C10
C11
D9
D10
General-purpose I/O port 2
D10
Document Number: 002-05637 Rev.*B
Page 30 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
9
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
9
E2
E3
G1
G2
-
-
-
-
-
G3
H1
H2
H3
J1
J2
J4
-
5
6
7
8
-
-
-
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
96
95
94
93
98
99
46
48
49
10
11
12
-
-
-
-
-
General-purpose I/O port 3
-
9
13
14
15
16
17
18
19
-
10
11
12
13
14
15
-
-
-
-
-
2
5
6
7
8
9
J4
L5
K5
J5
H5
L6
-
-
-
-
-
-
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
L5
K5
L3
K3
J5
K6
J6
L7
K7
J7
K8
C1
C2
B3
D1
D2
D3
E1
C4
B4
C5
B5
A3
A2
K9
L9
L10
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
74
73
72
71
76
77
24
26
27
-
L3
19
20
-
22
23
24
25
26
27
2
3
4
-
-
-
-
60
59
58
-
62
63
28
30
31
General-purpose I/O port 4
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
C4
B4
C5
D6
A3
A2
K9
L9
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
L10
Document Number: 002-05637 Rev.*B
Page 31 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
Multi-
function
Serial
0
SIN0_0
SIN0_1
73
56
51
34
C11
H9
59
46
C11
H9
48
Multi-function serial interface
ch.0 input pin
-
Multi-function serial interface
ch.0 output pin.
This pin operates as SOT0
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA0 when it is
used in an I2C (operation mode
4).
SOT0_0
(SDA0_0)
72
57
71
50
35
49
E8
58
47
57
D9
47
SOT0_1
(SDA0_1)
H7
G10
D10
-
Multi-function serial interface
ch.0 clock I/O pin.
This pin operates as SCK0
when it is used in a
SCK0_0
(SCL0_0)
D10
46
UART/CSIO (operation modes
0 to 2) and as SCL0 when it is
used in an I2C (operation mode
4).
SCK0_1
(SCL0_1)
58
53
36
31
G10
J10
48
43
G9
-
Multi-
function
Serial
1
Multi-function serial interface
ch.1 input pin
SIN1_1
J10
35
Multi-function serial interface
ch.1 output pin.
This pin operates as SOT1
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA1 when it is
used in an I2C (operation mode
4).
SOT1_1
(SDA1_1)
54
32
J8
44
J8
36
Multi-function serial interface
ch.1 clock I/O pin.
This pin operates as SCK1
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL1 when it is
used in an I2C (operation mode
4).
SCK1_1
(SCL1_1)
55
33
H10
45
H10
37
Document Number: 002-05637 Rev.*B
Page 32 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
Multi-
function
Serial
2
Multi-function serial interface
ch.2 input pin
Multi-function serial interface
ch.2 output pin.
SIN2_2
59
37
G9
49
F10
40
This pin operates as SOT2
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA2 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.2 clock I/O pin.
This pin operates as SCK2
when it is used in a
SOT2_2
(SDA2_2)
63
41
G8
53
F9
44
45
SCK2_2
(SCL2_2)
64
42
F10
54
E11
UART/CSIO (operation modes
0 to 2) and as SCL2 when it is
used in an I2C (operation mode
4).
Multi-
function
Serial
3
SIN3_1
SIN3_2
2
80
17
C1
K6
2
C1
J5
2
-
Multi-function serial interface
ch.3 input pin
39
29
Multi-function serial interface
ch.3 output pin.
This pin operates as SOT3
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA3 when it is
used in an I2C (operation mode
4).
SOT3_1
(SDA3_1)
3
81
18
C2
J6
3
C2
K6
3
-
SOT3_2
(SDA3_2)
40
30
Multi-function serial interface
ch.3 clock I/O pin.
This pin operates as SCK3
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL3 when it is
used in an I2C (operation mode
4).
SCK3_1
(SCL3_1)
4
82
19
B3
L7
4
B3
J6
4
-
SCK3_2
(SCL3_2)
41
31
Document Number: 002-05637 Rev.*B
Page 33 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
Multi-
function
Serial
4
SIN4_0
SIN4_1
SIN4_2
87
65
82
65
43
60
D7
F9
C8
67
55
-
C8
E10
-
54
-
Multi-function serial interface
ch.4 input pin
-
SOT4_0
(SDA4_0)
Multi-function serial interface
ch.4 output pin.
This pin operates as SOT4
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA4 when it is
used in an I2C (operation mode
4).
88
66
83
66
44
61
A6
68
56
-
C7
E9
-
55
-
SOT4_1
(SDA4_1)
E11
D9
SOT4_2
(SDA4_2)
-
Multi-function serial interface
ch.4 clock I/O pin.
This pin operates as SCK4
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL4 when it is
used in an I2C (operation mode
4).
SCK4_0
(SCL4_0)
89
67
84
67
45
62
B6
69
-
B7
56
-
SCK4_1
(SCL4_1)
E10
A7
-
-
SCK4_2
(SCL4_2)
-
-
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_2
90
69
86
91
68
85
96
15
68
47
64
69
46
63
74
93
C6
E9
C7
A5
F8
B7
C4
F3
70
-
B6
-
Multi-function serial interface
ch.4 RTS output pin
-
-
-
-
-
71
-
C6
-
-
Multi-function serial interface
ch.4 CTS input pin
-
-
-
-
Multi-
function
Serial
5
76
-
C4
-
60
-
Multi-function serial interface
ch.5 input pin
Multi-function serial interface
ch.5 output pin.
This pin operates as SOT5
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA5 when it is
used in an I2C (operation mode
4).
SOT5_0
(SDA5_0)
95
16
73
94
B4
G1
75
-
B4
59
-
SOT5_2
(SDA5_2)
-
Multi-function serial interface
ch.5 clock I/O pin.
This pin operates as SCK5
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SCL5 when it is
used in an I2C (operation mode
4).
SCK5_0
(SCL5_0)
94
17
72
95
C5
G2
74
-
C5
-
58
-
SCK5_2
(SCL5_2)
Document Number: 002-05637 Rev.*B
Page 34 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
Multi-
function
Serial
6
SIN6_0
SIN6_1
5
83
90
D1
E4
5
D1
G2
-
Multi-function serial interface
ch.6 input pin
12
12
8
Multi-function serial interface
ch.6 output pin.
This pin operates as SOT6
when it is used in a
SOT6_0
(SDA6_0)
6
84
D2
6
D2
-
UART/CSIO (operation modes
0 to 2) and as SDA6 when it is
used in an I2C (operation mode
4).
SOT6_1
(SDA6_1)
11
7
89
85
E3
D3
11
7
G1
D3
7
-
Multi-function serial interface
ch.6 clock I/O pin.
This pin operates as SCK6
when it is used in a
SCK6_0
(SCL6_0)
UART/CSIO (operation modes
0 to 2) and as SCL6 when it is
used in an I2C (operation mode
4).
SCK6_1
(SCL6_1)
10
45
88
23
E2
K8
10
35
E3
K8
6
Multi-
function
Serial
7
Multi-function serial interface
ch.7 input pin
SIN7_1
27
Multi-function serial interface
ch.7 output pin.
This pin operates as SOT7
when it is used in a
UART/CSIO (operation modes
0 to 2) and as SDA7 when it is
used in an I2C (operation mode
4).
Multi-function serial interface
ch.7 clock I/O pin.
This pin operates as SCK7
when it is used in a
SOT7_1
(SDA7_1)
44
43
22
21
J7
34
33
J7
26
25
SCK7_1
(SCL7_1)
H6
K7
UART/CSIO (operation modes
0 to 2) and as SCL7 when it is
used in an I2C (operation mode
4).
Document Number: 002-05637 Rev.*B
Page 35 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
Real-time
clock
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
92
55
19
92
55
19
70
33
97
70
33
97
B5
72
45
14
72
45
14
A6
57
37
10
57
37
10
0.5 seconds pulse output pin of
Real-time clock
H10
G3
B5
H10
H1
A6
SUBOUT_1 Sub clock output pin
SUBOUT_2
H10
G3
H10
H1
Low-Power
Consumption
Mode
Deep standby mode return
WKUP0
92
53
73
96
70
31
51
74
B5
72
43
59
76
A6
57
35
48
60
signal input pin 0
Deep standby mode return
signal input pin 1
WKUP1
J10
C11
C4
J10
C11
C4
Deep standby mode return
signal input pin 2
WKUP2
Deep standby mode return
signal input pin 3
WKUP3
HDMI-
CEC/
Remote
Control
HDMI-CEC/Remote Control
CEC0
43
96
21
74
H6
C4
33
76
K7
C4
25
60
Reception ch.0 input/output pin
HDMI-CEC/Remote Control
CEC1
Reception ch.1 input/output pin
Document Number: 002-05637 Rev.*B
Page 36 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
Reset
Mode
External Reset Input pin.
A reset is valid when INITX=L.
Mode 0 pin.
INITX
38
16
K4
28
K4
21
During normal operation,
MD0=L must be input. During
serial programming to Flash
memory, MD0=H must be input.
Mode 1 pin.
MD0
47
25
L8
37
L8
29
During serial programming to
Flash memory, MD1=L must be
input.
MD1
46
24
K9
36
K9
28
Power
GND
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
Power supply Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
1
79
4
13
29
54
75
-
-
-
-
3
-
-
-
-
12
28
-
-
-
-
-
-
53
-
-
-
-
-
B1
J1
K1
K11
A10
A4
-
1
-
25
41
-
77
-
-
-
-
20
-
-
-
-
24
40
-
-
-
-
-
B1
-
K1
K11
-
1
-
18
33
-
61
-
-
-
-
16
-
-
-
-
-
32
-
-
-
-
-
26
35
51
76
97
-
-
-
-
25
-
-
-
-
34
50
-
-
-
-
-
-
75
-
-
-
-
-
A4
F1
F2
F3
B2
L1
K2
J3
-
L6
L4
L11
K10
J9
-
B10
C9
D11
A11
-
A7
-
C3
A5
A1
-
-
B2
L1
K2
J3
H4
-
L4
L11
K10
J9
H8
B10
C9
-
A11
D8
-
D4
C3
-
-
-
-
-
-
-
-
80
-
-
-
-
-
-
-
64
GND Pin
GND Pin
GND Pin
100
78
A1
Document Number: 002-05637 Rev.*B
Page 37 of 118
MB9A140NB Series
Pin No
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Name
Function Description
LQFP/
QFN-64
Clock
X0
X0A
X1
X1A
CROUT_0
CROUT_1
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
48
36
49
37
74
92
26
14
27
15
52
70
L9
L3
L10
K3
C10
B5
38
26
39
27
60
72
L9
L3
L10
K3
C10
A6
30
19
31
20
-
Built-in high-speed CR-osc clock
output port
57
ADC
power
A/D converter analog power
supply pin
A/D converter analog reference
voltage input pin
AVCC
AVRH
60
61
38
39
H11
F11
50
51
H11
F11
41
42
ADC
GND
C pin
AVSS
C
A/D converter GND pin
62
33
40
11
G11
L2
52
23
G11
L2
43
17
Power stabilization capacity pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05637 Rev.*B
Page 38 of 118
MB9A140NB Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
When the main oscillation is selected.
−
Oscillation feedback resistor
: Approximately 1 MΩ
P-ch
P-ch
Digital output
Digital output
−
With Standby mode control
X1
When the GPIO is selected.
−
−
−
−
−
CMOS level output.
N-ch
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
R
Pull-up resistor control
Digital input
: Approximately 33 kΩ
IOH = -4 mA, IOL = 4 mA
−
Standby mode control
Clock input
Standby mode control
Digital input
Standby mode control
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
Document Number: 002-05637 Rev.*B
Page 39 of 118
MB9A140NB Series
Type
Circuit
Remarks
CMOS level hysteresis input
Pull-up resistor
B
−
−
: Approximately 33 kΩ
Pull-up resistor
Digital input
C
−
−
Open drain output
CMOS level hysteresis input
Digital input
Digital output
N-ch
Document Number: 002-05637 Rev.*B
Page 40 of 118
MB9A140NB Series
Type
Circuit
Remarks
D
It is possible to select the sub
oscillation / GPIO function
When the sub oscillation is selected.
−
Oscillation feedback resistor
: Approximately 5 MΩ
P-ch
P-ch
Digital output
Digital output
X1A
−
With Standby mode control
When the GPIO is selected.
N-ch
−
−
−
−
−
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
R
Pull-up resistor control
Digital input
: Approximately 33 kΩ
IOH = -4 mA, IOL = 4 mA
−
Standby mode control
Clock input
Standby mode control
Digital input
Standby mode control
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05637 Rev.*B
Page 41 of 118
MB9A140NB Series
Type
Circuit
Remarks
E
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
Digital output
Digital output
: Approximately 33 kΩ
−
−
IOH = -4 mA, IOL = 4 mA
When this pin is used as an I2C pin, the
digital output P-ch transistor is always off
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
Digital output
Digital output
P-ch
P-ch
: Approximately 33 kΩ
−
−
IOH = -4 mA, IOL = 4 mA
When this pin is used as an I2C pin, the
digital output P-ch transistor is always off
N-ch
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
Document Number: 002-05637 Rev.*B
Page 42 of 118
MB9A140NB Series
Type
Circuit
Remarks
G
−
CMOS level hysteresis input
Mode input
H
−
−
−
CMOS level output
CMOS level hysteresis input
With standby mode control
IOH = -12.0 mA, IOL = 10.5 mA
Digital output
Digital output
P-ch
N-ch
R
Digital input
Standby mode control
I
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
Digital output
Digital output
: Approximately 33 kΩ
−
−
−
IOH = -4 mA, IOL = 4 mA
Available to control PZR registers.
When this pin is used as an I2C pin, the
digital output P-ch transistor is always off
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05637 Rev.*B
Page 43 of 118
MB9A140NB Series
6. Handling Precaution
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
.
Document Number: 002-05637 Rev.*B
Page 44 of 118
MB9A140NB Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress’ recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress Inc. recommends the solder reflow method, and has established a ranking
of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of
recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a
silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05637 Rev.*B
Page 45 of 118
MB9A140NB Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05637 Rev.*B
Page 46 of 118
MB9A140NB Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply..
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
Surface mount type
Size:
More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
Lead type
Load capacitance: Approximately 6 pF to 7 pF
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as
External clock
input
Can be used as
general-purpose
I/O ports.
X1(PE3),
X1A (P47)
Document Number: 002-05637 Rev.*B
Page 47 of 118
MB9A140NB Series
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this
series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistor stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on: VCC →AVCC → AVRH
Turning off: AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
Document Number: 002-05637 Rev.*B
Page 48 of 118
MB9A140NB Series
8. Block Diagram
TRSTX,TCK,
TDI,TMS
TDO
SWJ-DP
TPIU*1
ETM*1
SRAM0
8/16 Kbyte
ROM
Table
TRACEDx,
TRACECLK
I
SRAM1
8/16 Kbyte
D
NVIC
Sys
On-Chip Flash
64+32 Kbyte/
128+32 Kbyte/
256+32 Kbyte
Flash I/F
Security
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch.
CSV
CLK
X0
X1
Main
Source Clock
CR
PLL
CR
Osc
Sub
Osc
X0A
X1A
4 MHz 100 kHz
CROUT
MADx
External Bus I/F*2
MADATAx
MCSXx,
MOEX,
MWEX,
MALE,
MRDY,
AVCC,
AVSS,
AVRH
12-bit A/D Converter
Unit 0
ANxx
MCLKOUT,
Power-On
MDQMx
Reset
Unit 1
ADTGx
LVD
LVD Ctrl
Regulator
C
IRQ-Monitor
TIOAx
TIOBx
Base Timer
16-bit 8ch./
32-bit 4ch.
CRC
Accelerator
Watch Counter
External Interrupt
Controller
16-pin + NMI
INTx
NMIX
MD0,
MD1
MODE-Ctrl
GPIO
P0x,
P1x,
.
.
.
PIN-Function-Ctrl
HDMI-CEC/
Remote Reciver Control
PEx
CEC0,CEC1
SCKx
SINx
Multi-Function Serial I/F
8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)*2
RTCCO,
SUBOUT
Real-Time Clock
SOTx
CTS4
RTS4
WKUPx
Deep Standby Ctrl
*1: For the MB9AF141LB/MB, MB9AF142LB/MB, and MB9AF144LB/MB, ETM is not available.
*2: For the MB9AF141LB, MB9AF142LB and MB9AF144LB, the External Bus Interface is not available. And the Multi-function
Serial Interface does not support hardware flow control in these products.
Document Number: 002-05637 Rev.*B
Page 49 of 118
MB9A140NB Series
9. Memory Size
See “Memory size” in “1. Product Lineup” to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
Cortex-M3 Private
0x4006_1000
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_F000
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
Peripherals
DMAC
0xE000_0000
Reserved
EXT-bus I/F
Reserved
RTC
Reserved
Watch Counter
CRC
0x7000_0000
External Device
MFS
Area
0x6000_0000
Reserved
Reserved
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
0x4400_0000
0x4200_0000
0x4000_0000
32Mbytes
Bit band alias
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
GPIO
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
Reserved
CR Trim
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Reserved
0x4002_8000
0x4002_7000
A/DC
Reserved
Reserved
Base Timer
0x4002_6000
0x4002_5000
0x2008_0000
0x2000_0000
0x1FFF_0000
0x0020_8000
0x0020_0000
0x0010_4000
0x0010_0000
SRAM1
SRAM0
Reserved
Flash(Work area)
Reserved
Reserved
See the next page
"lMemory Map (2)"
for the memory size
details.
Security/CR Trim
0x4001_6000
0x4001_5000
Dual Timer
Reserved
Flash(Main area)
0x4001_3000
SW WDT
HW WDT
0x4001_2000
0x4001_1000
0x0000_0000
Clock/Reset
0x4001_0000
Reserved
Flash I/F
0x4000_1000
0x4000_0000
Document Number: 002-05637 Rev.*B
Page 50 of 118
MB9A140NB Series
Memory Map (2)
MB9AF144LB/MB/NB
MB9AF142LB/MB/NB
MB9AF141LB/MB/NB
0x2008_0000
0x2008_0000
0x2008_0000
Reserved
Reserved
Reserved
0x2000_4000
0x2000_0000
0x1FFF_C000
0x2000_2000
0x2000_0000
0x1FFF_E000
0x2000_2000
0x2000_0000
0x1FFF_E000
SRAM1
16Kbytes
SRAM1
8Kbytes
SRAM1
8Kbytes
SRAM0
8Kbytes
SRAM0
8Kbytes
SRAM0
16Kbytes
Reserved
Reserved
Reserved
SA4-7 (8 KBx4)
Reserved
0x0020_8000
0x0020_0000
0x0020_8000
0x0020_0000
0x0020_8000
0x0020_0000
SA4-7 (8 KBx4)
Reserved
SA4-7 (8 KBx4)
Reserved
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
Reserved
Reserved
0x0004_0000
SA9-11 (64 KBx3)
0x0002_0000
0x0000_0000
SA9 (64 KB)
0x0001_0000
0x0000_0000
SA8 (48 KB)
SA8 (48 KB)
SA8 (48 KB)
SA2-3 (8 KBx2)
SA2-3 (8 KBx2)
SA2-3 (8 KBx2)
0x0000_0000
Refer to the programming manual for the detail of Flash main area.
MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual
Document Number: 002-05637 Rev.*B
Page 51 of 118
MB9A140NB Series
Peripheral Address Map
Start address
End address
Bus
AHB
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_F000
0x4004_0000
0x4006_0000
0x4006_1000
0x4000_0FFF
0x4000_FFFF
Flash memory I/F register
Reserved
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_EFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x41FF_FFFF
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual Timer
Reserved
Reserved
Base Timer
Reserved
APB1
A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
HDMI-CEC/Remote control Receiver
Low-Voltage Detector
Deep standby mode Controller
Reserved
APB2
Multi-function serial
CRC
Watch Counter
Real-time clock
Reserved
External bus interface
Reserved
AHB
DMAC register
Reserved
Document Number: 002-05637 Rev.*B
Page 52 of 118
MB9A140NB Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Document Number: 002-05637 Rev.*B
Page 53 of 118
MB9A140NB Series
List of Pin Status
Power-on
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep standby RTC
mode or Deep
standby Stop mode
state
from
Deep
reset or
low-voltage
detection
state
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
standby
mode
state
state
Function
group
Power
supply
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
unstable
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
Main
A
crystal
oscillator
input pin/
External
main clock
input
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
selected
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at "0"
Internal
input fixed
at 0
GPIO
selected
External
main clock Setting
input
selected
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
disabled
B
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Hi-Z /
Main
crystal
oscillator
output pin
Hi-Z /
Hi-Z /
When
When
When
When
When
When
Internal input
fixed at 0/
or Input
Internal
input fixed
at 0
Internal
input fixed
at 0
oscillation
stops *1,
Hi-Z /
Internal
input fixed
at 0
oscillation
stops *1,
Hi-Z /
Internal
input fixed
at 0
oscillation
stops *1,
Hi-Z /
Internal
input fixed
at 0
oscillation
stops *1,
Hi-Z /
Internal
input fixed
at 0
oscillation
stops *1,
Hi-Z /
Internal
input fixed
at 0
oscillation
stops *1,
Hi-Z /
Internal
input fixed
at 0
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
INITX
input pin
Pull-up / Input
enabled
C
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input enabled
Document Number: 002-05637 Rev.*B
Page 54 of 118
MB9A140NB Series
Return
from
Deep
standby
mode
state
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep standby RTC
mode or Deep
standby Stop mode
state
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply stable
Power supply stable Power supply stable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
INITX = 1
SPL = 0 SPL = 1
INITX = 1
-
-
-
-
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input enabled
E
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
Sub
crystal
F
oscillator
input pin /
External
sub clock
input
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
selected
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
External
sub clock
input
Hi-Z /
Hi-Z/
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
selected
G
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Hi-Z /
Sub
crystal
oscillator
output pin
Hi-Z /
Hi-Z /
When
When
When
When
When
Internal input
fixed at 0 /
or Input
Maintain
previous
state
Internal
input fixed
at 0
Internal
input fixed
at 0
oscillation
stops *2,
Hi-Z /
Internal
input fixed
at 0
oscillation
stops *2,
Hi-Z /
Internal
input fixed
at 0
oscillation
stops *2,
Hi-Z/
Internal
input fixed
at 0
oscillation
stops *2,
Hi-Z/
Internal
input fixed
at 0
oscillation
stops *2,
Hi-Z/
Internal
input fixed
at 0
enable
Document Number: 002-05637 Rev.*B
Page 55 of 118
MB9A140NB Series
Return
from
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep standby RTC
mode or Deep
standby Stop mode
state
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep
standby
mode
state
Function
group
state
Power
supply
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply
stable
Power supply stable
Power supply stable
INITX = 1
unstable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
Hi-Z /
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
H
Hi-Z
Maintain
previous
state
NMIX
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z /
WKUP
input
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
GPIO
selected
I
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Internal
input fixed
at 0
enabled
Hi-Z
Hi-Z
selected
GPIO
selected
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Maintain
previous
state
Maintain
previous
state
GPIO
J
Hi-Z /
Hi-Z /
selected
Internal
input fixed
at 0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
GPIO
Resource
selected
Hi-Z /
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
K
Hi-Z
GPIO
selected
External
interrupt
enabled
selected
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Resource
other than
above
Internal
input fixed
at 0
GPIO
selected
L
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Internal
input fixed
at 0
Hi-Z
selected
GPIO
selected
Document Number: 002-05637 Rev.*B
Page 56 of 118
MB9A140NB Series
Return
from
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep standby RTC
mode or Deep
standby Stop mode
state
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep
standby
mode
state
Function
group
state
Power
supply
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply
stable
Power supply stable
Power supply stable
INITX = 1
unstable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Analog
input
selected
Hi-Z
enabled
enabled
enabled
enabled
enabled
enabled
enabled
M
Resource
other than
above
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
selected
GPIO
selected
Hi-Z /
Internal
input
fixed at 0
/
Analog
input
enabled
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Analog
input
selected
Hi-Z
enabled
enabled
enabled
enabled
enabled
enabled
enabled
External
interrupt
enabled
selected
Maintain
previous
state
N
GPIO
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Resource
other than
above
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Internal
input fixed
at 0
selected
GPIO
selected
Trace
selected
Setting
disabled
Setting
disabled
Setting
disabled
Trace
output
GPIO
Hi-Z /
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
O
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Internal
input fixed
at 0
Hi-Z
selected
GPIO
selected
Document Number: 002-05637 Rev.*B
Page 57 of 118
MB9A140NB Series
Return
from
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep standby RTC
mode or Deep
standby Stop mode
state
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep
standby
mode
state
Function
group
state
Power
supply
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply
stable
Power supply stable
Power supply stable
INITX = 1
unstable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
-
-
-
SPL = 0
SPL = 1
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input
fixed
at 0 /
Analog
input
enabled
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Analog
input
selected
Hi-Z
enabled
enabled
enabled
enabled
enabled
enabled
Trace
selected
Trace
output
P
GPIO
Resource
other than
above
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Internal
input
selected
fixed at 0
GPIO
selected
Hi-Z /
Internal
input
fixed at 0
/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at 0
/
Analog
input
enabled
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Analog
input
selected
Hi-Z
enabled
enabled
enabled
enabled
enabled
enabled
Trace
selected
Trace
output
Q
External
interrupt
enabled
selected
Maintain
previous
state
GPIO
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
GPIO
selected
Resource
other than
above
Hi-Z /
Internal
input
selected
fixed at 0
GPIO
selected
Document Number: 002-05637 Rev.*B
Page 58 of 118
MB9A140NB Series
Return
from
Deep
standby
mode
state
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep standby RTC
mode or Deep
standby Stop mode
state
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
Power supply
stable
Power supply
stable
Power supply stable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
INITX = 1
INITX = 1
-
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
input
fixed at 0
/
Analog
input
enabled
Hi-Z /
Internal
input
fixed at 0
/
Analog
input
enabled
Hi-Z /
WKUP
input
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Internal
input fixed
at 0 /
Analog
input
Analog
input
selected
Hi-Z
enabled
enabled
enabled
enabled
enabled
enabled
WKUP
input
enabled
WKUP
enabled
Maintain
previous
state
R
enabled
External
interrupt
enabled
selected
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
Hi-Z /
Internal
input
selected
Internal
input fixed
at 0
Hi-Z /
fixed at 0
Internal
input fixed
at 0
selected
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Resource
other than
above
selected
GPIO
GPIO
S
Hi-Z /
Hi-Z /
Internal
input
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
Hi-Z
fixed at 0
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z /
WKUP
input
WKUP
input
enabled
WKUP
enabled
Maintain
previous
state
enabled
Setting
disabled
Setting
disabled
Setting
disabled
External
interrupt
enabled
selected
Resource
other than
above
T
Maintain
previous
state
Maintain
previous
state
GPIO
selected
GPIO
Hi-Z /
Internal
input
selected
Internal
input fixed
at 0
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
fixed at 0
Internal
input fixed
at 0
Hi-Z
selected
GPIO
selected
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and
Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
Document Number: 002-05637 Rev.*B
Page 59 of 118
MB9A140NB Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Rating
Symbol
VCC
Unit
Remarks
Min
VSS - 0.5
VSS - 0.5
Max
Power supply voltage *1, *2
Analog power supply voltage *1, *3
VSS + 4.6
VSS + 4.6
V
V
AVCC
Analog reference voltage *1, *3
AVRH
VSS - 0.5
VSS + 4.6
V
VCC + 0.5
(≤ 4.6 V)
VSS + 6.5
AVCC + 0.5
(≤ 4.6 V)
VCC + 0.5
(≤ 4.6 V)
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
Input voltage *1
VI
5 V tolerant
Analog pin input voltage *1
Output voltage *1
VIA
VO
VSS - 0.5
V
10
39
mA
mA
L level maximum output current *4
L level average output current *5
IOL
-
P80/P81 pins
P80/P81 pins
4
mA
mA
mA
mA
IOLAV
-
10.5
100
50
L level total maximum output current
L level total average output current *6
∑IOL
∑IOLAV
-
-
- 10
39
mA
mA
H level maximum output current *4
H level average output current *5
IOH
-
P80/P81 pins
P80/P81 pins
- 4
12
- 100
- 50
300
+ 150
mA
mA
mA
mA
mW
°C
IOHAV
-
H level total maximum output current
H level total average output current *6
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that VSS = AVSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a
100 ms period.
*6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-05637 Rev.*B
Page 60 of 118
MB9A140NB Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Value
Parameter
Power supply voltage
Symbol
VCC
Conditions
Unit
Remarks
Min
1.65 *2
1.65
2.7
AVCC
AVSS
1
Max
3.6
3.6
AVCC
AVCC
AVSS
10
-
-
V
V
V
V
V
µF
°C
Analog power supply voltage
AVCC
AVCC = VCC
AVCC ≥ 2.7 V
AVCC< 2.7 V
AVRH
-
Analog reference voltage
AVRL
CS
TA
-
--
-
Smoothing capacitor
Operating temperature
For Regulator *1
- 40
+ 85
*1: See "C Pin" in "7. Handling Devices" for the connection of the smoothing capacitor.
*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or
built-in Low-speed CR is possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this datasheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-05637 Rev.*B
Page 61 of 118
MB9A140NB Series
12.3 DC Characteristics
12.3.1 Current Rating
(VCC = AVCC = 1.65 V to 3.6 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
mA
Remarks
Typ *3
Max *4
CPU: 40 MHz,
Peripheral: 40 MHz
CPU: 40 MHz,
Peripheral: the clock stops
NOP operation
15.5
21
*1, *5
PLL
Rrun mode
8.7
1.8
12
mA
mA
*1, *5
*1
High-speed
CR
ICC
CPU/ Peripheral: 4 MHz *2
2.9
Rrun mode
Sub
CPU/ Peripheral: 32 kHz
CPU/ Peripheral: 100 kHz
Peripheral: 40 MHz
110
125
9
680
700
12.5
1.6
μA
μA
mA
mA
μA
μA
*1, *6
*1
Rrun mode
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Power supply
current
VCC
*1, *5
*1
Peripheral: 4 MHz *2
Peripheral: 32 kHz
0.8
96
ICCS
670
680
*1, *6
*1
Sleep mode
Low-speed
CR
Peripheral: 100 kHz
110
Sleep mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=3.6 V
*4: TA=+85°C, VCC=3.6 V
*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05637 Rev.*B
Page 62 of 118
MB9A140NB Series
Value
Typ *2 Max *2
Pin
name
Parameter
Symbol
Conditions
Unit
mA
Remarks
*1, *3
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
2.1
-
2.5
3.4
35
Main Timer mode
Sub Timer mode
RTC mode
mA
μA
μA
μA
μA
μA
*1, *3
*1, *4
*1, *4
*1, *4
*1, *4
*1
ICCT
12
-
330
29
9.8
-
ICCR
280
28
When LVD is off
TA = + 25°C,
When LVD is off
9
ICCH
Stop mode
TA = + 85°C,
When LVD is off
-
270
7
μA
μA
*1
TA = + 25°C,
When LVD is off,
When RAM is off
1.25
*1, *4, *5
TA = + 25°C,
When LVD is off,
When RAM is on
Power supply
current
VCC
5.3
18
μA
*1, *4, *5
Deep Standby
Stop mode
ICCHD
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
When LVD is off,
When RAM is on
TA = + 25°C,
70
100
9
μA
μA
μA
*1, *4, *5
*1, *4, *5
*1, *5
-
When LVD is off,
When RAM is off
1.9
5.9
TA = + 25°C,
When LVD is off,
When RAM is on
20
μA
*1, *5
Deep Standby
RTC mode
ICCRD
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
When LVD is off,
When RAM is on
75
μA
μA
*1, *5
*1, *5
-
105
*1: When all ports are fixed.
*2: VCC=3.6 V
*3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
*5: RAM on/off setting is on-chip SRAM only.
Document Number: 002-05637 Rev.*B
Page 63 of 118
MB9A140NB Series
Low-Voltage Detection Current
(VCC = 1.65 V to 3.6 V, VDDI = 1.1 V to 1.3 V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
At operation
for reset
VCC = 3.6 V
0.13
0.3
0.3
μA
At not detect
Low-voltage detection
circuit (LVD) power
supply current
ICCLVD
VCC
At operation
for interrupt
VCC = 3.6 V
0.13
μA
At not detect
Flash Memory Current
Parameter
(VCC = 1.65 V to 3.6 V, VDDI = 1.1 V to 1.3 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Pin
name
Symbol
Conditions
Unit
Remarks
Typ
Max
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
9.5
11.2
mA
*1
*1: The current at which to write or erase Flash memory, ICCFLASH is added to ICC
.
A/D Converter Current
(VCC = VCC28 = AVCC = 1.65 V to 3.6 V, VDDI = 1.1 V to 1.3 V, VSS = AVSS = 0 V, TA = - 40°C to +85°C)
Value
Pin
name
Parameter
Symbol
Conditions
At 1unit operation
At stop
Unit
mA
Remarks
Typ
0.27
Max
0.42
Power supply current
ICCAD
AVCC
0.03
0.72
0.02
10
μA
mA
μA
At 1unit operation
AVRH=3.6 V
1.29
2.6
Reference power
supply current
ICCAVRH
AVRH
At stop
Document Number: 002-05637 Rev.*B
Page 64 of 118
MB9A140NB Series
12.3.2 Pin Characteristics
(VCC = AVCC = 1.65 V to 3.6 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
VCC ≥ 2.7 V
Unit
Remarks
Min
Typ
Max
CMOS
VCC × 0.8
hysteresis
input pin,
MD0, MD1
-
VCC + 0.3
V
H level input
VCC < 2.7 V
VCC × 0.7
VCC × 0.8
voltage
(hysteresis
input)
VIHS
VCC ≥ 2.7 V
5V tolerant
input pin
-
-
-
-
VSS + 5.5
V
V
V
V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC × 0.7
VSS - 0.3
CMOS
VCC × 0.2
VCC × 0.3
VCC × 0.2
hysteresis
input pin,
MD0, MD1
L level input
voltage
(hysteresis
input)
VILS
5V tolerant
input pin
VSS - 0.3
VCC < 2.7 V
VCC × 0.3
VCC ≥ 2.7 V,
IOH = - 4 mA
VCC - 0.5
4 mA type
P80/P81
VCC
VCC < 2.7 V,
IOH = - 2 mA
VCC - 0.45
H level
output voltage
VOH
VCC ≥ 2.7 V,
IOH = - 12 mA
VCC - 0.4
-
-
-
VCC
0.4
0.4
V
V
V
VCC < 2.7 V,
IOH = - 6.5 mA
VCC ≥ 2.7 V,
IOL = 4 mA
4 mA type
VSS
VCC < 2.7 V,
IOL = 2 mA
L level
output voltage
VOL
VCC ≥ 2.7 V,
IOL = 10.5 mA
P80/P81
-
VSS
VCC < 2.7 V,
IOL = 5 mA
-
- 5
-
-
-
+ 5
μA
μA
Input leak current
IIL
CEC0,
CEC1
VCC = AVCC = AVRH =
VSS = AVSS = 0.0 V
+1.8
VCC ≥ 2.7 V
21
-
33
-
66
Pull-up resistor
value
RPU
Pull-up pin
kΩ
VCC < 2.7 V
134
Other than
VCC,
Input capacitance
CIN
VSS,
-
-
5
15
pF
AVCC,
AVSS, AVRH
Document Number: 002-05637 Rev.*B
Page 65 of 118
MB9A140NB Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
MHz
Remarks
name
Min
Max
VCC ≥ 2.7 V
4
4
48
20
When crystal oscillator is
connected
VCC < 2.7 V
Input frequency
fCH
When using external
clock
-
-
4
48
MHz
ns
X0,
X1
When using external
clock
Input clock cycle
tCYLH
-
20.83
250
PWH/tCYLH,
PWL/tCYLH
When using external
clock
When using external
clock
Input clock pulse width
45
-
55
5
%
Input clock rising time and tCF,
falling time
-
ns
tCR
fCM
-
-
-
-
-
-
40
40
MHz
MHz
Master clock
fCC
Base clock (HCLK/FCLK)
Internal operating
clock *1 frequency
fCP0
fCP1
fCP2
-
-
-
-
-
-
-
-
-
40
40
40
MHz
MHz
MHz
APB0 bus clock *2
APB1 bus clock *2
APB2 bus clock *2
tCYCC
-
-
25
-
ns
Base clock (HCLK/FCLK)
tCYCP0
tCYCP1
tCYCP2
-
-
-
-
-
-
25
25
25
-
-
-
ns
ns
ns
APB0 bus clock *2
APB1 bus clock *2
APB2 bus clock *2
Internal operating
clock[1] cycle time
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
*2: For about each APB bus which each peripheral is connected to, see 8. Block Diagram in this datasheet.
X0
Document Number: 002-05637 Rev.*B
Page 66 of 118
MB9A140NB Series
12.4.2 Sub Clock Input Characteristics
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
When crystal oscillator is
connected
-
-
32.768
-
kHz
Input frequency
fCL
tCYLL
-
-
-
32
10
-
-
100
kHz
When using external clock
When using external clock
X0A,
X1A
Input clock cycle
31.25
μs
PWH/tCYLL,
PWL/tCYLL
Input clock pulse width
45
-
55
%
When using external clock
X0A
12.4.3 Built-in CR Oscillation Characteristics
Built-in high-speed CR
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
TA = + 25°C
Unit
Remarks
Min
3.96
Typ
Max
4.04
4
4
4
VCC ≥ 2.7 V
TA = + 25°C
VCC < 2.7 V
When trimming *1
3.9
4.1
Clock frequency
fCRH
MHz
TA =
- 40°C to + 85°C
3.84
4.16
TA =
- 40°C to + 85°C
2.8
-
-
-
5.2
30
When not trimming
*2
Frequency stabilization
time
tCRWT
-
μs
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value.
This period is able to use High-speed CR clock as source clock.
Built-in low-speed CR
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
50
Typ
Max
150
Clock frequency
fCRL
-
100
kHz
Document Number: 002-05637 Rev.*B
Page 67 of 118
MB9A140NB Series
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol
Unit
μs
Remarks
Min
100
Max
PLL oscillation stabilization wait time *1
(LOCK UP time)
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency *2
tLOCK
fPLLI
-
fPLLO
fCLKPLL
-
-
4
5
75
-
-
-
-
-
16
37
150
40
MHz
multiple
MHz
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of
the Main PLL)
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min
100
Typ
Max
PLL oscillation stabilization wait time *1
(LOCK UP time)
tLOCK
-
-
μs
PLL input clock frequency
PLL multiple rate
fPLLI
-
fPLLO
fCLKPLL
3.8
19
4
-
4.2
35
MHz
multiple
MHz
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency *2
72
-
-
-
150
40
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
Note:
−
Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency/temperature
has been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Main PLL connection
Main PLL
PLL input
clock
PLL macro
clock
Main clock (CLKMO)
oscillation clock
(CLKPLL)
K
M
Main
PLL
High-speed CR clock (CLKHC)
divider
divider
N
divider
Document Number: 002-05637 Rev.*B
Page 68 of 118
MB9A140NB Series
12.4.6 Reset Input Characteristics
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Reset input time
Symbol
tINITX
Pin name
Conditions
Unit
ns
Remarks
Min
Max
INITX
-
500
-
12.4.7 Power-on Reset Timing
(VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
1
Typ
Max
-
Power supply shut down time
Power ramp rate
tOFF
-
-
-
ms
*1
dV/dt
Vcc:0.2 V to 1.65 V
0.2
1000
mV/μs *2
VCC
Time until releasing Power-on
reset
tPRT
-
1.34
-
16.09
ms
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per “12. 4. 6.Reset
Input Characteristics”.
1.65V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary:
VDH: detection voltage of Low Voltage detection reset. See “12.6 Low-Voltage Detection Characteristics”
Document Number: 002-05637 Rev.*B
Page 69 of 118
MB9A140NB Series
12.4.8 External Bus Timing
External bus clock output characteristics
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
MCLKOUT *1
Conditions
Unit
Min
Max
VCC ≥ 2.7 V
VCC < 2.7 V
-
-
40
20
MHz
MHz
Output frequency
tCYCLE
*1: The external bus clock output (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family Peripheral Manual.
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
MCLKOUT
External bus signal input/output characteristics
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Value
Unit
Remarks
VIH
VIL
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
V
V
V
V
Signal input characteristics
-
VOH
VOL
Signal output characteristics
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
Document Number: 002-05637 Rev.*B
Page 70 of 118
MB9A140NB Series
Separate Bus Access Asynchronous SRAM Mode
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tOEW
Pin name
Conditions
Unit
ns
Min
Max
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MOEX
MOEX
MCLK×n-3
-
Min pulse width
MCSX ↓ → Address output
delay time
-9
-12
+9
+12
MCSX[7:0],
MAD[24:0]
MOEX,
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
MOEX ↑ →
Address hold time
0
MAD[24:0]
MCLK×m-9
MCLK×m-12
MCSX ↓ →
MOEX ↓ delay time
MOEX ↑ →
MOEX,
MCSX[7:0]
0
MCSX ↑ time
MCLK×m-9
MCLK×m-12
MCSX ↓ →
MCSX,
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MDQM[1:0]
30
38
MOEX,
MADATA[15:0]
MOEX,
MADATA[15:0]
-
MOEX ↑ →
Data hold time
tDH - OE
0
-
-
MWEX
tWEW
MWEX
MCLK×n-3
0
Min pulse width
MWEX ↑ → Address output
delay time
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MWEX,
MAD[24:0]
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL - DV
tWEH - DX
MCLK×n-9
MCLK×n-12
MCSX ↓ →
MWEX ↓ delay time
MWEX,
MCSX[7:0]
MWEX ↑ →
MCSX ↑ delay time
MCSX ↓→
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCSX,
MDQM ↓ delay time
MDQM[1:0]
MWEX ↓→
Data output time
MWEX ↑ →
MCSX,
MADATA[15:0]
MWEX,
MADATA[15:0]
MCLK-12
MCLK+12
MCLK×m+9
MCLK×m+12
0
Data hold time
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
Document Number: 002-05637 Rev.*B
Page 71 of 118
MB9A140NB Series
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
Document Number: 002-05637 Rev.*B
Page 72 of 118
MB9A140NB Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
ns
Min
Max
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC <2.7 V
VCC ≥ 2.7 V
VCC <2.7 V
12
13
MCLK,
Address delay time
tAV
1
1
1
1
1
MAD[24:0]
tCSL
tCSH
tREL
tREH
tDS
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK,
MCSX delay time
MOEX delay time
MCSX[7:0]
9
12
9
MCLK,
MOEX
12
24
37
Data set up →
MCLK ↑ time
MCLK ↑ →
MCLK,
-
-
MADATA[15:0]
MCLK,
tDH
0
1
1
1
1
Data hold time
MADATA[15:0]
9
12
9
12
9
12
9
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
MCLK,
MWEX
MWEX delay time
MDQM[1:0]
delay time
MCLK,
MDQM[1:0]
12
MCLK + 18
MCLK + 24
18
MCLK ↑ →
Data output time
MCLK,
MCLK + 1
1
MADATA[15:0]
MCLK ↑ →
Data hold time
MCLK,
MADATA[15:0]
24
Note:
−
When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
Document Number: 002-05637 Rev.*B
Page 73 of 118
MB9A140NB Series
Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Multiplexed
Symbol
tALE-CHMADV
tCHMADH
Pin name
Conditions
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
Unit
ns
ns
Min
Max
+10
+20
MCLK×n+10
MCLK×n+20
-2
address delay time
MALE,
MADATA[15:0]
MCLK×n+0
MCLK×n+0
Multiplexed
address hold time
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05637 Rev.*B
Page 74 of 118
MB9A140NB Series
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tCHAL
Pin name
Conditions
Unit
ns
ns
ns
ns
Remarks
Min
Max
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
9
12
9
1
1
MCLK,
MALE delay time
ALE
tCHAH
12
MCLK ↑ →
Multiplexed
Address delay time
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
tCHMADV
1
1
tOD
ns
ns
MCLK,
MADATA[15:0]
MCLK ↑ →
Multiplexed
Data output time
tCHMADX
tOD
Note:
−
When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05637 Rev.*B
Page 75 of 118
MB9A140NB Series
External Ready Input Timing
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
MCLK ↑
MRDY input
setup time
VCC ≥ 2.7 V
23
37
MCLK,
MRDY
tRDYI
-
ns
VCC < 2.7 V
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-05637 Rev.*B
Page 76 of 118
MB9A140NB Series
12.4.9 Base Timer Input Timing
Timer input timing
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
TIOAn/TIOBn
(when using as ECK,
TIN)
Conditions
Unit
Remarks
Min
2tCYCP
Max
tTIWH
tTIWL
,
Input pulse width
-
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
2tCYCP
Max
TIOAn/TIOBn
(when using as
TGIN)
tTRGH
,
Input pulse width
-
-
ns
tTRGL
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see “8. Block Diagram” in this datasheet.
Document Number: 002-05637 Rev.*B
Page 77 of 118
MB9A140NB Series
12.4.10 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Min Max
VCC ≥ 2.7 V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
-
8
-
8
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVI
- 30
50
0
+ 30
- 20
36
0
+ 20
ns
ns
ns
Master mode
tIVSHI
-
-
-
-
tSHIXI
tSLSH
tSHSL
Serial clock L pulse width
Serial clock H pulse width
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
33
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "8. Block Diagram" in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL= 30 pF.
Document Number: 002-05637 Rev.*B
Page 78 of 118
MB9A140NB Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05637 Rev.*B
Page 79 of 118
MB9A140NB Series
CSIO (SPI = 0, SCINV = 1)
Parameter
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Min Max
VCC ≥ 2.7 V
Min Max
Pin
name
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
tSHOVI
tIVSLI
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
- 30
+ 30
- 20
+ 20
ns
Master mode
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
50
0
-
-
36
0
-
-
ns
ns
tSLIXI
tSLSH
tSHSL
Serial clock L pulse width
Serial clock H pulse width
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
33
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see “8. Block Diagram” in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05637 Rev.*B
Page 80 of 118
MB9A140NB Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05637 Rev.*B
Page 81 of 118
MB9A140NB Series
CSIO (SPI = 1, SCINV = 0)
Parameter
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Min Max
VCC ≥ 2.7 V
Min Max
Pin
name
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
tIVSLI
tSLIXI
tSOVLI
50
-
-
-
36
-
-
-
ns
ns
ns
Master mode
0
0
2tCYCP - 34
2tCYCP - 34
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
33
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "8. Block Diagram" in this datasheet.
−
−
These characteristics only guarantees the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL= 30 pF.
Document Number: 002-05637 Rev.*B
Page 82 of 118
MB9A140NB Series
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
tF
VIH
VIH
SCK
SOT
SIN
VIL
VIL
tR
tSHOVE
*
VOH
VOL
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05637 Rev.*B
Page 83 of 118
MB9A140NB Series
CSIO (SPI = 1, SCINV = 1)
Parameter
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Min Max
VCC ≥ 2.7 V
Min Max
Pin
name
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
- 30
4tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
Master mode
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
tIVSHI
tSHIXI
tSOVHI
50
-
-
-
36
-
-
-
ns
ns
ns
0
0
2tCYCP - 34
2tCYCP - 34
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
33
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "8. Block Diagram" in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05637 Rev.*B
Page 84 of 118
MB9A140NB Series
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
Parameter
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Symbol
Conditions
Unit
Remarks
Min
tCYCP + 10
tCYCP + 10
Max
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
tSLSH
tSHSL
tF
-
-
5
5
ns
ns
ns
ns
CL = 30 pF
-
-
SCK rising time
tR
tF
tR
tSHSL
tSLSH
SCK
VIH
VIH
VIH
IL
IL
IL
V
V
V
Document Number: 002-05637 Rev.*B
Page 85 of 118
MB9A140NB Series
12.4.11 External Input Timing
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Min
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Max
A/D converter trigger
input
*1
ADTG
-
2tCYCP
-
ns
ns
tINH,
tINL
Input pulse width
*2
2tCYCP + 100 *1
-
INTxx,
NMIX
External interrupt
NMI
*3
*4
500
600
-
-
ns
ns
WKUPx
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Multi-function Timer is connected to, see 8. Block Diagram in this datasheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in Timer mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
Document Number: 002-05637 Rev.*B
Page 86 of 118
MB9A140NB Series
12.4.12 I2C Timing
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Standard-mode
Fast-mode
Min Max
Parameter
Symbol
Conditions
Unit Remarks
Min
Max
100
SCL clock frequency
(Repeated) START condition hold
time
FSCL
0
0
400
kHz
μs
tHDSTA
4.0
-
0.6
-
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
(Repeated) START condition setup
time
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
SCL ↑ → SDA ↓
Data hold time
CL = 30 pF,
*1
R = (Vp/IOL
)
tHDDAT
tSUDAT
tSUSTO
0
3.45 *2
0
0.9 *3
μs
ns
μs
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
250
4.0
-
-
100
0.6
-
-
Bus free time between
STOP condition and
START condition
Noise filter
tBUF
tSP
4.7
-
-
1.3
-
-
μs
*4
*4
-
2 tCYCP
2 tCYCP
ns
*1: R and C represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see 8. Block Diagram in this datasheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05637 Rev.*B
Page 87 of 118
MB9A140NB Series
12.4.13 ETM Timing
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
TRACECLK,
Conditions
VCC ≥ 2.7 V
Unit
Remarks
Min
Max
2
2
-
11
Data hold
tETMH
ns
TRACED[3:0]
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
15
40
20
-
MHz
MHz
ns
TRACECLK
frequency
1/ tTRACE
-
TRACECLK
25
50
TRACECLK
clock cycle
tTRACE
-
ns
Note:
−
When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-05637 Rev.*B
Page 88 of 118
MB9A140NB Series
12.4.14 JTAG Timing
(VCC = 1.65 V to 3.6 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
TMS, TDI setup time
TMS, TDI hold time
Symbol
tJTAGS
Pin name
TCK,
Conditions
VCC ≥ 2.7 V
Unit
ns
Remarks
Min
Max
15
15
-
-
TMS, TDI
VCC < 2.7 V
VCC ≥ 2.7 V
TCK,
TMS, TDI
tJTAGH
ns
ns
VCC < 2.7 V
VCC ≥ 2.7 V
-
-
25
45
TCK,
TDO
TDO delay time
tJTAGD
VCC < 2.7 V
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05637 Rev.*B
Page 89 of 118
MB9A140NB Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 1.65 V to 3.6 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C)
Value
Typ
Pin
Parameter
Resolution
Symbol
Unit
Remarks
name
Min
Max
-
-
-
-
-
-
-
-
-
-
-
-
12
bit
Integral Nonlinearity
± 2
± 2.2
± 6
± 4.5
± 2.5
± 15
AVRH ± 15
-
LSB
LSB
mV
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
VZT
VFST
ANxx
ANxx
AVRH ± 6
-
mV
2.0 *1
4.0 *1
10 *1
0.6
AVCC ≥ 2.7 V
Conversion time
-
-
-
-
-
-
-
-
-
μs
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
Sampling time *2
tS
10
us
1.2
-
-
1.8 V< AVCC < 2.7 V
3.0
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
100
200
500
Compare clock cycle *3
tCCK
-
1000
1.0
ns
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
State transition time to
operation permission
Power supply current
(analog + digital)
tSTT
-
-
-
-
μs
-
-
0.27
0.03
0.42
10
mA
μA
A/D 1unit operation
When A/D stops
A/D 1unit operation
AVRH=3.6 V
AVCC
Reference power supply
current
(between AVRH to AVSS)
-
0.72
1.29
mA
-
AVRH
-
-
-
0.02
-
2.6
9.4
2.2
μA
When A/D stops
Analog input capacity
Analog input resistor
CAIN
pF
AVCC ≥ 2.7 V
RAIN
-
-
-
kΩ
5.5
10.5
4
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
Interchannel disparity
Analog port input leak
current
-
-
-
-
-
-
-
-
-
LSB
μA
V
ANxx
ANxx
5
Analog input voltage
AVSS
2.7
AVRH
AVCC
AVSS
AVCC ≥ 2.7 V
AVCC < 2.7 V
-
-
AVRH
AVRL
-
-
V
V
AVCC
AVSS
Reference voltage
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 2.7 V, HCLK=40 MHz
1.8 V < AVCC < 2.7 V, HCLK=40 MHz
1.65 V < AVCC < 1.8 V, HCLK=40 MHz
sampling time: 0.6 μs, compare time: 1.4 μs
sampling time: 1.2 μs, compare time: 2.8 μs
sampling time: 3 μs, compare time: 7 μs
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and the compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual
Analog Macro Port.
The register setting of the A/D Converter are reflected in the operation according to the APB bus clock timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see 8. Block Diagram in this datasheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Document Number: 002-05637 Rev.*B
Page 90 of 118
MB9A140NB Series
Comparator
ANxx
Analog input pin
REXT
RAIN
Analog
signal source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
Sampling time[ns]
RAIN
:
Input resistor of A/D[kΩ] = 2.2 kΩ at 2.7 V < AVCC < 3.6 V
Input resistor of A/D[kΩ] = 5.5 kΩ at 1.8 V < AVCC < 2.7 V
Input resistor of A/D[kΩ] = 10.5 kΩ at 1.65 V < AVCC < 1.8 V
Input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V
Output impedance of external circuit [kΩ]
CAIN
:
REXT
:
(Equation 2) tC = tCCK × 14
tC:
Compare time
Compare clock cycle
tCCK
:
Document Number: 002-05637 Rev.*B
Page 91 of 118
MB9A140NB Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
Integral Nonlinearity:
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to
change the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
Analog input
VZT
Actual conversion characteristics
AVSS
AVRH
AVSS
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Linearity error of digital output N =
[LSB]
V(N + 1) T - VNT
Differential linearity error of digital output N =
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
VNT:
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
Document Number: 002-05637 Rev.*B
Page 92 of 118
MB9A140NB Series
12.6 Low-Voltage Detection Characteristics
12.6.1 Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Value
Typ
1.50
1.55
1.55
Parameter
Symbol
Conditions
Unit
Remarks
Min
1.38
1.43
1.43
Max
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
1.60
1.65
1.65
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHR *1 = 00000
SVHR *1 = 00001
SVHR *1 = 00010
SVHR *1 = 00011
SVHR *1 = 00100
SVHR *1 = 00101
SVHR *1 = 00110
SVHR *1 = 00111
SVHR *1 = 01000
SVHR *1 = 01001
SVHR *1 = 01010
SVHR *1 = 01011
SVHR *1 = 01100
SVHR *1 = 01101
SVHR *1 = 01110
SVHR *1 = 01111
SVHR *1 = 10000
SVHR *1 = 10001
SVHR *1 = 10010
SVHR *1 = 10011
Same as SVHR = 00000 value
1.47 1.60 1.73
Same as SVHR = 00000 value
1.52 1.65 1.78
Same as SVHR = 00000 value
1.56 1.70 1.84
Same as SVHR = 00000 value
1.61 1.75 1.89
Same as SVHR = 00000 value
1.66 1.80 1.94
Same as SVHR = 00000 value
1.70 1.85 2.00
Same as SVHR = 00000 value
1.75 1.90 2.05
Same as SVHR = 00000 value
1.79 1.95 2.11
Same as SVHR = 00000 value
1.84 2.00 2.16
Same as SVHR = 00000 value
1.89 2.05 2.21
Same as SVHR = 00000 value
2.30 2.50 2.70
Same as SVHR = 00000 value
2.39 2.60 2.81
Same as SVHR = 00000 value
2.48 2.70 2.92
Same as SVHR = 00000 value
2.58 2.80 3.02
Same as SVHR = 00000 value
2.67 2.90 3.13
Same as SVHR = 00000 value
2.76 3.00 3.24
Same as SVHR = 00000 value
2.85 3.10 3.35
Same as SVHR = 00000 value
2.94 3.20 3.46
Same as SVHR = 00000 value
LVD stabilization wait
time
*2
tLVDW
-
-
-
-
-
-
5200 × tCYCP
200
μs
μs
LVD detection delay
time
tLVDDL
*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to 00000 by Low-Voltage Detection
Reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05637 Rev.*B
Page 93 of 118
MB9A140NB Series
12.6.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Value
Typ
1.70
Parameter
Detected voltage
Symbol
Conditions
SVHI = 00100
Unit
Remarks
Min
1.56
Max
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
1.84
1.89
1.89
1.94
1.94
2.00
2.00
2.05
2.05
2.11
2.11
2.16
2.16
2.21
2.21
2.27
2.70
2.81
2.81
2.92
2.92
3.02
3.02
3.13
3.13
3.24
3.24
3.35
3.35
3.46
3.46
3.56
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
1.61
1.61
1.66
1.66
1.70
1.70
1.75
1.75
1.79
1.79
1.84
1.84
1.89
1.89
1.93
2.30
2.39
2.39
2.48
2.48
2.58
2.58
2.67
2.67
2.76
2.76
2.85
2.85
2.94
2.94
3.04
1.75
1.75
1.80
1.80
1.85
1.85
1.90
1.90
1.95
1.95
2.00
2.00
2.05
2.05
2.10
2.50
2.60
2.60
2.70
2.70
2.80
2.80
2.90
2.90
3.00
3.00
3.10
3.10
3.20
3.20
3.30
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
SVHI = 01011
SVHI = 01100
SVHI = 01101
SVHI = 01110
SVHI = 01111
SVHI = 10000
SVHI = 10001
SVHI = 10010
SVHI = 10011
*1
LVD stabilization wait time
LVD detection delay time
tLVDW
-
-
-
-
-
-
5200 × tCYCP
200
μs
μs
tLVDDL
*1: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05637 Rev.*B
Page 94 of 118
MB9A140NB Series
12.7 Flash Memory Write/Erase Characteristics
12.7.1 Write / Erase time
(VCC = 1.65 V to 3.6 V, TA = - 40°C to + 85°C)
Value
Parameter
Large Sector
Small Sector
Unit
Remarks
Typ *1
Max *1
1.1
0.3
2.7
0.9
Sector erase time
s
Includes write time prior to internal erase
Half word (16-bit)
write time
30
528
18
μs
Not including system-level overhead time
Includes write time prior to internal erase
Chip erase time
6.8
s
*1: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12.7.2 Erase/write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
Remarks
1,000
20 *1
10 *1
10,000
*1: At average + 85°C
Document Number: 002-05637 Rev.*B
Page 95 of 118
MB9A140NB Series
12.8 Return Time from Low-Power Consumption Mode
12.8.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 1.65 V to 3.6 V, VDDI = 1.1 V to 1.3 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max *1
Sleep mode
tCYCC
40
High-speed CR Timer mode,
Main Timer mode,
80
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
350
690
278
700
880
523
μs
μs
μs
tICNT
RTC mode,
Stop mode
318
278
603
523
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
*1: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt *1)
External
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*1: External interrupt is set to detecting fall edge.
Document Number: 002-05637 Rev.*B
Page 96 of 118
MB9A140NB Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt *1)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*1: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual.
Document Number: 002-05637 Rev.*B
Page 97 of 118
MB9A140NB Series
12.8.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 1.65 V to 3.6 V, VDDI = 1.1 V to 1.3 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max *1
Sleep mode
148
148
263
263
High-speed CR Timer mode,
Main Timer mode,
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
258
322
278
483
516
523
μs
μs
μs
tRCNT
RTC/Stop mode
318
278
603
523
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
*1: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
Document Number: 002-05637 Rev.*B
Page 98 of 118
MB9A140NB Series
Operation example of return from low power consumption mode (by internal resource reset *1)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*1: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral
Manual.
−
The time during the power-on reset/low-voltage detection reset is excluded. See 12.4.7. Power-on Reset Timing
12.4. AC Characteristics in 12. Electrical Characteristics for the detail on the time during the power-on reset/low -voltage
detection reset.
−
−
When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05637 Rev.*B
Page 99 of 118
MB9A140NB Series
13.Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Main: 64 KB
Work: 32 KB
MB9AF141LBPMC1-G-JNE2
MB9AF142LBPMC1-G-JNE2
MB9AF144LBPMC1-G-JNE2
MB9AF141LBPMC-G-JNE2
MB9AF142LBPMC-G-JNE2
MB9AF144LBPMC-G-JNE2
MB9AF141LBQN-G-AVE2
MB9AF142LBQN-G-AVE2
MB9AF144LBQN-G-AVE2
MB9AF141MBPMC-G-JNE2
MB9AF142MBPMC-G-JNE2
MB9AF144MBPMC-G-JNE2
MB9AF141MBPMC1-G-JNE2
MB9AF142MBPMC1-G-JNE2
MB9AF144MBPMC1-G-JNE2
MB9AF141MBBGL-GE1
16 KB
Plastic LQFP 64-pin
(0.5 mm pitch),
(LQD064)
Main: 128 KB
Work: 32 KB
16 KB
32 KB
16 KB
16 KB
32 KB
16 KB
16 KB
32 KB
16 KB
16 KB
32 KB
16 KB
16 KB
32 KB
16 KB
16 KB
32 KB
16 KB
16 KB
32 KB
Main: 256 KB
Work: 32 KB
Main: 64 KB
Work: 32 KB
Plastic LQFP 64-pin
(0.65 mm pitch),
(LQG064)
Main: 128 KB
Work: 32 KB
Main: 256 KB
Work: 32 KB
Main: 64 KB
Work: 32 KB
Plastic QFN 64-pin
(0.5 mm pitch),
(VNC064)
Main: 128 KB
Work: 32 KB
Main: 256 KB
Work: 32 KB
Main: 64 KB
Work: 32 KB
Plastic LQFP 80-pin
(0.5 mm pitch),
(LQH080)
Main: 128 KB
Work: 32 KB
Tray
Main: 256 KB
Work: 32 KB
Main: 64 KB
Work: 32 KB
Plastic LQFP 80-pin
(0.65 mm pitch),
(LQJ080)
Main: 128 KB
Work: 32 KB
Main: 256 KB
Work: 32 KB
Main: 64 KB
Work: 32 KB
Plastic PFBGA 96-pin
(0.5 mm pitch),
(FDG096)
Main: 128 KB
Work: 32 KB
MB9AF142MBBGL-GE1
Main: 256 KB
Work: 32 KB
MB9AF144MBBGL-GE1
Main: 64 KB
Work: 32 KB
MB9AF141NBPMC-G-JNE2
MB9AF142NBPMC-G-JNE2
MB9AF144NBPMC-G-JNE2
Plastic LQFP 100-pin
(0.5 mm pitch),
(LQI100)
Main: 128 KB
Work: 32 KB
Main: 256 KB
Work: 32 KB
Document Number: 002-05637 Rev.*B
Page 100 of 118
MB9A140NB Series
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Main: 64 KB
Work: 32 KB
MB9AF141NBPQC-G-JNE2
MB9AF142NBPQC-G-JNE2
MB9AF144NBPQC-G-JNE2
MB9AF141NBBGL-GE1
MB9AF142NBBGL-GE1
MB9AF144NBBGL-GE1
16 KB
Plastic QFP 100-pin
(0.65 mm pitch),
(PQH100)
Main: 128 KB
Work: 32 KB
16 KB
32 KB
16 KB
16 KB
32 KB
Main: 256 KB
Work: 32 KB
Tray
Main: 64 KB
Work: 32 KB
Plastic PFBGA 112-pin
(0.8 mm pitch),
(LBC112)
Main: 128 KB
Work: 32 KB
Main: 256 KB
Work: 32 KB
Document Number: 002-05637 Rev.*B
Page 101 of 118
MB9A140NB Series
14.Package Dimensions
Package Type
Package Code
LQFP 100
LQI100
4
4
D
D
5
7
5
7
D1
D1
75
51
51
75
76
50
50
76
E1
E1
E
E
5
7
5
7
4
4
3
6
100
26
26
100
1
1
25
25
2
5
7
e
0.1 0
C
A-B
D
3
BOTTOM VIEW
0.2 0
C A-B D
b
8
0.0 8
C
A-B
D
TOP VIEW
2
A
9
A
SEATING
PLANE
c
A1
A'
0.25
b
L1
0.0 8
C
10
SECTION A-A'
L
SIDE VIEW
DETAIL A
NOTES :
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE MOLD PARTING
LINE COINCIDENT WITH WHERE THE LEAD EXITS THE BODY.
3. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H.
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
4. TO BE DETERMINED AT SEATING PLANE C.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLEPROTRUSION IS 0.25mm PRE SIDE.
c
D
D1
e
16.00 BSC
14.00 BSC
0.50 BSC
DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE H.
6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED.
E
16.00 BSC
14.00 BSC
7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOWER BODY
SECTIONS. DIMENSIONS D1 AND E1 ARE DETERMINED AT THE LARGEST
FEATURE OF THE BODY EXCLUSIVE OF MOLD FLASH AND GATE BURRS.
BUT INCLUDING ANY MISMATCH BETWEEN THE UPPER AND LOWER
SECTIONS OF THE MOLDER BODY.
E1
L
0.45
0.60 0.75
L1
0.30 0.50 0.70
8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR
PROTRUSION (S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED b
MAXIMUM BY MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE LEAD FOOT.
9. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP.
10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO
THE LOWEST POINT OF THE PACKAGE BODY.
PACKAGE OUTLINE, 100 LEAD LQFP
14.0X14.0X1.7 MM LQI100 REV*A
002-11500 *A
Document Number: 002-05637 Rev.*B
Page 102 of 118
MB9A140NB Series
Package Type
Package Code
QFP 100
PQH100
D
4
D1
5
7
80
51
51
80
81
50
50
81
E1
E
4
5
7
6
3
100
31
31
100
1
30
30
1
2
5
7
e
0.20
C
A-B
D
3
BOTTOM VIEW
b
0.40
C
A-B D
0.13
C A-B
D
8
TOP VIEW
2
9
c
A
SEATING
PLANE
L2
A'
10
0.10
C
b
SECTION A-A'
DETAIL A
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
3.35
A
A1
b
0.05
0.27
0.11
0.45
0.37
0.23
0.32
c
D
23.90 BSC
20.00 BSC
0.65 BSC
D1
e
E
17.90 BSC
14.00 BSC
E1
0
8
L
0.73
0.88 1.03
1.95 REF
0.25 BSC
L1
L2
PACKAGE OUTLINE, 100 LEAD QFP
20.00X14.00X3.35 MM PQH100 REV**
002-15156 **
Document Number: 002-05637 Rev.*B
Page 103 of 118
MB9A140NB Series
Package Type
Package Code
LQFP 80
LQH080
4
D
5
7
D1
60
41
41
60
61
40
40
61
5
7
E1
E
4
3
6
80
21
21
80
1
20
20
1
2
5
8
7
D
3
0.10
C
C
A-B D
BOTTOM VIEW
e
0.08
A-B
D
b
0.20
C A-B D
TOP VIEW
2
A
A
SEATING
PLANE
9
c
A'
L1
0.25
0.08
C
A1
b
L
10
SIDE VIEW
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
c
D
D1
e
14.00 BSC.
12.00 BSC.
0.50 BSC
E
14.00 BSC.
12.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 MM LQH080 Rev **
002-11501 **
Document Number: 002-05637 Rev.*B
Page 104 of 118
MB9A140NB Series
Package Type
Package Code
LQFP 80
LQJ080
4
D
5
7
D1
60
41
41
60
61
40
40
61
E1
E
5
7
4
3
6
80
21
21
80
1
20
b
20
1
2
A-B
5
7
D
0.10
C
C
e
3
0.20
C A-B D
ddd
A-B
D
8
2
A
9
A
SEATING
PLANE
c
A'
A1
b
0.10
C
0.2 5
L
L1
10
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.16 0.32 0.38
0.09 0.20
0.20
c
D
D1
e
16.00 BSC
14.00 BSC
0.65 BSC
E
16.00 BSC
14.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
0
8
PACKAGE OUTLINE, 80 LEAD LQFP
14.0X14.0X1.7 MM LQJ080 REV**
002-14043 **
Document Number: 002-05637 Rev.*B
Page 105 of 118
MB9A140NB Series
Package Type
Package Code
LQFP 64
LQD064
4
D
D1
5
7
48
33
33
48
32
32
49
49
5
7
E1
E
4
3
6
17
17
64
64
1
16
16
1
2
5
7
e
A-B D
3
0.10
0.08
C A-B D
BOTTOM VIEW
0.20
C
C
A-B
D
8
b
TOP VIEW
2
A
9
c
A
SEATING
PLANE
b
0.25
A'
A1
10
SECTION A-A'
L1
0.08
C
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.2
c
0.20
D
D1
e
12.00 BSC.
10.00 BSC.
0.50 BSC
E
12.00 BSC.
10.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
002-11499 **
Document Number: 002-05637 Rev.*B
Page 106 of 118
MB9A140NB Series
Package Type
Package Code
LQFP 64
LQG064
4
D
5
7
D1
48
33
33
48
49
32
32
49
E1
E
5
7
4
3
64
17
17
64
1
16
16
1
2
5
7
BOTTOM VIEW
e
3
0.10
C A-B D
0.20
C A-B D
0.13
C
A-B
D
b
8
TOP VIEW
2
A
A
9
SEATI NG
PLA NE
A1
10
0.2 5
L
c
A'
L1
b
0.10
C
SECTION A -A'
SIDE VIEW
DIMENSION
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.00
0.27 0.32 0.37
0.09 0.20
0.20
c
D
D1
e
14.00 BSC
12.00 BSC
0.65 BSC
E
14.00 BSC
12.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
0
L1
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
002-13881 **
Document Number: 002-05637 Rev.*B
Page 107 of 118
MB9A140NB Series
Package Type
Package Code
QFN 64
VNC064
0.10
C
A B
D2
A
D
48
33
33
48
0.10
2X
C
32
32
49
49
0.10
C A B
5
(ND-1)
e
E
E2
17
64
64
17
1
16
16
1
4
INDEXMARK
8
9
e
B
b
L
0.10
0.05
C A B
0.10
2X
C
C
TOP VIEW
SIDE VIEW
BOTTOMVIEW
0.10
C
A
SEATINGPLANE
0.05
C
C
A1
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
MIN. NOM. MAX.
0.90
2. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994.
3. N IS THE TOTAL NUMBER OF TERMINALS.
A
0.00
9.00 BSC
9.00 BSC
0.05
1
4
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL
HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL,
D
E
b
THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE OR E SIDE.
MAX. PACKAGE WARPAGE IS 0.05mm.
0.20 0.25 0.30
6.00 BSC
5
D
2
6.
7.
8
E
2
e
6.00 BSC
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
0.50 BSC
9
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS WELL AS THE TERMINALS.
R
L
N
0.20 REF
0.40 0.45
0.35
64
16
ND
PACKAGE OUTLINE, 64 LEAD QFN
9.0X9.0X0.9 MM VNC064 6.0X6.0 MM EPAD (SAWN) Rev*.*
002-13234 **
Document Number: 002-05637 Rev.*B
Page 108 of 118
MB9A140NB Series
Package Type
Package Code
FBGA 112
LBC112
A
0.20
2X
C
11
10
9
6
8
7
6
5
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
7
PIN A1
CORNER
6
B
0.20
C
2X
TOP VIEW
BOTTOM VIEW
DETAILA
5
C
112xφ b
0.10
C
SIDE VIEW
0.08
C A B
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. SOLDER BALL POSITION DESIGNATIO
DIMENSIONS
NOM.
SYMBOL
N PER JEP95, SECTION 3, SPP-020.
MIN.
-
MAX.
1.45
0.45
3. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.
A
A1
D
-
0.35
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
0.25
10.00 BSC
E
10.00 BSC
8.00 BSC
8.00 BSC
11
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASUREDWITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
11
112
0.45
WHEN THERE IS AN ODD NUMBEROF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
b
0.35
0.55
eD
eE
SD
SE
0.80 BSC
0.80 BSC
0.00
WHEN THERE IS AN EVEN NUMBEROF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY
CHAMFER, LASER OR INK MARK
7.
0.00
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATESTHE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
PACKAGE OUTLINE, 112 BALL FBGA
10.00X10.00X1.45 MM LBC112 REV**
002-13225 **
Document Number: 002-05637 Rev.*B
Page 109 of 118
MB9A140NB Series
Package Type
Package Code
FBGA 96
FDG096
A
0.20
2X
C
11
10
9
6
8
7
6
5
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
PIN A1
CORNER
6
B
7
0.20
2X
C
TOP VIEW
BOTTOM VIEW
DETAIL A
0.20
C
C
5
0.08
C
96xφ b
0.05
SIDE VIEW
DETAIL A
C
A B
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. SOLDER BALL POSITION DESIGNATIO
DIMENSIONS
NOM.
SYMBOL
N PER JEP95, SECTION 3, SPP-020.
MIN.
MAX.
1.30
0.35
3. "e" REPRESENTSTHE SOLDER BALL GRID PITCH.
A
A1
D
-
-
0.25
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
0.15
6.00 BSC
E
6.00 BSC
5.00 BSC
5.00 BSC
11
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASUREDWITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
11
96
WHEN THERE IS AN ODD NUMBEROF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
0.30
b
0.20
0.40
eD
eE
SD
SE
0.50 BSC
0.50 BSC
0.00
WHEN THERE IS AN EVEN NUMBEROF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY
CHAMFER, LASER OR INK MARK
7.
0.00
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
PACKAGE OUTLINE, 96 BALL FBGA
6.0X6.0X1.3 MM FDG096 REV**
002-13224 **
Document Number: 002-05637 Rev.*B
Page 110 of 118
MB9A140NB Series
15.Errata
This chapter describes the errata for MB9A140N, MB9A140NA and MB9A140MB series. Details include errata trigger conditions,
scope of impact, available workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
15.1 Part Numbers Affected
Part Number
Initial Revision
MB9AF141NPMC-G-JNE2, MB9AF142NPMC-G-JNE2, MB9AF144NPMC-G-JNE2,
MB9AF141NPQC-G-JNE2, MB9AF142NPQC-G-JNE2, MB9AF144NPQC-G-JNE2,
MB9AF141NBGL-GE1, MB9AF142NBGL-GE1, MB9AF144NBGL-GE1,
MB9AF141MPMC-G-JNE2, MB9AF142MPMC-G-JNE2, MB9AF144MPMC-G-JNE2,
MB9AF141MPMC1-G-JNE2, MB9AF142MPMC1-G-JNE2, MB9AF144MPMC1-G-JNE2,
MB9AF141MBGL-GE1, MB9AF142MBGL-GE1, MB9AF144MBGL-GE1,
MB9AF141LPMC1-G-JNE2, MB9AF142LPMC1-G-JNE2, MB9AF144LPMC1-G-JNE2,
MB9AF141LPMC-G-JNE2, MB9AF142LPMC-G-JNE2, MB9AF144LPMC-G-JNE2,
MB9AF141LQN-G-AVE2, MB9AF142LQN-G-AVE2, MB9AF144LQN-G-AVE2
Rev. A
MB9AF141NAPMC-G-JNE2, MB9AF142NAPMC-G-JNE2, MB9AF144NAPMC-G-JNE2,
MB9AF141NAPQC-G-JNE2, MB9AF142NAPQC-G-JNE2, MB9AF144NAPQC-G-JNE2,
MB9AF141NABGL-GE1, MB9AF142NABGL-GE1, MB9AF144NABGL-GE1,
MB9AF141MAPMC-G-JNE2, MB9AF142MAPMC-G-JNE2, MB9AF144MAPMC-G-JNE2,
MB9AF141MAPMC1-G-JNE2, MB9AF142MAPMC1-G-JNE2, MB9AF144MAPMC1-G-JNE2,
MB9AF141MABGL-GE1, MB9AF142MABGL-GE1, MB9AF144MABGL-GE1,
MB9AF141LAPMC1-G-JNE2, MB9AF142LAPMC1-G-JNE2, MB9AF144LAPMC1-G-JNE2,
MB9AF141LAPMC-G-JNE2, MB9AF142LAPMC-G-JNE2, MB9AF144LAPMC-G-JNE2,
MB9AF141LAQN-G-AVE2, MB9AF142LAQN-G-AVE2, MB9AF144LAQN-G-AVE2
Rev. B
MB9AF141NBPMC-G-JNE2, MB9AF142NBPMC-G-JNE2, MB9AF144NBPMC-G-JNE2,
MB9AF141NBPQC-G-JNE2, MB9AF142NBPQC-G-JNE2, MB9AF144NBPQC-G-JNE2,
MB9AF141NBBGL-GE1, MB9AF142NBBGL-GE1, MB9AF144NBBGL-GE1,
MB9AF141MBPMC-G-JNE2, MB9AF142MBPMC-G-JNE2, MB9AF144MBPMC-G-JNE2,
MB9AF141MBPMC1-G-JNE2, MB9AF142MBPMC1-G-JNE2, MB9AF144MBPMC1-G-JNE2,
MB9AF141MBBGL-GE1, MB9AF142MBBGL-GE1, MB9AF144MBBGL-GE1,
MB9AF141LBPMC1-G-JNE2, MB9AF142LBPMC1-G-JNE2, MB9AF144LBPMC1-G-JNE2,
MB9AF141LBPMC-G-JNE2, MB9AF142LBPMC-G-JNE2, MB9AF144LBPMC-G-JNE2,
MB9AF141LBQN-G-AVE2, MB9AF142LBQN-G-AVE2, MB9AF144LBQN-G-AVE2
15.2 Qualification Status
Product Status: In Production − Qual.
Document Number: 002-05637 Rev.*B
Page 111 of 118
MB9A140NB Series
15.3 Errata Summary
This table defines the errata applicability to available devices.
Items
Part Number
Refer to 15.1
Refer to 15.1
Refer to 15.1
Refer to 15.1
Refer to 15.1
Silicon Revision
Initial rev.
Fix Status
[1] FLASH lower bank read during write
[2] FLASH read during write & erase suspend
[3] Regulator issue
Fixed in Rev. A
Fixed in Rev. A
Fixed in Rev. B
Fixed in Rev. B
Initial rev.
Initial rev., Rev. A
Initial rev., Rev. A
[4] HDMI-CEC arbitration lost issue
[5] HDMI-CEC polling message issue
Initial rev., Rev. A , Rev. B
Next silicon is not planned
1. FLASH lower bank read during write
PROBLEM DEFINITION
During writing (programming) to FLASH memory of an upper bank, FLASH memory of a lower bank could not be read at a
specific timing in some operation combinations.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This issue may happen when read data or fetch instruction from the FLASH memory lower bank (smaller sector), while a write
(program) operation to the FLASH memory upper bank (larger sector) is in progress.
SCOPE OF IMPACT
Instructions could not be fetched (read) correctly from the lower bank, and then execution of the (corrupted) instructions may
cause a hard fault or run-away. If an instruction in RAM reads a data from the lower bank while writing to the upper bank, an
incorrect value might be read.
WORKAROUND
To rewrite the upper bank of FLASH memory, put the write instruction in RAM instead of the lower bank and execute it from the
RAM. Do not access the lower bank until the write operation is completed (RDY=1). Especially to avoid a vector fetch from
the lower bank of the FLASH memory by an interrupt occurred, the interrupt should be prohibited or the vector address should
be set to RAM by the vector table offset register.
FIX STATUS
This issue was fixed in Rev. A.
2. FLASH Read during Write & Sector Erase Suspend
PROBLEM DEFINITION
When writing is executed during sector erase suspend, FLASH memory could not be read correctly at a specific timing.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This issue may happen when read data or fetch instruction from the FLASH memory bank (higher or lower), while a write
(program) operation is in progress to the opposite bank which has a sector erase suspended. The following flow could not be
executed correctly.
(a) Erase a sector of a bank
(b) Suspend the sector erase operation
(c) Write to a different sector of the bank
(d) Execute an instruction or read data in the opposite bank
SCOPE OF IMPACT
Instructions could not be fetched (read) correctly, and then execution of the (corrupted) instructions may cause a hard fault or
run-away. If an instruction in RAM reads a data from the bank, an incorrect value might be read.
Document Number: 002-05637 Rev.*B
Page 112 of 118
MB9A140NB Series
WORKAROUND
Do not execute the write operation to a different sector in the same bank at sector erase suspend.
FIX STATUS
This issue was fixed in Rev. A.
3. Regulator issue
PROBLEM DEFINITION
The regulator does not get initialized while internal power-up sequence.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This issue rarely happens depending on states of internal circuits which the user cannot control.
SCOPE OF IMPACT
MCU does not start operation if this issue occurs.
WORKAROUND
This error cannot be avoided by any software.
FIX STATUS
This issue was fixed in Rev. B.
4. HDMI-CEC arbitration lost issue
PROBLEM DEFINITION
Large external load on CEC bus may cause arbitration lost.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
The arbitration lost detection mechanism samples outputting signals and determines that arbitration lost occurs if sampled
signals do not match the outputting signals. The large external load on the CEC bus increases slew rate of the signals. The
increased slew rate makes the mismatch between outputting signals and sampled signals and the mismatch misleads MCU
that arbitration lost occurs.
SCOPE OF IMPACT
Once the arbitration lost is detected, the CEC aborts the transmission. Any transmission cannot be completed.
WORKAROUND
This error cannot be avoided by any software. Reduce the external load.
FIX STATUS
This issue was fixed in Rev. B.
5. HDMI-CEC polling message issue
PROBLEM DEFINITION
Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node.
Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another
node.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This error always happens.
SCOPE OF IMPACT
MCU does not reply properly to another node.
Document Number: 002-05637 Rev.*B
Page 113 of 118
MB9A140NB Series
WORKAROUND
The software workaround is applied to Error #1.
1. Store 0x0 to SFREE register.
2. Monitor CEC line with GPIO and wait until 1 lasts for the signal free time.
3. Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register.
It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored 0x0F.
If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device
receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases:
4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
4-A-2. Return back to step 2 above
If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps.
4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA
4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds state low on the CEC line
4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
4-B-4. Return back to step 2 above
For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The
specification says signal free time must be more than and equals to 5-bit.
FIX STATUS
The user uses the workaround to avoid the issue. The next silicon fixing the issue is not planned.
Document Number: 002-05637 Rev.*B
Page 114 of 118
MB9A140NB Series
16.Major Changes
Spansion Publication Number: DS706-00040
Page
Section
Change Results
Revision 2.0
FEATURE
On-chip Memories
Revised the descriptions of [Flash memory].
Added the descriptions of "Unique ID".
2
5
Unique ID
PRODUCT LINEUP
Function
6
Added the descriptions.
48
53
HANDLING DEVICES
MEMORY MAP
Memory Map (2)
PIN STATUS IN EACH CPU STATE
List of Pin Status
ELECTRICAL CHARACTERISTICS
3.DC Characteristics
Revised the Pin status type of "I".
58
65
Revised the descriptions of Power supply current.
Added the "Flash memory write/erase current".
Added the footnote.
(1) Current rating
4.AC Characteristics
Revised the table and the footnote.
69
(3) Built-in CR Oscillation Characteristics
Built-in high-speed CR
(7) External Bus Timing
Revised the table and the figure.
73, 74
Separate Bus Access Asynchronous
SRAM Mode
75
Separate Bus Access Synchronous SRAM Mode
80, 82,
84, 86
89
Revised the title to "CSIO Timing".
Revised the note.
Revised the footnote.
(9) CSIO Timing
(11) I2C Timing
Revised the parameter.
Revised the symbol.
Corrected the value.
Revised the parameter.
Revised the symbol.
Corrected "Conditions" and "Value" in the table.
Added the Item.
5. 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
92
94
95
Definition of 12-bit A/D Converter Terms
6. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
Added the footnote.
Added the Item.
96
(2) Interrupt of Low-Voltage Detection
-
Revision 2.1
-
Company name and layout design change
Revision 3.0
Corrected the Series name.
-
-
-
-
MB9A140NA Series → MB9A140NB Series
Corrected the Product name as follows.
MB9AF144LB, MB9AF142LB, MB9AF141LB
MB9AF144MB, MB9AF142MB, MB9AF141MB
MB9AF144NB, MB9AF142NB, MB9AF141NB
Added the Item.
FEATURES
2
External Bus Interface
Multi-function Serial Interface
PRODUCT LINEUP
Maximum area size : Up to 256 Mbytes
Corrected the description of "I2C"
3
6
Added the footnote
Function
51
52
BLOCK DIAGRAM
MEMORY MAP
Memory Map (1)
Corrected the figure
Corrected the address "External Device Area"
ELECTRICAL CHARACTERISTICS
2.Recommended Operating Conditions
3.DC Characteristics
(1)Current rating
63
Add the footnote
Corrected the Condition
Delete the minimum value
Corrected the remarks
Add the footnote
64,65
Document Number: 002-05637 Rev.*B
Page 115 of 118
MB9A140NB Series
Page
Section
Change Results
Corrected the figure of "MS bit=1"
Corrected the figure
(9)CSIO Timing
Synchronous serial (SPI=1, SCINV=1)
(9) CSIO Timing
External clock(EXT=1):asynchronous only
(12)I2C Timing
86
Corrected the description as follows.
Typical mode → Standard-mode
High-speed mode→ Fast-mode
Corrected the terminal name
88
91
5.12-bit A/D Converter
Electrical Characteristics for
the A/D Converter
AN00 ~ AN23 → ANxx
Corrected the minimum value of "Sampling time"
Corrected the max and min value of "State transition time to operation
permission"
Corrected the footnote
ORDERING INFORMATON
98
Corrected the "Part number"
Revision 4.0
Memory Map
Memory map(2)
53
Added the summary of Flash memory sector and the note
Electrical Characteristics
3. DC Characteristics
(1) Current rating
Changed the table format
Added Main Timer mode current
Moved A/D Converter Current
64 - 66
Electrical Characteristics
3. DC Characteristics
(2) Pin Characteristics
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
67
70
Added input leak current of CEC pin at power off.
Added the figure of Main PLL connection
Added Time until releasing Power-on reset
Changed the figure of timing
71
Modified from UART Timing to CSIO/UART Timing
80 - 87
92
Changed from Internal shift clock operation to Master mode
Changed from External shift clock operation to Slave mode
Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
Added Conversion time at AVcc < 2.7V
(9) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Electrical Characteristics
8. Return Time from Low-Power Consumption
Mode
98 - 101
102, 103
Added Return Time from Low-Power Consumption Mode
Changed notation of part number
Ordering Information
Note: Please see “Document History” about later revised information.
Document Number: 002-05637 Rev.*B
Page 116 of 118
MB9A140NB Series
Document History
Document Title: MB9A140NB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05637
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-05637.
No change to document contents or format.
**
–
AKIH
AKIH
06/08/2015
*A
5206810
04/07/2016 Updated to Cypress format.
Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power Supply
rise time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments
(Page 69)
Modified RTC description in “Features, Real-Time Clock(RTC)” as below
Changed starting count value from 01 to 00. Deleted “second , or day of the week” in
the Interrupt function (Page 3)
Added Notes for JTAG (Page 38), Changed “J-TAG” to” JTAG” in “4 List of Pin
Functions” (Page 27)
Updated Package code and dimensions as follows (Page 8-15, 100-110)
FPT-64P-M38 -> LQD064, FPT-64P-M39 -> LQG064,
*B
5534251
YSKA
06/01/2017
LCC-64P-M24
-> VNC064, FPT-80P-M37 -> LQH080,
FPT-80P-M40 -> LQJ080, BGA-96P-M07 -> FDG096,
FPT-100P-M23 -> LQI100, FPT-100P-M36 -> PQH100
BGA-112P-M04 -> LBC112
Added “15. Errata” (Page 111)
Add “Analog reference voltage(AVRL)” in “12.2 Recommended Operating Conditions”
and “12.6 12-bit A/D Converter”(Page 61, 90)
Corrected the following statement
Analog port input current Analog port input leak current
in chapter 12.6. 12-bit A/D Converter (Page 90)
Added the Baud rate spec in “12.5.10 CSIO/UART Timing”(Page 78, 80, 82, 84)
Document Number: 002-05637 Rev.*B
Page 117 of 118
MB9A140NB Series
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© Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
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Document Number: 002-05637 Rev.*B
June 1, 2017
Page 118 of 118
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