MB9AF154MB [SPANSION]
This document states the current technical specifications regarding;
| 型号： | MB9AF154MB |
| 厂家： | 
SPANSION |
| 描述： | This document states the current technical specifications regarding |
| 文件： | 总133页 (文件大小：3574K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products.
MB9A150RB Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF154MB/NB/RB, MB9AF155MB/NB/RB,
MB9AF156MB/NB/RB
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9A150RB_DS706-00047
Revision 3.0
Issue Date April 28, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
MB9A150RB Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AF154MB/NB/RB, MB9AF155MB/NB/RB,
MB9AF156MB/NB/RB
Data Sheet (Full Production)
Description
The MB9A150RB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have
peripheral functions such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I2C).
The products which are described in this data sheet are placed into TYPE8 product categories in FM3
Family Peripheral Manual.
Note: ARM and Cortex are theregistered trademarks of ARM Limited in the EU and other countries.
Publication Number MB9A150RB_DS706-00047
Revision 3.0
Issue Date April 28, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
D a t a S h e e t
Features
32-bit ARM Cortex-M3 Core
Processor version: r2p1
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
Dual operation Flash memory
Dual Operation Flash memory has the upper bank and the lower bank.
So, this series could implement erase, write and read operations
for each bank simultaneously.
Main area: Up to 512 Kbytes (Upto 496 Kbytes upper bank + 16 Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is
connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0: Up to 32 Kbytes
SRAM1: Up to 32 Kbytes
External Bus Interface
Supports SRAM, NOR NAND Flash memory device
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size : Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
Multi-function Serial Interface (Max 16 channels)
16 channels with 16 steps×9-bit FIFO
Operation mode is selectable from the followings for each channel.
UART
CSIO
I2C
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)
Various error detection functions available (parity errors, framing errors, and overrun errors)
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[I2C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
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D a t a S h e e t
DMA Controller (8channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2 units
Conversion time: 2.0 μs @ 2.7 V to 3.6 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion:
4 steps)
Base Timer (Max 16channels)
Operation mode is selectable from the followings for each channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 103 high-speed general-purpose I/O Ports@120 pin Package
Some ports are 5 V tolerant I/O
See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins.
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down counters.
Operation mode is selectable from the followings for each channel.
Free-running
Periodic (=Reload)
One-shot
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D a t a S h e e t
Multi-function Timer
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3ch.
Input capture × 4ch.
Output compare × 6ch.
A/D activation compare × 2ch.
Waveform generator × 3ch.
16-bit PPG timer × 3ch.
The following function can be used to achieve the motor control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Quadrature Position/Revolution Counter (QPRC)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use as the up/down counter.
The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
HDMI-CEC/Remote Control Reception (Up to 2channels)
HDMI-CEC transmission
Header block automatic transmission by judging Signal free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data
Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)
HDMI-CEC reception
Automatic ACK reply function available
Line error detection function available
Remote control reception
4 bytes reception buffer
Repeat code detection function available
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of
the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The Watch counter is used for wake up from sleep and timer mode.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
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D a t a S h e e t
External Interrupt Controller Unit
Up to 24 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
The Hardware watchdog timer is clocked by the built-in Low-speed CR oscillator. Therefore, the Hardware
watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby RTC and Deep
Standby Stop modes.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Built-in High-speed CR Clock: 4 MHz
Built-in Low-speed CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
If external clock failure (clock stop) is detected, reset is asserted.
If external frequency anomaly is detected, interrupt or reset is asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage that has been set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
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D a t a S h e e t
Low-Power Consumption Mode
Six low-power consumption modes supported.
Sleep
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value of RAM and not)
Deep Standby Stop (selectable between keeping the value of RAM and not)
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM).*
*: MB9AF154MB, F155MB and F156MB support only SWJ-DP.
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Wide range voltage: VCC = 1.65 V to 3.6 V
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Product Lineup
Memory size
Product name
MB9AF154MB/NB/RB MB9AF155MB/NB/RB MB9AF156MB/NB/RB
On-chip
Flash
memory
Main area
Work area
256 Kbytes
32 Kbytes
384 Kbytes
32 Kbytes
512 Kbytes
32 Kbytes
SRAM0
SRAM1
Total
16 Kbytes
16 Kbytes
32 Kbytes
24 Kbytes
24 Kbytes
48 Kbytes
32 Kbytes
32 Kbytes
64 Kbytes
On-chip
SRAM
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
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D a t a S h e e t
Function
MB9AF154MB
MB9AF154NB
MB9AF155NB
MB9AF156NB
100/112
MB9AF154RB
MB9AF155RB
MB9AF156RB
120
Product name
MB9AF155MB
MB9AF156MB
80/96
Pin count
CPU
Cortex-M3
40 MHz
Freq.
Power supply voltage range
DMAC
1.65V to 3.6V
8ch.
Addr: 25-bit (Max)
R/W Data: 8-/16-bit
(Max)
CS: 8 (Max)
Support: SRAM,
NOR Flash memory
Addr: 25-bit (Max)
R/W Data: 8-/16-bit
(Max)
Addr: 21-bit (Max)
R/W Data: 8-bit (Max)
CS: 4 (Max)
Support: SRAM,
NOR Flash memory
External Bus Interface
CS: 8 (Max)
Support: SRAM,
NOR Flash memory,
NAND Flash memory
16ch. (Max)
Enabled channels : ch.0
to ch.15
10ch. (Max)
Enabled channels :
ch.0 to ch.7, ch.10,
ch.11
14ch. (Max)
Enabled channels :
ch.0 to ch.13
Multi-function Serial Interface
(UART/CSIO/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation
16ch. (Max)
2ch.
compare
Input capture
Free-run timer
Output compare
Waveform
generator
4ch.
3ch.
6ch.
MF-
Timer
1 unit (Max)
3ch.
3ch.
PPG
QPRC
2ch. (Max)
1 unit
Dual Timer
HDMI-CEC/ Remote Control
Reception
2ch. (Max)
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
23 pins (Max) +
NMI × 1
External Interrupts
24 pins (Max) + NMI × 1
I/O ports
66 pins (Max)
17ch. (2 units)
83 pins (Max)
103 pins (Max)
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
24ch. (2 units)
Yes
2ch.
High-speed
Low-speed
4 MHz
100 kHz
Built-in
CR
Debug Function
Unique ID
SWJ-DP
SWJ-DP/ETM
Yes
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See Electrical Characteristics 4.AC Characteristics (3)Built-in CR Oscillation Characteristics for
accuracy of built-in CR.
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Packages
MB9AF154MB MB9AF154NB MB9AF154RB
MB9AF155MB MB9AF155NB MB9AF155RB
MB9AF156MB MB9AF156NB MB9AF156RB
Product name
Package
LQFP: FPT-80P-M37 (0.5 mm pitch)
BGA: BGA-96P-M07 (0.5 mm pitch)
LQFP: FPT-100P-M23 (0.5 mm pitch)
BGA: BGA-112P-M04 (0.8 mm pitch)
LQFP: FPT-120P-M37 (0.5 mm pitch)
: Supported
-
-
-
-
-
-
-
-
-
-
Note: See Package Dimensions for detailed information on each package.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
9
D a t a S h e e t
Pin Assignment
FPT-120P-M37
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
90 VSS
P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0
P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0
P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0
P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0
P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0
P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0
P56/SIN1_0/TIOA8_0/INT08_2/CEC1_1/MADATA06_0
P57/SOT1_0/TIOA9_0/MADATA07_0
89 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0
88 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2
87 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1
86 P23/AN16/SCK0_0/RTO00_1/TIOA7_1
85 P24/SIN2_1/RTO01_1/TIOB14_1/INT01_2
84 P25/SOT2_1/RTO02_1/TIOA14_1/TIOB11_2
83 P26/SCK2_1/RTO03_1/TIOA11_2
82 P27/SIN15_0/RTO04_1/TIOA6_2/INT02_2
81 P28/ADTG_4/SOT15_0/RTO05_1/TIOB6_2
80 P1F/AN15/ADTG_5/SCK15_0/FRCK0_1/TIOB9_2/MAD23_0
79 P1E/AN14/RTS4_1/DTTI0X_1/TIOA9_2/INT23_2/MAD22_0
78 P1D/AN13/CTS4_1/IC03_1/TIOA13_1/INT22_2/MAD21_0
77 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT21_2/MAD20_0
76 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0
75 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0
74 P19/AN09/SCK2_2/TIOA9_1/MAD17_0
73 P18/AN08/SOT2_2/TIOA8_1/MAD16_0
72 AVSS
P58/SCK1_0/TIOA10_0/MADATA08_0 10
P59/SIN7_0/TIOA11_0/INT09_2/MADATA09_0 11
P5A/SOT7_0/TIOA12_0/INT16_2/MADATA10_0 12
P5B/SCK7_0/TIOA13_0/INT17_2/MADATA11_0 13
P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA12_0 14
P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA13_0 15
P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA14_0 16
P33/ADTG_6/SIN9_0/SIN6_1/TIOB3_1/INT04_0/MADATA15_0 17
P34/SOT9_0/FRCK0_0/TIOB4_1/TIOA15_2/MNALE_0 18
P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT08_1/MNCLE_0 19
P36/SIN5_2/IC02_0/TIOB14_0/INT09_1/MNWEX_0 20
P37/SOT5_2/IC01_0/TIOA14_0/INT10_1/MNREX_0 21
P38/SCK5_2/IC00_0/TIOA8_2/INT11_1 22
LQFP - 120
71 AVRH
70 AVCC
69 P17/AN07/SIN2_2/INT04_1/MAD15_0
68 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0
67 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0
66 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0
65 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0
64 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0
63 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0
62 P10/AN00
P39/ADTG_2/SIN10_0/DTTI0X_0/TIOB8_2/INT06_0 23
P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 24
P3B/SCK10_0/RTO01_0/TIOA1_1 25
P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 26
P3D/SOT11_0/RTO03_0/TIOA3_1 27
P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 28
P3F/RTO05_0/TIOA5_1 29
VSS 30
61 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
FPT-100P-M23
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
75 VSS
P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0
P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0
P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0
P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0
P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0
P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0
P56/INT08_2/CEC1_1/MADATA06_0
74 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0
73 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2
72 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1
71 P23/AN16/SCK0_0/TIOA7_1
70 P1F/AN15/ADTG_5/FRCK0_1/TIOB9_2/MAD23_0
69 P1E/AN14/RTS4_1/DTTI0X_1/TIOA9_2/INT23_2/MAD22_0
68 P1D/AN13/CTS4_1/IC03_1/TIOA13_1/INT22_2/MAD21_0
67 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT21_2/MAD20_0
66 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0
65 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0
64 P19/AN09/SCK2_2/TIOA9_1/MAD17_0
63 P18/AN08/SOT2_2/TIOA8_1/MAD16_0
62 AVSS
P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA07_0
P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA08_0 10
P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA09_0 11
P33/ADTG_6/SIN9_0/SIN6_1/TIOB3_1/INT04_0/MADATA10_0 12
P34/SOT9_0/FRCK0_0/TIOB4_1/TIOA15_2/MADATA11_0 13
P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT08_1/MADATA12_0 14
P36/SIN5_2/IC02_0/TIOB14_0/INT09_1/MADATA13_0 15
P37/SOT5_2/IC01_0/TIOA14_0/INT10_1/MADATA14_0 16
P38/SCK5_2/IC00_0/TIOA8_2/INT11_1/MADATA15_0 17
P39/ADTG_2/SIN10_0/DTTI0X_0/TIOB8_2/INT06_0 18
P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 19
P3B/SCK10_0/RTO01_0/TIOA1_1 20
LQFP - 100
61 AVRH
60 AVCC
59 P17/AN07/SIN2_2/INT04_1/MAD15_0
58 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0
57 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0
56 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0
55 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0
54 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0
53 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0
52 P10/AN00
P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 21
P3D/SOT11_0/RTO03_0/TIOA3_1 22
P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 23
P3F/RTO05_0/TIOA5_1 24
VSS 25
51 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
11
D a t a S h e e t
FPT-80P-M37
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
60 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0
59 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2
58 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1
57 P23/AN16/SCK0_0/TIOA7_1
P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0
P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0
P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0
P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0
P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0
P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0
P56/INT08_2/CEC1_1/MADATA06_0
56 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0
55 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0
54 P19/AN09/SCK2_2/TIOA9_1/MAD17_0
53 P18/AN08/SOT2_2/TIOA8_1/MAD16_0
52 AVSS
P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA07_0
P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA08_0 10
P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA09_0 11
P33/ADTG_6/SIN6_1/TIOB3_1/INT04_0/MADATA10_0 12
P39/ADTG_2/SIN10_0/DTTI0X_0/INT06_0 13
P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 14
P3B/SCK10_0/RTO01_0/TIOA1_1 15
51 AVRH
LQFP - 80
50 AVCC
49 P17/AN07/SIN2_2/INT04_1/MAD15_0
48 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0
47 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0
46 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0
45 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0
44 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0
43 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0
42 P10/AN00
P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 16
P3D/SOT11_0/RTO03_0/TIOA3_1 17
P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 18
P3F/RTO05_0/TIOA5_1 19
VSS 20
41 VCC
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
BGA-112P-M04
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
VSS
VCC
P50
P53
P30
P34
P37
P3B
VCC
VCC
VSS
P81
VSS
P51
P54
P31
P35
P38
P3C
P3F
VSS
C
P80
P52
VSS
P55
P32
P36
P3A
P3E
VSS
X1A
X0A
VCC
P61
P60
VSS
P33
P39
P3D
VSS
P40
INITX
VSS
P0E
P0F
P62
P0B
P0C
P0D
P63
P07
P08
P09
P0A
TRSTX
VCC
VSS
P20
VSS
TDI
TDO/
SWO
TCK/
SWCLK
P05
VSS
P22
VSS
P06
P21
P56
P23
AN15
AN11
AVRH
AVSS
AVCC
AN00
VCC
Index
AN14
AN10
AN07
AN04
VSS
MD1
X0
AN12
AN09
AN06
AN03
AN01
VSS
X1
AN13
AN08
VSS
AN02
P4E
G
H
J
P44
P43
P42
P41
P4C
P49
P48
P45
AN05
P4D
P4B
P4A
K
L
MD0
VSS
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
13
D a t a S h e e t
BGA-96P-M07
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
VSS
VCC
P50
P53
P56
VSS
P32
P3A
P3D
VCC
VSS
P81
VSS
P51
P54
P30
VSS
P33
P3B
P3E
VSS
C
P80
P52
VSS
P55
P31
VSS
P39
P3C
VSS
X1A
X0A
VCC
P61
VSS
P63
P62
P0F
P0D
P0E
VSS
P0C
P0B
P07
TRSTX
VSS
P20
VSS
TDI
TDO/
SWO
TCK/
SWCLK
P60
P0A
VSS
P22
P21
Index
P23
VSS
AN11
AN08
AN06
AN04
VSS
MD1
X0
AN10
AN07
AN05
AN03
AN01
VSS
X1
AN09
AVRH
AVSS
AVCC
AN00
VCC
VSS
G
H
J
P3F
INITX
VSS
P48
P45
P44
P4A
P49
VSS
P4D
P4C
P4B
AN02
P4E
K
L
MD0
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
14
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
List of Pin Function
List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
1
1
B1
1
B1
VCC
P50
-
SIN3_1
AIN0_2
TIOB8_0
INT00_0
MADATA00_0
P51
2
2
C1
2
C1
E
K
SOT3_1
(SDA3_1)
BIN0_2
TIOB9_0
INT01_0
MADATA01_0
P52
3
3
C2
3
C2
E
K
SCK3_1
(SCL3_1)
ZIN0_2
TIOB10_0
INT02_0
MADATA02_0
P53
4
5
6
4
5
6
B3
D1
D2
4
5
6
B3
D1
D2
E
E
E
K
K
K
SIN6_0
TIOB11_0
TIOA1_2
INT07_2
MADATA03_0
P54
SOT6_0
(SDA6_0)
TIOB12_0
TIOB1_2
INT18_1
MADATA04_0
P55
ADTG_1
SCK6_0
(SCL6_0)
7
7
D3
7
D3
E
K
TIOB13_0
INT19_1
MADATA05_0
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
15
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P56
INT08_2
CEC1_1
MADATA06_0
SIN1_0
8
-
D5
-
8
-
E1
-
8
H*
R
TIOA8_0
P57
SOT1_0
(SDA1_0)
9
-
-
-
-
-
-
-
-
-
-
-
-
H*
H*
E
J
J
TIOA9_0
MADATA07_0
P58
SCK1_0
(SCL1_0)
10
11
TIOA10_0
MADATA08_0
P59
SIN7_0
TIOA11_0
INT09_2
MADATA09_0
P5A
K
SOT7_0
(SDA7_0)
12
13
-
-
-
-
-
-
-
-
E
E
K
K
TIOA12_0
INT16_2
MADATA10_0
P5B
SCK7_0
(SCL7_0)
TIOA13_0
INT17_2
MADATA11_0
P30
AIN0_0
TIOB0_1
TIOA13_2
INT03_2
WKUP4
14
-
-
-
-
E
S
MADATA12_0
P30
AIN0_0
TIOB0_1
TIOA13_2
INT03_2
WKUP4
-
9
E1
9
E2
E
S
MADATA07_0
16
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P31
SCK6_1
(SCL6_1)
BIN0_0
TIOB1_1
TIOB13_2
INT04_2
15
-
-
-
-
E
K
MADATA13_0
P31
SCK6_1
(SCL6_1)
BIN0_0
TIOB1_1
TIOB13_2
INT04_2
-
10
E2
10
E3
E
K
MADATA08_0
P32
SOT6_1
(SDA6_1)
ZIN0_0
TIOB2_1
INT05_2
MADATA14_0
P32
16
-
11
-
-
E3
-
-
11
-
-
G1
-
E
E
E
K
K
K
SOT6_1
(SDA6_1)
ZIN0_0
TIOB2_1
INT05_2
MADATA09_0
P33
-
ADTG_6
SIN9_0
17
SIN6_1
TIOB3_1
INT04_0
MADATA15_0
P33
ADTG_6
SIN6_1
12
-
G2
-
-
12
E4
TIOB3_1
INT04_0
MADATA10_0
SIN9_0
E
K
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
17
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P34
SOT9_0
(SDA9_0)
FRCK0_0
TIOB4_1
TIOA15_2
MNALE_0
P34
18
-
-
-
-
-
-
E
J
SOT9_0
(SDA9_0)
FRCK0_0
TIOB4_1
-
13
F1
E
J
TIOA15_2
MADATA11_0
P35
SCK9_0
(SCL9_0)
IC03_0
TIOB5_1
TIOB15_2
INT08_1
MNCLE_0
P35
19
-
-
-
-
E
K
SCK9_0
(SCL9_0)
IC03_0
TIOB5_1
TIOB15_2
INT08_1
MADATA12_0
P36
-
14
F2
-
-
E
K
SIN5_2
IC02_0
20
-
-
-
-
-
-
E
E
K
K
TIOB14_0
INT09_1
MNWEX_0
P36
SIN5_2
IC02_0
-
15
F3
TIOB14_0
INT09_1
MADATA13_0
VSS
-
-
-
-
-
-
-
-
-
-
-
-
F1
F2
F3
-
-
-
VSS
VSS
18
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P37
SOT5_2
(SDA5_2)
IC01_0
TIOA14_0
INT10_1
MNREX_0
P37
21
-
-
-
-
-
-
-
-
E
K
SOT5_2
(SDA5_2)
IC01_0
TIOA14_0
INT10_1
-
16
G1
E
K
MADATA14_0
P38
SCK5_2
(SCL5_2)
22
-
IC00_0
TIOA08_2
INT11_1
MADATA15_0
P39
17
18
G2
F4
E
E
K
K
ADTG_2
SIN10_0
DTTI0X_0
INT06_0
TIOB8_2
P3A
13
-
G3
-
23
SOT10_0
(SDA10_0)
RTO00_0
TIOA0_1
INT07_0
RTCCO_2
SUBOUT_2
P3B
24
19
G3
14
H1
E
K
SCK10_0
(SCL10_0)
25
26
20
21
H1
H2
15
16
H2
H3
E
E
J
RTO01_0
TIOA1_1
P3C
SIN11_0
RTO02_0
TIOA2_1
INT18_2
K
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
19
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P3D
SOT11_0
(SDA11_0)
27
-
22
-
G4
B2
17
-
J1
E
J
RTO03_0
TIOA3_1
VSS
B2
-
P3E
SCK11_0
(SCL11_0)
28
23
H3
18
J2
E
E
K
J
RTO04_0
TIOA4_1
INT19_2
P3F
29
24
J2
19
J4
RTO05_0
TIOA5_1
VSS
30
31
25
26
L1
J1
20
-
L1
-
-
-
VCC
P40
SIN12_0
TIOA0_0
INT12_1
P41
32
27
J4
-
-
E
E
K
K
SOT12_0
(SDA12_0)
33
28
L5
-
-
TIOA1_0
INT13_1
P42
SCK12_0
(SCL12_0)
34
35
29
30
K5
J5
-
-
-
-
E
E
K
K
TIOA2_0
INT08_0
P43
ADTG_7
SIN13_0
TIOA3_0
INT09_0
P44
21
-
L5
-
SOT13_0
(SDA13_0)
TIOA4_0
INT10_0
MAD00_0
P45
SCK13_0
TIOA5_0
INT11_0
MAD01_0
36
37
31
32
H5
L6
E
E
K
K
21
L5
22
-
K5
-
22
K5
20
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
-
-
-
-
K2
J3
-
-
K2
J3
VSS
VSS
-
-
-
-
-
-
-
-
-
H4
-
-
-
VSS
-
-
-
L6
L2
L4
K1
VSS
38
39
40
33
34
35
L2
L4
K1
23
24
25
C
VSS
VCC
P46
41
36
L3
26
L3
D
F
X0A
P47
42
43
37
38
K3
K4
27
28
K3
K4
D
B
G
C
X1A
INITX
P48
SIN3_2
INT14_1
MAD02_0
P49
44
39
K6
29
J5
E
K
SOT3_2
(SDA3_2)
AIN0_1
TIOB0_0
INT20_1
MAD03_0
P4A
45
40
J6
30
K6
E
K
SCK3_2
(SCL3_2)
BIN0_1
TIOB1_0
INT21_1
MAD04_0
P4B
46
47
41
42
L7
31
32
J6
E
E
K
K
IGTRG_0
ZIN0_1
TIOB2_0
INT22_1
MAD05_0
P4C
K7
L7
SCK7_1
(SCL7_1)
AIN1_2
TIOB3_0
INT12_0
CEC0_0
48
43
H6
33
K7
H*
R
MAD06_0
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
21
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P4D
SOT7_1
(SDA7_1)
BIN1_2
TIOB4_0
INT13_0
MAD07_0
P4E
49
50
44
J7
34
J7
H*
K
SIN7_1
ZIN1_2
TIOB5_0
INT06_2
MAD08_0
SIN14_0
P70
45
K8
35
K8
H*
K
-
-
-
-
-
-
-
-
SOT14_0
(SDA14_0)
51
52
53
E
E
E
J
TIOA4_2
P71
SCK14_0
(SCL14_0)
-
-
-
-
-
-
-
-
K
K
TIOB4_2
INT13_2
P72
SIN2_0
TIOA6_0
INT14_2
P73
SOT2_0
(SDA2_0)
54
55
-
-
-
-
-
-
-
-
E
E
K
J
TIOB6_0
INT15_2
P74
SCK2_0
(SCL2_0)
MD1
PE0
MD0
X0
56
57
58
46
47
48
K9
L8
L9
36
37
38
K9
L8
L9
C
G
A
E
D
A
PE2
X1
59
49
L10
39
L10
A
B
PE3
VSS
VCC
P10
60
61
50
51
L11
K11
40
41
L11
K11
-
-
62
52
J11
42
J11
F
L
AN00
22
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P11
AN01
SIN1_1
FRCK0_2
TIOB8_1
INT02_1
WKUP1
MAD09_0
P12
63
53
J10
43
J10
F
P
AN02
SOT1_1
(SDA1_1)
64
54
J8
44
J8
F
L
IC00_2
TIOB9_1
MAD10_0
VSS
-
-
-
-
K10
J9
-
-
K10
J9
-
-
VSS
P13
AN03
SCK1_1
(SCL1_1)
IC01_2
TIOB10_1
RTCCO_1
SUBOUT_1
MAD11_0
P14
65
55
H10
45
H10
F
L
AN04
SIN0_1
66
56
H9
46
H9
IC02_2
F
M
TIOB11_1
INT03_1
MAD12_0
P15
AN05
SOT0_1
(SDA0_1)
67
57
H7
47
G10
F
M
IC03_2
TIOB12_1
INT14_0
MAD13_0
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
23
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P16
AN06
SCK0_1
(SCL0_1)
68
58
G10
48
G9
F
M
TIOB13_1
INT15_0
MAD14_0
P17
AN07
69
59
G9
49
F10
SIN2_2
INT04_1
MAD15_0
AVCC
F
M
70
71
72
60
61
62
H11
F11
G11
50
51
52
H11
F11
G11
-
-
-
AVRH
AVSS
P18
AN08
SOT2_2
(SDA2_2)
73
63
G8
53
F9
F
F
L
L
TIOA8_1
MAD16_0
P19
AN09
SCK2_2
(SCL2_2)
74
-
64
-
F10
H8
54
-
E11
-
TIOA9_1
MAD17_0
VSS
-
P1A
AN10
SIN4_1
IC00_1
TIOA10_1
INT05_1
MAD18_0
P1B
75
65
F9
55
E10
F
M
AN11
SOT4_1
(SDA4_1)
76
66
E11
56
E9
F
M
IC01_1
TIOA11_1
INT20_2
MAD19_0
24
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P1C
AN12
SCK4_1
(SCL4_1)
77
67
E10
-
-
F
M
IC02_1
TIOA12_1
INT21_2
MAD20_0
P1D
AN13
CTS4_1
IC03_1
78
68
F8
-
-
F
M
TIOA13_1
INT22_2
MAD21_0
P1E
AN14
RTS4_1
DTTI0X_1
TIOA9_2
INT23_2
MAD22_0
P1F
79
69
E9
-
-
F
M
AN15
ADTG_5
FRCK0_1
TIOB9_2
MAD23_0
70
-
D11
-
-
-
-
-
80
F
L
SCK15_0
(SCL15_0)
-
-
-
-
-
-
B10
C9
-
-
-
-
B10
C9
VSS
VSS
-
-
-
D11
VSS
P28
ADTG_4
SOT15_0
(SDA15_0)
81
82
-
-
-
-
-
-
-
-
E
E
J
RTO05_1
TIOB6_2
P27
SIN15_0
RTO04_1
TIOA6_2
INT02_2
K
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
25
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P26
SCK2_1
(SCL2_1)
83
84
85
86
-
-
-
-
-
-
-
-
-
-
-
-
E
J
RTO03_1
TIOA11_2
P25
SOT2_1
(SDA2_1)
E
E
F
J
RTO02_1
TIOA14_1
TIOB11_2
P24
SIN2_1
RTO01_1
TIOB14_1
INT01_2
P23
K
L
AN16
71
-
D10
-
57
-
D10
-
SCK0_0
(SCL0_0)
TIOA7_1
RTO00_1
P22
AN17
SOT0_0
(SDA0_0)
87
88
72
E8
58
D9
F
F
L
P
ZIN1_1
TIOB7_1
P21
AN18
SIN0_0
BIN1_1
TIOB10_2
INT06_1
WKUP2
P20
73
C11
59
C11
AN19
CROUT_0
AIN1_1
TIOA10_2
INT05_0
MAD24_0
VSS
89
74
C10
60
C10
F
M
90
91
75
76
A11
A10
-
-
A11
-
-
-
VCC
26
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P00
TRSTX
61
A10
TIOA14_2
MCSX7_0
92
77
A9
E
I
SCK8_0
(SCL8_0)
-
-
P01
TCK
93
94
78
79
B9
62
B9
E
E
I
I
SWCLK
P02
TDI
63
B11
B11
TIOB14_2
MCSX6_0
SOT8_0
P03
-
-
95
96
80
81
A8
B8
64
A9
TMS
E
E
I
I
SWDIO
P04
65
B8
TDO
SWO
P05
AN20
TRACED0
SIN8_0
SIN4_2
TIOA5_2
INT00_1
MCSX5_0
VSS
97
82
C8
D8
D9
-
-
-
-
-
-
F
O
-
-
-
P06
AN21
TRACED1
SOT4_2
(SDA4_2)
98
83
F
O
TIOB5_2
INT01_1
MCSX4_0
P07
AN22
66
A8
ADTG_0
MCLKOUT_0
INT23_1
TRACED2
99
84
A7
F
O
-
-
-
SCK4_2
(SCL4_2)
-
-
-
A7
VSS
-
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
27
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P08
AN23
TRACED3
CTS4_2
TIOA0_2
INT16_0
MCSX3_0
P09
100
85
B7
-
-
F
O
TRACECLK
RTS4_2
TIOB0_2
INT17_0
MCSX2_0
P0A
101
102
86
87
C7
D7
-
-
E
N
S
SIN4_0
67
C8
INT00_2
WKUP5
MCSX1_0
P0B
H*
SOT4_0
(SDA4_0)
TIOB6_1
INT18_0
CEC0_1
MCSX0_0
P0C
103
88
A6
68
C7
B7
H*
H*
R
K
SCK4_0
(SCL4_0)
104
89
B6
69
TIOA6_1
INT19_0
MALE_0
VSS
-
-
-
-
D4
C3
-
-
-
-
-
C3
VSS
P0D
RTS4_0
TIOA3_2
INT20_0
MDQM0_0
P0E
105
90
C6
70
B6
E
E
K
K
CTS4_0
TIOB3_2
INT21_0
MDQM1_0
VSS
106
-
91
-
A5
-
71
-
C6
A5
-
28
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
WKUP0
P68
107
108
92
B5
72
A6
E
H
SCK3_0
(SCL3_0)
-
-
-
-
E
K
TIOB7_2
INT12_2
P67
SOT3_0
(SDA3_0)
109
110
-
-
-
-
-
-
-
-
E
E
K
K
TIOA7_2
INT22_0
P66
SIN3_0
TIOA12_2
INT11_2
P65
SCK5_1
(SCL5_1)
111
-
-
-
-
-
-
-
-
E
K
TIOB7_0
TIOB12_2
INT23_0
P64
SOT5_1
(SDA5_1)
112
113
E
E
K
K
TIOA7_0
INT10_2
P63
TIOB15_1
INT03_0
MWEX_0
SIN5_1
P62
93
-
D6
-
73
-
B5
-
ADTG_3
SCK5_0
(SCL5_0)
114
94
C5
74
C5
E
K
TIOA15_1
INT07_1
MOEX_0
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
29
D a t a S h e e t
Pin No
I/O Circuit Pin State
Pin Name
Type
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
P61
SOT5_0
(SDA5_0)
115
95
B4
75
B4
E
J
TIOB2_2
P60
SIN5_0
IGTRG_1
TIOA2_2
INT15_1
WKUP3
CEC1_0
MRDY_0
VCC
116
96
C4
76
C4
H*
Q
117
118
97
98
A4
A3
77
78
A4
A3
-
P80
TIOB15_0
INT16_1
P81
E
E
K
K
119
99
A2
A1
79
80
A2
A1
TIOA15_0
INT17_1
VSS
120
100
-
*: 5V tolerant I/O
30
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
Pin Function Pin Name
Function Description
LQFP- LQFP- BGA- LQFP- BGA-
120
99
7
23
114
81
80
17
35
-
62
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
86
87
88
89
97
98
99
100
100
84
7
18
94
-
70
12
30
-
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
71
72
73
74
82
83
84
85
112
A7
D3
F4
C5
-
D11
E4
J5
80
66
7
13
74
-
-
12
-
96
A8
D3
G3
C5
-
-
G2
-
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
A/D converter external trigger
input pin
-
-
-
J11
J10
J8
42
43
44
45
46
47
48
49
53
54
55
56
-
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
E11
E10
F8
A/D converter analog input pin.
ANxx describes ADC ch.xx.
-
-
-
-
-
-
E9
D11
D10
E8
C11
C10
C8
D9
A7
B7
57
58
59
60
-
-
66
-
D10
D9
C11
C10
-
-
A8
-
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
31
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
Base timer ch.0 TIOApin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOApin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOApin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOApin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOApin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOApin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOApin
Base timer ch.6 TIOB pin
Base timer ch.7 TIOApin
Base timer ch.7 TIOB pin
120
32
24
100
45
14
101
33
25
5
46
15
6
34
26
116
47
16
115
35
100
27
19
85
40
9
86
28
20
5
112
J4
G3
B7
J6
80
-
14
-
30
9
96
-
Base Timer
0
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
H1
-
K6
E2
-
E1
C7
L5
H1
D1
L7
E2
D2
K5
H2
C4
K7
E3
B4
J5
G4
C6
H6
E4
A5
H5
H3
-
-
-
Base Timer
1
-
15
5
31
10
6
H2
D1
J6
E3
D2
-
H3
C4
L7
G1
B4
-
J1
B6
K7
G2
C6
L5
J2
-
41
10
6
Base Timer
2
29
21
96
42
11
95
30
22
90
43
12
91
31
23
-
-
16
76
32
11
75
-
17
70
33
12
71
21
18
-
Base Timer
3
27
105
48
17
106
36
Base Timer
4
28
51
49
18
52
44
13
-
J7
F1
-
34
-
-
J7
-
-
Base Timer
5
37
29
97
50
19
98
53
32
24
82
45
14
83
-
L6
J2
22
19
-
35
-
K5
J4
-
K8
-
C8
K8
F2
D9
-
-
-
-
-
Base Timer
6
104
82
89
-
B6
-
69
-
B7
-
54
-
-
-
-
103
81
88
-
A6
-
68
-
C7
-
Base Timer
7
112
86
109
111
87
-
71
-
-
72
-
-
-
57
-
-
58
-
-
D10
-
-
E8
-
D10
-
-
D9
-
108
32
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
Pin Function Pin Name
Function Description
Base timer ch.8 TIOApin
Base timer ch.8 TIOB pin
Base timer ch.9 TIOApin
Base timer ch.9 TIOB pin
Base timer ch.10 TIOApin
Base timer ch.10 TIOB pin
Base timer ch.11 TIOApin
Base timer ch.11 TIOB pin
Base timer ch.12 TIOApin
Base timer ch.12 TIOB pin
Base timer ch.13 TIOApin
Base timer ch.13 TIOB pin
Base timer ch.14 TIOApin
Base timer ch.14 TIOB pin
Base timer ch.15 TIOApin
Base timer ch.15 TIOB pin
LQFP- LQFP- BGA- LQFP- BGA-
120
8
100
8
112
D5
G8
G2
C1
J10
F4
-
80
8
53
-
2
43
-
-
96
E1
F9
-
C1
J10
-
Base Timer
8
TIOA8_0
TIOA8_1
TIOA8_2
TIOB8_0
73
22
2
63
23
9
63
17
2
53
18
-
TIOB8_1
TIOB8_2
Base Timer
9
TIOA9_0
TIOA9_1
TIOA9_2
TIOB9_0
-
74
79
3
64
80
10
75
89
4
65
88
11
76
83
5
66
84
12
77
110
6
67
111
13
78
14
7
68
15
21
84
92
20
85
94
119
114
18
118
113
19
64
69
3
54
70
-
65
74
4
55
73
-
66
-
5
56
-
-
67
-
6
57
-
-
68
9
7
58
10
16
-
77
15
-
F10
E9
C2
J8
D11
-
F9
C10
B3
H10
C11
-
E11
-
D1
H9
-
54
-
3
44
-
-
55
60
4
45
59
-
56
-
5
46
-
-
-
-
6
47
-
-
-
E11
-
C2
J8
-
TIOB9_1
TIOB9_2
Base Timer
10
TIOA10_0
TIOA10_1
TIOA10_2
TIOB10_0
TIOB10_1
TIOB10_2
TIOA11_0
TIOA11_1
TIOA11_2
TIOB11_0
TIOB11_1
TIOB11_2
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
TIOA14_0
TIOA14_1
TIOA14_2
TIOB14_0
TIOB14_1
TIOB14_2
TIOA15_0
TIOA15_1
TIOA15_2
TIOB15_0
TIOB15_1
TIOB15_2
-
E10
C10
B3
H10
C11
-
E9
-
D1
H9
-
Base Timer
11
Base Timer
12
-
-
-
-
E10
-
D2
H7
-
D2
G10
-
-
-
E2
D3
G9
E3
-
Base Timer
13
-
F8
E1
D3
G10
E2
G1
-
A9
F3
-
B11
A2
C5
F1
A3
D6
F2
9
7
48
10
-
-
61
-
Base Timer
14
-
A10
-
-
B11
A2
C5
-
A3
B5
-
-
79
99
94
13
98
93
14
63
79
74
-
78
73
-
Base Timer
15
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
33
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
100
112
80
96
Debugger
SWCLK
Serial wire debug interface
clock input pin
93
78
B9
62
B9
Serial wire debug interface
data input / output pin
Serial wire viewer output pin
J-TAG test clock input pin
J-TAG test data input pin
J-TAG debug data output pin
J-TAG test mode state
input/output pin
SWDIO
95
80
A8
64
A9
SWO
TCK
TDI
96
93
94
96
81
78
79
81
B8
B9
B11
B8
65
62
63
65
B8
B9
B11
B8
TDO
TMS
95
80
A8
64
A9
TRACECLK Trace CLK output pin of ETM
TRACED0
101
97
98
99
100
92
36
37
44
45
46
47
48
49
50
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
89
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
C7
C8
D9
A7
B7
A9
H5
L6
K6
J6
L7
K7
H6
J7
K8
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
-
-
-
-
-
-
-
-
-
TRACED1
Trace data output pin of ETM
TRACED2
TRACED3
-
TRSTX
J-TAG test reset input pin
61
21
22
29
30
31
32
33
34
35
43
44
45
46
47
48
49
53
54
55
56
-
A10
L5
K5
J5
K6
J6
L7
K7
J7
K8
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
External
Bus
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
External bus interface
address bus
-
-
-
60
-
-
-
C10
34
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
Pin Function Pin Name
Function Description
LQFP- LQFP- BGA- LQFP- BGA-
120
103
102
101
100
98
97
94
92
105
106
100
88
87
86
85
83
82
79
77
90
91
112
A6
D7
C7
B7
D9
C8
B11
A9
C6
A5
80
68
67
-
-
-
96
C7
C8
-
-
-
External
Bus
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MDQM0_0
MDQM1_0
External bus interface chip
select output pin
-
-
63
61
70
71
B11
A10
B6
C6
External bus interface byte
mask signal output pin
External bus interface read
enable signal for SRAM
MOEX_0
MWEX_0
MNALE_0
114
113
18
94
93
-
C5
D6
-
74
73
-
C5
B5
-
External bus interface write
enable signal for SRAM
External bus interface ALE
signal to control NAND Flash
memory output pin
External bus interface CLE
signal to control NAND Flash
memory output pin
External bus interface read
enable signal to control
NAND Flash memory
MNCLE_0
MNREX_0
19
21
20
-
-
-
-
-
-
-
-
-
-
-
-
External bus interface write
MNWEX_0 enable signal to control
NAND Flash memory
MADATA00_0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
C1
C2
B3
D1
D2
D3
D5
E1
E2
E3
E4
F1
F2
F3
G1
G2
2
3
4
5
6
7
8
9
10
11
12
-
-
-
C1
C2
B3
D1
D2
D3
E1
E2
E3
G1
G2
-
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
External bus interface data bus
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
-
-
-
-
-
-
Latch enable signal for
MALE_0
multiplex
104
89
B6
69
B7
MRDY_0
External RDY input signal
116
99
96
84
C4
A7
76
66
C4
A8
MCLKOUT_0 External bus clock output pin
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
35
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
100
112
80
96
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
INT09_1
INT09_2
INT10_0
INT10_1
INT10_2
INT11_0
INT11_1
INT11_2
INT12_0
INT12_1
INT12_2
INT13_0
INT13_1
INT13_2
INT14_0
INT14_1
INT14_2
2
97
102
3
98
85
4
63
82
113
66
14
17
69
15
89
75
16
23
88
50
24
114
5
2
82
87
3
83
-
4
53
-
C1
C8
D7
C2
D9
-
B3
J10
-
D6
H9
E1
E4
G9
E2
C10
F9
E3
F4
C11
K8
G3
C5
D1
K5
F2
D5
J5
2
-
67
3
-
-
4
43
-
73
46
9
12
49
10
60
55
11
13
59
35
14
74
5
-
-
8
-
-
-
21
-
-
22
-
-
33
-
-
34
-
-
47
29
-
C1
-
C8
C2
-
External interrupt request 00
input pin
External interrupt request 01
input pin
-
B3
J10
-
External interrupt request 02
input pin
93
56
9
B5
H9
E2
G2
F10
E3
C10
E10
G1
G3
C11
K8
H1
C5
D1
-
-
E1
-
-
-
L5
-
-
K5
-
-
External interrupt request 03
input pin
12
59
10
74
65
11
18
73
45
19
94
5
29
14
8
30
15
-
31
16
-
32
17
-
43
27
-
44
28
-
External interrupt request 04
input pin
External interrupt request 05
input pin
External interrupt request 06
input pin
External interrupt request 07
input pin
34
19
8
External interrupt request 08
input pin
35
20
11
36
21
112
37
22
110
48
32
108
49
33
52
67
44
53
External interrupt request 09
input pin
F3
-
H5
G1
-
L6
G2
-
H6
J4
External interrupt request 10
input pin
External interrupt request 11
input pin
K7
-
-
J7
-
-
G10
J5
-
External interrupt request 12
input pin
-
J7
External interrupt request 13
input pin
L5
-
H7
K6
-
57
39
-
External interrupt request 14
input pin
36
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
100
112
80
96
External
Interrupt
INT15_0
INT15_1
INT15_2
INT16_0
INT16_1
INT16_2
INT17_0
INT17_1
INT17_2
INT18_0
INT18_1
INT18_2
INT19_0
INT19_1
INT19_2
INT20_0
INT20_1
INT20_2
INT21_0
INT21_1
INT21_2
INT22_0
INT22_1
INT22_2
INT23_0
INT23_1
INT23_2
68
116
54
100
118
12
101
119
13
103
6
26
104
7
28
105
45
76
106
46
77
109
47
78
111
99
58
96
-
85
98
-
86
99
-
88
6
G10
C4
-
B7
A3
-
C7
A2
-
A6
D2
H2
B6
D3
H3
C6
J6
E11
A5
L7
E10
-
48
76
-
-
78
-
-
79
-
68
6
16
69
7
18
70
30
56
71
31
-
-
32
-
G9
C4
-
-
A3
-
-
A2
-
C7
D2
H3
B7
D3
J2
B6
K6
E9
C6
J6
-
-
L7
-
-
A8
-
External interrupt request 15
input pin
External interrupt request 16
input pin
External interrupt request 17
input pin
External interrupt request 18
input pin
21
89
7
External interrupt request 19
input pin
23
90
40
66
91
41
67
-
42
68
-
84
69
External interrupt request 20
input pin
External interrupt request 21
input pin
External interrupt request 22
input pin
K7
F8
-
A7
E9
-
66
-
External interrupt request 23
input pin
79
Non-Maskable Interrupt input
pin
NMIX
107
92
B5
72
A6
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
37
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
92
93
94
95
96
97
98
100
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
-
112
A9
B9
B11
A8
B8
C8
D9
A7
B7
C7
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
C11
E8
D10
-
80
61
62
63
64
65
-
-
66
-
96
A10
B9
B11
A9
B8
-
-
A8
-
GPIO
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
99
General-purpose I/O port 0
100
101
102
103
104
105
106
107
62
63
64
65
66
67
68
69
73
74
75
76
77
-
-
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
-
-
-
-
60
59
58
57
-
C8
C7
B7
B6
C6
A6
J11
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
General-purpose I/O port 1
78
79
80
89
88
87
86
85
-
-
-
C10
C11
D9
D10
-
General-purpose I/O port 2
84
-
-
-
-
83
-
-
-
-
82
-
-
-
-
81
-
-
-
-
38
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
Pin Function Pin Name
Function Description
LQFP- LQFP- BGA- LQFP- BGA-
120
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
41
42
44
45
46
47
48
49
50
2
100
9
112
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
80
9
10
11
12
-
-
-
-
-
13
14
15
16
17
18
19
-
96
E2
E3
G1
G2
-
-
-
-
-
G3
H1
H2
H3
J1
J2
J4
-
GPIO
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
P60
P61
P62
P63
P64
P65
P66
P67
P68
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
General-purpose I/O port 3
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
-
-
-
-
-
-
-
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
-
L5
K5
L3
K3
J5
K6
J6
L7
K7
J7
K8
C1
C2
B3
D1
D2
D3
E1
-
General-purpose I/O port 4
3
4
5
6
7
8
9
3
4
5
6
7
8
-
General-purpose I/O port 5
10
11
12
13
116
115
114
113
112
111
110
109
108
-
-
-
-
96
95
94
93
-
-
-
-
-
-
-
-
-
C4
B4
C5
D6
-
-
-
-
-
-
-
-
-
76
75
74
73
-
-
-
-
-
-
-
-
-
C4
B4
C5
B5
-
-
-
-
-
General-purpose I/O port 6
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
39
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
100
112
80
96
GPIO
P70
P71
P72
P73
P74
P80
P81
PE0
PE2
PE3
51
52
53
54
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
General-purpose I/O port 7
55
-
-
-
-
118
119
56
58
59
98
99
46
48
49
A3
A2
K9
L9
L10
78
79
36
38
39
A3
A2
K9
L9
L10
General-purpose I/O port 8
General-purpose I/O port E
40
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
Pin Function Pin Name
Function Description
LQFP- LQFP- BGA- LQFP- BGA-
120
88
66
100
73
56
112
C11
H9
80
59
46
96
C11
H9
Multi-
function
Serial
0
SIN0_0
SIN0_1
Multi-function serial interface
ch.0 input pin
Multi-function serial interface
ch.0 output pin.
This pin operates as SOT0
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA0
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.0 clock I/O pin.
This pin operates as SCK0
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL0
when it is used in an I2C
(operation mode 4).
SOT0_0
87
67
86
68
72
57
71
58
E8
H7
58
47
57
48
D9
G10
D10
G9
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
D10
G10
SCK0_1
(SCL0_1)
Multi-
function
Serial
1
SIN1_0
SIN1_1
8
63
-
53
-
-
43
-
Multi-function serial interface
ch.1 input pin
J10
J10
Multi-function serial interface
ch.1 output pin.
This pin operates as SOT1
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA1
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.1 clock I/O pin.
This pin operates as SCK1
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL1
when it is used in an I2C
(operation mode 4).
SOT1_0
(SDA1_0)
9
-
-
J8
-
-
J8
SOT1_1
(SDA1_1)
64
10
65
54
-
44
-
SCK1_0
(SCL1_0)
-
-
SCK1_1
(SCL1_1)
55
H10
45
H10
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
41
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
100
112
80
96
Multi-
function
Serial
2
SIN2_0
SIN2_1
SIN2_2
53
85
69
-
-
59
-
-
G9
-
-
49
-
-
Multi-function serial interface
ch.2 input pin
F10
Multi-function serial interface
ch.2 output pin.
This pin operates as SOT2
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA2
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.2 clock I/O pin.
This pin operates as SCK2
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL2
when it is used in an I2C
(operation mode 4).
SOT2_0
(SDA2_0)
54
84
73
55
83
74
-
-
-
-
-
-
-
-
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
63
-
G8
-
53
-
F9
-
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
-
-
-
-
SCK2_2
(SCL2_2)
64
F10
54
E11
Multi-
function
Serial
3
SIN3_0
SIN3_1
SIN3_2
110
2
44
-
2
39
-
C1
K6
-
2
29
-
C1
J5
Multi-function serial interface
ch.3 input pin
Multi-function serial interface
ch.3 output pin.
This pin operates as SOT3
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA3
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.3 clock I/O pin.
This pin operates as SCK3
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL3
when it is used in an I2C
(operation mode 4).
SOT3_0
(SDA3_0)
109
3
-
3
-
-
3
-
SOT3_1
(SDA3_1)
C2
J6
-
C2
K6
-
SOT3_2
(SDA3_2)
45
108
4
40
-
30
-
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
4
B3
L7
4
B3
J6
SCK3_2
(SCL3_2)
46
41
31
42
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
Pin Function Pin Name
Function Description
LQFP- LQFP- BGA- LQFP- BGA-
120
102
75
100
87
65
82
112
D7
F9
80
67
55
-
96
C8
E10
-
Multi-
function
Serial
4
SIN4_0
SIN4_1
SIN4_2
Multi-function serial interface
ch.4 input pin
97
C8
Multi-function serial interface
ch.4 output pin.
This pin operates as SOT4
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA4
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.4 clock I/O pin.
This pin operates as SCK4
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL4
when it is used in an I2C
(operation mode 4).
SOT4_0
103
76
88
66
83
89
67
84
A6
E11
D9
68
56
-
C7
E9
-
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
98
SCK4_0
(SCL4_0)
104
77
B6
69
-
B7
-
SCK4_1
(SCL4_1)
E10
A7
SCK4_2
(SCL4_2)
99
-
-
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
105
79
101
106
78
90
69
86
91
68
85
C6
E9
C7
A5
F8
B7
70
-
-
71
-
-
B6
-
-
C6
-
-
Multi-function serial interface
ch.4 RTS output pin
Multi-function serial interface
ch.4 CTS input pin
100
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
43
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
116
113
20
100
96
-
112
C4
-
80
76
-
96
C4
-
Multi-
function
Serial
5
SIN5_0
SIN5_1
SIN5_2
Multi-function serial interface
ch.5 input pin
15
F3
-
-
Multi-function serial interface
ch.5 output pin.
This pin operates as SOT5
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA5
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.5 clock I/O pin.
This pin operates as SCK5
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL5
when it is used in an I2C
(operation mode 4).
SOT5_0
(SDA5_0)
115
112
21
95
-
B4
-
75
-
B4
-
SOT5_1
(SDA5_1)
SOT5_2
(SDA5_2)
16
94
-
G1
C5
-
-
-
SCK5_0
(SCL5_0)
114
111
22
74
-
C5
-
SCK5_1
(SCL5_1)
SCK5_2
(SCL5_2)
17
G2
-
-
44
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
Pin Function Pin Name
Function Description
LQFP- LQFP- BGA- LQFP- BGA-
120
100
112
D1
E4
80
96
D1
G2
Multi-
function
Serial
6
SIN6_0
SIN6_1
5
5
5
Multi-function serial interface
ch.6 input pin
Multi-function serial interface
ch.6 output pin.
17
12
12
SOT6_0
6
16
7
6
11
7
D2
E3
D3
E2
6
11
7
D2
G1
D3
E3
(SDA6_0)
This pin operates as SOT6
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA6
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.6 clock I/O pin.
This pin operates as SCK6
when it is used in a
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
UART/CSIO (operation
modes 0 to 2) and as SCL6
when it is used in an I2C
(operation mode 4).
SCK6_1
(SCL6_1)
15
10
10
Multi-
function
Serial
7
SIN7_0
SIN7_1
11
50
-
45
-
K8
-
35
-
K8
Multi-function serial interface
ch.7 input pin
Multi-function serial interface
ch.7 output pin.
This pin operates as SOT7
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA7
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.7 clock I/O pin.
This pin operates as SCK7
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL7
when it is used in an I2C
(operation mode 4).
SOT7_0
(SDA7_0)
12
49
13
48
-
-
J7
-
-
-
J7
-
SOT7_1
(SDA7_1)
44
-
34
-
SCK7_0
(SCL7_0)
SCK7_1
(SCL7_1)
43
H6
33
K7
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
45
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
100
112
80
96
Multi-
SIN8_0
function
Multi-function serial interface
ch.8 input pin
97
82
C8
-
-
Serial
8
Multi-function serial interface
ch.8 output pin.
This pin operates as SOT8
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA8
when it is used in an I2C
(operation mode 4).
SOT8_0
(SDA8_0)
94
79
B11
-
-
Multi-function serial interface
ch.8 clock I/O pin.
This pin operates as SCK8
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL8
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.9 input pin
Multi-function serial interface
ch.9 output pin.
This pin operates as SOT9
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA9
when it is used in an I2C
(operation mode 4).
SCK8_0
(SCL8_0)
92
17
18
77
12
13
A9
E4
F1
-
-
-
-
-
-
Multi-
SIN9_0
function
Serial
9
SOT9_0
(SDA9_0)
Multi-function serial interface
ch.9 clock I/O pin.
This pin operates as SCK9
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL9
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.10 input pin
Multi-function serial interface
ch.10 output pin.
This pin operates as SOT10
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA10
when it is used in an I2C
(operation mode 4).
SCK9_0
(SCL9_0)
19
23
24
14
18
19
F2
F4
G3
-
-
Multi-
SIN10_0
function
13
14
G3
H1
Serial
10
SOT10_0
(SDA10_0)
Multi-function serial interface
ch.10 clock I/O pin.
This pin operates as SCK10
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL10
when it is used in an I2C
(operation mode 4).
SCK10_0
(SCL10_0)
25
20
H1
15
H2
46
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
Pin Function Pin Name
Function Description
LQFP- LQFP- BGA- LQFP- BGA-
120
100
112
80
96
Multi-
Multi-function serial interface
ch.11 input pin
SIN11_0
function
26
21
H2
16
H3
Serial
11
Multi-function serial interface
ch.11 output pin.
This pin operates as SOT11
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA11
when it is used in an I2C
(operation mode 4).
SOT11_0
(SDA11_0)
27
22
G4
17
J1
Multi-function serial interface
ch.11 clock I/O pin.
This pin operates as SCK11
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL11
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.12 input pin
Multi-function serial interface
ch.12 output pin.
This pin operates as SOT12
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA12
when it is used in an I2C
(operation mode 4).
SCK11_0
(SCL11_0)
28
32
33
23
27
28
H3
J4
18
-
J2
-
Multi-
SIN12_0
function
Serial
12
SOT12_0
(SDA12_0)
L5
-
-
Multi-function serial interface
ch.12 clock I/O pin.
This pin operates as SCK12
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL12
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.13 input pin
Multi-function serial interface
ch.13 output pin.
This pin operates as SOT13
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA13
when it is used in an I2C
(operation mode 4).
SCK12_0
(SCL12_0)
34
35
36
29
30
31
K5
J5
-
-
-
-
-
-
Multi-
SIN13_0
function
Serial
13
SOT13_0
(SDA13_0)
H5
Multi-function serial interface
ch.13 clock I/O pin.
This pin operates as SCK13
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL13
when it is used in an I2C
(operation mode 4).
SCK13_0
(SCL13_0)
37
32
L6
-
-
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
47
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
100
112
80
96
Multi-
Multi-function serial interface
ch.14 input pin
SIN14_0
function
50
-
-
-
-
Serial
14
Multi-function serial interface
ch.14 output pin.
This pin operates as SOT14
when it is used in a
(SDA14_0) UART/CSIO (operation
modes 0 to 2) and as SDA14
when it is used in an I2C
SOT14_0
51
-
-
-
-
(operation mode 4).
Multi-function serial interface
ch.14 clock I/O pin.
This pin operates as SCK14
SCK14_0
(SCL14_0)
when it is used in a
52
82
81
-
-
-
-
-
-
-
-
-
-
-
-
UART/CSIO (operation
modes 0 to 2) and as SCL14
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.15 input pin
Multi-function serial interface
ch.15 output pin.
This pin operates as SOT15
when it is used in a
Multi-
function
Serial
15
SIN15_0
SOT15_0
(SDA15_0) UART/CSIO (operation
modes 0 to 2) and as SDA15
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.15 clock I/O pin.
This pin operates as SCK15
SCK15_0
(SCL15_0)
when it is used in a
80
-
-
-
-
UART/CSIO (operation
modes 0 to 2) and as SCL15
when it is used in an I2C
(operation mode 4).
48
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
Pin Function Pin Name
Function Description
LQFP- LQFP- BGA- LQFP- BGA-
120
100
112
80
96
Multi-
Input signal of waveform
generator to control outputs
RTO00 to RTO05 of
DTTI0X_0
function
23
18
F4
13
G3
Timer
0
DTTI0X_1
79
69
E9
-
-
multi-function timer 0.
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
18
80
63
22
75
64
21
76
65
20
77
66
19
78
67
13
70
53
17
65
54
16
66
55
15
67
56
14
68
57
F1
D11
J10
G2
F9
-
-
43
-
55
44
-
56
45
-
-
46
-
-
47
-
-
16-bit free-run timer ch.0
external clock input pin
J10
-
E10
J8
-
E9
H10
-
J8
G1
E11
H10
F3
E10
H9
F2
16-bit input capture input pin
of multi-function timer 0.
ICxx describes channel
number.
-
H9
-
F8
H7
-
G10
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG00
when it is used in PPG0
output mode.
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG00
when it is used in PPG0
output mode.
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG02
when it is used in PPG0
output mode.
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG02
when it is used in PPG0
output mode.
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG04
when it is used in PPG0
output mode.
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG04
when it is used in PPG0
output mode.
RTO00_0
(PPG00_0)
24
86
25
85
26
84
27
83
28
82
29
81
19
71
20
-
G3
D10
H1
-
14
57
15
-
H1
D10
H2
-
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
21
-
H2
-
16
-
H3
-
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
22
-
G4
-
17
-
J1
-
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
23
-
H3
-
18
-
J2
-
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
24
-
J2
-
19
-
J4
-
RTO05_1
(PPG04_1)
IGTRG_0
IGTRG_1
46
116
41
96
L7
C4
31
76
J6
C4
PPG IGMT mode external
trigger input pin
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
49
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
120
14
45
2
15
46
3
16
47
4
89
48
88
49
87
50
107
65
24
107
65
24
100
9
112
E1
J6
C1
E2
L7
C2
E3
K7
B3
C10
H6
C11
J7
80
9
96
E2
K6
C1
E3
Quadrature
Position/
Revolution
Counter
0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
40
2
10
41
3
11
42
4
74
43
73
44
72
45
92
55
19
92
55
19
30
2
10
31
3
11
32
4
60
33
59
34
58
35
72
45
14
72
45
14
J6
C2
G1
L7
B3
C10
K7
C11
J7
ZIN0_1
ZIN0_2
Quadrature
Position/
Revolution
Counter
1
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
E8
D9
K8
A6
H10
H1
A6
H10
H1
ZIN1_2
K8
B5
H10
G3
B5
H10
G3
Real-time
clock
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
0.5 seconds pulse output pin of
Real-time clock
SUBOUT_1 Sub clock output pin
SUBOUT_2
Low-Power
Consumption
Mode
Deep standby mode return
signal input pin 0
Deep standby mode return
signal input pin 1
Deep standby mode return
signal input pin 2
Deep standby mode return
signal input pin 3
WKUP0
107
63
92
53
73
96
9
B5
J10
C11
C4
72
43
59
76
9
A6
J10
C11
C4
WKUP1
WKUP2
88
WKUP3
116
14
Deep standby mode return
signal input pin 4
WKUP4
E1
E2
Deep standby mode return
signal input pin 5
WKUP5
102
87
D7
67
C8
HDMI-
CEC/
Remote
Control
Reception
HDMI-CEC/Remote Control
Reception ch.0 input/output
pin
CEC0_0
CEC0_1
CEC1_0
CEC1_1
48
103
116
8
43
88
96
8
H6
A6
C4
D5
33
68
76
8
K7
C7
C4
E1
HDMI-CEC/Remote Control
Reception ch.1 input/output
pin
50
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Pin No
Pin function Pin name
Function description
LQFP- LQFP- BGA- LQFP- BGA-
120
100
112
80
96
Reset
External Reset Input pin.
A reset is valid when
INITX=L.
INITX
43
38
K4
28
K4
Mode
Mode 0 pin.
During normal operation,
MD0=L must be input. During
serial programming to Flash
memory, MD0=H must be
input.
MD0
57
47
L8
37
36
L8
Mode 1 pin.
During serial programming to
Flash memory, MD1=L must
be input.
MD1
56
46
K9
K9
Power
GND
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
GND pin
1
31
40
61
91
117
-
-
-
-
30
-
-
-
-
39
60
-
-
-
-
-
-
90
-
-
-
-
-
1
26
35
51
76
97
-
-
-
-
25
-
-
-
-
34
50
-
-
-
-
-
-
75
-
-
-
-
-
B1
J1
1
-
25
41
-
77
-
-
-
-
20
-
-
-
-
24
40
-
-
-
-
-
B1
-
K1
K11
-
A4
F1
F2
F3
B2
L1
K2
J3
K1
K11
A10
A4
-
-
-
B2
L1
K2
J3
H4
-
L4
L11
K10
J9
H8
B10
C9
-
A11
D8
-
D4
C3
-
-
L6
L4
L11
K10
J9
-
B10
C9
D11
A11
-
A7
-
C3
A5
A1
-
-
-
-
-
-
-
80
GND pin
GND pin
GND pin
120
100
A1
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
51
D a t a S h e e t
Pin No
LQFP- LQFP- BGA- LQFP- BGA-
Pin Function Pin Name
Function Description
120
100
112
80
96
Clock
X0
Main clock (oscillation) input
pin
58
48
L9
38
L9
Sub clock (oscillation) input
pin
Main clock (oscillation) I/O
pin
X0A
X1
41
59
36
49
L3
26
39
L3
L10
L10
X1A
CROUT_0
CROUT_1
Sub clock (oscillation) I/O pin
Built-in High-speed CR-osc
clock output port
42
89
107
37
74
92
K3
C10
B5
27
60
72
K3
C10
A6
ADC
AVCC
Power
A/D converter analog power
supply pin
A/D converter analog reference
voltage input pin
70
71
72
38
60
61
62
33
H11
F11
G11
L2
50
51
52
23
H11
F11
G11
L2
AVRH
ADC
AVSS
GND
A/D converter GND pin
C pin
Power stabilization capacity
pin
C
52
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
When the main oscillation is
selected.
Oscillation feedback resistor
: Approximately 1 MΩ
With standby mode control
Digital output
Digital output
P-ch
P-ch
X1
When the GPIO is selected.
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
N-ch
R
: Approximately 33 kΩ
IOH= -4 mA, IOL= 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
B
CMOS level hysteresis input
Pull-up resistor
: Approximately 33 kΩ
Pull-up resistor
Digital input
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
53
D a t a S h e e t
Type
Circuit
Remarks
C
Open drain output
CMOS level hysteresis input
Digital input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is
selected.
Oscillation feedback resistor
: Approximately 5MΩ
With standby mode control
P-ch
P-ch
Digital output
Digital output
X1A
When the GPIO is selected.
CMOS level output.
N-ch
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
IOH= -4 mA, IOL= 4 mA
R
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
54
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Type
Circuit
Remarks
E
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
: Approximately 33 kΩ
Digital output
Digital output
IOH= -4 mA, IOL= 4 mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
IOH= -4 mA, IOL= 4 mA
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital output
Digital output
P-ch
P-ch
N-ch
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
G
CMOS level hysteresis input
Mode input
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
55
D a t a S h e e t
Type
H
Circuit
Remarks
CMOS level output
CMOS level hysteresis input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
IOH= -4 mA, IOL= 4 mA
Available to control PZR
registers.
When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
56
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
57
D a t a S h e e t
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and
has established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
58
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant
aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum
laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
59
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator
to stabilize the oscillation.
• Surface mount type
Size : More than 3.2 mm × 1.5 mm
Load capacitance : Approximately 6 pF to 7 pF
• Lead type
Load capacitance : Approximately 6 pF to 7 pF
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
61
D a t a S h e e t
Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock
input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
• Example of Using an External Clock
Device
X0(X0A)
Set as
Can be used as
general-purpose
I/O ports.
External clock
input
X1(PE3),
X1A (P47)
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
C pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7uF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistor stays low, as well as the distance between the mode pins and VCC pins or VSS pins is
as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
62
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC →AVCC → AVRH
Turning off : AVRH → AVCC → VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between
Flash memory products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash memory
products and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant
I/O.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
63
D a t a S h e e t
Block Diagram
TRSTX,TCK,
TDI,TMS
SWJ-DP
ETM*
SRAM0
16/24/32 Kbyte
TDO
ROM
Table
TRACEDx,
TRACECLK
TPIU*
I
SRAM1
16/24/32 Kbyte
D
NVIC
Sys
On-Chip Flash
256+32 Kbyte/
384+32 Kbyte/
512+32 Kbyte
Flash I/F
Security
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch.
CSV
CLK
X0
X1
Main
Source Clock
CR
PLL
CR
Osc
Sub
Osc
X0A
X1A
4 MHz 100 kHz
CROUT
MADx
AVCC,
AVSS,
AVRH
MADATAx
External Bus I/F
12-bit A/D Converter
Unit 0
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT
ANxx
Unit 1
Power-On
Reset
ADTGx
LVD
LVD Ctrl
TIOAx
TIOBx
Base Timer
16-bit 16ch./
32-bit 8ch.
Regulator
C
IRQ-Monitor
CRC Accelerator
Watch Counter
AINx
BINx
ZINx
QPRC
2ch.
WKUPx
Deep Standby Ctrl
CEC0,
CEC1
HDMI-CEC/
Remote Reciver Control
A/D Activation Compare
2ch.
RTCCO,
SUBOUT
Real-Time Clock
16-bit Input Capture
4ch.
IC0x
External Interrupt
Controller
24-pin + NMI
INTx
16-bit Free-run Timer
3ch.
FRCK0
NMIX
16-bit Output Compare
6ch.
MD0,
MD1
MODE-Ctrl
GPIO
DTTI0X
RTO0x
P0x,
P1x,
Waveform Generator
3ch.
.
.
.
PIN-Function-Ctrl
PEx
SCKx
SINx
SOTx
CTS4
RTS4
16-bit PPG
3ch.
IGTRG
Multi-Function Serial I/F
16ch.
HW flow control(ch.4)
Multi-function Timer × 1
*: For the MB9AF154MB, MB9AF155MB, and MB9AF156MB, ETM is not available.
Memory Size
See Memory size in Product Lineup to confirm the memory size.
64
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
DMAC
Reserved
0x4004_0000
0x4003_F000
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
EXT-bus I/F
Reserved
RTC
Reserved
Watch Counter
CRC
0x7000_0000
0x6000_0000
External Device
Area
MFS
Reserved
0x4003_6000
0x4003_5000
Reserved
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
0x4400_0000
0x4200_0000
0x4000_0000
32Mbytes
Bit band alias
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
GPIO
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
Reserved
CR Trim
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Reserved
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
A/DC
QPRC
Reserved
Base Timer
PPG
0x2008_0000
0x2000_0000
0x1FF8_0000
0x0020_8000
0x0020_0000
0x0010_4000
0x0010_0000
SRAM1
SRAM0
Reserved
Reserved
Flash(Work area)
Reserved
0x4002_1000
0x4002_0000
See "Memory Map (2)"
for the memory size
details.
MFT Unit0
Reserved
Security/CR Trim
0x4001_6000
0x4001_5000
Dual Timer
Reserved
Flash(Main area)
0x4001_3000
SW WDT
HW WDT
0x4001_2000
0x4001_1000
0x0000_0000
Clock/Reset
0x4001_0000
Reserved
Flash I/F
0x4000_1000
0x4000_0000
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
65
D a t a S h e e t
Memory Map (2)
MB9AF156MB/NB/RB
MB9AF155MB/NB/RB
MB9AF154MB/NB/RB
0x2008_0000
0x2008_0000
0x2008_0000
Reserved
Reserved
Reserved
0x2000_8000
0x2000_0000
0x2000_6000
0x2000_0000
0x1FFF_A000
SRAM1
32 Kbytes
0x2000_4000
0x2000_0000
0x1FFF_C000
SRAM1
24 Kbytes
SRAM1
16 Kbytes
SRAM0
16 Kbytes
SRAM0
24 Kbytes
SRAM0
32 Kbytes
0x1FFF_8000
0x0020_8000
Reserved
Reserved
Reserved
0x0020_8000
0x0020_0000
0x0020_8000
0x0020_0000
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
SA7(8KB)
SA6(8KB)
SA5(8KB)
SA4(8KB)
0x0020_0000
Reserved
Reserved
Reserved
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
0x0010_4000
0x0010_2000
0x0010_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
Reserved
0x0008_0000
Reserved
SA15(64KB)
SA14(64KB)
SA13(64KB)
SA12(64KB)
SA11(64KB)
SA10(64KB)
SA9(64KB)
SA8(48KB)
0x0006_0000
SA13(64KB)
SA12(64KB)
SA11(64KB)
SA10(64KB)
SA9(64KB)
SA8(48KB)
0x0004_0000
SA11(64KB)
SA10(64KB)
SA9(64KB)
SA8(48KB)
SA3(8KB)
SA2(8KB)
SA3(8KB)
SA2(8KB)
SA3(8KB)
SA2(8KB)
0x0000_0000
0x0000_0000
0x0000_0000
For more information about Flash (Main area)/Flash (Work area), see MB9AB40N/A40N/340N/140N/150R,
MB9B520M/320M/120M Series Flash Programming Manual.
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_F000
0x4004_0000
0x4006_0000
0x4006_1000
0x4000_0FFF
Flash memory I/F register
AHB
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_EFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x41FF_FFFF
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual Timer
Reserved
Multi-function timer unit0
Reserved
PPG
Base Timer
APB1 Quadrature Position/Revolution Counter
A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
HDMI-CEC/Remote control Reception
Low-Voltage Detector
Deep standby mode Controller
APB2
Reserved
Multi-function serial
CRC
Watch Counter
Real-time clock
Reserved
External bus interface
Reserved
AHB
DMAC register
Reserved
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
67
D a t a S h e e t
Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
68
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
List of Pin Status
Power-on
Return from
Deep
standby
reset or
low-voltage
detection
state
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
A
Main crystal
oscillator input pin/
Input
Input
Input
Input
Input
Input
Input
Input
Input
External main clock enabled
input selected
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
External main clock Setting
Setting
disabled
Setting
disabled
input selected
disabled
B
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Hi-Z /
Internal
input fixed Internal
at 0/
or Input
enable
state/When state/When state/When state/When state/When state/When
oscillation oscillation oscillation oscillation oscillation oscillation
Hi-Z /
Hi-Z /
Internal
Main crystal
oscillator output pin
stops*1,
Hi-Z /
Internal
stops*1,
Hi-Z /
Internal
stops*1,
Hi-Z /
Internal
stops*1,
Hi-Z /
Internal
stops*1,
Hi-Z /
Internal
stops*1,
Hi-Z /
Internal
input fixed input fixed
at 0
at 0
input fixed input fixed input fixed input fixed input fixed input fixed
at 0
at 0
at 0
at 0
at 0
at 0
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
INITX
input pin
C
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
E
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
69
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Return from
Deep
standby
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
F
Sub crystal oscillator
input pin /
Input
Input
Input
Input
Input
Input
Input
Input
Input
External sub clock
input selected
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z/
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
External sub clock
input selected
Setting
disabled
Setting
disabled
Setting
disabled
G
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Maintain
previous
Hi-Z /
Internal
state/When state/When state/When state/When state/When
Hi-Z /
Hi-Z /
Internal
Maintain oscillation oscillation oscillation oscillation oscillation
Sub crystal oscillator input fixed Internal
previous
state
stops*2,
Hi-Z /
Internal
stops*2,
Hi-Z /
Internal
stops*2,
Hi-Z/
Internal
stops*2,
Hi-Z/
Internal
stops*2,
Hi-Z/
Internal
output pin
at 0/
or Input
enable
input fixed input fixed
at 0
at 0
input fixed input fixed input fixed input fixed input fixed
at 0
at 0
at 0
at 0
at 0
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
NMIX selected
Hi-Z /
WKUP
input
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
GPIO
selected
H
Resource other than
above selected
GPIO
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Internal
input fixed
at 0
enabled
Hi-Z
selected
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Return from
Deep
standby
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Hi-Z
Maintain
previous
state
Maintain
previous
state
I
GPIO
selected
Internal
input fixed
at 0
Resource selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Resource selected
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
GPIO
selected
J
Hi-Z
GPIO
selected
Maintain
previous
state
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Resource other than
above selected
K
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
Hi-Z
GPIO
selected
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at "0" /
Analog
input
at 0 /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
L
Resource other than
above selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
M
Maintain
previous
state
External interrupt
enabled selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Resource other than
above selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
71
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Return from
Deep
standby
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
N
Trace
output
Trace selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Resource other than
above selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Trace
output
Trace selected
O
GPIO
selected
Internal
input fixed
at 0
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
External interrupt
enabled selected
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Resource other than
above selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed input fixed
Analog input
selected
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
at 0 /
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Hi-Z /
WKUP
input
enabled
WKUP
input
enabled
WKUP
enabled
Maintain
previous
state
P
enabled
External interrupt
enabled selected
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Resource other than
above selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Power-on
reset or
low-voltage
detection
state
Return from
Deep
standby
Device Run mode
internal or Sleep
reset state mode state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc
mode or Deep standby
Stop mode state
INITX
input state
mode state
Function
group
Power
supply
unstable
Power
supply
stable
Power
supply
stable
INITX = 1
-
Maintain
previous
state
Power supply stable
Power supply stable Power supply stable
INITX = 1 INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
SPL = 0
SPL = 1
Maintain
previous
state
SPL = 0
SPL = 1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
enabled
Setting
disabled
Setting
Setting
disabled
disabled
Hi-Z /
WKUP
input
WKUP
input
enabled
WKUP
enabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
enabled
Q
External interrupt
enabled selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Resource other than
above selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
External interrupt
enabled selected
GPIO
selected
Internal
input fixed
at 0
R
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Resource other than
above selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
GPIO
selected
Hi-Z /
WKUP
input
WKUP
input
enabled
WKUP
enabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
enabled
External interrupt
enabled selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
S
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Resource other than
above selected
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z
GPIO
selected
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode,
Deep Standby RTC mode, and Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
73
D a t a S h e e t
Electrical Characteristics
1. Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit Remarks
Min
Max
Power supply voltage*1, *2
VCC
AVCC
AVRH
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 4.6
VSS + 4.6
VSS + 4.6
VCC + 0.5
(≤ 4.6 V)
VSS + 6.5
AVCC + 0.5
(≤ 4.6 V)
VCC + 0.5
(≤ 4.6 V)
V
V
V
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
Input voltage*1
VI
V
V
5 V tolerant
Analog pin input voltage*1
Output voltage*1
VIA
VO
VSS - 0.5
V
L level maximum output current*4
L level average output current*5
L level total maximum output current
L level total average output current*6
H level maximum output current*4
H level average output current*5
H level total maximum output current
H level total average output current*6
Power consumption
IOL
IOLAV
∑IOL
∑IOLAV
IOH
IOHAV
∑IOH
∑IOHAV
PD
-
-
-
-
-
-
-
-
-
10
4
100
50
- 10
- 4
- 100
- 50
300
+ 150
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*6: The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100 ms.
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
2. Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Value
Parameter
Symbol Conditions
Unit
Remarks
Min
Max
3.6
Power supply voltage
Analog power supply voltage
VCC
AVCC
-
-
1.65*2
1.65
V
V
V
V
3.6
AVCC = VCC
AVCC ≥ 2.7 V
AVCC < 2.7 V
For built-in
Regulator*1
2.7
AVCC
AVCC
Analog reference voltage
AVRH
-
AVCC
Smoothing capacitor
Operating temperature
CS
TA
-
-
1
10
μF
- 40
+ 85
°C
*1 : See C Pin in Handling Devices for the connection of the smoothing capacitor.
*2 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this
data sheet. If you are considering application under any conditions other than listed herein, please contact
sales representatives beforehand.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
75
D a t a S h e e t
3. DC Characteristics
(1) Current rating
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter Symbol
Conditions
Unit Remarks
Typ*3 Max*4
CPU: 40 MHz,
Peripheral: 40 MHz
CPU: 40 MHz,
Peripheral: the clock stops
NOP operation
17.5
8
23.7 mA *1, *5
PLL
Run mode
11
mA *1, *5
High-speed
CR
Run mode
Sub
Run mode
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
ICC
CPU/ Peripheral: 4 MHz*2
CPU/ Peripheral: 32 kHz
CPU/ Peripheral: 100 kHz
Peripheral: 40 MHz
1.9
120
140
11
3.1
810
830
15
mA *1
μA *1, *6
μA *1
Power
supply
current
VCC
mA *1, *5
mA *1
Peripheral: 4 MHz*2
Peripheral: 32 kHz
0.82
105
125
1.7
ICCS
800
810
μA *1, *6
μA *1
Peripheral: 100 kHz
Sleep mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=3.6 V
*4: TA=+85°C, VCC=3.6 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
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Value
Pin
name
Parameter Symbol
Conditions
Unit Remarks
mA *1, *3
mA *1, *3
μA *1, *4
μA *1, *4
μA *1, *4
μA *1, *4
μA *1
Typ*2 Max*2
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
2.0
2.7
3.2
45
Main
Timer mode
-
ICCT
15
-
Sub
Timer mode
440
40
13
-
ICCR
RTC mode
Stop mode
380
38
11
-
ICCH
TA = + 85°C,
When LVD is off
TA = + 25°C,
370
μA *1
When LVD is off,
When RAM is off
2.0
9.2
12
25
μA *1, *4, *5
μA *1, *4, *5
Power
supply
current
ICCRD
TA = + 25°C,
When LVD is off,
When RAM is on
VCC
Deep
Standby
RTC mode
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
When LVD is off,
When RAM is on
TA = + 25°C,
125
195
10
μA *1, *4, *5
μA *1, *4, *5
μA *1, *5
-
When LVD is off,
When RAM is off
1.4
8.6
TA = + 25°C,
When LVD is off,
When RAM is on
23
μA *1, *5
Deep
ICCHD
Standby
Stop mode
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
120
190
μA *1, *5
-
When LVD is off,
When RAM is on
μA *1, *5
*1: When all ports are fixed.
*2: VCC=3.6 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
*5: RAM on/off setting is on-chip SRAM only.
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· Low-Voltage Detection Current
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
At operation
for reset
VCC = 3.6 V
0.13
0.3
μA At not detect
μA At not detect
Low-voltage
detection circuit
(LVD) power
supply current
ICCLVD
VCC
At operation
for interrupt
VCC = 3.6 V
0.13
0.3
· Flash Memory Current
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
9.5
11.2
mA
*
*: The current at which to write or erase Flash memory, ICCFLASH is added to ICC.
· A/D Converter Current
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to +85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
mA
μA
Remarks
Typ
Max
At 1unit
operation
0.27
0.42
Power supply
current
ICCAD
AVCC
AVRH
At stop
0.03
0.72
0.02
10
1.29
2.6
At 1unit
operation
AVRH=3.6 V
mA
Reference power
supply current
ICCAVRH
At stop
μA
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
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(2) Pin Characteristics
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Parameter Symbol Pin name
Conditions
Unit Remarks
Min
Max
CMOS
hysteresis
input pin,
MD0, MD1
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC × 0.8
-
-
-
-
VCC + 0.3
V
H level input
voltage
(hysteresis
input)
VCC × 0.7
VCC × 0.8
VCC × 0.7
VIHS
5V tolerant
input pin
VSS + 5.5
V
V
V
CMOS
hysteresis
input pin,
MD0, MD1
VCC × 0.2
VCC × 0.3
VCC × 0.2
VSS - 0.3
VSS - 0.3
L level input
voltage
(hysteresis
input)
VILS
5 V tolerant
input pin
VCC < 2.7 V
VCC × 0.3
VCC ≥ 2.7 V,
IOH = - 4 mA
VCC - 0.5
H level
output voltage
VOH
4mA type
-
-
VCC
V
V
VCC < 2.7 V,
IOH = - 2 mA
VCC - 0.45
VCC ≥ 2.7 V,
IOL = 4 mA
L level
output voltage
VOL
4mA type
-
VSS
0.4
VCC < 2.7 V,
IOL = 2 mA
-
- 5
-
-
-
+ 5
μA
μA
CEC0_0,
CEC0_1,
CEC1_0,
CEC1_1
Input leak
current
VCC = AVCC
AVRH = VSS
=
=
IIL
+1.8
AVSS = 0.0 V
VCC ≥ 2.7 V
21
-
33
-
66
Pull-up
resistor value
RPU Pull-up pin
kΩ
VCC < 2.7 V
134
Other than
VCC,
Input
capacitance
VSS,
AVCC,
CIN
-
-
5
15
pF
AVSS,
AVRH
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4. AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Input frequency
Input clock cycle
Symbol
Conditions
Unit
Remarks
Min
4
Max
48
VCC ≥ 2.7V
VCC < 2.7V
When crystal oscillator
is connected
When using external
clock
When using external
clock
When using external
clock
MHz
MHz
ns
4
20
fCH
-
-
4
48
250
55
X0,
X1
tCYLH
-
20.83
45
Input clock pulse
width
PWH/tCYLH,
PWL/tCYLH
%
Input clock rising
time and falling
time
tCF,
tCR
When using external
clock
-
-
5
ns
fCM
fCC
-
-
-
-
-
-
40
40
MHz Master clock
Base clock
(HCLK/FCLK)
MHz
Internal operating
clock*1 frequency
fCP0
fCP1
fCP2
-
-
-
-
-
-
-
-
-
40
40
40
MHz APB0 bus clock*2
MHz APB1 bus clock*2
MHz APB2 bus clock*2
Base clock
tCYCC
-
-
25
-
ns
(HCLK/FCLK)
Internal operating
clock*1 cycle time
tCYCP0
tCYCP1
tCYCP2
-
-
-
-
-
-
25
25
25
-
-
-
ns
ns
ns
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral
Manual.
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
X0
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D a t a S h e e t
(2) Sub Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal
-
-
32.768
-
kHz oscillator is
connected*
Input frequency
fCL
When using
external clock
When using
external clock
When using
external clock
-
-
32
10
45
-
-
-
100
31.25
55
kHz
X0A,
X1A
Input clock cycle
tCYLL
-
μs
Input clock pulse
width
PWH/tCYLL,
PWL/tCYLL
%
*: For more information about crystal oscillator, see Sub crystal oscillator in Handling Devices.
X0A
(3) Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
MHz
μs
Remarks
Min
TA = + 25°C,
VCC ≥ 2.7V
3.94
4
4
4
4
4
4.06
4.08
4.12
4.1
TA = - 20°C to + 85°C,
3.92
3.88
3.9
VCC ≥ 2.7V
TA = - 40°C to + 85°C,
When trimming*1
VCC ≥ 2.7V
Clock frequency
fCRH
TA = + 25°C,
VCC < 2.7V
TA = - 40°C to + 85°C
VCC < 2.7V
3.66
4.20
TA =
- 40°C to + 85°C
2.8
-
4
-
5.2
30
When not trimming
Frequency
stabilization time
2
tCRWT
-
*
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature
trimming.
*2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value.
This period is able to use High-speed CR clock as source clock.
Built-in Low-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ Max
Parameter
Symbol
Conditions
Unit
Remarks
Min
Clock frequency
fCRL
-
50
100
150
kHz
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(4-1) Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKPLL
4
5
75
-
-
-
-
-
16
37
150
40
MHz
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral
Manual.
(4-2) Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for input
clock of Main PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKPLL
3.8
19
72
-
4
-
-
4.2
35
150
40
MHz
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
-
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral
Manual.
Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency
has been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
Main PLL
clock
(CLKPLL)
PLL input
clock
PLL macro
oscillation clock
Main clock (CLKMO)
K
M
divider
Main
PLL
divider
High-speed CR clock (CLKHC)
N
divider
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
(5) Reset Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
(6) Power-on Reset Timing
Parameter
(VCC= 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Symbol
Unit
Remarks
Min
0
Max
Power supply rising time
tVCCR
tOFF
-
-
ms
ms
Power supply shut down time
1
VCC
Time until releasing
Power-on reset
tPRT
1.34
16.09
ms
VCC_minimum
VDH_minimum
VCC
0.2V
tVCCR
0.2V
0.2V
tPRT
tOFF
Internal reset
Reset active
Release
start
CPU Operation
Glossary
・VCC_minimum : Minimum VCC of recommended operating conditions
・VDH_minimum : Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset
See 6. Low-Voltage Detection Characteristics
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(7) External Bus Timing
External bus clock output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
40
VCC ≥ 2.7 V
VCC < 2.7 V
-
-
MHz
MHz
Output frequency
tCYCLE
MCLKOUT*
20
*: The external bus clock (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family
Peripheral Manual.
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
MCLKOUT
External bus signal input/output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol Conditions
Value
Unit
Remarks
VIH
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
V
V
V
V
Signal input characteristics
Signal output characteristics
VIL
-
VOH
VOL
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
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D a t a S h e e t
Separate Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tOEW
Pin name
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
MOEX
MOEX
MCLK×n-3
-
Min pulse width
MCSX ↓ → Address
output delay time
MOEX ↑ →
Address hold time
MCSX ↓ →
MOEX ↓ delay time
MOEX ↑ →
MCSX ↑ time
MCSX[7:0],
MAD[24:0]
MOEX,
-9
-12
+9
+12
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
MCLK×m+9
MCLK×m+12
MCLK×m-9 MCLK×m+9
0
MAD[24:0]
VCC < 2.7 V MCLK×m-12 MCLK×m+12
MOEX,
MCSX[7:0]
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
MCLK×m+9
MCLK×m+12
MCLK×m-9 MCLK×m+9
0
MCSX ↓ →
MCSX,
MDQM[1:0]
MOEX,
MADATA[15:0]
MOEX,
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MOEX ↑ →
Data hold time
MWEX
Min pulse width
MWEX ↑ → Address
output delay time
MCSX ↓ →
MWEX ↓ delay time
MWEX ↑ →
MCSX ↑ delay time
MCSX ↓→
MDQM ↓ delay time
MCSX ↓→
Data output time
MWEX ↑ →
VCC < 2.7 V MCLK×m-12 MCLK×m+12
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
20
38
-
-
tDH - OE
0
-
-
MADATA[15:0]
tWEW
MWEX
MCLK×n-3
MWEX,
MAD[24:0]
MCLK×m+9
MCLK×m+12
MCLK×n+9
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL-DV
0
MCLK×n-9
VCC < 2.7 V MCLK×n-12 MCLK×n+12
MWEX,
MCSX[7:0]
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
MCLK×m+9
MCLK×m+12
MCLK×n+9
0
MCSX,
MDQM[1:0]
MCSX,
MADATA[15:0]
MWEX,
MCLK×n-9
VCC < 2.7 V MCLK×n-12 MCLK×n+12
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MCLK-9
MCLK-12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
tWEH - DX
0
Data hold time
MADATA[15:0]
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
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D a t a S h e e t
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
86
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Separate Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tAV
Pin name
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
9
12
9
12
9
12
9
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MCLK,
MAD[24:0]
Address delay time
1
tCSL
1
1
1
1
MCLK,
MCSX[7:0]
MCSX delay time
MOEX delay time
tCSH
tREL
12
9
12
MCLK,
MOEX
tREH
tDS
19
37
Data set up →
MCLK ↑ time
MCLK ↑ →
MCLK,
MADATA[15:0]
MCLK,
-
tDH
0
-
Data hold time
MADATA[15:0]
9
12
9
12
9
12
9
12
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
1
MCLK,
MWEX
MWEX delay time
1
1
MDQM[1:0]
delay time
MCLK,
MDQM[1:0]
1
MCLK+1
1
MCLK+18
MCLK+24
18
MCLK ↑ →
Data output time
MCLK ↑ →
Data hold time
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
24
Note: When the external load capacitance CL = 30 pF.
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
tAV
tAV
Address
Address
MAD[24:0]
MOEX
tREL
tREH
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[1:0]
tWEL
MWEX
tDS
tDH
RD
Invalid
WD
MADATA[15:0]
tODS
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Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tALE-CHMADV
tCHMADH
Pin name
Conditions
Unit
ns
Min
Max
+10
+20
VCC ≥ 2.7 V
VCC < 2.7 V
Multiplexed
address delay time
Multiplexed
0
MALE,
MADATA[15:0]
VCC ≥ 2.7 V MCLK×n+0 MCLK×n+10
VCC < 2.7 V MCLK×n+0 MCLK×n+20
ns
address hold time
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
88
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D a t a S h e e t
Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Max
Parameter
Symbol
tCHAL
Pin name
Conditions
Unit Remarks
Min
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
9
12
9
ns
ns
ns
ns
1
MCLK,
ALE
MALE delay time
tCHAH
1
1
12
MCLK ↑ →
Multiplexed
Address delay time
MCLK ↑ →
Multiplexed
Data output time
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
tCHMADV
tOD
ns
ns
MCLK,
MADATA[15:0]
tCHMADX
1
tOD
Note: When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
89
D a t a S h e e t
NAND Flash Memory Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tNREW
Pin name
Conditions
Unit
ns
Min
Max
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MNREX
Min pulse width
Data setup →
MNREX↑time
MNREX↑→
Data hold time
MNREX
MCLK×n-3
-
MNREX,
MADATA[15:0]
MNREX,
20
38
-
-
tDS – NRE
ns
tDH – NRE
0
-
ns
MADATA[15:0]
VCC ≥ 2.7 V MCLK×m-9
MCLK×m+9
MNALE↑→
MNWEX delay time
MNALE↓→
MNWEX delay time
MNCLE↑→
MNWEX delay time
MNWEX↑→
MNCLE delay time
MNWEX
Min pulse width
MNWEX↓→
Data output time
MNALE,
MNWEX
MNALE,
MNWEX
MNCLE,
MNWEX
MNCLE,
MNWEX
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
ns
VCC < 2.7 V MCLK×m-12 MCLK×m+12
VCC ≥ 2.7 V MCLK×m-9
MCLK×m+9
VCC < 2.7 V MCLK×m-12 MCLK×m+12
VCC ≥ 2.7 V MCLK×m-9
MCLK×m+9
VCC < 2.7 V MCLK×m-12 MCLK×m+12
ns
ns
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MCLK×m+9
MCLK×m+12
0
ns
MNWEX
MCLK×n-3
-
ns
MNWEX,
MADATA[15:0]
MNWEX,
- 9
-12
+ 9
+12
MCLK×m+9
MCLK×m+12
tNWEL – DV
tNWEH – DX
ns
MNWEX↑→
Data hold time
0
ns
MADATA[15:0]
Note: When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16).
90
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
NAND Flash Memory Read
MCLK
MNREX
MADATA[15:0]
Read
NAND Flash Memory Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
91
D a t a S h e e t
NAND Flash Memory Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
92
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
External Ready Input Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol Pin name Conditions
Unit Remarks
Min
Max
MCLK ↑
MRDY input
setup time
VCC ≥ 2.7 V
19
MCLK,
MRDY
tRDYI
-
ns
VCC < 2.7 V
37
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
93
D a t a S h e e t
(8) Base Timer Input Timing
Timer input timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Input pulse width
Symbol Pin name Conditions
Unit Remarks
Min
Max
TIOAn/TIOBn
(when using as
TGIN)
tTRGH
tTRGL
,
-
2tCYCP
-
ns
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see Block Diagram in this data
sheet.
94
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
(9) CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Pin
VCC ≥ 2.7 V
Parameter
Symbol
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx
Min
Max
Min
Max
Serial clock cycle time
tSCYC
4tCYCP
-
4tCYCP
-
SCK ↓ → SOT delay time
tSLOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
Master mode
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
Serial clock L pulse width
Serial clock H pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
tSHIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx,
SINx
2tCYCP
10
-
2tCYCP
10
-
SCKx
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see Block Diagram in
this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
95
D a t a S h e e t
tSCYC
VOH
SCK
SOT
VOL
VOL
tSLOVI
VOH
VOL
tIVSHI
VIH
tSHIXI
VIH
VIL
SIN
VIL
Master mode
tSLSH
tSHSL
VIH
tR
VIH
tF
VIH
SCK
VIL
VIL
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
96
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
CSIO (SPI = 0, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Pin
VCC ≥ 2.7 V
Parameter
Symbol
tSCYC
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx
Min
Max
Min
Max
Serial clock cycle time
4tCYCP
-
4tCYCP
-
SCK ↑ → SOT delay time
tSHOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
Master mode
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
Serial clock L pulse width
Serial clock H pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
tSLIXI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
SCKx,
SINx
2tCYCP
10
-
2tCYCP
10
-
SCKx
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see Block Diagram in
this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
97
D a t a S h e e t
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
98
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
CSIO (SPI = 1, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Pin
VCC ≥ 2.7 V
Parameter
Symbol
tSCYC
Conditions
Unit
ns
name
SCKx
SCKx,
SOTx
SCKx,
SINx Master mode
SCKx,
SINx
Min
Max
Min
Max
Serial clock cycle time
4tCYCP
-
4tCYCP
-
SCK ↑ → SOT delay time
tSHOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
Serial clock L pulse width
Serial clock H pulse width
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
tIVSLI
tSLIXI
tSOVLI
tSLSH
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
SCKx,
SOTx
2tCYCP
30
-
2tCYCP
30
-
-
-
2tCYCP
10
-
2tCYCP
10
-
SCKx
-
-
tCYCP
10
+
tCYCP
10
+
tSHSL
SCKx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
-
-
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see Block Diagram in
this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
99
D a t a S h e e t
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
tF
VIH
VIH
SCK
SOT
SIN
VIL
VIL
tR
tSHOVE
VOH
VOL
*
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
100
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
CSIO (SPI = 1, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Pin
name
VCC ≥ 2.7 V
Parameter
Symbol
Conditions
Unit
Min
Max
Min
Max
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
Serial clock L pulse width
Serial clock H pulse width
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
tSHIXI
tSOVHI
tSLSH
50
0
-
-
30
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Master mode
2tCYCP
30
2tCYCP
10
tCYCP
10
-
2tCYCP
30
2tCYCP
10
tCYCP
10
-
-
-
-
-
SCKx
SCKx
-
-
+
+
tSHSL
-
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
Slave mode
10
20
10
20
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes: The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see Block Diagram in
this data sheet.
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
101
D a t a S h e e t
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol Conditions
Unit Remarks
Min
Max
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
tSLSH
tSHSL
tF
tCYCP + 10
tCYCP + 10
-
-
5
5
ns
ns
ns
ns
CL = 30 pF
-
-
SCK rising time
tR
tF
tR
t
t
SLSH
SHSL
SCK
V
V
V
IH
IH
IH
VIL
VIL
V
IL
102
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
(10) External Input Timing
Parameter Symbol
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin name
Conditions
Unit
Remarks
Min
Max
A/D converter
trigger input
Free-run timer
input clock
Input capture
Waveform
ADTG
FRCKx
ICxx
1
-
2tCYCP
*
-
ns
tINH,
Input pulse width
tINL
DTIxX
generator
*2
*3
2tCYCP + 100*1
500
-
-
ns
ns
INTxx,
NMIX
External interrupt,
NMI
Deep Standby
wake up
WKUPx
*4
600
-
ns
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Multi-function Timer is connected to, see Block Diagram in this
data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in Timer mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
103
D a t a S h e e t
(11) Quadrature Position/Revolution Counter timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
Unit
Min
Max
AIN pin H width
AIN pin L width
BIN pin H width
BIN pin L width
tAHL
tALL
tBHL
tBLL
-
-
-
-
BIN rising time from
AIN pin H level
AIN falling time from
BIN pin H level
BIN falling time from
AIN pin L level
AIN rising time from
BIN pin L level
AIN rising time from
BIN pin H level
BIN falling time from
AIN pin H level
AIN falling time from
BIN pin L level
BIN rising time from
AIN pin L level
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
PC_Mode2 or
PC_Mode3
QCR:CGSC=0
QCR:CGSC=0
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
2tCYCP
*
-
ns
ZIN pin H width
ZIN pin L width
tZHL
tZLL
AIN/BIN rising and falling
time from determined ZIN
level
Determined ZIN level from
AIN/BIN rising and falling
time
tZABE
QCR:CGSC=1
QCR:CGSC=1
tABEZ
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see Block
Diagram in this data sheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
104
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
105
D a t a S h e e t
(12) I2C Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Standard-mode Fast-mode
Parameter
Symbol Conditions
Unit Remarks
Min
Max
Min Max
SCL clock frequency
(Repeated) START condition
hold time
fSCL
0
100
0
400 kHz
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
(Repeated) START condition
setup time
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
4.7
-
0.6
-
μs
SCL ↑ → SDA ↓
Data hold time
CL = 30 pF,
R = (VP/IOL)*1
tHDDAT
tSUDAT
tSUSTO
0
3.45*2
0
0.9*3 μs
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
250
4.0
-
-
100
0.6
-
-
ns
μs
Bus free time between
STOP condition and
START condition
tBUF
tSP
4.7
2
-
-
1.3
2
-
-
μs
Noise filter
-
ns
4
4
tCYCP
*
tCYCP*
*1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies
the requirement of tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
106
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
(13) ETM Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Min Max
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
2
11
TRACECLK,
TRACED[3:0]
Data hold
tETMH
ns
2
15
-
40 MHz
20 MHz
TRACECLK
frequency
1/ tTRACE
-
TRACECLK
25
50
-
-
ns
ns
TRACECLK
clock cycle
tTRACE
Note: When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
107
D a t a S h e e t
(14) JTAG Timing
Parameter
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Symbol Pin name Conditions
Unit
ns
Remarks
Min
Max
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
TMS, TDI setup
time
TCK,
TMS, TDI
tJTAGS
15
-
TCK,
TMS, TDI
TMS, TDI hold time tJTAGH
TDO delay time tJTAGD
15
-
ns
-
-
25
45
TCK,
TDO
ns
VCC < 2.7V
Note: When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
108
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
5. 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
-
Pin
name
Parameter
Symbol
Unit
Remarks
Min
-
-
Max
12
± 4.5
Resolution
Integral Nonlinearity
Differential
-
-
-
-
bit
LSB
± 2.4
-
-
-
-
-
± 2.3
± 7
± 2.5
± 15
LSB
mV
Nonlinearity
Zero transition voltage
Full-scale transition
voltage
VZT
VFST
ANxx
ANxx
AVRH ± 7 AVRH ± 15 mV
2.0
4.0
10
0.6
1.2
3.0
100
200
500
-
-
-
-
-
-
-
-
-
AVCC ≥ 2.7 V
Conversion time*1
-
-
-
-
μs
us
ns
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
Sampling time*2
tS
10
Compare clock
cycle*3
tCCK
-
1000
1.0
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
State transition time to
operation permission
Analog input capacity
tSTT
-
-
-
-
-
-
μs
CAIN
9.4
2.2
5.5
10.5
4
pF
AVCC ≥ 2.7 V
Analog input resistor
RAIN
-
-
-
kΩ 1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
LSB
Interchannel disparity
Analog port input leak
current
-
-
-
-
-
-
-
-
-
-
-
ANxx
ANxx
AVRH
5
μA
Analog input voltage
AVSS
2.7
AVCC
AVRH
AVCC
V
AVCC ≥ 2.7 V
AVCC < 2.7 V
Reference voltage
V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 2.7 V, HCLK=40 MHz
1.8 V < AVCC < 2.7 V, HCLK=40 MHz
sampling time: 0.6 μs, compare time: 1.4 μs
sampling time: 1.2 μs, compare time: 2.8 μs
1.65 V < AVCC < 1.8 V, HCLK=40 MHz sampling time: 3 μs, compare time: 7 μs
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family
Peripheral Manual Analog Macro Part.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
For the number of the APB bus to which the A/D Converter is connected, see Block Diagram.
The base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
109
D a t a S h e e t
ANxx
Analog input pin
Comparator
REXT
RAIN
Analog
signal source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS: Sampling time[ns]
RAIN: input resistor of A/D[kΩ] = 2.2 kΩ at 2.7 V < AVCC < 3.6 V
input resistor of A/D[kΩ] = 5.5 kΩ at 1.8 V < AVCC < 2.7 V
input resistor of A/D[kΩ] = 10.5 kΩ at 1.65 V < AVCC < 1.8 V
CAIN: input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V
REXT: Output impedance of external circuit[kΩ]
(Equation 2) tC = tCCK × 14
tC: Compare time
tCCK: Compare clock cycle
110
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Definition of 12-bit A/D Converter Terms
Resolution:
Integral Nonlinearity:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition
point (0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to
change the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
characteristics
0xFFE
0x(N+1)
0xN
{1 LSB(N-1) + VZT}
0xFFD
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actually-measured
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Actually-measured
value)
Ideal characteristics
0x001
(Actually-measured value)
VZT
Actual conversion characteristics
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT: Voltage at which the digital output changes from 0x000 to 0x001.
VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
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D a t a S h e e t
6. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
SVHR*1 = 00000
SVHR*1 = 00001
SVHR*1 = 00010
SVHR*1 = 00011
SVHR*1 = 00100
SVHR*1 = 00101
SVHR*1 = 00110
SVHR*1 = 00111
SVHR*1 = 01000
SVHR*1 = 01001
SVHR*1 = 01010
SVHR*1 = 01011
SVHR*1 = 01100
SVHR*1 = 01101
SVHR*1 = 01110
SVHR*1 = 01111
SVHR*1 = 10000
SVHR*1 = 10001
SVHR*1 = 10010
SVHR*1 = 10011
-
Unit
Remarks
Min
1.38
1.43
1.43
Typ
1.50
1.55
1.55
Max
1.60
1.65
1.65
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
LVD stabilization
wait time
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
Same as SVHR = 00000 value
1.47 1.60 1.73
Same as SVHR = 00000 value
1.52 1.65 1.78
Same as SVHR = 00000 value
1.56 1.70 1.84
Same as SVHR = 00000 value
1.61 1.75 1.89
Same as SVHR = 00000 value
1.66 1.80 1.94
Same as SVHR = 00000 value
1.70 1.85 2.00
Same as SVHR = 00000 value
1.75 1.90 2.05
Same as SVHR = 00000 value
1.79 1.95 2.11
Same as SVHR = 00000 value
1.84 2.00 2.16
Same as SVHR = 00000 value
1.89 2.05 2.21
Same as SVHR = 00000 value
2.30 2.50 2.70
Same as SVHR = 00000 value
2.39 2.60 2.81
Same as SVHR = 00000 value
2.48 2.70 2.92
Same as SVHR = 00000 value
2.58 2.80 3.02
Same as SVHR = 00000 value
2.67 2.90 3.13
Same as SVHR = 00000 value
2.76 3.00 3.24
Same as SVHR = 00000 value
2.85 3.10 3.35
Same as SVHR = 00000 value
2.94 3.20 3.46
Same as SVHR = 00000 value
5200 ×
tLVDW
-
-
μs
μs
2
tCYCP
*
LVD detection
delay time
tLVDDL
-
-
-
200
*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to 00000 by
Low-Voltage Detection Reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
112
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D a t a S h e e t
(2) Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Value
Typ
1.70
1.75
1.75
1.80
1.80
1.85
1.85
1.90
1.90
1.95
1.95
2.00
2.00
2.05
2.05
2.10
2.50
2.60
2.60
2.70
2.70
2.80
2.80
2.90
2.90
3.00
3.00
3.10
3.10
3.20
3.20
3.30
Parameter
Symbol Conditions
Unit
Remarks
Min
1.56
1.61
1.61
1.66
1.66
1.70
1.70
1.75
1.75
1.79
1.79
1.84
1.84
1.89
1.89
1.93
2.30
2.39
2.39
2.48
2.48
2.58
2.58
2.67
2.67
2.76
2.76
2.85
2.85
2.94
2.94
3.04
Max
1.84
1.89
1.89
1.94
1.94
2.00
2.00
2.05
2.05
2.11
2.11
2.16
2.16
2.21
2.21
2.27
2.70
2.81
2.81
2.92
2.92
3.02
3.02
3.13
3.13
3.24
3.24
3.35
3.35
3.46
3.46
3.56
5200 ×
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
LVD stabilization
wait time
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
SVHI = 01011
SVHI = 01100
SVHI = 01101
SVHI = 01110
SVHI = 01111
SVHI = 10000
SVHI = 10001
SVHI = 10010
SVHI = 10011
-
tLVDW
-
-
-
-
μs
μs
tCYCP
*
LVD detection delay
time
tLVDDL
-
200
*: tCYCP indicates the APB2 bus clock cycle time.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
113
D a t a S h e e t
7. Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(VCC = 1.65V to 3.6V, TA = - 40°C to + 85°C)
Value
Parameter
Unit
Remarks
Typ*
Max*
Large Sector
Small Sector
1.1
2.7
Sector erase
time
Includes write time prior to internal
erase
s
0.3
30
0.9
Half word (16-bit)
write time
Not including system-level overhead
time
528
μs
Includes write time prior to internal
erase
Chip erase time
11.2
30.5
s
*: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle
of erase/write.
(2) Write cycles and data hold time
Erase/write cycles (cycle) Data hold time (year)
Remarks
1,000
10,000
20*
10*
*: At average + 85C
114
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
8. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
・Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
tCYCC
Sleep mode
μs
High-speed CR Timer mode,
Main Timer mode,
40
80
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
350
690
700
880
μs
μs
tICNT
RTC mode,
Stop mode
278
523
μs
318
278
603
523
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
*: The maximum value depends on the accuracy of built-in CR.
・Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
115
D a t a S h e e t
・Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
・When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3
Family Peripheral Manual.
116
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
・Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
148
263
μs
High-speed CR Timer mode,
Main Timer mode,
148
263
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
258
322
278
483
516
523
μs
μs
μs
tRCNT
RTC/Stop mode
318
278
603
523
μs
μs
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
*: The maximum value depends on the accuracy of built-in CR.
・Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
117
D a t a S h e e t
・Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
・When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3
Family Peripheral Manual.
・The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on
Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time
during the power-on reset/low-voltage detection reset.
・When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait
time or the Main PLL clock stabilization wait time.
・The internal resource reset means the watchdog reset and the CSV reset.
118
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Main: 256 Kbyte
Work: 32 Kbyte
MB9AF154MBPMC-G-JNE2
MB9AF155MBPMC-G-JNE2
MB9AF156MBPMC-G-JNE2
MB9AF154MBBGL-GE1
MB9AF155MBBGL-GE1
MB9AF156MBBGL-GE1
MB9AF154NBPMC-G-JNE2
MB9AF155NBPMC-G-JNE2
MB9AF156NBPMC-G-JNE2
MB9AF154NBBGL-GE1
MB9AF155NBBGL-GE1
MB9AF156NBBGL-GE1
MB9AF154RBPMC-G-JNE2
MB9AF155RBPMC-G-JNE2
MB9AF156RBPMC-G-JNE2
32 Kbyte
48 Kbyte
64 Kbyte
32 Kbyte
48 Kbyte
64 Kbyte
32 Kbyte
48 Kbyte
64 Kbyte
32 Kbyte
48 Kbyte
64 Kbyte
32 Kbyte
48 Kbyte
64 Kbyte
Plastic LQFP 80-pin
(0.5 mm pitch),
Main: 384 Kbyte
Work: 32 Kbyte
(FPT-80P-M37)
Main: 512 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Plastic PFBGA 96-pin
(0.5 mm pitch),
Main: 384 Kbyte
Work: 32 Kbyte
(BGA-96P-M07)
Main: 512 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Plastic LQFP 100-pin
(0.5 mm pitch),
Main: 384 Kbyte
Work: 32 Kbyte
Tray
(FPT-100P-M23)
Main: 512 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Plastic PFBGA 112-pin
(0.8 mm pitch),
Main: 384 Kbyte
Work: 32 Kbyte
(BGA-112P-M04)
Main: 512 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Plastic LQFP 120-pin
(0.5 mm pitch),
Main: 384 Kbyte
Work: 32 Kbyte
(FPT-120P-M37)
Main: 512 Kbyte
Work: 32 Kbyte
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
119
D a t a S h e e t
Package Dimensions
120-pin plastic LQFP
Lead pitch
0.50 mm
16.0 mm × 16.0 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.70 mm Max
0.88 g
Code
(Reference)
(FPT-120P-M37)
P-LFQFP120-16 × 16-0.50
120-pin plastic LQFP
(FPT-120P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00 ± 0.20(.709 ± .008) SQ
*
16.00 ± 0.10(.630 ± .004) SQ
90
61
Details of "A" part
91
60
1.50+–00..1200 .059–+..000048
(Mounting height)
0.25(.010)
0.08(.003)
0˚~8˚
INDEX
0.60± 0.15
(.024± .006)
"A"
0.10± 0.05
120
31
(.004± .002)
(Stand off)
1
30
LEAD No.
0.145+–00..0035
+.002
)
(
.006–.001
0.50(.020)
0.22± 0.05
(.009± .002)
M
0.08(.003)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
C
2010 FUJITSU SEMICONDUCTOR LIMITED F120037Sc(1)-1-1
120
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
D a t a S h e e t
100-pin plastic LQFP
Lead pitch
0.50 mm
14.00 mm × 14.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.65 g
Sealing method
Mounting height
Weight
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
1.50
-0.10
+.008
.059
-.004
(
)
(Mounting height)
INDEX
0°~8°
0.10±0.10
(.004±.004)
(Stand off)
100
26
0.50±0.20
(.020±.008)
"A"
0.25(.010)
0.60±0.15
1
25
(.024±.006)
0.50(.020)
0.22±0.05
(.009±.002)
0.145±0.055
(.006±.002)
M
0.08(.003)
Dimensions in mm (inches).
Note:The values in parenthesesare reference values.
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
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80-pin plastic LQFP
Lead pitch
0.50 mm
12.00 mm × 12.00 mm
Gullwing
Package width ×
package length
Lead shape
Lead bend
direction
Normal bend
Plastic mold
1.70 mm MAX
0.47 g
Sealing method
Mounting height
Weight
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551± .008)SQ
*12.00± 0.10(.472± .004)SQ
0.145± 0.055
(.006± .002)
60
41
Details of "A" part
61
40
1.50–+00..1200
(Mounting height)
.059+–..000048
0.25(.010)
0~8°
0.08(.003)
0.50± 0.20
(.020± .008)
0.60± 0.15
0.10± 0.05
(.004± .002)
(Stand off)
(.024± .006)
INDEX
80
21
"A"
1
20
0.50(.020)
0.22± 0.05
M
0.08(.003)
(.009± .002)
Dimensions in mm (inches).
C
Note: The values in parentheses are reference values.
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
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D a t a S h e e t
112-ball plastic PFBGA
Ball pitch
0.80 mm
10.00 × 10.00 mm
Soldering ball
Plastic mold
Ф 0.45 mm
Package width ×
package length
Lead shape
Sealing method
Ball size
Mounting height
Weight
1.45 mm Max.
0.22 g
(BGA-112P-M04)
112-ball plastic PFBGA
(BGA-112P-M04)
10.00±0.10(.394±.004)
0.20(.008) S
B
0.80(.031)
REF
B
11
10
9
0.80(.031)
REF
8
A
7
10.00±0.10
(.394±.004)
6
5
4
3
2
1
L
K
J
H
G
F
E D
C
B
A
(INDEX AREA)
0.20(.008) S
1.25±0.20
(.049±.008)
(Seated height)
INDEX
0.35±0.10
(.014±.004)
(Stand off)
A
112-Ф0.45±010
(112-Ф0.18±.004)
M
Ф0.08(.003) S A B
S
0.10(.004) S
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
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96-pin plastic FBGA
Lead pitch
0.5 mm
6.00 mm × 6.00 mm
Ball
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.30 mm MAX
0.08 g
(BGA-96P-M07)
96-pin plastic FBGA
(BGA-96P-M07)
5.00(.197)
REF
B
6.00±0.10(.236±.004)
0.50
(.020)
TYP
0.20(.008) S
B
11
10
9
8
A
7
5.00(.197)
REF
6.00±0.10
(.236±.004)
6
5
0.50(.020)
TYP
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
(INDEX AREA)
0.20(.008) S
INDEX
A
96-ø0.30±0.10
(96-ø.012±.004)
M
ø0.05(.002)
S A B
S
1.15±0.15
(.045±.006)
(Seated height)
0.08(.003) S
0.25±0.10
(.010±.004)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2012 FUJITSU SEMICONDUCTOR LIMITED B96007S-c-1-1
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Major Changes
Page
Section
Change Results
Revision 0.1
-
-
-
Initial release
Preliminary → Data Sheet
Revision 1.0
-
FEATURES
On-chip Memories
Corrected the description of "Flash memory".
2
PRODUCT LINEUP
Function
Corrected the value of channel number of the "Base Timer".
8
HANDLING DEVICES
• Added the description of "Crystal oscillator circuit".
• Added the description of "Sub crystal oscillator".
Corrected the figure.
62
BLOCK DIAGRAM
65
• TIOA: input → input/output
• TIOB: output → input
MEMORY MAP
Memory Map (1)
Memory Map (2)
Corrected the value of address of "SRAM0".
66
67
Added the footnote.
PIN STATUS IN EACH CPU STATE
• List of Pin Status
• Corrected the Return from Deep standby mode state of
"Pin status type H".
71, 72
• Corrected the functon group of "Pin status type I".
ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current Rating
• Revised the value of "TBD".
• Revised the typical value of "Power supply voltage
(ICCH, ICCT, ICCR)".
77, 78
• Added the "Flash Memory Write/Erase current (ICCFLASH)".
• Added the footnote.
4. AC Characteristics
• Added the description of Note of "Input frequency (FCL)".
• Added the footnote.
• Reviced the condition.
(2) Sub Clock Input Characteristics
(3) Built-in CR Oscillation Characteristics
• Built-in high-speed CR
81
• Corrected the value.
• Added the item of "Frequency stabilization time".
• Added the footnote.
(7) External Bus Timing
• Separate Bus Access Asynchronous SRAM
Mode
• Corrected the value.
• Deleted the "MWEX ↓ → Data output time".
• Added the "MCSX ↓ → Data output time".
• Corrected the figure.
• Corrected the "MCLK↑ → Data output time".
• Added the "MCLK↑ → Data hold time".
• Corrected the figure.
85, 86
87
• Separate Bus Access Synchronous SRAM
Mode
(9) CSIO Timming
Corrected the description of section title.
UART Timming → CSIO Timming
Corrected the description of "Note".
UART is connected → Multi-function Serial is connected
Added the footnote.
95, 97,
99, 101
(12) I2C Timing
106
109
5. 12-bit A/D Converter
• Revised the parameter.
• Revised the symbol.
• Corrected the value.
Definition of 12-bit A/D Converter Terms
• Revised the parameter.
• Revised the symbol.
111
6. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
• Corrected "Conditions" and "Value" in the table.
• Added the Item.
• Added the footnote.
112
113
(2) Interrupt of Low-Voltage Detection
Added the Item.
Revision 1.1
-
-
Company name and layout design change
Revision 2.0
Corrected the Series name.
-
-
-
MB9A150R Series → MB9A150RA Series
Corrected the Product name as follows.
MB9AF156MA, MB9AF155MA, MB9AF154MA
MB9AF156NA, MB9AF155NA, MB9AF154NA
MB9AF156RA, MB9AF155RA, MB9AF154RA
Added the Item.
-
FEATURES
2
•External Bus Interface
•Multi-function Serial Interface
•Multi-function Timer
PRODUCT LINEUP
•Function
• Maximum area size : Up to 256 Mbytes
2
4
Corrected the description of "I2C"
Corrected the channel count of "A/D activation compare"
8
Added the footnote
April 28, 2015, MB9A150RB_DS706-00047-3v0-E
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D a t a S h e e t
Page
Section
Change Results
Delete the following packages.
•FPT-100P-M36
9
PACKAGES
•FPT-80P-M40
PIN ASSIGNMENT
FPT-100P-M36
-
Delete the Item
Corrected the description of section title.
FPT-80P-M37/M40 →FPT-80P-M37
12
FPT-80P-M37
LIST OF PIN FUNCTION
•List of numbers
•List of pin functions
MEMORY MAP
•Memory Map (1)
15 – 30
31 - 52
65
Delete column of terminal number "QFP-100"
Delete column of terminal number "QFP-100"
Corrected the address "External Device Area"
ELECTRICAL CHARACTERISTICS
2.Recommended Operating Conditions
75
Add the footnote
•Corrected the Condition
•Delete the minmun value
•Corrected the remarks
•Add the footnote
3.DC Characteristics
(1)Current rating
76, 77
(9)CSIO Timing
•Synchronous serial (SPI=1, SCINV=1)
(9) CSIO Timing
• External clock(EXT=1):asyntironous only
101
101
Corrected the figure of "MS bit=1"
Corrected the figure
Add the terminal as follows
•FRCKx
•ICxx
102
105
(10)External Input Timing
•DTTIxX
Corrected the description as follows.
•Typical mode → Standard-mode
•High-speed mode → Fast-mode
•Corrected the terminal name
AN00 to AN23 → ANxx
•Corrected the minmum value of "Sampling time"
•Corrected the max and min value of "State transition time to
oprerationpermission"
(12)I2C Timing
5.12-bit A/D Converter
•Electrical Characteristics for
the A/D Converter
108
•Corrected the footnote
114
ORDERING INFORMATON
Corrected the "Part number"
Revision 3.0
Corrected the Series name.
-
-
-
MB9A150RA Series → MB9A150RB Series
Corrected the Product name as follows.
MB9AF156MB, MB9AF155MB, MB9AF154MB
MB9AF156NB, MB9AF155NB, MB9AF154NB
MB9AF156RB, MB9AF155RB, MB9AF154RB
-
Memory Map
· Memory map(2)
66
Added the summary of Flash memory sector
Electrical Characteristics
3. DC Characteristics
(1) Current rating
· Changed the table format
· Added Main TIMER mode current
· Moved A/D Converter Current
76 - 78
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
82
· Added the figure of Main PLL connection
· Added Time until releasing Power-on reset
· Changed the figure of timing
83
95 - 102
109
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition voltage
· Added the value of conversion time at AVCC < 2.7 V
(8) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
Electrical Characteristics
8. Return Time from Low-Power Consumption
Mode
115 - 118
119
Added Return Time from Low-Power Consumption Mode
Ordering Information
Changed notation of part number
120 - 124 Package Dimensions
Deleted FPT-100P-M36 and FPT-80P-M40
126
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MB9A150RB_DS706-00047-3v0-E, April 28, 2015
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D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2012-2015 Cypress All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM
ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of
,
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.
130
MB9A150RB_DS706-00047-3v0-E, April 28, 2015
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