ICX423AL [SONY]

Diagonal 11mm (Type 2/3) CCD Image Sensor for CCIR B/W Video Cameras; 为CCIR B / W视频摄像机对角线11毫米（ 2/3型） CCD图像传感器


型号：	ICX423AL
厂家：	SONY CORPORATION
描述：	Diagonal 11mm (Type 2/3) CCD Image Sensor for CCIR B/W Video Cameras 为CCIR B / W视频摄像机对角线11毫米（ 2/3型） CCD图像传感器传感器换能器图像传感器 CD 摄像机
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中文：	中文翻译
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ICX423AL

Diagonal 11mm (Type 2/3) CCD Image Sensor for CCIR B/W Video Cameras

Description

20 pin DIP (Ceramic)

The ICX423AL is an interline CCD solid-state image

sensor suitable for CCIR B/W video cameras with a

diagonal 11mm (Type 2/3) system. Compared with the

current product ICX083AL, basic characteristics such

as sensitivity and smear are improved drastically and

high saturation characteristics are realized.

This chip features a field period readout system and

an electronic shutter with variable charge-storage

time. This chip is compatible with the pins of the

ICX083AL and has the same drive conditions.

Pin 1

Features

• High sensitivity (+3.0dB compared with the ICX083AL)

• Low smear (–10.0dB compared with the ICX083AL)

• High saturation signal (+2.0dB compared with the ICX083AL)

• High resolution and Low dark current

• Excellent antiblooming characteristics

• Continuous variable-speed shutter

Pin 11

Optical black position

(Top View)

Device Structure

• Interline CCD image sensor

• Optical size:

Diagonal 11mm (Type 2/3)

• Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels

• Total number of pixels:

• Chip size:

795 (H) × 596 (V) approx. 470K pixels

10.25mm (H) × 8.5mm (V)

• Unit cell size:

• Optical black:

11.6µm (H) × 11.2µm (V)

Horizontal (H) direction: Front 3 pixels, rear 40 pixels

Vertical (V) direction:

Horizontal 22

Front 12 pixels, rear 2 pixels

• Number of dummy bits:

• Substrate material:

Vertical 1 (even fields only)

Silicon

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E01X23-PS

ICX423AL

Block Diagram and Pin Configuration

(Top view)

Vφ

Vφ3

GND

Vφ2

SUB

GND

OUT

Note)

SS 13

Vφ1

Horizontal Register

GND

Hφ

HIS

Hφ1

Note)

: Photo sensor

Pin Description

Pin No. Symbol

Description

Signal output

Description

Vφ⁴

Vφ3

Vφ2

SUB

GND

Vφ1

V^OUT

VGG

VSS

GND

Vertical register transfer clock

Substrate (overflow drain)

GND

Output amplifier gate bias

Output amplifier source

GND

Reset drain

Reset gate clock

Protective transistor bias

Vertical register transfer clock

Protective transistor bias

V^L

Hφ1

Hφ2

HIS

Horizontal register transfer clock

Horizontal register input source bias

GND

V^DD

GND

Output amplifier drain power

– 2 –

ICX423AL

Absolute Maximum Ratings

Item

Substrate voltage SUB – GND

Ratings

–0.3 to +55

–0.3 to +20

–55 to +10

–15 to +20

to +10

Unit

Remarks

HIS, V^DD, RD, VOUT, VSS – GND

Supply voltage

HIS, V^DD, RD, VOUT, VSS – SUB

Vertical clock input pins – GND

Vertical clock input pins – SUB

Vertical clock input

voltage

Voltage difference between vertical clock input pins

Voltage difference between horizontal clock input pins

Hφ¹, Hφ2 – Vφ4

to +15

to +17

–17 to +17

–10 to +15

–55 to +10

–65 to +0.3

–0.3 to +30

–0.3 to +24

–0.3 to +20

–30 to +80

–10 to +60

Hφ1, Hφ2, RG, VGG – GND

Hφ1, Hφ2, RG, VGG – SUB

V^L– SUB

Vφ1, Vφ3, HIS, VDD, RD, VOUT – VL

RG – VL

Vφ2, Vφ4, VGG, VSS, Hφ1, Hφ2 – VL

Storage temperature

°C

Operating temperature

27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Bias Conditions

Item

Symbol Min.

Typ.

15.0

4.2

Max. Unit

Remarks

Output amplifier drain voltage

Reset drain voltage

V^DD

14.7

3.8

15.3

4.6

VRD

V^RD= VDD

Output amplifier gate voltage

VGG

VSS

Ground with 750Ω resistor

Output amplifier source

±5%

Substrate voltage adjustment range

Substrate voltage adjustment precision

Reset gate clock voltage adjustment range

Reset gate clock voltage adjustment precision

Protective transistor bias

VSUB

∆VSUB

VRGL

∆VRGL

–3

3.0

–3

–11

14.7

–10.5

–10

15.3

Horizontal register input source bias

VHIS

15.0

VHIS = VDD

– 3 –

ICX423AL

DC Characteristics

Item

Output amplifier drain current

Input current

Symbol Min.

Typ.

Max.

Unit

µA

Remarks

I^DD

IIN1

IIN2

Input current

µA

Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value

The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the

image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to

the indicated voltage. The adjustment precision is ±3%.

VSUB code — one character indication

VRGL code — one character indication

↑

VRGL code VSUB code

"Code" and optimal setting correspond to each other as follows.

VRGL code

Optimal setting

0.5 1.0 1.5 2.0 2.5 3.0

VSUB code

Optimal setting 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0

<Example> "5K" → VRGL = 2.0V

VSUB = 12.0V

This must no exceed the VVL voltage of the vertical clock waveform.

1) Current to each pin when 20V is applied to VDD, RD, VOUT, VSS, HIS and SUB pins, while pins that are

not tested are grounded.

2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are

not tested are grounded. However, 20V is applied to SUB pin.

3) Current to each pin when 15V is applied sequentially to Hφ1, Hφ2, RG and VGG pins, while pins that are

not tested are grounded. However, 15V is applied to SUB pin.

4) Current to VL pin when 30V is applied to Vφ1, Vφ3, HIS, VDD, RD and VOUT pins or when, 24V is applied

to RG pin or when, 20V is applied to Vφ2, Vφ4, VGG, VSS, Hφ1 and Hφ2 pins, while VL pin is grounded.

However, GND and SUB pins are left open.

Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.

– 4 –

ICX423AL

Clock Voltage Conditions

Waveform

diagram

Item

Symbol

Min.

14.5

–0.6

Typ.

Max. Unit

Remarks

Readout clock voltage V^VT

15.0

15.5

VVH1, VVH2,

VVH3, VVH4

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2

VVL1, VVL2,

V^VL3, VVL4

–9.6

VφV

8.9

Vφ = VVHn – VVLn (n = 1 to 4)

| VVH1 – VVH2 |

VVH3 – VVH

VVH4 – VVH

VVHH

0.2

Vertical transfer clock

voltage

–0.5

0.8

1.0

0.8

8.0

–3.0

13.0

3.0

32.0

High-level coupling

Low-level coupling

VVHL

VVLH

VVLL

VφH

6.0

–3.5

6.0

Horizontal transfer

clock voltage

VHL

VφRG

Reset gata clock

voltage

VRGL

Substrate clock voltage VφSUB

27.0

The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the

specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of

the image sensor has not significance.

Waveform

diagram

Item

Symbol

Min.

Typ.

Max. Unit

Remarks

VRGL

VφRG

–0.2

0.2

9.5

Reset gate clock

voltage

8.5

9.0

– 5 –

ICX423AL

Clock Equivalent Circuit Constant

Symbol

Typ.

2700

2600

950

Item

Min.

Max. Unit

Remarks

CφV1, CφV3

Capacitance between vertical transfer

clock and GND

CφV2, CφV4

CφV12, CφV34

CφV23, CφV41

CφV13

Capacitance between vertical transfer

clocks

1000

500

CφV24

Capacitance between horizontal

transfer clock and GND

CφH1, CφH2

CφHH

Capacitance between horizontal

transfer clocks

Capacitance between reset gate clock

and GND

CφRG

Capacitance between substrate clock

and GND

CφSUB

800

R1, R2, R3, R4

RGND

Vertical transfer clock series resistor

Vertical transfer clock ground resistor

Horizontal transfer clock series resistor

Ω

RφH

Vφ2

Vφ1

CφV12

RφH

Hφ1

Hφ2

CφV1

CφV2

CφHH

CφV41

CφV23

CφV13

CφH2

CφH1

CφV24

RGND

CφV3

CφV4

CφV34

Vφ4

Vφ3

Vertical transfer clock equivalent circuit

Horizontal transfer clock equivalent circuit

– 6 –

ICX423AL

Drive Clock Waveform Conditions

(1) Readout clock waveform

100%

90%

φM

VVT

φM

10%

twh

(2) Vertical transfer clock waveform

Vφ1

Vφ3

VVH1

VVHH

VVH

VVHH

VVHL

VVH3

VVL1

VVL3

VVLH

VVLL

VVL

Vφ2

Vφ4

VVHH

VVH4

VVHH

VVH

VVHL

VVH2

VVLH

_VVL2VVLH

VVLL

VVL4

VVL

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2

VφV = VVHn – VVLn (n = 1 to 4)

– 7 –

ICX423AL

(3) Horizontal transfer clock waveform · Reset gate clock waveform

twh

90%

10%

VφH, VφRG

twl

HL, VRGL

(4) Substrate clock waveform

100%

90%

φM

VφSUB

φM

10%

SUB

twh

Clock Switching Characteristics

twh

twl

Symbol

Unit

Remarks

Item

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

Readout clock

2.3 2.5

62.6

1.3

0.5

0.1

µs During readout

Vφ1, Vφ2

Vφ3, Vφ4

Hφ

0.74

62.1

0.1

µs

Vertical transfer

clock

During imaging

µs

0.1

15 19

0.01

15 19 ns During imaging

Horizontal

transfer clock

During

parallel-serial

conversion

Hφ1

5.38

0.01

µs

Hφ2

5.38

Reset gate

clock

φRG

11 13

1.5 1.8

2.0

0.5

2.0

During drain

charge

Substrate clock φSUB

0.5 µs

– 8 –

ICX423AL

Image Sensor Characteristics

Item Symbol Min.

Sensitivity

(Ta = 25°C)

Typ.

Max. Unit Measurement method

Remarks

700

1000

Saturation signal

Smear

Vsat

Vdt

∆Vdt

1000

Ta = 60°C

–130

–120

Video signal shading

Dark signal

Dark signal shading

Flicker

Ta = 60°C

Lag

0.5

Image Sensor Characteristics Measurement Method

Measurement conditions

1) In the following measurements, the substrate voltage and the reset gate clock voltage are set to the values

indicated on the device, and the device drive conditions are at the typical values of the bias and clock

voltage conditions.

2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical

black (OB) level is used as the reference for the signal output, and the value measured at point [ A] in the

drive circuit example is used.

Definition of standard imaging conditions

1) Standard imaging condition I:

Use a pattern box (luminance 706cd/m², color temperature of 3200K halogen source) as a subject. (Pattern

for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter

and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the

standard sensitivity luminous intensity.

2) Standard imaging condition II :

Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.

Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter.The luminous intensity is adjusted

to the value indicated in each testing item by the lens diaphragm.

1. Sensitivity

Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s,

measure the signal output (Vs) at the center of the screen and substitute the value into the following formula.

250

S = Vs ×

[mV]

2. Saturation signal

Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with

average value of signal output, 350mV, measure the minimum value of the signal output.

– 9 –

ICX423AL

3. Smear

Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to

500 times the intensity with average value of the signal output, 350mV. When the readout clock is stopped

and the charge drain is executed by the electronic shutter at the respective H blankings, measure the

maximum value (VSm [mV]) of the signal output and substitute the value into the following formula.

500

VSm

350

Sm = 20 × log

× 100 [dB] (1/10V method conversion value)

4. Video signal shading

Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so

that the average value of the signal output is 350mV. Then measure the maximum (Vmax [mV]) and

minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula.

SH = (Vmax – Vmin)/350 × 100 [%]

5. Dark signal

Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and

the device in the light-obstructed state, using the horizontal idle transfer level as a reference.

6. Dark signal shading

After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark

signal output and substitute the values into the following formula.

∆Vdt = Vdmax – Vdmin [mV]

7. Flicker

Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal

output is 350mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then

substitute the value into the following formula.

F = (∆Vf/350) × 100 [%]

8. Lag

Adjust the signal output value generated by strobe light to 350mV. After setting the strobe light so that it

strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following

formula.

Lag = (Vlag/350) × 100 [%]

FLD

Light

Strobe light

timing

Signal output 350mV

Vlag (lag)

Output

– 10 –

ICX423AL

^{D D}V

G N D

N C

^LV

1 φ V

G N D

S U B

2 φ V

O U V T

G G V

^{S S}V

G N D

R D

R G

L V

1 φ H

2 φ H

3 φ V

4 φ V

H I S

– 11 –

ICX423AL

Spectral Sensitivity Characteristics (includes lens characteristics, excludes light source characteristics)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

400

500

600

700

800

900

1000

Wave Length [nm]

Sensor Readout Clock Timing Chart

2.5

Odd Field

1.5

2.6 2.5 2.5

33.6

0.2

Even Field

Unit: µs

– 12 –

ICX423AL

3 4 0

3 3 5

3 3 0

3 2 5

3 2 0

3 1 5

3 1 0

2 5

2 0

1 5

1 0

6 2 5

6 2 0

– 13 –

ICX423AL

2 0

1 0

2 2

2 0

1 0

4 0

3 0

2 0

1 0

7 5 2

7 5 0

7 4 5

– 14 –

ICX423AL

Notes on Handling

1) Static charge prevention

CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following

protective measures.

a) Either handle bare handed or use non-chargeable gloves, clothes or material.

Also use conductive shoes.

b) When handling directly use an earth band.

c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.

d) Ionized air is recommended for discharge when handling CCD image sensor.

e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.

2) Soldering

a) Make sure the package temperature does not exceed 80°C.

b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron

with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.

c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering

tool, use a thermal controller of the zero cross On/Off type and connect it to ground.

3) Dust and dirt protection

Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and

dirt. Clean glass plates with the following operation as required, and use them.

a) Operate in clean environments (around class 1000 is appropriate).

b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces.

Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity

ionized air is recommended.)

c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.

d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when

moving to a room with great temperature differences.

e) When a protective tape is applied before shipping, just before use remove the tape applied for

electrostatic protection. Do not reuse the tape.

4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition

exceeding the normal using condition, consult our company.

5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage

in such conditions.

6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical

shocks.

– 15 –

ICX423AL

6 . 0

2 -

( A T S T A N D O F F )

2 0 . 3 2

0 ˚ t o 9 ˚

5 . 5 ± 0 . 2

3 . 2 ± 0 . 3

2 0 . 2 ± 0 . 3

1 . 0

5 . 0

Sony Corporation

– 16 –

ICX423AL [SONY]

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