ICX424AQ [SONY]

Diagonal 6mm Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras; 用正方形像素的彩色摄像机对角线6毫米逐行扫描CCD图像传感器
ICX424AQ
型号: ICX424AQ
厂家: SONY CORPORATION    SONY CORPORATION
描述:

Diagonal 6mm Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
用正方形像素的彩色摄像机对角线6毫米逐行扫描CCD图像传感器

传感器 换能器 图像传感器 CD 摄像机
文件: 总27页 (文件大小:257K)
中文:  中文翻译
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ICX424AQ  
Diagonal 6mm (Type 1/3) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras  
Description  
16 pin DIP (Plastic)  
The ICX424AQ is a diagonal 6mm (Type 1/3) interline  
CCD solid-state image sensor with a square pixel  
array which supports VGA format. Progressive scan  
allows all pixels signals to be output independently  
within approximately 1/60 second. This chip features  
an electronic shutter with variable charge-storage  
time which makes it possible to realize full-frame still  
images without a mechanical shutter. High sensitivity  
and low dark current are achieved through the  
adoption of the HAD (Hole-Accumulation Diode)  
sensors.  
This chip is suitable for applications such as FA  
and surveillance cameras.  
Features  
Progressive scan allows individual readout of the image signals  
from all pixels.  
Pin 1  
2
High vertical resolution still images without a mechanical shutter  
Square pixel  
Supports VGA format  
V
2
Horizontal drive frequency: 24.54MHz  
No voltage adjustments (reset gate and substrate bias are not  
adjusted.)  
R, G, B primary color mosaic filters on chip  
High resolution, high color reproductivity, high sensitivity, low dark  
current  
8
H
31  
Pin 9  
Optical black position  
(Top View)  
Continuous variable-speed shutter  
Low smear  
Excellent anti-blooming characteristics  
Horizontal register: 5.0V drive  
16-pin high precision plastic package (enables dual-surface standard)  
Device Structure  
Interline CCD image sensor  
Image size:  
Diagonal 6mm (Type 1/3)  
Number of effective pixels: 659 (H) × 494 (V) approx. 330K pixels  
Total number of pixels:  
Chip size:  
Unit cell size:  
Optical black:  
692 (H) × 504 (V) approx. 350K pixels  
5.79mm (H) × 4.89mm (V)  
7.4µm (H) × 7.4µm (V)  
Horizontal (H) direction: Front 2 pixels, rear 31 pixels  
Vertical (V) direction:  
Horizontal 16  
Vertical 5  
Front 8 pixels, rear 2 pixels  
Number of dummy bits:  
Substrate material:  
Silicon  
Wfine CCD is trademark of Sony corporation.  
Represents a CCD adopting progressive scan, primary color filter and square pixel.  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E01Z29A25-PS  
ICX424AQ  
Block Diagram and Pin Configuration  
(Top View)  
8
7
6
5
4
3
2
1
G
R
G
R
G
R
B
G
B
B
G
G
B
R
G
R
G
R
G
B
G
B
G
G
Note)  
16  
Horizontal register  
Note)  
: Photo sensor  
9
10  
11  
12 13 14  
15  
Pin Description  
Pin No. Symbol  
Description  
Pin No. Symbol  
Description  
Supply voltage  
1
Vφ3  
Vertical register transfer clock  
Vertical register transfer clock  
Vertical register transfer clock  
9
VDD  
Supply voltage for the substrate  
voltage generation  
2
Vφ2  
10  
SUBCIR  
3
4
5
6
7
8
Vφ1  
11  
12  
13  
14  
15  
16  
GND  
φSUB  
VL  
GND  
NC  
Substrate clock  
GND  
CGG  
GND  
VOUT  
GND  
Protective transistor bias  
Reset gate clock  
1
Output amplifier gate  
φRG  
Hφ1  
GND  
Horizontal register transfer clock  
Horizontal register transfer clock  
Signal output  
Hφ2  
1
DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance  
of 1000pF.  
2 –  
ICX424AQ  
Absolute Maximum Ratings  
Item  
Substrate clock φSUB GND  
Ratings  
0.3 to +36  
0.3 to +18  
22 to +9  
15 to +16  
to +10  
Unit  
V
Remarks  
VDD, VOUT, CGG, SUBCIR GND  
V
Supply voltage  
VDD, VOUT, CGG, SUBCIR φSUB  
Vφ1, Vφ2, Vφ3 GND  
V
V
Clock input voltage  
Vφ1, Vφ2, Vφ3 φSUB  
V
2
Voltage difference between vertical clock input pins  
Voltage difference between horizongal clock input pins  
Hφ1, Hφ2 Vφ3  
to +15  
V
to +16  
V
16 to +16  
10 to +15  
55 to +10  
65 to +0.3  
0.3 to +27.5  
0.3 to +20.5  
0.3 to +17.5  
30 to +80  
10 to +60  
10 to +75  
V
Hφ1, Hφ2 GND  
V
Hφ1, Hφ2 φSUB  
V
VL φSUB  
V
Vφ2, Vφ3 VL  
V
RG GND  
V
Vφ1, Hφ1, Hφ2, GND VL  
Storage temperature  
V
°C  
°C  
°C  
Performance guarantee temperature  
Operating temperature  
2
+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.  
+16V (Max.) is guaranteed for power-on and power-off.  
3 –  
ICX424AQ  
Bias Conditions  
Item  
Symbol Min.  
Typ.  
Max.  
Unit Remarks  
V
Supply voltage  
Protective transistor bias  
Substrate clock  
Reset gate clock  
1
VDD  
VL  
14.55  
15.0  
15.45  
1
2
3
φSUB  
φRG  
VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power  
supply for the V driver should be used.  
2
3
Set SUBCIR pin to open when applying a DC bias to the substrate clock pin.  
Do not apply a DC bias to the reset gate clock pins, because a DC bias is generated within the CCD.  
DC Characteristics  
Item  
Symbol Min.  
Typ.  
7
Max.  
9
Unit Remarks  
mA  
Supply current  
IDD  
Clock Voltage Conditions  
Item  
Waveform  
Diagram  
Symbol  
Min.  
Typ.  
Max. Unit  
Remarks  
Readout clock voltage VVT  
14.55 15.0 15.45  
V
V
V
1
VVH02  
0.05  
0
0
0.05  
0.05  
2
2
VVH = VVH02  
VVH1, VVH2, VVH3 0.2  
VVL = VVL1 (VVL3)/2  
(During 24.54MHz)  
VVL1, VVL2, VVL3  
VVL1, VVL2, VVL3  
7.8  
7.5  
7.2  
7.0  
V
V
2
2
VVL = VVL1 (VVL3)/2  
(During 12.27MHz)  
8.0  
7.5  
Vertical transfer clock  
voltage  
Vφ1, Vφ2, Vφ3  
| VVL1 VVL3 |  
VVHH  
6.8  
7.5  
8.05  
0.1  
V
V
V
V
V
V
V
V
V
V
V
V
V
2
2
2
2
2
2
3
3
3
4
4
4
5
1.0  
High-level coupling  
High-level coupling  
Low-level coupling  
Low-level coupling  
VVHL  
2.3  
VVLH  
1.0  
VVLL  
1.0  
VφH  
4.75  
0.05  
0.8  
5.0  
0
5.25  
0.05  
Horizontal transfer  
clock voltage  
VHL  
VCR  
2.5  
5.0  
Cross-point voltage  
VφRG  
4.5  
5.5  
0.8  
Reset gate clock  
voltage  
VRGLH VRGLL  
VRGL VRGLm  
Low-level coupling  
Low-level coupling  
0.5  
Substrate clock voltage VφSUB  
21.5  
22.5  
23.5  
4 –  
ICX424AQ  
Clock Equivalent Circuit Constants  
Symbol  
Typ.  
3900  
3300  
3300  
1000  
1000  
1000  
47  
Item  
Min.  
Max. Unit Remarks  
CφV1  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
CφV2  
Capacitance between vertical transfer clock and GND  
Capacitance between vertical transfer clocks  
CφV3  
CφV12  
CφV23  
CφV31  
CφH1, CφH2  
CφHH  
Capacitance between horizontal transfer clock and GND  
Capacitance between horizontal transfer clocks  
Capacitance between reset gate clock and GND  
Capacitance between substrate clock and GND  
30  
CφRG  
6
CφSUB  
R1, R2  
R3  
560  
33  
Vertical transfer clock series resistor  
18  
RGND  
100  
10  
Vertical transfer clock ground resistor  
Horizontal transfer clock series resistor  
Reset gate clock series resistor  
RφH1, RφH2  
RφRG  
39  
R1  
R2  
Vφ1  
Vφ2  
CφV12  
CφV1  
CφV2  
CφV3  
RφH1  
RφH2  
Hφ2  
Hφ1  
RGND  
CφHH  
CφV31  
CφV23  
CφH2  
CφH1  
R3  
Vφ3  
Vertical transfer clock equivalent circuit  
Horizontal transfer clock equivalent circuit  
RφRG  
φRG  
CφRG  
Reset gate clock equivalent circuit  
5 –  
ICX424AQ  
Drive Clock Waveform Conditions  
(1) Readout clock waveform  
VT  
100%  
90%  
φM  
VVT  
φM  
2
10%  
0%  
0V  
tr  
twh  
tf  
Note) Readout clock is used by composing vertical transfer clocks Vφ2 and Vφ3.  
(2) Vertical transfer clock waveform  
VVH1  
Vφ1  
VVHH  
VVH  
VVHL  
VVLH  
V
VL01  
VH02  
VVL1  
V
VL  
V
VLL  
Vφ2  
V
VH2  
V
VVHH  
VVH  
VVHL  
VVLH  
VVL2  
VVL  
VVLL  
VVH3  
Vφ3  
VVHH  
VVH  
VVHL  
VVL03  
VVLH  
VVL  
VVLL  
V
V
V
VH = VVH02  
VL = (VVL01 + VVL03)/2  
VL3 = VVL03  
VφV1 = VVH1 VVL01  
VφV2 = VVH02 VVL2  
VφV3 = VVH3 VVL03  
6 –  
ICX424AQ  
(3) Horizontal transfer clock waveform  
tf  
tr  
Hφ1, Hφ2  
twh  
Hφ2  
90%  
VCR  
VφH  
twl  
VφH  
2
10%  
Hφ1  
VHL  
two  
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.  
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.  
(4) Reset gate clock waveform  
φRG  
tr  
twh  
tf  
VRGH  
RG waveform  
twl  
VφRG  
Point A  
V
V
V
RGLH  
RGLL  
RGLm  
V
RGL  
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from  
Point A in the above diagram until the rising edge of RG.  
In addition, VRGL is the average value of VRGLH and VRGLL.  
VRGL = (VRGLH + VRGLL)/2  
Assuming VRGH is the minimum value during the interval twh, then:  
VφRG = VRGH VRGL  
Negative overshoot level during the falling edge of RG is VRGLm.  
(5) Substrate clock waveform  
φSUB  
100%  
90%  
φM  
VφSUB  
φM  
2
10%  
V
SUB  
0%  
(A bias generated within the CCD)  
tr  
twh  
tf  
7 –  
ICX424AQ  
Clock Switching Characteristics (Horizontal drive frequency: 24.54MHz)  
twh  
twl  
tr  
tf  
Item  
Symbol  
VT  
Unit Remarks  
Min. Typ. Max.Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.  
During  
Readout clock  
2.3 2.5  
0.5  
0.5  
µs  
readout  
Vertical transfer Vφ1, Vφ2,  
When using  
CXD3400N  
15  
250 ns  
clock  
Vφ3  
Hφ1  
Hφ2  
10.5 14.6  
10.5 14.6  
10.5 14.6  
10.5 14.6  
6.4 10.5  
6.4 10.5  
6.4 10.5  
6.4 10.5  
Horizontal  
transfer clock  
ns  
ns  
tf tr 2ns  
Reset gate clock φRG  
Substrate clock φSUB  
6
8
25.8  
4
3
During drain  
charge  
0.75 0.9  
0.5  
0.5 µs  
two  
Min. Typ. Max.  
Item  
Symbol  
Unit Remarks  
1
Horizontal transfer clock Hφ1, Hφ2 10.5 14.6  
ns  
Clock Switching Characteristics (Horizontal drive frequency: 12.27MHz)  
twh  
twl  
tr  
tf  
Item  
Symbol  
VT  
Unit Remarks  
Min. Typ. Max.Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.  
During  
µs  
Readout clock  
4.6 5.0  
0.5  
0.5  
readout  
Vertical transfer Vφ1, Vφ2,  
When using  
CXD3400N  
15  
350 ns  
clock  
Vφ3  
Hφ1  
Hφ2  
24 30  
25 31.5  
25 30  
10 17.5  
10 15  
10 17.5  
10 15  
Horizontal  
transfer clock  
ns  
ns  
tf tr 2ns  
26.5 31.5  
Reset gate clock φRG  
Substrate clock φSUB  
11 13  
1.5 1.8  
62.5  
3
3
During drain  
charge  
0.5  
0.5 µs  
two  
Min. Typ. Max.  
Item  
Symbol  
Unit Remarks  
1
Horizontal transfer clock Hφ1, Hφ2 21.5 25.5  
ns  
1
The overlap period of twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.  
8 –  
ICX424AQ  
Image Sensor Characteristics  
(Ta = 25°C)  
Measurement  
method  
Item  
Symbol Min.  
Typ.  
Max. Unit  
Remarks  
G Sensitivity  
Sg  
600  
0.4  
0.3  
500  
750  
0.55  
0.45  
mV  
0.7  
1
1
1
2
3
4
4
5
5
6
7
8
8
8
9
1/30s accumulation  
Rr  
Sensitivity  
comparison  
Rb  
0.6  
Saturation signal  
Smear  
Vsat  
Sm  
mV  
Ta = 60°C  
100  
92  
20  
25  
8
dB  
%
Zone 0 and I  
Zone 0 to II'  
Video signal shading SHg  
%
%
Srg  
Sbg  
Vdt  
Uniformity between  
video signal channels  
8
%
Dark signal  
Dark signal shading  
Line crawl G  
Line crawl R  
Line crawl B  
Lag  
2
mV  
mV  
%
Ta = 60°C  
Ta = 60°C  
0.5  
3.8  
3.8  
3.8  
0.5  
Vdt  
Lcg  
%
Lcr  
%
Lcb  
%
Lag  
Note) All image sensor characteristic data noted above is for operation in 1/60s progressive scan mode.  
Zone Definition of Video Signal Shading  
659 (H)  
12  
12  
12  
V
10  
H
8
H
8
494 (V)  
Zone 0, I  
Zone II, II'  
10  
Ignored region  
V
10  
Effective pixel region  
Measurement System  
CCD signal output [ A]  
Gr/Gb  
S/H  
CCD  
C.D.S  
AMP  
Gr/Gb channel signal output [ B]  
R/B channel signal output [ C]  
R/B  
S/H  
Note) Adjust the amplifier gain so that the gain between [ A] and [ B], and between [ A] and [ C] equals 1.  
9 –  
ICX424AQ  
Image Sensor Characteristics Measurement Method  
Measurement conditions  
(1) In the following measurements, the device drive conditions are at the typical values of the bias and clock  
voltage conditions.  
(2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical  
black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb  
channel signal output or the R/B channel signal output of the measurement system.  
Color coding of this image sensor & Readout  
The primary color filters of this image sensor are arranged in  
Gb  
R
B
Gr  
B
Gb  
R
B
Gr  
B
the layout shown in the figure on the left (Bayer arrangement).  
Gr and Gb denote the G signals on the same line as the R  
signal and the B signal, respectively.  
Gb  
R
Gb  
R
Gr  
Gr  
Horizontal register  
Color Coding Diagram  
All pixels signals are output successively in a 1/60s period.  
The R signal and Gr signal lines and Gb signal and B signal lines are output successively.  
10 –  
ICX424AQ  
Image sensor readout mode  
The diagram below shows the output methods for the following two readout modes.  
(1) Progressive scan mode  
R
G
R
G
R
G
B
G
B
G
VOUT  
1. Progressive scan mode  
In this mode, all pixel signals are output in non-interlace format in 1/60s.  
All pixel signals within the same exposure period are read out simultaneously, making this mode suitable for  
high resolution image capturing.  
(2) Center scan mode  
Undesired portions (Swept by vertical register high-speed transfer)  
Picture center cut-out portion  
2. Center scan mode  
This is the center scan mode using the progressive scan method.  
The undesired portions are swept by vertical register high-speed transfer, and the picture center portion is  
cut out.  
There are the mode (120 frames/s) which outputs 222 lines of an output line portion, and the mode  
(240 frames/s) which outputs 76 lines.  
11 –  
ICX424AQ  
Definition of standard imaging conditions  
(1) Standard imaging condition I:  
Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject.  
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR  
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined  
as the standard sensitivity testing luminous intensity.  
(2) Standard imaging condition II:  
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.  
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted  
to the value indicated in each testing item by the lens diaphragm.  
1. G Sensitivity,sensitivity comparison  
Set to standard imaging condition I. After setting the electronic shutter mode with a shutter speed of  
1/100s, measure the signal outputs (VGr, VGb, VR and VB ) at the center of each Gr, Gb, R and B channel  
screens, and substitute the values into the following formula.  
VG = (VGr + VGb)/2  
100  
Sg = VG ×  
[mV]  
30  
Rr = VR/VG  
Rb = VB/VG  
2. Saturation signal  
Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the  
average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal  
outputs.  
3. Smear  
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of  
the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R  
signal output and B signal output (Gra, Gba, Ra and Ba), and then adjust the luminous intensity to 500  
times the intensity with average value of the Gr signal output, 150mV. After the readout clock is stopped and  
the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum  
value (Vsm [mV]), independent of the Gr, Gb, R and b signal outputs, and substitute the values into the  
following formula.  
Gra + Gba + Ra + Ba  
4
1
500  
1
10  
Sm = 20 × log Vsm ÷  
×
×
[dB] (1/10V method conversion value)  
(
)
4. Video signal shading  
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so  
that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and  
minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula.  
SHg = (Grmax Grmin)/150 × 100 [%]  
12 –  
ICX424AQ  
5. Uniformity between video signal channels  
After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of the R signal  
and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of the B signal, and substitute the values  
into the following formula.  
Srg = | (Rmax Rmin)/150 | × 100 [%]  
Sbg = | (Bmax Bmin)/150 | × 100 [%]  
6. Dark signal  
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and  
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.  
7. Dark signal shading  
After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark  
signal output and substitute the values into the following formula.  
Vdt = Vdmax Vdmin [mV]  
8. Line crawls  
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Gr signal  
output is 150mV, and then insert R, G, and B filters and measure the difference between G signal lines  
(Glr, Glg, Glb [mV]).as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the  
values into the following formula.  
Gli  
Gai  
Lci =  
× 100 [%] (i = w, r, g, b)  
9. Lag  
Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it  
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following  
formula.  
Lag = (Vlag/150) × 100 [%]  
VD  
V2  
Light  
Strobe light  
timing  
Signal output 150mV  
Vlag (lag)  
Output  
13 –  
ICX424AQ  
O U V T  
D D V  
G N D  
S U B C I R  
G N D  
S φ U B  
G G C  
G N D  
N C  
1 φ V  
L V  
R φ G  
2 φ V  
3 φ V  
1 φ H  
2 φ H  
14 –  
ICX424AQ  
Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics)  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
G
R
B
400  
450  
500  
550  
600  
650  
700  
Wave Length [nm]  
15 –  
ICX424AQ  
8
7
6
5
4
3
2
1
7
1
5 2 5  
2
1
5 1 0  
5 0 8  
4 9 4  
3
2
1
8
7
6
5
4
3
2
1
7
1
5 2 5  
5 1 0  
2
1
4 9 4  
16 –  
ICX424AQ  
17 –  
ICX424AQ  
1 2 5  
1 2 3  
1 6  
1 0 7 7 2 1  
1
3 5  
1
1
7 8 0  
18 –  
ICX424AQ  
8
7
6
5
4
3
2
1
1
2 6 2  
2 6 1  
2 4 6  
2 4 5  
3 5 7  
3 5 6  
1 3 7  
1 3 6  
2 4  
2 1  
2 0  
8
7
6
5
4
3
2
1
1
2 6 2  
2 6 1  
2 4 6  
2 4 5  
3 5 7  
3 5 6  
19 –  
ICX424AQ  
7 2  
3 5  
20 –  
ICX424AQ  
7 2  
3 5  
21 –  
ICX424AQ  
8
7
6
5
4
3
2
1
1
1 3 1  
1 3 0  
1 2 9  
1 0 6  
1 0 5  
2 8 4  
2 8 3  
2 1 0  
2 0 9  
3 0  
2 7  
2 6  
8
7
6
5
4
3
2
1
1
1 3 1  
1 3 0  
1 2 9  
1 0 6  
1 0 5  
2 8 4  
2 8 3  
22 –  
ICX424AQ  
7 2  
3 5  
23 –  
ICX424AQ  
7 2  
3 5  
24 –  
ICX424AQ  
Notes on Handling  
1) Static charge prevention  
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following  
protective measures.  
a) Either handle bare handed or use non-chargeable gloves, clothes or material.  
Also use conductive shoes.  
b) When handling directly use an earth band.  
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.  
d) Ionized air is recommended for discharge when handling CCD image sensors.  
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.  
2) Soldering  
a) Make sure the package temperature does not exceed 80°C.  
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W  
soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount,  
cool sufficiently.  
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering  
tool, use a thermal controller of the zero-cross On/Off type and connect it to ground.  
3) Dust and dirt protection  
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and  
dirt. Clean glass plates with the following operations as required, and use them.  
a) Perform all assembly operations in a clean room (class 1000 or less).  
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should  
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized  
air is recommended.)  
c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass.  
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when  
moving to a room with great temperature differences.  
e) When a protective tape is applied before shipping, just before use remove the tape applied for  
electrostatic protection. Do not reuse the tape.  
4) Installing (attaching)  
a) Remain within the following limits when applying a static load to the package. Do not apply any load  
more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to  
limited portions. (This may cause cracks in the package.)  
Cover glass  
50N  
50N  
1.2Nm  
Plactic package  
Compressive strength  
Torsional strength  
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the  
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for  
installation, use either an elastic load, such as a spring plate, or an adhesive.  
25 –  
ICX424AQ  
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated  
voltage value is indicated on the rear surface.Therefore, the adhesive should not be applied to this area,  
and indicated values should be transferred to other locations as a precaution.  
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.  
In addition, the cover glass and seal resin may overlap with the notch of the package.  
e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be  
generated by the fragments of resin.  
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-  
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.  
(reference)  
5) Others  
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high  
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the  
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a  
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off  
mode should be properly arranged. For continuous using under cruel condition exceeding the normal  
using condition, consult our company.  
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or  
usage in such conditions.  
c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD  
characteristics.  
26 –  
ICX424AQ  
2 . 5  
0 . 2 5  
t o 0 9 ˚ ˚  
1 1 . 4 3  
0 . 1 5 3 . 3 5 ±  
0 . 3 3 . 5 ±  
1 . 2 7  
0 . 1 1 1 . 4 ±  
9 . 5  
3 . 1  
1 . 2  
5 . 7  
8 . 4  
2 . 5  
0 . 5  
2 . 5  
~
~
Sony Corporation  
27 –  

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