ICX412 [SONY]
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor; 时序发生器和信号处理器的帧读出CCD图像传感器
| 型号： | ICX412 |
| 厂家： | 
SONY CORPORATION |
| 描述： | Timing Generator and Signal Processor for Frame Readout CCD Image Sensor |
| 文件： | 总46页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD3412GA
Timing Generator and Signal Processor for Frame Readout CCD Image Sensor
Description
96 pin LFLGA (Plastic)
The CXD3412GA is a timing generator and CCD
signal processor IC for the ICX412 CCD image sensor.
Features
• Timing generator functions
• Horizontal drive frequency 22.5MHz
(base oscillation frequency 45MHz)
• Supports frame readout/draft (sextuple speed)/
AF (auto focus)
Absolute Maximum Ratings
• High-speed/low-speed shutter function
• Horizontal and vertical drivers for CCD image
sensor
• Supply voltage
VDDa, VDDb, VDDc, VDDd
VSS – 0.3 to +7.0
VSS – 0.3 to +4.0
–10.0 to VSS
V
V
V
V
VDDe, VDDf, VDDg
• CCD signal processor functions
• Correlated double sampling
• Programmable gain amplifier (PGA) allows gain
adjustment over a wide range (–6 to +42dB)
• 10-bit A/D converter
VL
VH
VL – 0.3 to +26.0
• Input voltage (analog)
VIN
VSS – 0.3 to VDD + 0.3
VSS – 0.3 to VDD + 0.3
V
V
• Input voltage (digital)
• Chip Scale Package (CSP):
CSP allows vast reduction in the CCD camera
block footprint
VI
• Output voltage
VO1
VSS – 0.3 to VDD + 0.3
VL – 0.3 to VSS + 0.3
VL – 0.3 to VH + 0.3
V
V
V
VO2
Applications
VO3
• Operating temperature
Topr
Digital still cameras
–20 to +75
°C
°C
Structure
• Storage temperature
Tstg
Silicon gate CMOS IC
–55 to +125
Applicable CCD Image Sensors
Recommended Operating Conditions
ICX412 (Type 1/1.8, 3240K pixels)
• Supply voltage
VDDd
3.0 to 5.5
V
VDDa, VDDb, VDDc, VDDd,
VDDe, VDDf, VDDg
3.0 to 3.6
0.0
V
V
V
V
VM
VH
14.5 to 15.5
–7.0 to –8.0
VL
• Operating temperature
Topr
–20 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E02217-PS
CXD3412GA
Block Diagram
A1 A2 C7 D8 D7
B8 B6 B9 A6 C5
A3 A4 B4 A5 C4 B5
E2 F2 F3 E3 F1
C4
AVDD5
AVSS6
C7
C8
A9
A8
B7
A7
C6
C9
E9
E8
D9
E7
F9
F8
F7
G9
G8
G7
H7
H8
K7
K8
K9
H9
D0 (LSB)
B3
B2
B1
C3
C2
C1
D3
D2
D1
E1
Serial Port
Register
DAC
D1
D2
C8
D3
C9
D4
CDS
PGA
ADC
CCDIN
AVDD1
AVDD2
AVSS1
Latch
D5
D6
D7
D8
AVSS2
XSHPI
D9 (MSB)
Dummy Pixel
Black Level
Auto Zero
XSHDI
PBLKI
XSHP
XSHD
PBLK
ADCLKI
CLPOBI
CLPDMI
Preblanking
G1
G2
G3
L3
Auto Zero
VSS4
ADCLK
CLPOB
CLPDM
H1
H2
H3
XRS
V
V
DD4
DD2
RG
VSS5
J3
OSCI
OSCO
CKI
L1
K1
J1
V
SS2
V
DD3
H1
H2
Pulse Generator
J8
J9
CKO
J2
1/2
MCKO
K2
V
SS3
J7
ID/EXP
WEN
N9
M9
SNCSL
N8
Selector
Latch
SSI1
L2
M1
N1
Serial Port
Register
SCK1
SEN1
VH
VM
VL
M5
L4
V Driver
M6
SSGSL
L8
SSG
M8 M3 M7
L5 N5 M4 L6 N6 N4 N7
N2 M2
L9 K3 L7 N3
– 2 –
CXD3412GA
Pin Configuration (Top View)
A
B
C
D
E
F
NC
D2
NC
D1
SCK2
D0
SSI2
SEN2
TEST4
TEST3
TEST5
AVSS5
AVSS4
AVDD4
C9
C8
C7
AVSS6
AVDD3
C4
AVDD5
AVSS3
CCDIN
D5
D4
D3
C3
D8
D7
D6
C1
C2
AVSS1
D9
DVDD1
DVSS3
DVSS1
DVDD2
AVSS2
PBLKI
PBLK
XRS
AVDD2
XSHDI
XSHD
AVDD1
XSHPI
XSHP
DVSS2
G
H
ADCLKI CLPOBI CLPDMI
ADCLK CLPOB CLPDM
VDD4
VDD3
J
CKI
CKO
MCKO
SSI1
VD
V
SS5
V
SS3
H1
RG
H2
K
L
OSCO
OSCI
SCK1
VDD5
VDD2
VSS2
V
SS4
VM
V2
V1A
VH
V3A
VL
VSS1
SSGSL
RST
VDD1
M
N
TEST1
TEST2
WEN
SEN1
1
HD
2
V
SS6
V4
4
V1B
5
V3B
6
SUB
7
SNCSL
8
ID/EXP
9
3
– 3 –
CXD3412GA
Pin Description
Pin
Symbol
No.
I/O
Description
A1 NC
—
—
I
No connected. (Open)
No connected. (Open)
A2 NC
A3 SCK2
A4 SSI2
A5 TEST3
A6 AVSS4
A7 C8
CCD signal processor block serial interface clock input. (Schmitt trigger)
CCD signal processor block serial interface data input. (Schmitt trigger)
CCD signal processor block test input 3. Connect to DVSS.
CCD signal processor block analog GND.
Capacitor connection.
I
I
—
—
—
—
O
O
O
I
A8 AVSS6
A9 AVDD5
B1 D2
CCD signal processor block analog GND.
CCD signal processor block analog power supply.
ADC output.
B2 D1
ADC output.
B3 D0
ADC output (LSB).
B4 SEN2
B5 TEST5
B6 AVDD4
B7 C7
CCD signal processor block serial interface enable input. (Schmitt trigger)
CCD signal processor block test input 5. Connect to DVDD.
CCD signal processor block analog power supply.
Capacitor connection.
I
—
—
—
—
O
O
O
I
B8 AVDD3
B9 AVSS3
C1 D5
CCD signal processor block analog power supply.
CCD signal processor block analog GND.
ADC output.
C2 D4
ADC output.
C3 D3
ADC output.
C4 TEST4
C5 AVSS5
C6 C9
CCD signal processor block test input 4. Connect to DVSS.
CCD signal processor block analog GND.
Capacitor connection.
—
—
—
—
I
C7 C3
Capacitor connection.
C8 C4
Capacitor connection.
C9 CCDIN
D1 D8
CCD output signal input.
O
O
O
—
—
—
O
—
—
—
ADC output.
D2 D7
ADC output.
D3 D6
ADC output.
D7 C1
Capacitor connection.
D8 C2
Capacitor connection.
D9 AVSS1
E1 D9
CCD signal processor block analog GND.
ADC output (MSB).
E2 DVDD1
E3 DVSS1
E7 AVSS2
CCD signal processor block digital power supply. (Power supply for ADC)
CCD signal processor block digital GND. (GND for ADC)
CCD signal processor block analog GND.
– 4 –
CXD3412GA
Pin
No.
Symbol
I/O
Description
E8 AVDD2
E9 AVDD1
F1 DVSS2
F2 DVSS3
F3 DVDD2
—
—
—
—
—
CCD signal processor block analog power supply.
CCD signal processor block analog power supply.
CCD signal processor block digital GND.
CCD signal processor block digital GND.
CCD signal processor block digital power supply.
Pulse input for horizontal and vertical blanking period pulse cleaning.
(Schmitt trigger)
F7 PBLKI
I
F8 XSHDI
F9 XSHPI
G1 ADCLKI
G2 CLPOBI
G3 CLPDMI
G7 PBLK
I
I
CCD data level sample-and-hold pulse input. (Schmitt trigger)
CCD precharge level sample-and-hold pulse input. (Schmitt trigger)
Clock input for analog/digital conversion. (Schmitt trigger)
CCD optical black signal clamp pulse input. (Schmitt trigger)
CCD dummy signal clamp pulse input. (Schmitt trigger)
Pulse output for horizontal and vertical blanking period pulse cleaning.
CCD data level sample-and-hold pulse output.
I
I
I
O
O
O
G8 XSHD
G9 XSHP
CCD precharge level sample-and-hold pulse output.
Clock output for analog/digital conversion.
Logical phase can be adjusted by serial interface data.
H1 ADCLK
H2 CLPOB
O
O
CCD optical black signal clamp pulse output.
Horizontal/vertical OB pattern can be changed by serial interface data.
H3 CLPDM
H7 XRS
H8 VDD4
H9 VDD3
J1 CKI
O
O
—
—
I
CCD dummy signal clamp pulse output.
Sample-and-hold pulse output for analog/digital conversion phase alignment.
Timing generator block digital power supply. (Power supply for CDS block)
Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2)
Inverter input.
J2 CKO
O
—
—
O
O
O
O
—
—
O
—
I
Inverter output.
J3
J7
VSS5
Timing generator block digital GND.
VSS3
Timing generator block digital GND.
J8 H1
CCD horizontal register clock output.
J9 H2
CCD horizontal register clock output.
K1 OSCO
K2 MCKO
K3 VDD5
K7 VDD2
K8 RG
Inverter output for oscillation. When not used, leave open or connect a capacitor.
System clock output for signal processor IC.
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block digital power supply. (Power supply for RG)
CCD reset gate pulse output.
K9 VSS2
L1 OSCI
L2 SSI1
Timing generator block digital GND.
Inverter input for oscillation. When not used, fix to low.
Timing generator block serial interface data input. Schmitt trigger input.
I
– 5 –
CXD3412GA
Pin
No.
Symbol
VSS4
I/O
Description
Timing generator block digital GND.
L3
—
—
O
L4 VM
L5 V1A
L6 V3A
Timing generator block digital GND. (GND for vertical driver)
CCD vertical register clock output.
CCD vertical register clock output.
Timing generator block digital GND.
Internal SSG enable.
O
L7
L8 SSGSL
L9 VDD1
VSS1
—
I
—
I
High: Internal SSG valid, Low: External sync valid
(With pull-down resistor)
Timing generator block digital power supply. (Power supply for common logic block)
Timing generator block serial interface clock input.
Schmitt trigger input.
M1 SCK1
M2 VD
I/O Vertical sync signal input/output.
Timing generator block test input 1.
Normally fix to GND.
M3 TEST1
I
(With pull-down resistor)
M4 V2
M5 VH
M6 VL
O
—
—
CCD vertical register clock output.
Timing generator block 15.0V power supply. (Power supply for vertical driver)
Timing generator block –7.5V power supply. (Power supply for vertical driver)
Timing generator block test input 2.
M7 TEST2
I
Normally fix to GND.
(With pull-down resistor)
Timing generator block reset input.
High: Normal operation, Low: Reset control
Normally apply reset during power-on.
M8 RST
I
Schmitt trigger input/No protective diode on power supply side.
M9 WEN
N1 SEN1
O
I
Memory write timing pulse output.
Timing generator block serial interface strobe input.
Schmitt trigger input.
N2 HD
N3 VSS6
N4 V4
I/O Horizontal sync signal input/output.
—
O
O
O
O
Timing generator block digital GND.
CCD vertical register clock output.
CCD vertical register clock output.
CCD vertical register clock output.
CCD electronic shutter pulse output.
N5 V1B
N6 V3B
N7 SUB
Control input used to switch sync system.
High: CKI sync, Low: MCKO sync
N8 SNCSL
N9 ID/EXP
I
(With pull-down resistor)
Vertical direction line identification pulse output/exposure time identification pulse
output.
O
Switching possible using the serial interface data. (Default: ID)
– 6 –
CXD3412GA
Electrical Characteristics
Timing Generator Block Electrical Characteristics
DC Characteristics
(Within the recommended operating conditions)
Item
Pins
Symbol
VDDa
VDDb
VDDc
VDDd
VI+
Conditions
Min.
3.0
Typ.
3.3
3.3
3.3
3.3
Max.
3.6
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage 1 VDD2
Supply voltage 2 VDD3
Supply voltage 3 VDD4
Supply voltage 4 VDD1, VDD5
3.0
5.25
3.6
3.0
3.0
3.6
0.8VDDd
Input
RST, SSI1,
SCK1, SEN1
1
2
voltage 1
VI–
0.2VDDd
0.3VDDd
0.2VDDd
0.4
VIH1
0.7VDDd
0.8VDDd
Input
TEST1, TEST2,
SNCSL, SSGSL
voltage 2
VIL1
VIH2
VIL2
Input/output
voltage
VD, HD
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
Feed current where IOH = –1.2mA
VDDd – 0.8
Pull-in current where IOL = 2.4mA
Feed current where IOH = –22.0mA VDDb – 0.8
Output
voltage 1
H1, H2
RG
Pull-in current where IOL = 14.4mA
0.4
Feed current where IOH = –3.3mA
V
DDa – 0.8
DDc – 0.8
Output
voltage 2
Pull-in current where IOL = 2.4mA
0.4
XSHP, XSHD,
XRS, PBLK,
CLPOB,
CLPDM,
ADCLK
VOH4
VOL4
Feed current where IOH = –3.3mA
V
V
V
Output
voltage 3
Pull-in current where IOL = 2.4mA
0.4
VOH5
VOL5
VOH6
VOL6
VOH7
VOL7
IOL
Feed current where IOH = –6.9mA
Pull-in current where IOL = 4.8mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –2.4mA
Pull-in current where IOL = 4.8mA
V1A/B, V2, V3A/B, V4 = –8.25V
V1A/B, V2, V3A/B, V4 = –0.25V
V1A/B, V3A/B = 0.25V
V
V
V
DDd – 0.8
DDd – 0.8
DDd – 0.8
10.0
V
V
Output
voltage 4
CKO
0.4
0.4
V
Output
voltage 5
MCKO
V
V
Output
voltage 6
ID/EXP,
WEN
0.4
V
mA
mA
mA
mA
mA
mA
V1A, V1B,
V3A, V3B,
V2, V4
IOM1
IOM2
IOH
–5.0
–7.2
–4.0
Output
current 1
5.0
V1A/B, V3A/B = 14.75V
IOSL
IOSH
SUB = –8.25V
5.4
Output
current 2
SUB
SUB = 14.75V
1
This input pin is a schmitt trigger input and it has protective diode of the power supply side in the IC.
It is not supported to 5V input.
2
These input pins are with pull-down resistor in the IC.
Note) This table indicates the conditions for 3.3V drive.
– 7 –
CXD3412GA
Inverter I/O Characteristics for Oscillation
Item Pins Symbol Conditions
(Within the recommended operating conditions)
Min.
Typ.
Max.
Unit
V
Logical Vth OSCI
LVth
VIH
VDDd/2
0.7VDDd
V
Input
OSCI
voltage
VIL
0.3VDDd
V
VOH
VOL
Feed current where IOH = –3.6mA VDDd – 0.8
V
Output
OSCO
voltage
Pull-in current where IOL = 2.4mA
0.4
5M
V
Feedback
resistor
OSCI,
OSCO
RFB
f
VIN = VDDd or VSS
500k
20
2M
Ω
Oscillation
frequency
OSCI,
OSCO
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins Symbol
Conditions
Min.
Typ.
Max.
Unit
V
Logical Vth
LVth
VDDd/2
VIH
0.7VDDd
V
Input
voltage
CKI
VIL
VIN
0.3VDDd
V
Input
amplitude
fmax 50MHz sine wave
0.3
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source.
Input amplitude is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item Symbol
(VH = 15.0V, VM = GND, VL = –7.5V)
Conditions
Min.
200
200
30
Typ.
350
350
60
Max.
500
500
90
Unit
ns
ns
ns
ns
ns
ns
V
TTLM VL to VM
TTMH VM to VH
Rise time
TTLH
VL to VH
TTML VM to VL
TTHM VH to VM
200
200
30
350
350
60
500
500
90
Fall time
TTHL
VCLH
VCLL
VCMH
VCML
VH to VL
1.0
1.0
1.0
1.0
V
Output noise voltage
V
V
Notes)
1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
– 8 –
CXD3412GA
Switching Waveforms
TTMH
90%
TTHM
90%
VH
VM
V1A (V1B, V3A, V3B)
TTLM
10%
90%
TTML
10%
90%
10%
10%
VL
TTLM
TTML
VM
90%
90%
V2 (V4)
10%
10%
VL
TTLH
TTHL
VH
90%
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
– 9 –
Serial interface data
Measurement Circuit
CKI
VD
HD
+3.3V
+15.0V
–7.5V
C6
C4
C5 C5
C6
C6
N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7
M4 V2
CLPDMI G3
M5 VH
M6 VL
CLPOBI G2
ADCLK H1
XSHPI F9
XSHDI F8
PBLKI F7
DVDD2 F3
DVSS3 F2
ADCLKI G1
AVDD1 E9
AVSS1 D9
AVSS2 E7
DVSS2 F1
DVSS1 E3
DVDD1 E2
E1 D9
L8 SSGSL
L9
VDD1
R1
M1 SCK1
M2 VD
C2
C1
C2
C1
M3 TEST1
N4 V4
R1
R1
C2
C1
C2
C2
C2
N5 V1B
N6 V3B
M7 TEST2
M8 RST
M9 WEN
C2
C2
C2
CXD3412GA
C2
C2
C1
C2
C2
C1
C1
R1
R1
N1
N2
L4
L5
L6
N7
L7
N8
N9
E8
D8
D7
D3
D2
D1
C9
C8
C7
SEN1
HD
AVDD2
C2
C2
R2
C2
VM
C1
R1
V1A
V3A
SUB
D6
D7
D8
VSS1
CCDIN
C4
C3
SNCSL
ID/EXP
C3
A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6
C1: 3300pF
C2: 560pF
C3: 820pF
C4: 8pF
C5: 215pF
C6: 10pF
R1: 30Ω
R2: 10Ω
CXD3412GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDD
d
SSI1
0.2VDD
d
0.8VDD
0.2VDD
ts1
d
SCK1
SEN1
SEN1
d
th1
ts2
0.2VDD
d
ts3
0.8VDD
d
(Within the recommended operating conditions)
Symbol
ts1
Definition
Min.
20
Typ.
Max.
Unit
ns
SSI1 setup time, activated by the rising edge of SCK1
SSI1 hold time, activated by the rising edge of SCK1
SCK1 setup time, activated by the rising edge of SEN1
SEN1 setup time, activated by the rising edge of SCK1
th1
ts2
ts3
20
ns
20
ns
20
ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode
VD
HD
V1A
Enlarged view
HD
0.2VDD
d
V1A
ts1
th1
0.8VDD
d
SEN1
0.2VDD
d
Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal
period during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
0
Typ.
Max.
Unit
ns
SEN1 setup time, activated by the falling edge of HD
SEN1 hold time, activated by the falling edge of HD
µs
113
– 11 –
CXD3412GA
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VD
HD
Enlarged view
VD
HD
0.2VDD
d
ts1
th1
0.8VDD
d
SEN1
0.2VDD
d
Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
0
Typ.
Max.
Unit
ns
SEN1 setup time, activated by the falling edge of VD
SEN1 hold time, activated by the falling edge of VD
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3412GA at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3412GA and controlled at the rising edge of SEN1. See "Description of Operation".
0.8VDDd
SEN1
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
15
Typ.
Max.
100
Unit
ns
Output signal delay, activated by the rising edge of SEN1
tpdPULSE
– 12 –
CXD3412GA
RST loading characteristics
RST
0.2VDD
d
0.2VDD
d
tw1
(Within the recommended operating conditions)
Symbol
Definition
Min.
28
Typ.
Max.
Unit
ns
tw1
RST pulse width
VD and HD phase characteristics
VD
HD
0.2VDD
d
0.2VDD
d
ts1
th1
0.2VDD
d
(Within the recommended operating conditions)
Symbol
Definition
Min.
0
Typ.
Max.
Unit
ns
ts1
th1
VD setup time, activated by the falling edge of HD
VD hold time, activated by the falling edge of HD
0
ns
HD loading characteristics
HD
0.2VDD
d
0.2VDD
d
ts1
th1
0.8VDD
d
MCKO
MCKO load capacitance = 10pF
Symbol
(Within the recommended operating conditions)
Definition
Min.
20
0
Typ.
Max.
Unit
ns
ts1
th1
HD setup time, activated by the rising edge of MCKO
HD hold time, activated by the rising edge of MCKO
ns
– 13 –
CXD3412GA
Output variation characteristics
0.8VDDd
MCKO
WEN, ID/EXP
tpd1
WEN and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
25
Typ.
Max.
70
Unit
ns
Time until the above outputs change after the rise of MCKO
– 14 –
CXD3412GA
CCD Signal Processor Block Electrical Characteristics
DC Characteristics
(Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Item
Pins
Symbol
VDDe
Conditions
Min.
3.0
Typ. Max. Unit
Supply voltage 1 DVDD1
Supply voltage 2 DVDD2
3.3 3.6
3.3 3.6
V
V
VDDf
3.0
AVDD1,
AVDD2,
Supply voltage 3 AVDD3,
AVDD4,
VDDg
3.0
3.3 3.6
V
AVDD5
Analog input
CCDIN
CIN
15
pF
V
capacitance
SCK2, SSI2,
VI+
1.8
SEN2, TEST3,
TEST4, XSHDI,
XSHPI, ADCLKI, VI–
CLPOBI,
Input voltage
1.1
V
CLPDMI, PBLKI
A/D clock duty ADCLKI
50
%
V
VOH
VOL
Feed current where IOH = –2.0mA VDDe – 0.9
Output voltage D0 to D9
Pull-in current where IOL = 2.0mA
0.4
V
Analog Characteristics
(Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Item
Symbol
Conditions
Min. Typ. Max. Unit
CCDIN input voltage amplitude
PGA maximum gain
VIN
PGA gain = 0dB, output full scale
PGA gain setting data = "3FFh"
PGA gain setting data = "000h"
900
1100 mV
dB
Gmax
Gmin
42
–6
10
PGA minimum gain
dB
ADC resolution
bit
ADC maximum conversion rate
ADC integral non-linearity error
Fc max
EL
22.5
MHz
LSB
LSB
PGA gain = 0dB
PGA gain = 0dB
±1.0
±0.5
ADC differential non-linearity error ED
CCDIN input connected to GND
via a coupling capacitor
PGA gain = 0dB
Signal-to-noise ratio
SNR
77
dB
CCDIN input voltage clamp level
CLP
OB
1.5
32
V
CCD optical black signal clamp
level
OBLVL = "8h"
PGA gain = 0dB
LSB
– 15 –
CXD3412GA
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDD
SSI2
0.2VDD
0.8VDD
ts1
SCK2
th1
ts2
SEN2
SEN2
0.2VDD
ts3
0.8VDD
The setting values are reflected to the operation 6 ADCLKI clocks after the serial data is loaded at the rise
of SEN2.
(Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
tp1
Definition
Min.
100
30
Typ.
Max.
Unit
ns
SCK2 clock period
ts1
th1
ts2
ts3
SSI2 setup time, activated by the rise of SCK2
SSI2 hold time, activated by the rise of SCK2
SCK2 setup time, activated by the rise of SEN2
SEN2 setup time, activated by the rise of SCK2
ns
30
ns
30
ns
30
ns
– 16 –
CXD3412GA
CDS/ADC Timing Chart
N
N + 1
N + 2
N + 3
CCDIN
XSHPI
XSHDI
tw1
ADCLKI
D0 to D9
DL
N – 10
N – 9
N – 8
N – 7
Set the input pulse polarity setting data D13, D14 and D15 of the serial interface data to "0".
(Fc = 22.5MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)
Symbol
tw1
Definition
Min.
44
Typ.
Max.
Unit
ns
ADCLKI clock period
ADCLKI clock duty
Data latency
50
9
%
DL
clocks
Preblanking Timing Chart
PBLKI
11 Clocks
ADCLKI
D0 to D9
11 Clocks
All "0"
– 17 –
CXD3412GA
Description of Operation
Pulses output from the CXD3412GA's timing generator block are controlled mainly by the RST pin and by the
serial interface data. The Pin Status Table is shown below, and the details of serial interface control are
described on page 20 and thereafter.
Pin Status Table
Pin
No.
Pin
No.
Symbol
NC
CAM
SLP
STB
RST
Symbol
C2
CAM
SLP
STB
RST
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D8
D9
E1
E2
E3
E7
E8
E9
F1
F2
F3
F7
F8
F9
G1
G2
G3
G7
G8
G9
H1
H2
H3
H7
H8
H9
J1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NC
AVSS1
D9
SCK2
SSI2
TEST3
AVSS4
C8
DVDD1
DVSS1
AVSS2
AVDD2
AVDD1
DVSS2
DVSS3
DVDD2
PBLKI
XSHDI
XSHPI
ADCLKI
CLPOBI
CLPDMI
PBLK
XSHD
XSHP
ADCLK
CLPOB
CLPDM
XRS
AVSS6
AVDD5
D2
D1
D0
SEN2
TEST5
AVDD4
C7
AVDD3
AVSS3
D5
ACT
ACT
ACT
ACT
ACT
ACT
ACT
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
ACT
ACT
ACT
H
D4
D3
TEST4
AVSS5
C9
H
ACT
C3
VDD4
—
—
C4
VDD3
CCDIN
D8
CKI
ACT
ACT
ACT
ACT
ACT
L
ACT
ACT
J2
CKO
D7
J3
VSS5
—
—
D6
J7
VSS3
C1
J8
H1
ACT
L
L
ACT
– 18 –
CXD3412GA
Pin
No.
Pin
No.
Symbol
H2
CAM
SLP
STB
RST
Symbol
CAM
ACT
SLP
L
STB
RST
H
1
J9
K1
K2
K3
K7
K8
K9
L1
L2
L3
L4
L5
L6
L7
L8
L9
M1
ACT
ACT
ACT
L
L
ACT
L
ACT
ACT
ACT
M2
M3
M4
M5
M6
M7
M8
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
VD
L
OSCO
MCKO
VDD5
VDD2
RG
ACT
ACT
TEST1
V2
—
ACT
VM
VM
VM
—
—
VH
—
—
—
VL
ACT
L
L
ACT
TEST2
RST
WEN
SEN1
VSS2
—
ACT
ACT
ACT
ACT
ACT
L
ACT
L
L
L
OSCI
SSI1
VSS4
ACT
ACT
ACT
ACT
ACT
ACT
ACT
DIS
ACT
L
ACT
L
DIS
H
1
—
—
HD
VM
VSS6
—
V1A
ACT
ACT
VH
VH
VH
VH
VM
VL
V4
ACT
ACT
ACT
ACT
ACT
ACT
VM
VH
VH
VH
ACT
L
VM
VH
VH
VH
ACT
L
VL
VM
VL
VL
ACT
L
V3A
V1B
VSS1
—
—
V3B
SSGSL
VDD1
SCK1
ACT
ACT
ACT
ACT
DIS
SUB
SNCSL
ID/EXP
ACT
ACT
ACT
1
It is for output. For input, all items are "ACT".
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin M5), VM (Pin L3) and VL (Pin M6),
respectively, in the controlled status.
– 19 –
CXD3412GA
Timing Generator Block Serial Interface Control
The CXD3412GA's timing generator block basically loads and reflects the timing generator block serial
interface data sent in the following format in the readout portion at the falling edge of HD. Here, readout portion
specifies the horizontal period during which V1A/B and V3A/B, etc. take the ternary value.
Note that some items reflect the timing generator block serial interface data at the falling edge of VD or the
rising edge of SEN1.
00 01 02 03 04 05 06 07
41 42 43 44 45
46 47
SSI1
SCK1
SEN1
There are two categories of timing generator block serial interface data: CXD3412GA timing generator block
drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data").
The details of each data are described below.
– 20 –
CXD3412GA
Control Data
Data Symbol
D00
Sunction
Data = 0
Data = 1
RST
All
0
10000001 → Enabled
Other values → Disabled
to
CHIP
Chip enable
D07
D08,
D09
All
0
CTG
Category switching
See D08 to D09 CTG.
D10
to
D12
All
0
MODE
Drive mode switching
See D10 to D12 MODE.
1
D13 SMD
D14 HTSG
D15 PTSG
D16
Electronic shutter mode switching
OFF
OFF
ON
ON
0
0
1
HTSG control switching
Internal SSG function switching
NTSC equivalent
PAL equivalent
0
All
0
to
—
—
—
—
D31
2
D32 FGOB
D33 EXP
Wide CLPOB generation switching
ID/EXP output switching
OFF
ID
ON
0
0
EXP
D34,
PTOB
D35
All
0
CLPOB waveform pattern switching
ADCLK logic phase switching
Standby control
See D34 to D35 PTOB.
1
0
D36,
LDAD
D37
See D36 to D37 LDAD.
See D38 to D39 STB.
D38,
STB
D39
All
0
D40
to
D47
All
0
—
—
—
—
1
See D13 SMD.
2
See D32 FGOB.
– 21 –
CXD3412GA
Shutter Data
Data Symbol
D00
Function
Data = 0
Data = 1
RST
10000001 → Enabled
Other values → Disabled
All
0
to
D07
CHIP
CTG
SVD
Chip enable
D08,
D09
All
0
Category switching
See D08 to D09 CTG.
D10
to
Electronic shutter vertical period
specification
All
0
See D10 to D19 SVD.
See D20 to D31 SHD.
See D32 to D41 SPL.
—
D19
D20
to
D31
Electronic shutter horizontal period
specification
All
0
SHD
SPL
—
D32
to
D41
All
0
High-speed shutter position specification
D42
to
All
0
—
D47
– 22 –
CXD3412GA
Detailed Description of Each Data
Shared data: D08 , D09 CTG [Category]
Of the data provided to the CXD3412GA by the serial interface, the CXD3412GA loads D10 and subsequent
data to each data register as shown in the table below according to the conbination of D08 and D09 .
D09
0
D08
0
Description of operation
Loading to control data register
Loading to shutter data register
Test mode
0
1
1
X
Note that the CXD3412GA can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode]
The CXD3412GA timing generator block drive mode can be switched as follows. However, the drive mode bits
are loaded to the CXD3412GA and reflected at the falling edge of VD.
D12
0
D11
0
D10
0
Description of operation
Draft mode (sextuple speed: default)
Frame mode (A field read out)
Frame mode (B field read out)
Frame mode
0
0
1
0
1
0
0
1
1
1
0
X
AF1 mode
1
1
X
AF2 mode
Control data: D15 PTSG [Internal SSG output pattern]
The CXD3412GA internal SSG output pattern can be switched as follows. However, the internal SSG output
pattern bits are loaded to the CXD3412GA and reflected at the falling edge of VD.
D15
0
Description of operation
NTSC equivalent pattern output
PAL equivalent pattern output
1
VD period in each pattern is defined as follows. However, care should be taken that HD period is changing by
the mode.
Frame mode
Draft mode
AF1 mode
AF2 mode
NTSC equivalent pattern 885H + 810ck 285H + 1455ck × 2 142H + 1384ck + 1383ck 71H + 1384ck
PAL equivalent pattern
884H + 1104ck
342H + 2592ck
171H + 1296ck
85H + 1960ck
See the Timing Charts for the actual operation.
– 23 –
CXD3412GA
Control data: D32 FGOB [Wide CLPOB generation]
This controls wide CLPOB generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
0
Description of operation
Wide CLPOB generation OFF
Wide CLPOB generation ON
1
Control data: D34 , D35 PTOB [CLPOB waveform pattern]
This indicates the CLPOB waveform pattern. The default is "Normal".
D35
0
D34
0
Waveform pattern
(Normal)
0
1
(Shifted rearward)
(Shifted forward)
(Wide)
1
0
1
1
Control data: D36 , D37 LDAD [ADCLK logic phase]
This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.
D37
0
D36
0
Degree of adjustment (°)
0
0
1
90
1
0
180
270
1
1
Control data: D38 , D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3412GA and
control is applied immediately at the rising edge of SEN1.
D39
X
D38 Symbol
Operating mode
0
1
1
CAM Normal operating mode
0
SLP
STB
Sleep mode
1
Standby mode
See the Pin Status Table for the pin status in each mode.
– 24 –
CXD3412GA
Control data/shutter data: [Electronic shutter]
The CXD3412GA realizes various electronic shutter functions by using control data D13 SMD and D14
HTSG and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below. These modes are switched using control data D13 SMD.
D13
0
Description of operation
Electronic shutter stopped mode
Electronic shutter mode
1
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.
MSB
LSB
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20
X
0
0
1
1
1
0
0
0
0
1
1
↓
↓
↓
1
C
3
SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[Electronic shutter mode]
During this mode, the shutter data items have the following meanings.
Symbol
SVD
Data
Description
Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)
Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)
Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
D10 to D19
D20 to D31
D32 to D41
SHD
SPL
Note) The bit data definition area is assured in terms of the CXD3412GA functions, and does not assure the
CCD characteristics.
The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)}
Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
– 25 –
CXD3412GA
VD
SHD
SVD
V1A
SUB
WEN
EXP
SMD
SVD
SHD
1
1
002h
10Fh
000h
050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL
000
001
002
VD
SVD
SHD
V1A
SUB
WEN
EXP
SMD
SPL
SVD
SHD
1
1
001h
002h
10Fh
000h
000h
0A3h
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD. At this time,
performing SPL > SVD setting applies to the state of SPL = SVD correspondingly.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice-versa.
– 26 –
CXD3412GA
[HTSG control mode]
This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG.
When control starts, V pulse modulation during readout period is not generated and the normal V transfer is
performed.
D14
0
Description of operation
Readout pulse (SG) normal operation
HTSG control mode
1
VD
V1A
SUB
VCK
WEN
EXP
HTSG
SMD
0
1
1
0
0
1
Exposure time
[EXP pulse]
The ID/EXP (Pin 9) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The
default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time
when it is high. In the draft mode, the transition point is the last SUB pulse falling edge, and midpoint value
(1443ck) of each V1A/B and V3A/B ternary output falling edge. When there is no SUB pulse, the later ternary
output falling edge (1538ck) is used. In the frame mode, the transition point is the last SUB pulse falling edge,
and each V1A/B and V3A/B ternary output falling edge (1348ck). When there is no SUB pulse, the V pulse
modulation falling edge just after ternary output (1386ck) is used. In addition, switching from ID to EXP is
performed at the timing (ID transition point of the horizontal period where V1A/B and V3A/B ternary output)
and reset to low.
See the EXP pulse indicated in the explanatory diagrams under Electronic Shutter for an image of operation.
– 27 –
Applicable CCD image sensor
MODE
Chart-1 Vertical Direction Timing Chart
• ICX412
Frame mode
A Field
B Field
VD
877
886
1
877
886 1
95
101
96
101
HD
SUB
C
High-speed sweep block
A
C
High-speed sweep block
B
V1A
V1B
V2
V3A
V3B
V4
1
3
5
7
1
3
5
7
9 11
2 4 6 8 2
4 6 8 10
CCD OUT
PBLK
CLPOB
Wide CLPOB
CLPDM
ID/EXP
WEN
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
1560 stages are fixed for high-speed sweep block.
VD of this chart is NTSC equivalent pattern (885H + 810ck units). For PAL equivalent pattern, it is 884H + 1104ck units.
Applicable CCD image sensor
MODE
Chart-2 Vertical Direction Timing Chart
• ICX412
Draft mode
VD
260
287 1
2
260
287 1 2
HD
SUB
D
D
V1A
V1B
V2
V3A
V3B
V4
6
4
6
4
3 10 15 22 27 30
8 13 20 25 28
3
1
10 15 22 27 30
13 20 25 28
CCD OUT
PBLK
1
8
CLPOB
Wide CLPOB
CLPDM
ID/EXP
WEN
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
VD of this chart is NTSC equivalent pattern (285H + 1455ck + 1455ck units). For PAL equivalent pattern, it is 342H + 2592ck units.
Applicable CCD image sensor
MODE
Chart-3 Vertical Direction Timing Chart
• ICX412
AF1 mode
VD
131
144
2
131
144
2
14
14
HD
SUB
High-speed
sweep block
High-speed
sweep block
E
D
E
E
D
E
Frame shift block
Frame shift block
V1A
V1B
V2
V3A
V3B
V4
6
4
6
4
CCD OUT
PBLK
CLPOB
Wide CLPOB
CLPDM
ID/EXP
WEN
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
75 stages are fixed for high-speed sweep block; 68 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (142H + 1384ck + 1383ck units). For PAL equivalent pattern, it is 171H + 1296ck units.
High-speed sweep block starts from 159H.
Applicable CCD image sensor
MODE
Chart-4 Vertical Direction Timing Chart
• ICX412
AF2 mode
VD
54
72
2
54
72
2
21
21
HD
SUB
High-speed
sweep block
High-speed
sweep block
E
D
E
Frame shift block
E
D
E
Frame shift block
V1A
V1B
V2
V3A
V3B
V4
6
6
4
4
CCD OUT
PBLK
CLPOB
Wide CLPOB
CLPDM
ID/EXP
WEN
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
116 stages are fixed for high-speed sweep block; 110 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (71H + 1384ck units). For PAL equivalent pattern, it is 85H + 1960ck units.
High-speed sweep block starts from 68H. However, in this case, NTSC equivalent pattern frame rate is 0.5ck longer than 1/120s.
Applicable CCD image sensor
MODE
Chart-5 Horizontal Direction Timing Chart
• ICX412
Frame mode
(2544)
0
50
100
150
200
250
300
350
400
450
500
550
HD
MCKO
H1
4
52
428
456/460/464
H2
162
276
V1A/B
238
352
V2
124
314
V3A/B
200
390
V4
52
52
120
SUB
454
PBLK
16
42
CLPOB (1)
CLPOB (2)
8
8
34
24
50
CLPOB (3)
50
50
CLPOB (4)
458
454
CLPOB (wide)
430
CLPDM
ID/EXP
WEN
124
124
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1.
CLPOB (wide) is output at the timing shown above at the position shown in Chart-1.
Applicable CCD image sensor
MODE
Chart-6 Horizontal Direction Timing Chart
• ICX412
Draft mode, AF1 mode, AF2 mode
(2624)
0
50
100
150
200
250
300
350
400
450
500
550
HD
MCKO
H1
4
52
508
536/540/544
H2
140
188
268
316
396
444
V1A/B
172
220
300
348
428
476
V2
124
204
252
332
380
460
V3A/B
156
236
284
364
412
492
V4
52
52
120
SUB
534
PBLK
16
42
CLPOB (1)
CLPOB (2)
8
8
34
24
50
CLPOB (3)
50
50
CLPOB (4)
538
534
CLPOB (wide)
510
CLPDM
ID/EXP
WEN
124
124
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
CLPOB (wide) is output at the timing shown above at the position shown in Chart-2, 3 and 4.
Applicable CCD image sensor
MODE
Chart-7 Horizontal Direction Timing Chart
(High-speed sweep: C)
• ICX412
Frame mode
(2544)
0
50
100
150
200
250
300
350
400
450
500
550
HD
MCKO
H1
4
52
428
456/460/464
H2
52
52
128
128
204
280
356
432
508
V1A/B
90
90
166
166
242
242
318
318
394
470
470
546
V2
204
280
356
432
508
V3A/B
394
546
V4
#1
#2
#3
#4
52
120
SUB
PBLK
CLPOB
CLPDM
ID/EXP
WEN
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID.
High-speed sweep of V1A/B, V2, V3A/B and V4 is performed up to 93H 580ck (#1560).
Applicable CCD image sensor
MODE
Chart-8 Horizontal Direction Timing Chart
(Frame shift, High-speed sweep: E)
• ICX412
AF1 mode, AF2 mode
(2624)
0
50
100
150
200
250
300
350
400
450
500
550
HD
MCKO
H1
4
52
508
536/540/544
H2
68
116
196
244
324
372
452
500
V1A/B
100
148
228
276
356
404
484
532
V2
52
132
180
260
308
388
436
516
V3A/B
84
164
242
292
340
420
468
548
V4
#1
#2
52
52
120
SUB
PBLK
16
42
CLPOB
CLPDM
ID/EXP
WEN
124
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. PBLK, CLPOB, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-3 and 4.
Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 11H 2548ck (#68) in AF1 mode and 18H 308ck (#110) in AF2 mode.
In addition, high-speed sweep is performed up to 141H 2612ck (#75) in AF1 mode and 70H 2612ck (#116) in AF2 mode.
Applicable CCD image sensor
MODE
Chart-9 Horizontal Direction Timing Chart
• ICX412
Frame mode
(2544)
0
(2544)
0
HD
[A Field]
V1A
[A]
V1B
V2
V3A
V3B
V4
[B Field]
V1A
[B]
V1B
V2
V3A
V3B
V4
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
Applicable CCD image sensor
MODE
Chart-10 Horizontal Direction Timing Chart
• ICX412
Draft mode, AF1 mode, AF2 mode
(2624)
0
(2544)
0
HD
[D]
V1A
V1B
V2
V3A
V3B
V4
The HD of this chart indicates the actual CXD3412GA load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 2.3 to 19.0µs (when the drive frequency is 22.5MHz).
This chart shows a period of 124ck (5.5µs). Internal SSG is at this timing.
Applicable CCD image sensor
MODE
Chart-11 High-Speed Phase Timing Chart
• ICX412
HD
HD'
CKI
CKO
ADCLK
1
428/508
52
MCKO
H1
H2
RG
XSHP
XSHD
XRS
HD' indicates the HD which is the actual CXD3412GA load timing.
The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
The logical phase of ADCLK can be specified by the serial interface data.
Applicable CCD image sensor
MODE
Chart-12 Vertical Direction Sequence Chart
• ICX412
Draft → Frame → Draft
VD
V1A
V1B
V2
V3A
V3B
V4
SUB
Mechanical
shutter
Close
Open
Exposure
time
A
B
C
D
E
F
A
0
B
0
C
0
E
3
E
CCD OUT
F
MODE
SMD
0
1
0
1
3
0
1
0
1
1
1
1
0
0
SHD
050h
050h
050h
050h
050h
000h
000h
050h
050h
This chart is a drive timing chart example of electronic shutter normal operation.
Data exposed at D includes a blooming component. For details, see the CCD image sensor data sheet.
The CXD3412GA does not generate the pulse to control mechanical shutter operation.
The switching timing of drive mode and electronic shutter data is not the same.
CXD3412GA
CCD Signal Processor Block Serial Interface Control
The CXD3412GA's CCD signal processor block basically loads the CCD signal processor block serial interface
data sent in the following format at the rising edge of SEN2, and the setting values are then reflected to the
operation 6 ADCLKI clocks after that.
CCD signal processor block serial interface control requires clock input to ADCLKI in order to load and reflect
the serial interface data to operation, so this should normally be performed when the timing generator block is
in the normal operation mode.
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
SSI2
SCK2
SEN2
There are four categories of CCD signal processor block serial interface data: standby control data, PGA gain
setting data, OB clamp level setting data, and input pulse polarity setting data.
Note that when data from multiple categories is loaded consecutively, the data for the category loaded last is
valid and data from other categories is lost. When transferring data from multiple categories, raise SEN2 for
each category and wait until the setting value 6 ADCKLI clocks after that has been reflected to operation, then
transmit the next category.
The detail of each data are described below.
Standby Control Data
Data
Symbol
Function
Data = 0
Data = 1
D00 TEST
Test code
Set to 0.
D01
to
D03
CTG
Category switching
D01 to D03 CTG
Set to All 0.
D04
to
FIXED
—
D14
D15 STB
Standby control
Normal operation mode
Standby mode
PGA Gain Setting Data
Data
Symbol
Function
Data = 0
Data = 1
D00 TEST
D01
Test code
Set to 0.
to
D03
CTG
Category switching
—
D01 to D03 CTG
Set to All 0.
D04,
D05
FIXED
GAIN
D06
to
PGA gain setting data
See D06 to D15 GAIN.
D15
– 40 –
CXD3412GA
OB Clamp Level Setting Data
Data Symbol
Function
Data = 0
Data = 1
D00 TEST
D01
Test code
Set to 0.
to
D03
CTG
Category switching
D01 to D03 CTG
Set to All 0.
D04
to
D11
—
FIXED
OBLVL
D12
to
OB clamp level setting data
See D12 to D15 OBLVL.
D15
Input Pulse Polarity Setting Data
Data Symbol
Function
Data = 0
Data = 1
D00 TEST
Test code
Set to 0.
D01
to
CTG
Category switching
D01 to D03 CTG
D03
D04
to
D12
—
FIXED
POL
Set to All 0.
Set to All 0.
D13
to
Input pulse polarity setting data
D15
– 41 –
CXD3412GA
Detailed Description of Each Data
Shared data: D01 to D03 CTG [Category]
Of the data provided to the CXD3412GA by the CCD signal processor block serial interface, the CXD3412GA
loads D04 and subsequent data to each data register as shown in the table below according to the
combination of D01 to D03 .
D01
0
D02
0
D03
0
Description of operation
Loading to standby control data register
Loading to PGA gain setting data register
Loading to OB clamp level setting data register
Loading to input pulse polarity setting data register
Access prohibited
0
0
1
0
1
0
0
1
1
1
X
X
Standby control data: D15 STB [Standby]
The operating mode of the CCD signal processor block is switched as follows. When the CCD signal processor
block is in standby mode, only the serial interface is valid.
D00
0
Description of operation
Normal operating mode
Standby mode
1
PGA gain setting data: D06 to D15 GAIN [PGA gain]
The CXD3412GA can set the programmable gain amplifier (PGA) gain from –6dB to +42dB in 1024 steps by
using PGA gain setting data D06 to D15 GAIN.
The PGA gain setting data is expressed as shown in the table below using D06 to D15 GAIN.
MSB
LSB
D06 D07 D08 D09 D10 D11 D12 D13 D14 D15
0
1
1
1
0
0
0
0
1
1
↓
↓
↓
GAIN is expressed as 1C3h .
1
C
3
For example, when GAIN is set to "000h", "080h", "220h", "348h" and "3FFh", the respective PGA gain setting
values are –6dB, 0dB, +20dB, +34dB and +42dB.
– 42 –
CXD3412GA
OB clamp level setting data: D12 to D15 OBLVL [OB clamp output]
The CXD3412GA can set the OPB clamp output value from 0 to 60LSB in 4LSB steps by using CCD signal
processor block control data D12 to D15 OBLVL.
The OPB clamp output setting data is expressed as shown in the table below using D12 to D15 OBLVL.
LSB
D12 D13 D14 D15
MSB
0
1
1
0
↓
OBLVL is expressed as 6h .
6
For example, when OBLVL is set to "0h", "1h", "8h" and "Fh", the respective OPB clamp output setting values
are 0LSB, 4LSB, 32LSB and 60LSB.
– 43 –
Application Circuit Block Diagram
F9 F8 F7 G3 G2
G9 G8 G7 H3 H2 H1
G1
B7
A7
C6
CCDOUT
CCDIN
C1
CCD
ICX412
C9
D7
D8
C7
C8
NC
A2
A1
B3
B2
B1
C3
C2
C1
D3
D2
D1
E1
J2
1µF
1µF
NC
D0 (LSB)
D1
C2
390pF
390pF
240pF
D2
C3
D3
C4
D4
D5
D6
D7
D8
Signal
Processor
Block
H1
H2
TG/CDS/PGA/ADC
CXD3412GA
D9 (MSB)
CKO
MCKO
J8
J9
RG
V1A
V1B
V2
K2
K8
L5
VD
HD
M2
N2
N5
M4
L5
ID/EXP
WEN
V3A
V3B
V4
N9
M9
N6
N4
N7
M8
N8
L8
RST
SUB
SNCSL
SSGSL
J1
K1
L1
M3 M7 A5 C4 B5
L2 N1 M1 A4 B4 A3
This block diagram illustrates connections with each circuit
block, and is not an actual circuit diagram. See the CCD
image sensor data sheet for an example of specific circuit
connections with the CCD image sensor.
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXD3412GA
Notes on Operation
1. Be sure to start up the timing generator block VL and VH pin power supplies at the timing shown in the
figure below in order to prevent the SUB pin of the CCD image sensor from going to negative potential. In
addition, start up the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pin and CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin power supplies at the same time either
before or at the same time as the VH pin power supply is started up.
15.0V
t1
20%
0V
20%
t2
–7.5V
t2 ≥ t1
2. Reset the timing generator block and CCD signal processor block during power-on. The timing generator
block is reset by inputting the reset signal to the RST pin. The CCD signal processor block is reset by
initializing the serial data.
3. Separate the timing generator block VDD1, VDD2, VDD3, VDD4 and VDD5 pins from the CCD signal processor
block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4, and AVDD5 pins.
Also, the ADC output driver stage is connected to the dedicated power supply pin DVDD1. Separating this pin
from other power supplies is recommended to avoid affecting the internal analog circuits.
4. The difference in potential between the timing generator block VDD4 pin supply voltage 3 VDDc and the CCD
signal processor block DVDD1, DVDD2, AVDD1, AVDD2, AVDD3, AVDD4 and AVDD5 pin supply voltages 1 VDDe, 2
VDDf and 3 VDDg should be 0.1V or less.
5. The timing generator block and CCD signal processor block ground pins should use a shared ground which
is connected outside the IC. When the set ground is divided into digital and analog blocks, connect the
timing generator block ground pins to the digital ground and the CCD signal processor block ground pins to
the analog ground. The difference in potential between the timing generator block VSS1, VSS2, VSS3, VSS4,
VSS5, VSS6 and VM and the CCD signal processor block DVSS1, DVSS2, DVSS3, AVSS1, AVSS2, AVSS3, AVSS4,
AVSS5 and AVSS6 should be 0.1V or less.
6. Do not perform serial communication with the CCD signal processor block during the effective image
period, as this may cause the picture quality to deteriorate. In addition, using SCK2, SSI2 and SEN2, which
are used by the CCD signal processor block, use of the dedicated ports is recommended. When using
these pins as shared ports with the timing generator block or other ICs, be sure to thoroughly confirm the
effects on picture quality before use.
– 45 –
CXD3412GA
Package Outline
Unit: mm
0.2
S
A
96PIN LFLGA
8.0
X
PIN 1 INDEX
1.3 MAX
0.10MAX
x4
0.15
DETAIL X
96 -φ0.45 ± 0.05
(0.3)
0.5
0.8
A
M
S A B
φ0.08
N
M
L
K
J
B
H
G
F
E
D
C
B
3 – φ0.50
A
1 2
0.5
3
4 5
6
7
0.8
8 9
PACKAGE STRUCTURE
0.5
(0.3)
PACKAGE MATERIAL
TERMINAL TREATMENT
TERMINAL MATERIAL
PACKAGE MASS
ORGANIC SUBSTRATE
NICKEL & GOLD PLATING
COPPER
LFLGA-96P-02
SONY CODE
EIAJ CODE
P-LFLGA96-12X8-0.8
JEDEC CODE
0.3g
Sony Corporation
– 46 –
相关型号：
ICX412AQ
Diagonal 8.933mm(Type 1/1.8) Frame Readout CCDImage Sensor with a Square Pixel for Color Cameras
ETC
ICX412AQF
Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras
SONY
ICX413AQ
Diagonal 28.40mm (Type 1.8) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
SONY
ICX414AL
Diagonal 8mm Progressive Scan CCD Solid-state Image Sensor with Square Pixel for EIA B/W Cameras
SONY
ICX414AQ
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
SONY
ICX415AL
Diagonal 8mm (Type 1/2) Progressive Scan CCD Solid-state Image Sensor with Square Pixel for CCIR B/W Cameras
SONY
ICX415AQ
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
SONY
©2020 ICPDF网 联系我们和版权申明