CXA3246Q [SONY]
8-bit 120MSPS Flash A/D Converter; 8位120MSPS的Flash A / D转换器
| 型号： | CXA3246Q |
| 厂家： | 
SONY CORPORATION |
| 描述： | 8-bit 120MSPS Flash A/D Converter |
| 文件： | 总22页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA3246Q
8-bit 120MSPS Flash A/D Converter
Description
48 pin QFP (Plastic)
The CXA3246Q is an 8-bit high-speed flash A/D
converter capable of digitizing analog signals at the
maximum rate of 120MSPS. ECL, PECL or TTL can
be selected as the digital input level in accordance
with the application. The TTL digital output level
allows 1:2 demultiplexed output.
Features
• Differential linearity error: ±0.5LSB or less
• Integral linearity error: ±0.5LSB or less
• High-speed operation with a maximum conversion
rate of 120MSPS
LEAD TREATMENT: PALLADIUM PLATING
Structure
Bipolar silicon monolithic IC
• Low input capacitance: 10pF
• Wide analog input bandwidth: 250MHz
• Low power consumption: 500mW
• 1:2 demultiplexed output
• 1/2 frequency-divided clock output
(with reset function)
Applications
• Magnetic recording (PRML)
• Communications (QPSK, QAM)
• LCDs
• Digital oscilloscopes
• Compatible with ECL, PECL and TTL digital input
levels
• TTL output "H" levels: 2.8V (Typ.)
• +3.3V line CMOS IC direct connecting available
• Single +5V power supply operation available
• Surface mounting package (48-pin QFP)
Pin Configuration (Top View)
12 11 10
9
8
7
6
5
4
3
2
1
CLK/E
CLKN/E
CLK/T
N.C.
13
14
15
16
17
18
19
20
21
22
23
24
RESETN/E
RESET/E
48
47
46
45
44
43
42
41
40
39
38
37
RESETN/T
SELECT
INV
N.C.
CLKOUT
DVCC2
DGND2
PBD7
N.C.
DVCC2
DGND2
PAD0
PAD1
PBD6
PBD5
PAD2
PAD3
PBD4
35
29
30
25 26 27
28
31
32 33
34
36
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E97902A8X-PS
CXA3246Q
Absolute Maximum Ratings (Ta = 25°C)
Unit
V
V
• Supply voltage
AVCC, DVCC1, DVCC2
DGND3
–0.5 to +7.0
–0.5 to +7.0
DVEE3
–7.0 to +0.5
V
DGND3 – DVEE3
VIN
VRT
–0.5 to +7.0
VRT – 2.7 to AVCC
2.7 to AVCC
V
V
V
• Analog input voltage
• Reference input voltage
VRB
VIN – 2.7 to AVCC
2.5
DVEE3 – 0.5 to DGND3 + 0.5
DGND1 – 0.5 to DVCC1 + 0.5
2.7
V
V
V
V
V
°C
W
|VRT – VRB|
ECL/PECL input pin
TTL input pin
VID 1 (|
Tstg
• Digital input voltage
• Storage temperature
/E –
N/E|)
–65 to +150
• Allowable power dissipation PD
1.6
(when mounted on a two-layer glass fabric base epoxy board with dimentions of 50mm × 50mm, 1.6mm thick)
Recommended Operating Conditions
With a single power supply With dual power supply Unit
Min.
+4.75
Typ.
+5.0
0
+5.0
0
Max.
Min.
Typ.
+5.0
0
0
–5.0
Max.
+5.25
+0.05
+0.05
–4.75
VRT
+4.1
+2.6
2.1
• Supply voltage
DVCC1, DVCC2, AVCC
+5.25 +4.75
+0.05 –0.05
+5.25 –0.05
+0.05
VRT
+4.1
+2.6
2.1
V
V
V
V
V
V
V
V
V
V
V
V
V
DGND1, DGND2, AGND –0.05
DGND3
DVEE3
VIN
+4.75
–0.05
VRB
+2.9
+1.4
1.5
–5.5
VRB
+2.9
+1.4
1.5
• Analog input voltage
•
Reference input voltage VRT
VRB
|VRT – VRB|
• Digital input voltage
ECL/PECL input pin : VIH DVEE3 + 1.5
: VIL DVEE3 + 1.1
DGND3 DVEE3 + 1.5
VIH – 0.4 DVEE3 + 1.1
DGND3
VIH – 0.4
TTL input pin
: VIH
: VIL
2.0
2.0
0.8
0.4
100
120
0.8
VID 1 (|
Maximum conversion rate Fc (Straight mode)
(DMUX mode)
/E –
N/E|)
0.4
100
120
–20
0.8
0.8
•
MSPS
MSPS
• Ambient temperature Ta
+75
–20
+75
°C
1
VID: Input Voltage Differential
ECL and PECL switching level
DGND3
VIH (max.)
VIL
VTH (DGND3 – 1.2V)
VIH
VID
VIL (min.)
– 2 –
CXA3246Q
Pin Description
Typical voltage
level with a single
power supply
Typical voltage
level with dual
power supply
[Symbol]
[Pin No.] [Description]
DVEE3
VRB
1
Digital power supply
Bottom reference voltage
Analog ground
0V
1.4 to 2.6V
0V
–5.0V
1.4 to 2.6V
0V
2
AGND
VRM1
3
4
Reference voltage mid point
Analog power supply
Analog signal input
—
—
AVCC
VIN
5
+5V
+5V
VRB to VRT
—
6
VRB to VRT
—
VRM2
7
Reference voltage mid point
Analog power supply
Reference voltage mid point
Analog ground
AVCC
VRM3
8
+5V
+5V
—
9
—
AGND
VRT
10
11
12
13
14
15
0V
0V
Reference voltage (typ.)
Digital power supply
ECL/PECL clock input
ECL/PECL clock input
TTL clock input
2.9 to 4.1V
+5V
2.9 to 4.1V
0V
DGND3
CLK/E
CLKN/E
CLK/T
N.C.
PECL
PECL
TTL
ECL
ECL
TTL
—
16 to 18 No connected pin
—
DVCC2
DGND2
19
20
Digital power supply
Digital ground
+5V
+5V
0V
0V
PAD0 to PAD7 21 to 28 PA side data output
TTL
TTL
0V
DGND1
DVCC1
DVCC2
DGND2
29
30
31
32
Digital ground
0V
Digital power supply
Digital power supply
Digital ground
+5V
+5V
+5V
0V
+5V
0V
PBD0 to PBD7 33 to 40 PB side data output
TTL
TTL
0V
DGND2
DVCC2
41
42
43
44
45
46
47
48
Digital ground
0V
Digital power supply
Clock output
+5V
+5V
TTL
TTL
TTL
TTL
ECL
ECL
CLKOUT
INV
TTL
Data output polarity inversion
Output mode selection
TTL reset input
TTL
SELECT
RESETN/T
RESET/E
RESETN/E
TTL
TTL
ECL/PECL reset input
ECL/PECL reset input
PECL
PECL
– 3 –
CXA3246Q
Block Diagram
AVCC
DVCC2
INV
44
DVCC1
30
DGND3
12
5
8
19 31 42
VRT
11
r1
r/2
(MSB)
r
PBD7
PBD6
PBD5
PBD4
PBD3
PBD2
PBD1
PBD0
40
39
38
37
36
35
34
33
1
2
r
6bit
•
•
•
r
r
63
64
65
8bit
VRM3
9
r
6bit
•
•
•
r
r
126
(LSB)
127
VRM2
VIN
r
r
7
6
128
129
(MSB)
PAD7
28
6bit
•
•
•
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
r
r
27
26
25
24
23
22
21
191
VRM1
4
192
r
193
8bit
6bit
•
•
•
r
r
254
255
r2
r/2
VRB
2
(LSB)
N.C.
N.C.
16
17
18
CLK/T
CLK/E
15
13
14
N.C.
CLKN/E
D
Q
Select
CLKOUT
43
Q
RESETN/T
RESETN/E
RESET/E
46
48
47
3
10
45
29
32
20
41
1
SELECT DGND1
DVEE3
AGND
DGND2
– 4 –
CXA3246Q
Pin Description and I/O Pin Equivalent Circuit
Standard
voltage level
Pin
No.
Symbol
I/O
Equivalent circuit
Description
Analog ground.
3, 10 AGND
GND
Separated from the digital ground.
Analog power supply.
Separated from the digital power
supply.
+5V
(typ.)
5, 8
AVCC
20, 29 DGND1
32, 41 DGND2
GND
Digital ground.
19, 30 DVCC1
31, 42 DVCC2
+5V
(typ.)
Digital power supply.
+5V (typ.)
(With a
single
power
Digital power supply.
supply)
Ground for ECL input.
+5V for PECL and TTL inputs.
12
DGND3
GND
(With dual
power
supply)
GND
(With a
single
power
supply)
Digital power supply.
–5V for ECL input.
1
DVEE3
–5V (typ.)
(With dual
power
Ground for PECL and TTL inputs.
supply)
No connected pin.
Not connected with the internal
circuits.
16, 17
18
N.C.
– 5 –
CXA3246Q
Pin
No.
Standard
voltage level
Equivalent circuit
Description
I/O
I
Symbol
CLK/E
13
Clock input.
CLK/E complementary input.
When left open, this pin goes to the
threshold voltage.
14
I
I
CLKN/E
Only CLK/E can be used for
operation, but complementary inputs
are recommended to attain fast and
stable operation.
DGND3
ECL/
PECL
13
48
Reset signal input.
When set to low level, the built-in
CLK frequency divider circuit can be
reset.
48
14 47
RESETN/E
RESETN/E complementary input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
DVEE3
47
15
RESET/E
CLK/T
I
I
Clock input.
Reset signal input.
When left open, this pin goes to high
level. When set to low level, the
built-in CLK frequency divider circuit
can be reset.
TTL
TTL
DVCC1
46
RESETN/T
I
I
Data output polarity inversion input.
When left open, this input goes to
high level.
(See Table 1. I/O Correspondence
Table.)
15 46
or
,
44
45
INV
1.5V
45
44
DGND1
DVEE3
Vcc
or
GND
Data output mode selection.
(See Table 2. Operation Mode
Table.)
SELECT
– 6 –
CXA3246Q
Standard
voltage level
Pin
No.
Symbol
I/O
I
Equivalent circuit
Description
Top reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
4.0V
(typ.)
11
9
r1
VRT
11
r/2
r
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
VRB
+
Comparator 1
VRM3
r
r
3
4
(VRT – VRB)
Comparator 63
Comparator 64
Comparator 127
9
7
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
VRB
+
7
4
VRM2
2
4
r
r
(VRT – VRB)
Comparator 128
Comparator 191
Reference voltage mid point.
By-pass to AGND with a 0.1µF chip
capacitor.
VRB
+
4
Comparator 192
VRM1
1
4
(VRT – VRB)
r
Comparator 255
r/2
Bottom reference voltage.
By-pass to AGND with a 1µF tantal
capacitor and a 0.1µF chip capacitor.
2.0V
(typ.)
2
2
VRB
I
r2
Comparator
AVCC
AVCC
VRT
to
6
VIN
I
Analog input.
VRB
Vref
6
AGND
DVEE3
PAD0
to
PAD7
Port A side data output.
TTL output; the high level is
clamped to approximately 2.8V.
21
to
28
O
O
O
DVCC1
DVCC2
21 to
33
to
40
PBD0
to
PBD7
Port B side data output.
TTL output; the high level is
clamped to approximately 2.8V.
28
40
TTL
to
33
43
DGND2
DVEE3
DGND1
Clock output.
(See Table 2. Operation Mode Table.)
TTL output; the high level is
clamped to approximately 2.8V.
43
CLKOUT
– 7 –
CXA3246Q
Electrical Characteristics
(AVCC, DVCC1, 2, DGND3 = +5V, AGND, DGND1, 2, DVEE3 = 0V, VRT = 4V, VRB = 2V, Ta = 25°C)
Item
Symbol
Conditions
Min.
Typ.
8
Max.
Unit
bits
Resolution
DC characteristics
Integral linearity error
Differential linearity error
EIL
EDL
±0.5
±0.5
LSB
LSB
VIN = 2Vp-p, Fc = 5MSPS
VIN = +3.0V + 0.07Vrms
Analog input
Analog input capacitance
Analog input resistance
Analog input current
CIN
RIN
IIN
10
20
100
pF
kΩ
µA
7
0
40
285
Reference input
2
Reference resistance
Reference current
Offset voltage VRT side
VRB side
Rref
Iref
EOT
EOB
400
2.7
6
600
3.3
8
740
5.0
10
3
Ω
3
mA
mV
mV
0
1.5
Digital input (ECL, PECL)
Digital input voltage: High VIH
DVEE3 + 1.5
DVEE3 + 1.1
DGND3
VIH – 0.4
V
V
: Low
VIL
Threshold voltage
VTH
DGND3 – 1.2
V
Digital input current : High IIH
VIH = DGND3 – 0.8V
VIL = DGND3 – 1.6V
–50
–50
20
20
5
µA
µA
pF
: Low
IIL
Digital input capacitance
Digital input (TTL)
Digital input voltage: High VIH
2.0
V
V
VIL
0.8
: Low
Threshold voltage
VTH
1.5
V
Digital input current : High IIH
VIH = 3.5V
VIL = 0.2V
–10
–20
5
0
5
µA
µA
pF
: Low
IIL
Digital input capacitance
Digital output (TTL)
Digital output voltage : High VOH
: Low
IOH = –2mA
IOL = 1mA
2.4
V
V
VOL
0.5
1.6
Switching characteristics
Maximum conversion rate Fc
DMUX mode
120
MSPS
ps
ns
ns
ns
ns
ns
ns
ns
Aperture jitter
Taj
10
1.4
Sampling delay
Tds
1.2
3.0
4.5
1.0
–0.5
3.0
Clock high pulse width
Clock low pulse width
Reset signal setup time
Reset signal hold time
Clock output delay
Data output delay
Tpw1
Tpw0
T_rs
T_rh
Td_clk
Tdo1
Tdo2
Tr
CLK
CLK
RESETN – CLK
RESETN – CLK
(CL = 5pF)
4.5
4 + 0.5
5.0
1
1
7.0
7.5
DMUX mode
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
(CL = 5pF)
T
3.5
ns
ns
ns
Output rise time
Output fall time
0.8 to 2.0V
0.8 to 2.0V
Tf
These characteristics are for PECL input unless otherwise specified.
– 8 –
CXA3246Q
Item
Symbol
Conditions
Min.
250
Typ.
Max.
Unit
Dynamic characteristics
Input bandwidth
S/N ratio
VIN = 2Vp-p, –3dB
Fc = 120MSPS,
fin = 1kHz Fs
DMUX mode
Fc = 120MSPS,
MHz
dB
46
42
{
dB
fin = 29.999MHz Fs
{
DMUX mode
Fc = 120MSPS,
fin = 1kHz Fs
5
Error rate
10–12
10–9
10–9
TPS
DMUX mode
Error > 16LSB
Fc = 120MSPS,
fin = 29.999MHz Fs
DMUX mode
Error > 16LSB
Fc = 100MSPS,
fin = 24.999MHz Fs
{
{
TPS
TPS
Straight mode
Error > 16LSB
{
Power supply
Supply current
ICC + IEE
AICC
DICC1
DICC2
98
140
87
36
15
1.5
700
mA
mA
mA
mA
mA
mW
70
45
20
5
0.5
400
AVcc Pin supply current
DVcc1 pin supply current
DVcc2 pin supply current
DGND3 pin supply current IEE
Power consumption
6
500
Pd
2
3
Rref: Resistance value between VRT and VRB
VRT – VRB
Iref =
Rref
1
T =
4
5
6
Fc
TPS: Times Per Sample
(VRT – VRB) 2
Pd = (ICC + IEE) · VCC +
Rref
– 9 –
CXA3246Q
INV
VIN
1
0
Step
D7
D0 D7
D0
VRT
255
254
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
.
.
.
.
.
.
.
.
.
128
127
.
.
.
1
0
1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
VRM2
VRB
0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
.
.
.
.
.
.
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Table 1. I/O Correspondence Table
– 10 –
CXA3246Q
Electrical Characteristics Measurement Circuit
Current Consumption Measurement Circuit
Sampling Delay Measurement Circuit
Aperture Jitter Measurement Circuit
100MHz
Amp
5V
5V
OSC1
φ: Variable
Icc
IEE
AVCC
DVCC1
DVCC2
DGND3
CLK/E
VIN
VRT
VIN
4V
1.95V
2V
8
Logic
fr
CXA3246Q
Analizer
CLK
5MHz PECL
1024
samples
OSC2
ECL
Buffer
DGND2
DGND1
AGND
VRB
100MHz
DVEE3
Aperture Jitter Measurement Method
Integral Linearity Error Measurement Circuit
Differential Linearity Error Measurement Circuit
+V
VRT
VIN
VRM2
VRB
S2
S1: ON when A < B
S2: ON when A > B
S1
CLK
129
∆υ
∆ t
–V
128
σ (LSB)
127
126
125
VIN
A < B A > B
Comparator
8
8
VIN
A8
to
B8
to
B1
Buffer
CXA3246Q
A1
CLK
Sampling timing fluctuation
(= aperture jitter)
A0
B0
“0”
“1”
DVM
000···00
to
Where σ (LSB) is the deviation of the output codes when
the largest slew rate point is sampled at the clock which
has exactly the same frequency as the analog input
signal, the aperture jitter Taj is:
111···10
Controller
∆υ
∆t
256
2
Taj = σ/
= σ/ (
)
× 2πf
Error Rate Measurement Circuit
8
VIN
A
Signal
Latch
CXA3246Q
Source
Comparator
A > B
Pulse
Counter
B
Fc
4
CLK
CLK
– 1kHz
+
Latch
2Vp-p Sine Wave
16LSB
1/8
Signal
Source
Fc
– 11 –
CXA3246Q
Description of Operation Modes
The CXA3246Q has two types of operation modes which are selected with Pin 45 (SELECT).
Operation
mode
SELECT Maximum
pin conversion rate
Data output
Clock output
Demultiplexed output The input clock is 1/2 frequency divided
DMUX mode
Straight mode
VCC
120MSPS
100MSPS
60Mbps
and output.
60MHz
Straight output
100Mbps
The input clock is inverted and output.
100MHz
GND
Table 2. Operation Mode Table
1. DMUX mode (See Application Circuit 1-(1), (2) and (3).)
Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the
data is output after being demultiplexed by this 1/2 frequency-divided clock. The 1/2 frequency-divided clock,
which has adequate setup time and hold time for the output data, is output from the clock output pin.
When using the multiple CXA3246Q in DMUX mode, the start timing of the 1/2 frequency-divided clocks
becomes out of phase, producing operation such as that shown in the example on the next page. As a
countermeasure, the CXA3246Q has a function that resets the 1/2 frequency-divided clocks.
When resetting this 1/2 frequency-divided clock, the low level of the reset signal should be input to the
RESETN pin (Pin 46 or 48). The reset signal requires the setup time (T_rs ≥ 1.0ns) and hold time (T_rh ≥
–0.5ns) to the clock rising edge because it is synchronized with and taken in the clock.
The reset period can be extended by making the low level period of the reset signal longer because the clock
output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start timing is
regarded as not important, the timing where the reset signal is set from high to low is not so consequence.
However, when the reset is released the timing where the reset signal is set from low to high must become
significant because the timing is used to commence the 1/2 frequency-divided clock. In this case, the setup
time (T_rs) is also necessary.
See the timing chart for detail. (This chart shows the example of reset for 2T.)
The A/D converter can operate at Fc (min.) = 120MSPS in this mode.
– 12 –
CXA3246Q
When the reset signal is not used
CLK
CXA3246Q
CLKOUT
DATA
A
CLK
CLK
8bit
8bit
RESETN
CXA3246Q
CLKOUT
DATA
B
CLK
RESETN
When the reset signal is used
CLK
Reset signal
CXA3246Q
(Reset period)
(Reset period)
CLKOUT
DATA
CLK
RESETN
A
CLK
8bit
8bit
CXA3246Q
B
CLKOUT
DATA
CLK
Reset signal
RESETN
2. Straight mode (See Application Circuits 1-(4), (5) and (6).)
Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the
clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter
as the system clock.
The A/D converter can operate at Fc (min.) = 100MSPS in this mode.
Digital input level and supply voltage settings
The logic input level for the CXA3246Q supports ECL, PECL and TTL levels.
The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and
reset signals) level.
Digital input level
DVEE3
DGND3
Supply voltage Application circuits
ECL
PECL
TTL
–5V
0V
0V
0V
+5V
+5V
±5V
+5V
+5V
(1) (4)
(2) (5)
(3) (6)
Table 3. Logic Input Level and Power Supply Settings
– 13 –
CXA3246Q
Application Circuit 1
(1) DMUX ECL input
+5V(D)
DG
ECL RESET signal
46
45 44
43 42
37
41 40 39 38
48
47
8 bit Digital Data
1
2
PBD0 to PBD7
8 bit Digital Data
36
35
34
33
32
31
30
29
28
27
26
Latch
3
4
5
6
7
8
9
10
11
12
8 bit Digital Data
PAD0 to PAD7
8 bit Digital Data
Latch
25
23
15 16 17 18 19 20 21 22
24
13 14
ECL-CLK
DG
+5V(D)
(2) DMUX PECL input
+5V(D)
DG
PECL RESET signal
46
45 44
43 42
37
41 40 39 38
48
47
8 bit Digital Data
1
PBD0 to PBD7
8 bit Digital Data
36
Latch
2
3
35
34
33
32
31
30
29
28
27
26
4
5
6
7
8
9
10
11
12
8 bit Digital Data
PAD0 to PAD7
8 bit Digital Data
Latch
25
23
15 16 17 18 19 20 21 22
24
13 14
PECL-CLK
DG
+5V(D)
(3) DMUX TTL input
+5V(D)
DG
TTL RESET signal
46
45 44
43 42
37
41 40 39 38
48
47
8 bit Digital Data
1
2
PBD0 to PBD7
8 bit Digital Data
36
35
34
33
32
31
30
29
28
27
26
Latch
3
4
5
6
7
8
9
10
11
12
8 bit Digital Data
PAD0 to PAD7
8 bit Digital Data
Latch
25
23
15 16 17 18 19 20 21 22
24
13 14
TTL-CLK
DG
+5V(D)
– 14 –
CXA3246Q
(4) Straight ECL input
+5V(D)
DG
DG
46 45
44
43 42
37
41 40 39 38
48
47
8-bit Digital Data
1
2
PBD0 to PBD7
8-bit Digital Data
36
35
34
33
32
31
30
29
28
27
26
Latch
3
4
5
6
7
8
9
10
11
12
25
23
15 16 17 18 19 20 21 22
24
13 14
ECL-CLK
ECL → TTL
DG
+5V(D)
(5) Straight PECL input
+5V(D)
DG
DG
46 45
44
43 42
37
41 40 39 38
48
47
8-bit Digital Data
1
PBD0 to PBD7
8-bit Digital Data
36
35
34
33
32
31
30
29
28
27
26
Latch
2
3
4
5
6
7
8
9
10
11
12
25
23
15 16 17 18 19 20 21 22
24
13 14
PECL-CLK
PECL → TTL
DG
+5V(D)
(6) Straight TTL input
+5V(D)
DG
DG
46 45
44
43 42
41 40 39 38
37
48
47
8-bit Digital Data
1
2
PBD0 to PBD7
8-bit Digital Data
36
35
34
33
32
31
30
29
28
27
26
Latch
3
4
5
6
7
8
9
10
11
12
25
23
15 16 17 18 19 20 21 22
24
13 14
TTL-CLK
DG
+5V(D)
– 15 –
CXA3246Q
Application Circuit 2
DMUX Mode TTL I/O (When a single power supply is used)
AG
Analog
input
AG
4V
+5V (A)
AG
2V
+5V
(D)
1µF
DG
1µF
AG
short
short
AG
10µF
10µF
12
10
9
6
4
2
1
11
8
7
5
3
CLK/E
13
14
48
RESETN/E
RESET/E
CLKN/E
CLK/T
N.C.
47
46
45
44
43
RESETN/T
SELECT
INV
15
16
17
18
TTL CLK
N.C.
N.C.
CLKOUT
DVCC2
DVCC2
DGND2
PBD7
19
42
41
40
C
C
DGND2
PAD0
20
21
PAD1
PAD2
PAD3
PBD6
PBD5
39
38
22
23
PBD4
24
37
25
28
31 32
34 35
26 27
29 30
33
36
C
Short the analog system and digital system at one point immediately
under the A/D converter. See the Notes on Operation.
is the chip capacitor of 0.1µF. Also, C is important to suppress the noise generated
during the TTL output circuit is operating. Place C at the fixed position
between the pins with the shortest distance.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 16 –
CXA3246Q
DMUX Mode Timing Chart (Select = VCC)
Tds
1.4ns (typ.)
N – 2
N + 5
N + 6
V
IN
N + 4
(Pin 6)
N + 2
N + 3
N – 1
T
N
N + 1
CLK
(Pin 13)
Tpw1 Tpw0
Tdo2; 5.0ns (typ.)
3.5ns (min)
7.5ns (max)
PAD0 to D7
(Pins 21 to 28)
2.0V
0.8V
N
N + 2
N + 3
PBD0 to D7
2.0V
0.8V
N + 1
(Pins 33 to 40)
Tdo1
Td_clk; 4.5ns (typ.)
≈T
≈T
T + 0.5ns (typ.)
7.0ns (max)
3.0ns (min)
2.0V
2.0V
0.8V
2.0V
0.8V
CLK OUT
(Pin 43)
(Reset period)
T_rs
0.8V
T_rh
T_rs
T_rh
RESETN
(Pin 48)
– 17 –
CXA3246Q
Straight Mode Timing Chart (Select = GND)
N + 3
N – 1
Tds
N + 2
V
IN
(Pin 6)
N + 1
N
1.4ns (typ.)
T
CLK
(Pin 13)
Tpw1
Tpw0
Tdo2; 5.0ns (typ.)
3.5ns (min)
7.5ns (max)
PAD0 to D7
(Pins 21 to 28)
2.0V
N – 4
N – 3
N – 2
N – 2
N – 1
N
0.8V
PBD0 to D7
(Pins 33 to 40)
2.0V
N – 3
N – 1
N
N + 1
0.8V
Td_clk; 4.5ns (typ.)
3.0ns (min)
7.0ns (max)
CLK OUT
(CLK is inverted
and output.)
2.0V
0.8V
(Pin 43)
– 18 –
CXA3246Q
Notes on Operation
• The CXA3246Q has the PECL and TTL input pins for the clock and reset input pins. When the clock is input
in PECL level, inputting the reset signal in PECL level is recommended. Also, when the clock is input in TTL
level, inputting the reset signal in TTL is recommended.
• The impedance of the input signal should be properly matched to ensure the CXA3246Q's stable operation at
the high speed.
• The power supply and grounding have a profound influence on converter performance. The power supply
and grounding method are particularly important during high-speed operation. General points for caution are
as follows.
— The ground pattern should be as large as possible. It is recommended to make the power supply and
ground patterns wider at an inner layer using a multi-layer board.
— To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the
respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc
and DVcc lines at one point each via a ferrite-bead filter, etc. Shorting the AGND and DGND patterns in
one place immediately under the A/D converter improves A/D converter performance.
— Be sure to turn the analog and digital power supplies on simultaneously. If not simultaneously, the IC does
not operate correctly.
— Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a
0.1µF or larger ceramic chip capacitor.
(Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.)
— It is recommended to place the ceramic chip capacitor of 0.1µF or more, in particular, between DVcc2
and DGND2 with the shortest distance. This has the effect to suppress the noise generated when the
CXA3246Q TTL output circuit operates.
— The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring
capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output
waveform since the original output slew rate is quite fast.
• The analog input pin VIN has an input capacitance of approximately 10pF. To drive the A/D converter with the
proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance
or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using
chip parts for resistors and capacitors, etc.
• The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them
to AGND with approximately 1µF tantal capacitor and 0.1µF chip capacitor as short as possible.
• If the CLKN/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time,
approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as the threshold
voltage VBB because it is too weak.
• When the digital input level is ECL or PECL level,
the digital input level is TTL,
/E pins should be used and
/E pins left open.
/T pins left open. When
/T pins should be used and
• The CXA3246Q TTL output high level is clamped to approximately 2.8V in the IC. This makes it possible to
directly interface with the 3.5V system CMOS IC.
• The CXA3026Q has the output pins P1
and P2 . However, in the CXA3246Q, these symbols are
changed as PA and PB . At this time, the P1 side of the CXA3026Q is changed to the PB side for the
CXA3246Q; the P2 side of the CXA3026Q to the PA side for the CXA3246Q.
• The pipeline delay of the CXA3246Q is smaller by one clock, compared to that of CXA3026Q.
– 19 –
CXA3246Q
Example of Representative Characteristics
Current consumption vs.
Ambient temperature characteristics
Current consumption vs.
Conversion rate characteristics
110
105
100
95
110
105
100
95
fCLK
4
fin =
– 1kHz
DMUX mode
CL = 5pF
90
90
–25
25
75
60
120
0
Ta – Ambient temperature [°C]
Fc – Conversion rate [MSPS]
Analog input current vs.
Analog input voltage characteristics
Reference current vs.
Ambient temperature characteristics
4
3
2
100
VRT = 4V
VRB = 2V
50
0
2
3
4
–25
25
75
Analog input voltage [V]
Ta – Ambient temperature [°C]
– 20 –
CXA3246Q
SNR vs. Input frequency response
Error rate vs. Conversion rate characteristics
50
40
30
20
10–6
fCLK
4
fin =
– 1kHz
10–7
10–8
Error > 16LSB
Fc = 120MSPS
10–9
10–10
1
3
5
10
30
50
120
140
Fc – Conversion rate [MSPS]
160
Input frequency [MHz]
Maximum conversion rate vs.
Ambient temperature characteristics
170
160
150
140
130
fCLK
4
fin =
– 1kHz
Error > 16LSB
Error rate: 10–9 TPS
–25
25
75
Ta – Ambient temperature [°C]
– 21 –
CXA3246Q
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
0.15
36
25
24
37
+ 0.2
0.1 – 0.1
48
13
1
12
+ 0.15
0.3 – 0.1
0.8
0.24
M
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER / PALLADIUM
PLATING
SONY CODE
EIAJ CODE
QFP-48P-L04
QFP048-P-1212
42/COPPER ALLOY
0.7g
JEDEC CODE
PACKAGE MASS
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 22 –
相关型号：
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