CXA3268AR [SONY]
Driver/Timing Generator for Color LCD Panels; 驱动器/时序发生器彩色LCD面板
| 型号： | CXA3268AR |
| 厂家： | 
SONY CORPORATION |
| 描述： | Driver/Timing Generator for Color LCD Panels |
| 文件： | 总42页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA3268AR
Driver/Timing Generator for Color LCD Panels
Description
72 pin LQFP (Plastic)
The CXA3268AR is an IC designed to drive the color
LCD panels ACX300, ACX301, ACX302 and ACX703.
This IC greatly reduces the number of peripheral
circuits and parts by incorporating a RGB driver and
timing generator for video signals onto a single chip.
This chip has a built-in serial interface circuit and
electronic attenuators which allow various settings to
be performed by microcomputer control, etc.
Features
• Digital input pin voltage
VIND (other than Pins 5, 10, 14, 15 and 16)
VSS – 0.3 to VDD + 0.3 V
VSS – 0.3 to +5.5
• Common input pin voltage
VINAD (Pins 14, 15 and 16)
• Color LCD panel ACX300, ACX301, ACX302 and
ACX703 driver
• Supports NTSC and PAL systems
• Supports 16:9 wide display (letter box and pulse
elimination display)
• Supports Y/color difference and RGB inputs
• Supports OSD input (digital input)
• Power saving function
VIND (Pins 5, 10)
V
GND, VSS – 0.3 to +5.5 V
• Operating temperature
Topr
• Storage temperature
Tstg
• Allowable power dissipation
PD (Ta ≤ 25°C)
–15 to +75
–55 to +150
737
°C
°C
• Serial interface circuit
• Electronic attenuators (D/A converter)
• Trap and LPF (f0, fc variable)
• COMMON and PSIG output circuits
• Sharpness function
mW
• 2-point γ correction circuit
Operating conditions
• Supply voltage
VCC1 – GND1
• R, G, B signal delay time adjustment circuit
• D/A output pin (0 to 3V, 8 level output)
• Output polarity inversion circuit
• Supports AC drive for LCD panel during no signal
2.7 to 3.6
V
V
V
V
VCC2 – GND2
VCC3 – GND3
VDD – Vss
11.0 to 14.0
11.0 to 14.0
2.7 to 3.6
Applications
• Input voltage
SIG.C voltage
VSIG.C
Compact LCD monitors, etc.
5.0 to 6.5
V
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VCC1
1
RGB input signal voltage (Pins 70, 71 and 72)
6
V
V
V
V
VRGB
0 to 0.7 (0.5 typ.) Vp-p
VCC2
VCC3
VDD
15
15
5.5
2
Y input signal voltage (Pin 71)
VY
0 to 0.5 (0.35 typ.) Vp-p
2
R-Y input voltage (Pin 72)
• Analog input pin voltage
VINA (Pins 57, 58 and 59)
VR-Y
0 to 0.49 (0.245 typ.) Vp-p
2
B-Y input voltage (Pin 70)
GND – 0.3 to VCC1 + 0.3 V
VB-Y
0 to 0.622 (0.311 typ.) Vp-p
VINA (Pins 3, 69)
VINA (Pin 30)
VINA (Pin 71)
VCC1
1.5 to VCC2 – 4
0.9
V
V
Vp-p
Vp-p
1 During RGB input
2 During Y/color difference input
VINA (Pins 70, 72)
0.8
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E99529B98-PS
CXA3268AR
Block Diagram
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
Vss Vss
GND3
+12.0V
+12.0V
PSIG-
BRT
Buf
55 +3.0V
36
35
34
VDD
TST11
OSD B
G OUT
PSIG-
BRIGHT
S/H
OSD RGB
CONTRAST
TRAP
Buf
Buf
Buf
Buf
56
57
LPF
FILTER
G DC DET
R OUT
USER-BRIGHT
GAMMA
POL SW
S/H
GEN
CONT
U-BRT
FILTER
BIAS
γ 1 γ 2
WHITLIM
SUB-CONT R
SUB-CONT B
OSD R 58
OSD G 59
NC 60
33 R DC DET
32 B OUT
LPF
R
CLAMP
G
B
BLK-LIM
31 B DC DET
30 SIG.C
BLKLIM
MODE
PIC-G
SUB-BRIGHT
HCK1 61
HCK2 62
Vcc1 63
HST 64
EN 65
SUB-BRT R
SUB-BRT B
HCK
GEN
CLAMP
G
R
B
29 GND2
SIG.C
GND2
POL SW
MATRIX
28 TST2
27 HDO
26 VDO
25 XCLR
24 RPD
23 Vss
+3.0V
COM-DC
HDO GEN
PLL
COUNTER
HCOUNTER
HPULSE
GEN
PICTURE DL1 DL1
VDO GEN
PULSE
ELM
HUE
VCK 66
VST 67
RGT 68
PIC-F
V CONTROL
V POSITION
HUE
COLOR
PHASE
COMPARATOR
CLAMP
CLP
Vss
HSYNC DET
H SKEW DET
V COUNTER
FIL IN
B/B-Y
G/Y
CKI
CKO
VDD
VDD
69
70
71
72
22
21
20
19
V SEP
MODE
CK
CONTROL
MCK
CLK
+3.0V
DA REF
R/R-Y
+3.0V
H.FILTER SYNC SEP
Vss
S/P CONV
REGISTER DAC
Buf
6
Buf
7
GND1
9
Vss
18
1
2
3
4
5
8
10
11
12
13
14
15
16
17
– 2 –
CXA3268AR
Pin Description
Pin
Input pin for
open status
Symbol
No.
I/O
Description
1
VSS
—
O
I
Digital 3.0V GND
2
FIL OUT
SYNC IN
SYNC OUT
CSYNC/HD
DA OUT
REF
H filter output (for using internal sync separation)
Sync separation circuit input (for using internal sync separation)
Sync separation circuit output (for using internal sync separation)
CSYNC/horizontal sync signal input
DAC output
3
4
O
I
5
6
O
O
O
—
I
7
Level shifter circuit REF voltage output for LCD panel
Trap f0 adjusting resistor connection
Analog 3.0V GND
8
F ADJ
GND1
VD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Vertical sync signal input
L
DWN
O
O
—
I
Up/down inversion switching signal output
16:9 wide display switching pulse output
Test (Leave this pin open.)
WIDE
TST1
SCK
Serial clock input
SEN
I
Serial load input
SDAT
R INJECT
VSS
I
Serial data input
O
—
—
—
O
I
Serial block current controlling resistor connection
Digital 3.0V GND
VDD
Digital 3.0V power supply
VDD
Digital 3.0V power supply
CKO
Oscillation cell output
CKI
Oscillation cell input
VSS
—
O
I
Digital 3.0V GND
RPD
Phase comparator output
XCLR
VDO
Power-on reset capacitor connection (timing generator block)
VDO pulse output
H
O
O
—
—
I
HDO
HDO pulse output
TST2
Test (Connect to GND.)
GND2
SIG.C
B DC DET
B OUT
R DC DET
R OUT
G DC DET
G OUT
VCC2
Analog 12.0V GND
R, G, B and PSIG output DC voltage adjustment
B signal DC voltage feedback circuit capacitor connection
B signal output
O
O
O
O
O
O
—
R signal DC voltage feedback circuit capacitor connection
R signal output
G signal DC voltage feedback circuit capacitor connection
G signal output
Analog 12.0V power supply
– 3 –
CXA3268AR
Pin
No.
Input pin for
open status
Symbol
I/O
Description
38
39
40
41
42
43
44
PSIG DC DET
PSIG OUT
TST3
O
O
PSIG signal DC voltage feedback circuit capacitor connection
PSIG output
—
—
O
Test (Leave this pin open.)
VCC3
Analog 12.0V COM (CS) power supply
Common pad voltage for LCD panel output (CS)
Analog 12.0V COM (CS) GND
COM
GND3
—
—
TST4
Test (Leave this pin open.)
LCD panel power supply on/off (Leave this pin open when not using
this function.)
45
POF
O
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
TST5
TST6
TST7
TST8
TST9
TST10
VSS
—
—
—
—
—
—
—
—
—
—
I
Test (Connect to GND.)
Test (Connect to GND.)
Test (Leave this pin open.)
Test (Leave this pin open.)
Test (Leave this pin open.)
Test (Leave this pin open.)
Digital 3.0V GND
VSS
Digital 3.0V GND
VDD
Digital 3.0V power supply
Test (Connect to GND.)
OSD B input
TST11
OSD B
OSD R
OSD G
NC
I
OSD R input
I
OSD G input
HCK1
HCK2
VCC1
HST
O
O
—
O
O
O
O
O
I
H clock pulse 1 output
H clock pulse 2 output
Analog 3.0V power supply
H start pulse output
EN
EN pulse output
VCK
V clock pulse output
VST
V start pulse output
RGT
FIL IN
B/B-Y
G/Y
Right/left inversion switching signal output
H filter input (for using internal sync separation)
B/B-Y signal input
I
I
G/Y signal input
R/R-Y
I
R/R-Y signal input
DWN: DOWN SCAN and UP SCAN, RGT: RIGHT SCAN and LEFT SCAN
H: pull-up processing, L: pull-down processing
– 4 –
CXA3268AR
Analog Block Pin Description
Pin
No.
Pin
voltage
Symbol
Equivalent circuit
Description
VCC1
23k
Amplifies and outputs the sync
portion of the video signal input
to FIL IN (Pin 69).
2
2
3
4
6
7
FIL OUT
2.15V
1.1V
—
200
GND1
VCC1
Sync separation circuit input.
Inputs the FIL OUT (Pin 2)
output signal via a capacitor.
SYNC IN
SYNC OUT
DA OUT
REF
200
3
GND1
VCC1
Sync separation output.
Positive polarity output in open
collector format.
4
GND1
VCC1
DA output.
Outputs the serial data
converted to DC voltage. The
current driving capacity is
±1.0mA (max.).
50
—
6
50
GND1
VCC1
REF output.
Outputs the serial data
converted to DC voltage. The
current driving capacity (sink)
is ±1.5mA (max.).
—
7
51k
GND1
– 5 –
CXA3268AR
Pin
No.
Pin
voltage
Symbol
Equivalent circuit
Description
Connect a resistor between this
pin and GND1 to control the
internal LPF and trap
VCC1
frequencies.
Connect a 33kΩ resistor
(tolerance ±2%, temperature
characteristics ±200ppm or less).
This pin is easily affected by
external noise, so make the
connection between the pin and
external resistor, and between
the GND side of the external
resistor and the GND1 pin as
close as possible.
6.5k
1.1V
8
9
F ADJ
8
10
GND1
—
—
Analog 3.0V GND.
GND1
VCC1
14
15
16
14
15
16
SCK
SEN
SDAT
Serial clock, serial load and
serial data inputs for serial
communication.
200
GND1
VCC1
Connect a resistor for setting
the injector current of the IIL
logic circuit. Connect a 15kΩ
resistor between this pin and
GND1. Use a resistor with a
deviation of ±2% and
17
29
30
R INJECT
0.7V
200
17
temperature characteristics of
±200ppm or less.
GND1
Analog 12.0V GND.
(for the RGB and PSIG output
circuits)
—
GND2
VCC2
R, G, B and PSIG output DC
voltage setting.
Preset
VCC2/2
140k
Connect a 0.01µF capacitor
between this pin and GND1.
When using a SIG.C of other
than VCC2/2, input the SIG.C
voltage from an external
source.
SIG.C
200
Variable
range:
5.0 to 6.5V
30
10p
140k
GND1
– 6 –
CXA3268AR
Pin
No.
Pin
voltage
Symbol
Equivalent circuit
Description
VCC2
VCC1
Smoothing capacitor connection
for the feedback circuit of R, G,
B and PSIG output DC level
control.
Connect a low-leakage
capacitor.
31
33
35
38
B DC DET
R DC DET
G DC DET
PSIG DC DET
31
33
35
38
1.8V
200
GND1
VCC2
R, G, B and PSIG signal
outputs.
The DC level is controlled to
match the SIG.C pin voltage.
Low output in power saving
mode.
32
34
36
39
B OUT
R OUT
G OUT
PSIG OUT
32
34
36
39
VCC2/2
(SIG.C =
preset)
10
166k
10
VCC2/2V output when preset.
GND2
Analog 12.0V power supply.
(for the RGB and PSIG output
circuits)
37
41
VCC2
12.0V
12.0V
Analog 12.0V power supply.
(for COM (CS) output)
VCC3
VCC3
COMMON voltage output.
The output voltage is controlled
by serial communication.
200
42
43
COM
—
—
42
90k
GND3
Analog 12.0V GND.
(for COM (CS) output)
GND3
VCC1
OSD pulse inputs.
When one of these input pins
exceeds the Vth1 level, all of
the outputs go to black limiter
level; when an input pin
exceeds the Vth2 level, only the
corresponding output goes to
white limiter level.
Vth1 =
VCC1 × 1/3
57
58
59
OSD B
OSD R
OSD G
57
58
59
50k
50k
Vth2 =
VCC1 × 2/3
GND1
– 7 –
CXA3268AR
Pin
voltage
Pin
No.
Equivalent circuit
Description
Symbol
VCC1
63
—
Analog 3.0V power supply.
VCC1
69
H filter input.
Input the video signal via a
capacitor.
200
69
FIL IN
1.2V
GND1
VDD1
In Y/color difference input
mode, input the Y signal to
Pin 71, the B-Y signal to Pin 70,
and the R-Y signal to Pin 72.
In RGB input mode, input the
B signal to Pin 70, the G signal
to Pin 71 and the R signal to
Pin 72.
G/Y 1.8V
R/R-Y,
B/B-Y,
RGB:
1.8V
70
71
72
70
71
72
B/B-Y
G/Y
R/R-Y
200
Y/color
difference:
2.0V
Pedestal clamp these pins with
external coupling capacitors.
GND1
– 8 –
CXA3268AR
Digital Block Pin Description
Pin
No.
Pin
voltage
Symbol
Equivalent circuit
Description
1
18
23
53
54
VSS
—
—
Digital 3.0V GND.
19
20
55
Digital 3.0V power supply.
VDD
Composite sync/horizontal sync
signal input, and serial clock,
serial load and serial data inputs
for serial communication.
5
CSYNC/HD
SCK
SEN
15
5
14
15
16
14 16
—
—
SDAT
VSS
10
10
VD
Vertical sync signal input.
VSS
—
—
—
21
22
24
CKO
CKI
Oscillation circuit output.
Oscillation circuit input.
Phase comparator output.
RPD
VDD
25
XCLR
—
Digital block system reset.
25
VSS
DWN
WIDE
VDO
HDO
POF
HCK1
HCK2
HST
EN
11
12
26
27
45
61
62
64
65
66
67
68
VDD
62
64
27
45
61
66
67
11
12
26
—
Digital block outputs.
65 68
VSS
VCK
VST
RGT
– 9 –
CXA3268AR
Test Pin Description
Pin
Pin
voltage
Symbol
No.
Equivalent circuit
Description
13
40
44
49
50
51
52
TST1
TST3
TST4
TST7
TST8
TST9
TST10
Test.
—
—
Leave these pins open.
28
47
48
56
TST2
TST5
TST6
TST11
Test.
Connect to GND.
– 10 –
CXA3268AR
Setting Conditions for Measuring Electrical Characteristics
Use the Electrical Characteristics Measurement Circuit on page 22 when measuring electrical characteristics.
For measurement, the digital block must be initialized and power saving must be canceled by performing
Settings 1 and 2 below. In addition, the serial data must be set to the initial settings shown in the table below.
Setting 1. Horizontal AFC adjustment
Input a signal and adjust the VCO using V22 so that WL and WH of the TP24 output waveform are the same.
Setting 2. Canceling power saving mode
The power-on default is power saving mode, so clear (set all "0") serial data PS0, PS1, PS2, PS4 and SYNC GEN.
Horizontal sync
signal
WS
WS
RPD (Pin 24)
WL
WH
WL
WH
WL = WH
Fig. 1. Horizontal AFC adjustment
Serial data initial settings
MSB
ADDRESS
LSB
MSB
D7
DATA
D4 D3
LSB
D0
D15 D14 D13 D12 D11 D10 D9 D8
D6
D5
D2
D1
(01000110/LSB)
(10001010/LSB)
(10001010/LSB)
(00111111/LSB)
(10011111/LSB)
(10011111/LSB)
(11111111/LSB)
(11111111/LSB)
(1011111/LSB)
(10000000/LSB)
(00000000/LSB)
(10000000/LSB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
USER-BRIGHT
SUB-BRIGHT R
SUB-BRIGHT B
CONTRAST
SUB-CONTRAST R
SUB-CONTRAST B
γ-2
γ-1
0
0
PSIG-BRIGHT
COM-DC
COLOR
HUE
WHITE-LIMITER
(00/LSB)
BLACK-LIMITER (11111/LSB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
FILTER (00/LSB)
REF (000/LSB)
LPF (000/LSB)
PICTURE-F0
PICTURE-GAIN (00000/LSB)
0
(00/LSB)
0
0
0
0
0
0
MODE (1)
DA (000/LSB)
SYNC GEN PS 4
PS 2 PS 1 PS 0
0
(0)
(0)
(0)
(0)
(0)
SLSYP (1) SLEXVD (0) SLDWN (0) SLRGT (0) SLSH2 (1) SLSH1 (1) SLWD (0) SLPL (0)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
0
0
SLFL (0) SLFR (0) SL4096 (0) SLCLP2 (0) SLCLP1 (0) SLVDP (0) SLHDP (0)
0
0
0
SLTST4 (0) SLTST3 (0) SLSH0 (1) SLTST2 (0) SLTST1 (0) SLTST0 (0)
0
0
H-POSITION (10000)
HD-POSITION (00000)
Note) If there is the possibility that data may be set at other than the above-noted addresses, set these data to "0".
– 11 –
CXA3268AR
Electrical Characteristics — DC Characteristics
Analog Block
Unless otherwise specified, Ta = 25°C, VCC1 = VDD =3.0V, VCC2/VCC3 = 12.0V,
SW4 = off for the current consumption measurement, see page 11 for the DAC.
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
Current consumption 1
(Y/color difference input)
I1
Measure the inflow current to Pin 63.
27.0 37.0 mA
Current consumption 2
(Y/color difference input)
I2
I3
Measure the inflow current to Pin 37.
Measure the inflow current to Pin 41.
3.8 5.0 mA
0.90 1.3 mA
Current consumption 3
(Y/color difference input)
Current consumption 1 (RGB input)
Current consumption 2 (RGB input)
Current consumption 3 (RGB input)
Current consumption 1 (PS0 = 1)
Current consumption 2 (PS0 = 1)
Current consumption 3 (PS0 = 1)
Current consumption 1 (PS2 = 1)
Current consumption 1 (PS4 = 1)
IRGB1 Measure the inflow current to Pin 63.
IRGB2 Measure the inflow current to Pin 37.
IRGB3 Measure the inflow current to Pin 41.
IPS01 Measure the inflow current to Pin 63.
IPS02 Measure the inflow current to Pin 37.
IPS03 Measure the inflow current to Pin 41.
IPS21 Measure the inflow current to Pin 63.
IPS41 Measure the inflow current to Pin 63.
23.0 30.0 mA
3.8 5.0 mA
0.90 1.3 mA
7.5 10.0 mA
0.18 0.35 mA
1.00 µA
26.5 36.5 mA
26.5 36.5 mA
7.0 9.5 mA
0.18 0.35 mA
1.00 µA
Current consumption 1 (SYNC GEN = 1) ISG1
Current consumption 2 (SYNC GEN = 1) ISG2
Current consumption 3 (SYNC GEN = 1) ISG3
Measure the inflow current to Pin 63.
Measure the inflow current to Pin 37.
Measure the inflow current to Pin 41.
During no input
FIL OUT pin voltage
SYNC IN pin voltage
SYNC OUT pin voltage
F ADJ pin voltage
V2
1.8 2.1 2.4
1.8 1.1 1.4
0.2 0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V3
During no input
V4
During no input
V8
0.8 1.1 1.4
0.4 0.7 1.0
5.8 6.0 6.2
1.5 1.8 2.1
1.5 1.8 2.1
1.5 1.8 2.1
1.5 1.8 2.1
0.9 1.2 1.5
1.7 2.0 2.3
1.5 1.8 2.1
1.5 1.8 2.1
1.7 2.0 2.3
1.5 1.8 2.1
0.3
R INJECT pin voltage
SIG.C pin voltage
V17
V30
V31
V33
V35
V38
V69
V70
V70
V71
V70
V70
V7
B DC DET pin voltage
R DC DET pin voltage
G DC DET pin voltage
PSIG DC DET pin voltage
FIL IN pin voltage
B/B-Y pin voltage 1
During Y/color difference input
During RGB input
B/B-Y pin voltage 2
G/Y pin voltage
R/R-Y pin voltage 1
R/R-Y pin voltage 2
REF pin voltage (power saving mode)
During Y/color difference input
During RGB input
I7 = 1.5mA
V57
V58
V59
OSD input resistance
80 100 120 kΩ
– 12 –
CXA3268AR
Digital Block (including some analog block)
(Ta = –15 to +75°C, VDD = VCC1 = 3.7 to 3.6V)
Measurement
conditions
Applicable
pins
Item
Symbol
Min.
Typ.
Max.
Unit
High level input voltage
Low level input voltage
VIH
VIL
VDD × 0.7
V
V
1
VDD × 0.3
High level threshold voltage VT
+1
2.6
V
2
3
Low level threshold voltage VT–1
0.6
0.4
V
Hysteresis voltage
VT+1 – VT
–
1
2
V
Schmitt buffer
High level threshold voltage VT
+2
2.6
V
Low level threshold voltage VT–2
0.6
0.2
V
Hysteresis voltage
VT+2 – VT
–
V
High level input current
Low level input current
High level input current
Low level input current
High level input current
Low level input current
High level input current
Low level input current
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Output leak current
| IIH1 |
| IIL1 |
| IIH2 |
| IIL2 |
| IIH3 |
| IIL3 |
| IIH4 |
| IIL4 |
VOL1
VOH1
VOL2
VOH2
VOL3
VOH3
VOL4
VOH4
| IOZ |
VI = VDD
1.0
1.0
3.0
100
100
3.0
1.0
2.0
0.3
µA
µA
µA
µA
µA
µA
µA
µA
V
4
VI = 0V
VI = VDD
5
VI = 0V
10
10
40
40
VI = VDD
6
VI = 0V
VI = VDD
7
VI = 0V
IOL = 1mA
IOH = –0.25mA
IOL = 2mA
IOH = –0.5mA
IOL = 4mA
IOH = –1mA
IOL = 1.5mA
IOH = –1.25mA
High impedance status
8
2.6
2.6
V
0.3
0.3
0.4
1.0
V
9
V
V
10
2.6
V
V
11
12
VDD – 0.5
V
µA
1
XCLR (Pin 25), CKI (Pin 22)
2
CSYNC/HD (Pin 5), VD (Pin 10)
3
SCK (Pin 14), SEN (Pin 15), SDAT (Pin 16)
CSYNC/HD (Pin 5), CKI (Pin 22)
XCLR (Pin 25)
4
5
6
VD (Pin 10)
7
SCK (Pin 14), SEN (Pin 15), SDAT (Pin 16)
8
DWN (Pin 11), WIDE (Pin 12), VCK (Pin 66), VST (Pin 67), RGT (Pin 68)
9
RPD (Pin 24), VDO (Pin 26), HDO (Pin 27), POF (Pin 45), HST (Pin 64), EN (Pin 65)
HCK1 (Pin 61), HCK2 (Pin 62)
10
11
CKO (Pin 21). However, when measuring the output pin (CKO), the input level of the input pin (CKI) should
be 0V or VDD.
RPD (Pin 24)
12
– 13 –
CXA3268AR
Electrical Characteristics
AC Characteristics
Unless otherwise specified, Settings 1 and 2, the serial data initial settings, and the following setting conditions
are required.
Ta = 25°C, VCC1 = 3.0V, VCC2 = VCC3 = 12V, GND1/2/3 = 0V, VSS = 0V, SW2 = ON, SW4 = ON,
SW32/34/36 = OFF, no video input, SG1 input to TP5
Note: Serial data values in the table are HEX notation.
Serial data
setting (HEX)
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
Maximum gain
between input and
output
Input SG2 (50mVp-p) to TP71 and
measure the output amplitude at TP36.
GMAX
CONT FFh
29
32 34
dB
Y/color difference
Maximum gain
between input and
output
Input SG2 (50mVp-p) to TP71 and
measure the output amplitude at TP36.
CONT FFh
MODE 00h
31
26 29
25 30
dB
dB
GRGBMAX
RGB
Assume the output amplitude at TP36 when
SG2 (0.5Vp-p) is input to TP71 as GMIN.
∆gcon = GMAX – GMIN
Amount of contrast
attenuation
Gcon
CONT 00h
Assume the inverted output amplitude at
TP36 when SG2 (0.35Vp-p) is input to TP71
CONT 2Fh as Vinv, and the non-inverted output
amplitude as Vninv.
Inverted and
non-inverted gain
difference
∆GINV
±0.3 dB
∆ginv = 20 log (Vninv/Vinv)
Input SG2 (0.35Vp-p) to TP71 (TP70, TP72),
measure the non-inverted output amplitude
at TP32, TP34 and TP36, and obtain the
maximum and minimum difference between
these values.
∆GRGB1
∆GRGB2
CONT 2Fh
0.6
dB
0.6
Gain difference
between R, G and
B
MODE 00h
CONT 2Fh
Set CONT = 26h, input SG2 (0.35Vp-p) to
TP71, and assume the non-inverted output
amplitude at TP32 and TP34 when SUB-
CONT R/B = 9Ah, 00h and FFh as V1, V2
and V3, respectively.
SUB-CONT
–5.5
∆GSC1
∆GSC2
–4.5
dB
00h
Sub-contrast
variable amount
SUB-CONT
2.0
0.8
2.7
∆Gsc1 = 20 log (V3/V1)
∆Gsc2 = 20 log (V2/V1)
FFh
SUB-BRT
R, B 00h
Set U-BRT = 1Ah and measure the non-
inverted level at TP32 and TP34 relative to
the non-inverted black level at TP36 when
SUB-BRT R/B = FFh and 00h.
–1.5 –1.0
1.2
∆VSB1
∆VSB2
Sub-bright
variable amount
V
V
SUB-BRT
R, B FFh
Set U-BRT = FFh, measure the inverted and
non-inverted black limit level at TP36 when
BLK-LIM = 00h and 1Fh, and assume the
difference from the output DC voltage as
VBL1 and VBL2, respectively.
BLK-LIM
00h
VBL1
VBL2
±1.6 ±2.1 ±2.7
±4.7 ±5.1 ±5.4
Black limiter
variable amount
BLK-LIM
1Fh
– 14 –
CXA3268AR
Serial data
setting (HEX)
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
Set CONT = FFh, input SG2 (0.35Vp-p) to
TP71, measure the inverted and non-inverted
white limit level when WHITE-LIM = 00h and
03h, and assume the difference from the
output DC voltage as VWL1 and VWL2,
respectively.
WHITE-LIM
VWL1
±1.2
±0.6
±0.6 ±0
±1.2 ±1.8
00h
White limiter
variable amount
V
WHITE-LIM
VWL2
03h
Measure the non-inverted black level at
TP32, TP34 and TP36, and obtain the
maximum and minimum difference between
these values.
Black level
difference between
R, G and B
mV
∆VB
300
Measure the output DC level (average
voltage) at TP32, TP34, TP36 and TP39.
RGB and PSIG
output DC voltage
5.8 6.0 6.2
±200
V
Vc
Measure the output average voltage
difference at TP32, TP34 and TP39 relative
to the output average voltage at TP36.
DC voltage
difference between
RGB and PSIG
mV
∆Vc
PSIG-BRT
01h
Measure the inverted and non-inverted black
level when PSIG-BRT = 01h and 7Fh and
assume the difference from the average DC
voltage Vc as VPB1 and VPB2, respectively.
VPB1
VPB2
∆UB1
∆UB2
±0.7
PSIG-BRT
variable amount
V
V
PSIG-BRT
7Fh
±4.2
U-BRT
00h
Measure the inverted and non-inverted black
level at TP36 when U-BRT = 00h and 7Ah
and assume the difference from the average
voltage as ∆UB1 and ∆UB2, respectively.
±0.8 ±1.5
±4.5 ±4.9
USER-BRT
variable amount
U-BRT
7Ah
Set BLK-LIM = 00h and measure the
difference between the inverted and non-
inverted black level at TP36 and TP39.
Level difference
between PSIG-BLK ∆VBB
and BLK-LIM
SLWD
1
350 mV
deg
Set U-BRT = 23h, CONT = 80h, COLOR =
40h, and assume the amplitude at TP32
when SG4 (56mVp-p) is input to TP72 as V1.
Similarly, assume the amplitude at TP34
when SG4 (100mVp-p) is input to TP70 as V2.
θ = tan – 1 (V1/V2). Assume the θ when HUE
= 00h, 80h and FFh as θa, θb and θc,
respectively.
θ1
HUE 00h
HUE FFh
–25
–20
Hue
variable amount
deg
θ2
20 25
θ1 = θa – θb, θ2 = θc – θb
Set CONT = 2Fh, input SG3 to TP71, and
measure the TP36 amplitude at f0 relative to
the TP36 amplitude at 100kHz when PIC-G
= 01h and 1Fh. f0 at PIC-f0 = 00h, 01h, 02h
and 03h is 2MHz, 2.2MHz, 2.6MHz and
2.9MHz, respectively.
PIC-G
01h
GP1
Picture
variable amount
GP2
–1.5
0
1.5
dB
PIC-G
1Fh
10 12
Input SG4 (50mVp-p) to TP70 and TP72,
and assume the output amplitude at TP32
and TP34 when COLOR = 00h, 80h and FFh
as V1, V2 and V3, respectively.
GC1 = 20 log (V1/V2)
COLOR
00h
GC1
–30 –20
Color
variable amount
dB
COLOR
FFh
GC2
5.0 6.0
GC2 = 20 log (V3/V2)
– 15 –
CXA3268AR
Serial data
setting (HEX)
Item
Symbol
Measurement conditions
Min. Typ. Max. Unit
0.85 1.00 1.15
Assume the TP34 output when SG4 (0.1Vp-p)
is input to TP72 as RR, the TP32 amplitude
when SG4 (0.1Vp-p) is input to TP70 as BB,
the TP34 amplitude when SG5 (0.1Vp-p) is
input to TP72 as RG, and the TP32 amplitude
when SG5 (0.1Vp-p) is input to TP70 as BG.
B-Y/R-Y = RR/BB,
B-Y/
R-Y
CONT 63h
Matrix amplitude
ratio
G-Y/
R-Y
0.41 0.51 0.61
0.15 0.19 0.23
COLOR
6Fh
G-Y/
B-Y
G-Y/R-Y = RG/RR,
G-Y/B-Y = BG/BB
LPF 01h
MODE 00h
Input SG3 to TP71 and measure the
frequency which results in –3dB relative to
the TP36 amplitude at 100kHz when LPF =
01h and 07h.
2.0 2.5
MHz
fc1
fc2
LPF characteristics
LPF 07h
MODE 00h
5.0 6.4
Set U-BRT = 30h, CONT = DFh, input SG7
(13.5MHz) to TP70, TP71 and TP72, and
measure the amount by which the output is
attenuated when FILTER = 01h relative to
FILTER = 00h. Similarly, input SG7 (14.5MHz)
to TP70, TP71 and TP72, and measure the
amount by which the output is attenuated
when FILTER = 02h relative to FILTER = 00h.
fo1
fo2
MODE 00h
MODE 00h
–27
–27
–20
–20
Trap
characteristics
dB
Set SW32, SW34 and SW36 = ON, input SG3
to TP70, TP71 and TP72, and measure the
frequency which results in –3dB relative to the
TP32, TP34 and TP36 amplitude at 100kHz.
Frequency
response
f RGB
MODE 00h
MHz
V
5.5
1.50
2.20
0.3
VREF1 REF 00h
VREF2 REF 07h
1.20 1.35
1.90 2.05
Measure the REF pin
Output current
REF adjustment
range
output voltage when
1.5mA, sink only
REF = 00h and 07h.
Output current
1.0mA
VDA1
VDA2
DA 00h
DA 07h
Measure the DA output
voltage when DA = 00h
and 07h.
DA adjustment
range
V
Output current
–1.0mA
2.7
Internal DAC
differential
non-linearity error
Measure under the measurement conditions
for each adjustment range.
–1.5
SDL
SL
1.5
2.0
LSB
LSB
Internal DAC
non-linearity error
Measure under the measurement conditions
for each adjustment range.
–2.0
Input SG2 (0.35mVp-p) to TP71 and measure
the amplitude at TP32, TP34 and TP36.
Assume the output amplitude when GAMMA1
= FFh as V1, when GAMMA1 = 3Fh as V2,
and when GAMMA1 = GAMMA2 = 3Fh as V3.
∆γ1 = 20 log (V1/V2)
∆γ1
14 16
12
Gamma
characteristics
CONT 41h
dB
dB
∆γ2
12 14 16
15.0 17.0
∆γ2 = 20 log (V3/V2)
Input SG6 to TP69 and measure the output
amplitude at TP2.
H FIL gain
Ghfil
– 16 –
CXA3268AR
Serial data
setting (HEX)
Item
Symbol
COMDC
Measurement conditions
Min. Typ. Max. Unit
Measure the COM output DC voltage when
COM-DC = 00h and FFh, and measure the
difference from the COM output DC voltage
when COM-DC = 80h.
COMMON control
range
±1.0
V
±1.3
Gradually increase the SYNC IN outflow
current and measure the current at which
SYNC OUT switches to high.
SYNC IN
sensitivity current
I SYNC
VOsync
20 31
µA
V
SYNC OUT on
voltage
Measure the SYNC OUT pin voltage during
SYNC IN no input.
0.2 0.4
Input SG4 to TP57, TP58 and TP59,
gradually raise the high level from 0V, and
assume the high level voltage at which the
output level goes to BLK-LIM level as
Vth1OSD, and the high level voltage at
which the output level goes to WHITE-LIM
level as Vth2OSD.
Vth1
OSD
1.2
0.8 1.0
OSD threshold
value
V
Vth2
OSD
1.8 2.0 2.2
Set SW32, SW34 and SW36 = ON,
input SG4 (0.35Vp-p) to TP71, and measure
the propagation delay time of the non-
inverted output rise and fall at TP32, TP34
and TP36 from TP71.
Propagation delay
time between input
and output
70 120 170
80 130 180
tLH1
tHL1
ns
ns
Y/color difference 1
Set SW32, SW34 and SW36 = ON,
input SG4 (0.35Vp-p) to TP70, TP71 and
TP72, and measure the propagation delay
time of the non-inverted output rise and fall
at TP32, TP34 and TP36 from TP70, TP71
and TP72.
70 110
60 110
tLH2
tHL2
160
160
Propagation delay
time between input
and output
MODE
00h
RGB input
Set SW32, SW34 and SW36 = ON,
input SG4 (0.35Vp-p) to TP71, and measure
the propagation delay time of the non-
inverted output rise and fall at TP32, TP34
and TP36 from TP71.
Propagation delay
time between input
and output
tLH3
tHL3
tLH4
tHL4
270 330 390
270 330 390
90 130 170
PIC-G
01h
ns
ns
Y/color difference 2
Set SW32, SW34 and SW36 = ON,
Propagation delay
time between OSD
input and output
input SG4 (3Vp-p) to TP57, TP58 and TP59,
and measure the propagation delay time of
the non-inverted rise and fall at TP70, TP71
and TP72 from TP57, TP58 and TP59.
210
170
250
Propagation delay
time between H FIL
and FIL OUT
Input SG6 to TP69 and measure the
propagation delay time of the rise and fall at
TP2 from TP69.
tLH7
tHL7
500 700 900
100 300 500
ns
ns
Propagation delay
time between
SYNC IN and
SYNC OUT
140 200 260
40 100 160
tLH8
tHL8
Set SW2 = OFF, input SG8 to TP3, and
measure the propagation delay time of the
rise and fall at TP4 from TP3.
– 17 –
CXA3268AR
Serial data
setting (HEX)
Item
Symbol
ts0
Measurement conditions
Min. Typ. Max. Unit
SEN setup time, activated by the rising edge
of SCK. (See Fig. 4.)
150
Data setup time
ns
SDAT setup time, activated by the rising
edge of SCK. (See Fig. 4.)
ts1
150
SEN hold time, activated by the rising edge
of SCK. (See Fig. 4.)
th0
150
Data hold time
ns
SDAT hold time, activated by the rising edge
of SCK. (See Fig. 4.)
th1
150
tw1L
tw1H
tw2
SCK pulse width. (See Fig. 4.)
SCK pulse width. (See Fig. 4.)
SEN pulse width. (See Fig. 4.)
210
210
1
ns
ns
µs
Minimum pulse
width
Measure the transition time of each output.
30pF load: RPD, VDO, HDO and POF
output pins
40pF load: EN and HST output pins
120pF load: HCK1 and HCK2 output pins
(See Fig. 2.)
30
30
tTLH
tTHL
ns
ns
Output transition
time
Measure the transition time of each output.
40pF load: DWN, WIDE, VCK, VST and
RGT output pins
50
50
tTLH
tTHL
(See Fig. 2.)
Measure HCK1/HCK2.
120pF load
(See Fig. 3.)
Cross-point time
difference
∆T
10 ns
Measure the HCK1/HCK2 duty.
120pF load
HCK duty
DTYHC
47 50 53
%
– 18 –
CXA3268AR
Electrical Characteristic Measurement Method Diagrams
∆T
90%
50%
10%
tTLH
tTHL
∆T
Fig. 2. Output transition time
measurement conditions
Fig. 3. Cross-point time difference
measurement conditions
SDTA
SCK
SEN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
ts1
th1
50%
tw1H
tw1L
50%
ts0
th0
tw2
Fig. 4. Serial transfer block measurement conditions
– 19 –
CXA3268AR
SG No.
SG1
Waveform
Horizontal sync signal
(CSYNC)
4.7µs
3.0Vp-p
1H
Amplitude variable
SG2
1H
Horizontal sync signal
Sine wave video signal; frequency and amplitude variable
0.1Vp-p
0.1Vp-p
SG3
1H
High level variable
25µs
10µs
0V
SG4
Horizontal sync signal
3V
10µs
Low level variable
SG5
25µs
Horizontal sync signal
– 20 –
CXA3268AR
SG No.
SG6
Waveform
Horizontal sync signal
(CSYNC)
50mVp-p
4.7µs
1H
Sine wave video signal
0.1Vp-p
SG7
1H
Horizontal sync signal
(CSYNC)
4.7ns
0.15Vp-p
SG8
1H
– 21 –
CXA3268AR
Electrical Characteristics Measurement Circuit
TP39
400P
+12V
A
SW39
+12V
A
47µ
1µ
TP42
TP45
0.1µ
10
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
+3V
47µ
1µ
A
10
55 VDD
36
TP36
G OUT
0.1µ
47µ
0.01µ
TP57
56 TST11
57
G DC DET 35
300P
SW36
SW34
SW32
10
0.1µ
34
OSD B
58 OSD R
TP34
R OUT
R DC DET 33
TP58
TP59
300P
300P
10
0.1µ
59
60
61
62
63
64
65
66
67
68
69
70
71
72
32
31
30
29
28
27
26
25
24
23
22
21
OSD G
NC
B OUT
B DC DET
SIG.C
GND2
TST2
HDO
TP32
0.01µ
+12V
A
TP61
TP62
HCK1
HCK2
Vcc1
HST
TP30
1µ
47µ
TP27
TP26
TP64
TP65
TP66
TP67
TP68
TP69
TP70
TP71
TP72
EN
VDO
0.1µ
VCK
VST
XCLR
RPD
TP24
1k
RGT
FIL IN
B/B-Y
Vss
1µ
CKI
0.01µ
0.01µ
0.01µ
CKO
3.3µ 1000p 33k
VDD 20
VDD 19
G/Y
10k
30p
2
10k
R/R-Y
3.3µ
+3V
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
V22 0.01µ 6800p
1µ
1
A
1
33k
15k
TP2
47µ
0.01µ
SW2
1k
TP3
TP5 TP6 TP7
TP14
TP16
TP15
TP11 TP12
SW4
TP4
1 Resistance value tolerance: ±2%, temperature coefficient: ±200ppm or less
Locate this resistor as close to the IC pin as possible to reduce the effects of external signals.
2 Varicap diode: 1T369 (SONY)
– 22 –
CXA3268AR
Description of Operation
1) RGB and Y/color difference signal processing block
Signal processing is comprised of picture, hue, matrix, LPF/trap, contrast, OSD, sample-and-hold, γ correction,
bright, sub-bright, sub-contrast and output circuits
• Input signal mode switching
The input mode (RGB input, Y/color difference input) can be switched by the serial communication settings.
(During internal sync separation signal input)
During RGB input: The G signal is input to Pins 71 and 69, the B signal to Pin 70, and the R-Y signal to
Pin 72.
During Y/color difference input: The Y signal is input to Pins 71 and 69, the B-Y signal to Pin 70, and the
R-Y signal to Pin 72.
(During external sync signal input)
During RGB input: The G signal is input to Pin 71, the B signal to Pin 70, the R signal to Pin 72,
CSYNC/HD to Pin 5, and VD to Pin 10.
During Y/color difference input: The Y signal is input to Pin 71, the B-Y signal to Pin 70, the R-Y signal to
Pin 72, CSYNC/HD to Pin 5, and VD to Pin 10.
• NTSC/PAL switching
The input system (NTSC/PAL) can be switched by the serial communication settings.
• Picture circuit
This performs aperture correction for the Y signal. The center frequency to be corrected and the correction
amount are controlled by serial communication. In addition, when not using the picture circuit, it can be turned
off by serial communication.
• Hue circuit
This is the hue adjustment circuit for the color difference signal. It is controlled by serial communication.
• Matrix circuit
This circuit converts Y, R-Y and B-Y signals into RGB signals.
• LPF circuit
This is the band limitation filter for the RGB signal. It is used to eliminate the noise component generated at
the front end of this IC. The cut-off frequency can be controlled by serial communication. In addition, when
not using the LPF, it can be turned off by serial communication.
• Trap circuit
This is used to eliminate the DSP clock and RGB decoder carrier leak generated at the front end of this IC.
The center frequency can be switched between 13.5MHz and 14.3MHz by serial communication. In addition,
when not using the trap, it can be turned off by serial communication.
• Contrast adjustment circuit
This adjusts the white-black amplitude to set the input RGB signal to the appropriate output level.
• OSD
This inputs the OSD pulses. There are two input threshold values: Vth1 (VCC1 × 1/3) and Vth2 (VCC1 × 2/3).
When an input exceeds Vth1, the corresponding output falls to the level specified by BLACK-LIMITE. When
an input exceeds Vth2, the corresponding output rises to the level specified by WHITE-LIMITER. Also, when
one of the RGB inputs exceeds Vth1, any signal outputs not exceeding Vth1 also fall to the level specified by
BLACK-LIMITER.
– 23 –
CXA3268AR
• Sample-and-hold circuit
This circuit performs time axis correction for the RGB output signals in order to support the RGB simultaneous
sampling systems of LCD panels.
HCK1
R
G
B
S/H1
S/H4
S/H4
S/H4
R
G
B
A
S/H2
A'
B
S/H3
SH3
B'
C
C'
SH1
SH2
SH4
RGT = H (normal)
SHS1
SHS2
A'
SHS3
A
SHS4
C'
SHS5
C
SHS6
B'
SH1
B
SH1: R signal SH pulse
SH2: G signal SH pulse
SH3: B signal SH pulse
SH4: RGB signal SH pulse
SH2 Through Through Through Through Through Through
SH3
SH4
A
C
C'
B'
C
B
B'
A'
B
A
A'
C'
SHS1,2,3,4,5,6: Serial data settings
RGT = L (right/left inversion)
SHS1
SHS2
A'
SHS3
SHS4
C'
SHS5
SHS6
B'
SH1
SH2
B
A
A
C
C
B
C'
B'
A'
SH3 Through Through Through Through Through Through
SH4 B' A' C'
C
B
A
The sample-and-hold circuit performs sample-and-hold by receiving the SH1 to SH4 pulses from the TG
block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be
compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation and
other timing is also generated by the digital block. The sample-and-hold timing changes according to the
phase relationship with the HCK pulse, so the timing should be set to the SHS1, 2 or 6 position in
accordance with the actual board.
• γ correction
In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The γ1
gain transition point A voltage changes as shown in Fig. 2 by adjusting the serial bus register γ1, and the γ2
gain transition point B voltage changes as shown in Fig. 3 by adjusting γ2.
B"
Output
Output
Output
B'
A'
B
B
B
A
A
A
Input
Input
Input
Fig. 1
Fig. 2
Fig. 3
– 24 –
CXA3268AR
• Bright circuit
This is used to adjust the black-black amplitude of polarity-inverted RGB output signals. It is not interlinked
with the γ transition points.
• White balance adjustment circuit
This is used to adjust the white balance. The black level is adjusted by SUB-BRIGHT, and the black-white
amplitude is adjusted by SUB-CONTRAST.
• Output circuit
RGB output (Pins 70, 71, and 72) signals are inverted each horizontal line by the FRP pulse (internal pulse)
supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage
(SIG.C) of the output signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG.C
(Pin 30)). In addition, the white level output is clipped at the limiter operation point that is set by the serial
communication WHITE-LIMITER, and the black level output is clipped at the limiter operation point that is set
by the serial communication BLACK-LIMITER.
The output PSIG signal level is normally adjusted by PSIG-BRIGHT, but during 16:9 display the level is
specified by BLACK-LIMITER during V blanking. In addition, the RGB output also simultaneously goes to
BLACK-LIMITER level output.
RGB IN
1H inverted signal
(internal)
16:9 display signal
(internal)
BLACK-LIMITER
Set by BLACK-LIMITER
PSIG OUT
SIG.C
Set by PSIG-BRIGHT
BLACK-LIMITER
BLACK-LIMITER
WHITE-LIMITER
SIG.C
RGB OUT
WHITE-LIMITER
BLACK-LIMITER
Set by BLACK-LIMITER
– 25 –
CXA3268AR
2) Common voltage generation circuit block
The common voltage circuit generates and supplies the common pad voltage to the LCD panel. The voltage
is offset by serial communication using the SIG.C voltage as the reference and then output.
3) DAC output circuit
There are two DAC output circuit systems. The DA OUT output circuit outputs DC 3.0V at equal divisions.
The REF output circuit generates and supplies the REF voltage for the panel level shifter circuit to the LCD
panel. Both circuits are controlled by serial communication.
4) Sync system
• H FIL
This amplifies the sync signal of the input video signal and eliminates the noise with an internal LPF. The sync
signal is clamped at the input, so be sure to input via a capacitor.
• SYNC SEP
This inputs the FIL OUT (Pin 2) output and performs sync separation. The signal is output from SYNC OUT
(Pin 4) as a positive polarity pulse.
5) Power saving circuit (PS circuit)
A power saving system can be realized together with the LCD panel by independently controlling (serial
communication) the operation of each output block. This system is also effective for improving picture
quality during power-on/off.
The serial data PS0, PS1, PS2, PS4 and SYNC GEN must be set in order to use this IC. For details of
the setting methods, see the "Description of Serial Control Operation" and "Power Supply and Power
Saving Sequence" items.
– 26 –
CXA3268AR
6) TG block
• PLL and AFC circuits
A PLL circuit can be comprised by connecting a PLL circuit phase comparator and frequency division counter
and external VCO and LPF circuits.
The PLL error detection signal is generated using the phase comparison output of the entire bottom of the
horizontal sync signal and the internal frequency division counter as the RPD output. RPD output is
converted to DC error voltage with the lag-lead filter, and then it changes the capacitance of the varicap
diode to stabilize the oscillation frequency.
The PLL of this system is adjusted by setting the reverse bias voltage of the varicap diode so that the point at
which RPD changes is at the center of the horizontal sync signal window as shown in the figure below.
Horizontal sync signal
WS
WS
RPD (Pin 24)
WL
WH
WL
WH
WL = WH
• H-Position
This adjusts the horizontal display position. Set this function so that the picture center matches the center of
the LCD panel.
• Right/left (RGT) and/or up/down inversion (DWN)
The video display direction can be switched. The horizontal direction can be switched between right scan and
left scan, and the vertical direction between down scan and up scan. Set the display direction in accordance
with the LCD panel mounting position.
• Wide mode
16:9 quasi-WIDE display can be achieved by converting the aspect ratio through pulse elimination processing.
During wide mode, vertical pulse elimination scanning is performed for both NTSC and PAL display and the
video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside the display area, the
black level set by BLACK-LIMITER (serial communication data) is wide-masked as the black signal within the
limited vertical blanking period.
This function achieves a quasi-display by simply pulse eliminating the video signal, so some video information
is lost.
Pulse elimination display
Black display
28 LINES
Black display area
228 LINES
Display area
Display area
172 LINES
28 LINES
Black display area
4:3 display
16:9 display
• AC driving of LCD panels during no signal
The output signal runs freely so that the LCD panel is AC driven even when there is no sync signal from the
FIL IN (Pin 69) pin or from the CSYNC/HD (Pin 5) and VD (Pin 10) pins. During this time, the sync separation
circuit stops and the auxiliary counter is used to generate the free running output pulses after detecting that
there is no vertical sync signal for approximately 3 fields (no signal state).
– 27 –
CXA3268AR
Description of Serial Control Operation
1) Control method
Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCK. This loading
operation starts from the falling edge of SEN and is completed at the next rising edge.
Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for
the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator)
block control data becomes valid each time the SEN signal is input.
In addition, if 16 bits of more of SCK are not input while SEN is low, the transferred data is not loaded to the
inside of the IC and is ignored. If 16 bits or more of SCK are input, the 16 bits of data before the rising edge of
the SEN pulse are valid data.
SDAT
SCK
SEN
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Serial transfer timing
A: ADDRESS
D: DATA
2) Serial data map
The serial data map is as follows. Values inside parentheses are the default values.
MSB
ADDRESS
LSB
MSB
DATA
LSB
D0
D15 D14 D13 D12 D11 D10 D9 D8
D7
D6
D5
D4 D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
USER-BRIGHT
SUB-BRIGHT R
SUB-BRIGHT B
CONTRAST
(10000000/LSB)
(10000000/LSB)
(10000000/LSB)
(10000000/LSB)
SUB-CONTRAST R (10000000/LSB)
SUB-CONTRAST B (10000000/LSB)
γ-2
γ-1
(00000000/LSB)
(00000000/LSB)
(1000000/LSB)
(10000000/LSB)
(10000000/LSB)
(10000000/LSB)
(0)
(0)
PSIG-BRIGHT
COM-DC
COLOR
HUE
WHITE-LIMITER
(00/LSB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
BLACK-LIMITER (10000/LSB)
FILTER (00/LSB)
REF (011/LSB)
LPF (000/LSB)
PICTURE-F0
PICTURE-GAIN (00000/LSB)
(0)
(00/LSB)
(0)
(0)
(0)
(0)
(0)
(0)
MODE (0)
DA (000/LSB)
SYNC GEN PS 4
PS 2 PS 1 PS 0
(0)
(1)
(1)
(1)
(1)
(1)
SLSYP (0) SLEXVD (0) SLDWN (0) SLRGT (0) SLSH2 (0) SLSH1 (0) SLWD (0) SLPL (0)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
(0)
(0)
(0)
(0)
SLFL (0) SLFR (0) SL4096 (0) SLCLP2 (0) SLCLP1 (0) SLVDP (0) SLHDP (0)
(0)
(0)
(0)
SLTST4 (0) SLTST3 (0) SLSH0 (0) SLTST2 (0) SLTST1 (0) SLTST0 (0)
(0)
(0)
H-POSITION (10000/LSB)
HD-POSITION (00000/LSB)
Note) If there is the possibility that data may be set at other than the above-noted addresses, set these data to "0".
– 28 –
CXA3268AR
3) Description of control data
• USER-BRIGHT
This adjusts the brightness of the RGB output signals. Adjustment from LSB → MSB increases the amplitude
(black-black).
• SUB-BRIGHT R/B
This adjusts the brightness of the R and B output signals using the G output signal as the reference.
Adjustment from LSB → MSB increases the amplitude (black-black).
• CONTRAST
This adjusts the contrast of the RGB output signals. Adjustment from LSB → MSB increases the amplitude
(black-white).
• SUB-CONTRAST R/B
This adjusts the contrast of the R and B output signals using the G output signal as the reference.
Adjustment from LSB → MSB increases the amplitude (black-black).
• γ-2
This sets the white side γ point level of the RGB output signals. Adjustment from MSB → LSB lowers the γ point.
When not adjusting γ-2, set γ-2: 11111111 (LSB). Set the γ-2 point to the white side of the γ-1 point.
• γ-1
This sets the black side γ point level of the RGB output signals. Adjustment from MSB → LSB lowers the γ point.
When not adjusting γ-1, set γ-1: 11111111 (LSB). Set the γ-1 point to the black side of the γ-2 point.
• PSIG-BRIGHT
This adjusts the bright level of the PSIG output signal. Adjustment from LSB → MSB increases the amplitude
(peak to peak).
Note: Do not set PSIG-BRIGHT: 0000000 (LSB), as this setting turns off the internal PSIG circuit.
• COM-DC
This adjusts the COMMON output voltage. Adjustment from LSB → MSB increases the output voltage.
• COLOR
This adjusts the color gain during Y/color difference input. Adjustment from LSB → MSB increases the gain.
• HUE
This adjusts the phase during Y/color difference input. Adjustment from LSB → MSB advances the phase.
• WHITE-LIMITER
This adjusts the white side limiter level of the RGB output signals. See the AC Characteristics for the output
level.
• BLACK-LIMITER
This adjusts the black side limiter level of the RGB output signals. Adjustment from LSB → MSB lowers the
limiter level.
– 29 –
CXA3268AR
• LPF
This switches the frequency response of the low-pass filter. Set the fc/–3dB frequency relative to the amplitude
100kHz reference. See the AC Characteristics for the output level.
fc (RGB input/no load/typ.)
LPF OFF
2.0MHz
D0
0
D2
0
D1
0
0
1
0
1
0
2.7MHz
0
1
1
3.4MHz
0
0
0
3.9MHz
1
0
1
4.9MHz
1
1
0
5.7MHz
1
1
1
6.4MHz
1
• REF
This adjusts the REF output voltage. Adjustment from LSB → MSB raises the output voltage level. See the
AC Characteristics for the output level.
• FILTER
This sets the trap (f0) center frequency. See the AC Characteristics for the output level.
D7
0
D6 Center frequency (f0)
0
1
0
1
TRAP OFF
13.5MHz
14.3MHz
—
0
1
1
• PICTURE-F0
This sets the picture center frequency (f0) during Y/color difference input. See the AC Characteristics for the
output level.
D1
0
D0 Center frequency (f0)
0
1
0
1
2.0MHz (typ.)
2.2MHz (typ.)
2.6MHz (typ.)
2.9MHz (typ.)
0
1
1
• PICTURE-VOLUME
This adjusts the picture gain during Y/color difference input. Adjustment from LSB → MSB raises the gain.
When not using the picture function (OFF), set PICTURE-VOLUME: 00000 (LSB).
– 30 –
CXA3268AR
• DA
This adjusts the DA output voltage. See the AC Characteristics for the output level.
• MODE
This switches the input signal.
Input signal
RGB input
D3
0
1
Y/color difference input
• SYNC GEN
This sync generator mode stops all output pulses other than the HDO and VDO output pulses. The PS0,
PS1, PS2 and PS4 settings have priority over the SYNC GEN setting. Normally set to "0".
Mode (SYNC GEN)
D5
0
Normal operation
All output pulses and corresponding output blocks other than the HDO and VDO output pulses are
stopped.
1
• PS0, PS1, PS2, PS4
These perform the power saving settings for each input and output block. Be sure to use these settings as
described in "Power Supply and Power Saving Sequence". The power-on default for this IC is power saving
mode, so the settings should be canceled by serial communication after power-on.
Mode (PS0, PS1, PS2, PS4)
D0, 1, 2, 4
0
1
Normal operation
The respective outputs and corresponding output blocks are stopped.
– 31 –
CXA3268AR
Power Supply and Power Saving Sequence
When using this IC, the power supply sequences described below must be followed during power-on/off to
ensure reliability as a LCD driving system. Thoroughly study the function specifications of each control method
(1), (2) and (3) before use.
Control timing (1)
Use this timing when not using the power saving (PS) function regardless of picture quality during power-
on/off.
Control timing (2)
Use this timing when using the power saving (PS) function regardless of picture quality during power-on/off.
Note that in this case an external switch is necessary.
Control timing (3)
Use this timing when using the power saving (PS) function and placing priority on picture quality during
power-on/off. Note that in this case an external switch is necessary.
Control timing (1)
(1) IC power-on (3V, 12V), LCD power-on (HVDD, VVDD)
(2) A settings: after the IC and LCD power supplies have risen
(3) IC power-off (3V, 12V), LCD power-off (HVDD, VVDD): optional
The LCD power supply (HVDD, VVDD) rise timing should adequately satisfy the panel specifications.
Serial data settings other than PS should be made during the control period from the rise of the IC 3V
power supply to (2).
Default
LCD display
Power-off
Default
LCD display
Power-off
Status
Power-on PS OFF
Power-on PS OFF
LCD power supply
IC 12V
Supply voltage
&
output signal
IC 3V
SYNC GEN circuit
PS4 circuit
2
2
PS2 circuit
PS1 circuit
PS0 circuit
1
1
IC power-on
LCD power-on PS0 → 0
PS1 → 0
A
IC power-off
LCD power-off
IC power-on
LCD power-on PS0 → 0
PS1 → 0
A
IC power-off
LCD power-off
Operation
Power-on/off
&
PS settings
(serial data)
PS2 → 0
PS4 → 0 (1)
PS2 → 0
PS4 → 0 (1)
SYNC GEN
SYNC GEN
→ 0
→ 0
Fig. 1
1 During IC power-on (default status), the PS mode is activated
(the PS0, PS1, PS2, PS4 and SYNC GEN data are all set to "1").
Therefore, the PS settings should be canceled via serial
communication in accordance with the sequence specifications.
2 When inputting the sync signal from an external source, set serial
data PS4 = 1.
Power supply
VCC/VDD
HVDD/
VVDD
CXA3268AR
LCD
Signal
Fig. 2. System block diagram
– 32 –
CXA3268AR
Control timing (2)
(1) IC power-on (3V, 12V), LCD power-on (HVDD, VVDD)
(2) A settings: after the IC and LCD power supplies have risen
(3) B settings: optional
(4) IC power-off (3V, 12V), LCD power-off (HVDD, VVDD): optional
It is possible to skip from step (2) to step (4) without making the B settings (dotted lines in the figure).
The LCD power supply (HVDD, VVDD) rise timing should adequately satisfy the panel specifications.
Serial data settings other than PS should be made during the control period from the rise of the IC 3V
power supply to (2).
PS (Default) LCD display
Power-on PS OFF
PS
LCD display
PS
Status
PS ON
PS OFF
PS ON Power-off
Supply voltage
&
output signal
LCD power supply
IC 12V
IC 3V
SYNC GEN circuit
PS4 circuit
2
2
PS2 circuit
PS1 circuit
PS0 circuit
1
IC power-on
LCD power-on PS0 → 0
PS1 → 0
A
B
A
B
IC power-off
LCD power-off
Operation
PS0 → 1
PS1 → 1
PS2 → 1
PS0 → 0
PS1 → 0
PS2 → 0
PS0 → 1
PS1 → 1
PS2 → 1
Power-on/off
&
PS settings
(serial data)
PS2 → 0
PS4 → 0 (1) PS4 → 1
PS4 → 0 (1) PS4 → 1
SYNC GEN
SYNC GEN
→ 1
SYNC GEN
SYNC GEN
→ 0
→ 0
→ 1
Fig. 1
1 During IC power-on (default status), the PS mode is activated
(the PS0, PS1, PS2, PS4 and SYNC GEN data are all set to "1").
Therefore, the PS settings should be canceled via serial
communication in accordance with the sequence specifications.
2 When inputting the sync signal from an external source, set serial
data PS4 = 1.
VCC/VDD
Power supply
3V output
POF pin
HVDD/
VVDD
CXA3268AR
SW
LCD
Signal
Fig. 2. System block diagram
– 33 –
CXA3268AR
Control timing (3)
(1) IC power-on (3V)
(2) IC power-on (12V), LCD power-on (HVDD, VVDD): after the IC power supply (3V) has completely risen
(3) A settings: after the IC (12V) and LCD power supplies have risen
(4) B settings: after the PLL has stabilized (stable RPD waveform) and the panel I/O power supply conditions
have been satisfied.
(5) C settings: optional
(6) D settings: after COM/CS, RGB and PSIG have fallen
(7) E settings: 100ms or more after the D settings
(8) IC power-off (12V), LCD power-off (HVDD, VVDD): after the HVDD and VVDD pin voltages have fallen
(9) IC power-off (3V): after the IC power supply (12V) has completely fallen
Serial data settings other than PS should be made during the control period from the rise of the IC 3V
power supply to (3).
The LCD power supply (HVDD, VVDD) rise timing should adequately satisfy the panel specifications.
PS (Default) LCD display
Power-on PS OFF
PS
LCD display
PS OFF
PS
PS ON
PS ON
Power-off
LCD power supply
IC 12V
Status
IC 3V
Supply voltage
&
output signal
SYNC GEN circuit
PS4 circuit
2
2
PS2 circuit
PS1 circuit
PS0 circuit
1
3
4
IC power-on
A
C
A
C
IC power-off
LCD power-on PS0 → 0
PS0 → 1
PS1 → 0
PS2 → 0
PS4 → 0 (1)
SYNC GEN
PS0 → 0
PS1 → 0
PS2 → 0
PS4 → 0
SYNC GEN
PS0 → 1
PS1 → 0
PS2 → 0
PS4 → 0 (1)
SYNC GEN
LCD power-off
PS1 → 0
PS2 → 0
PS4 → 0
SYNC GEN
Operation
Power-on/off
&
PS settings
(serial data)
→ 1
→ 0
→ 1
→ 0
B
D
E
B
D
E
PS0 → 0
PS1 → 0
PS2 → 0
PS4 → 0 (1)
SYNC GEN
→ 0
PS0 → 1
PS1 → 1
PS2 → 0
PS0 → 1
PS1 → 1
PS2 → 1
PS0 → 0
PS1 → 0
PS2 → 0
PS0 → 1
PS1 → 1
PS2 → 0
PS0 → 1
PS1 → 1
PS2 → 1
PS4 → 1
SYNC GEN
→ 1
PS4 → 0 (1) PS4 → 1
SYNC GEN SYNC GEN SYNC GEN SYNC GEN
PS4 → 0 (1) PS4 → 0 (1)
→ 0
→ 1
→ 0
→ 0
Fig. 1
1 During IC power-on (default status), the PS mode is activated
VCC/VDD
Power supply
(the PS0, PS1, PS2, PS4 and SYNC GEN data are all set to "1").
Therefore, the PS settings should be canceled via serial
communication in accordance with the sequence specifications.
2 When inputting the sync signal from an external source, set serial
data PS4 = 1.
3 When raising the power supplies, first raise the IC 3V power
supply, then raise the IC 12V and LCD power supplies.
4 When lowering the power supplies, first lower the LCD and IC
12V power supplies, then lower the IC 3V power supply.
3V output
POF pin
HVDD/
VVDD
CXA3268AR
SW
LCD
Signal
Fig. 2. System block diagram
– 34 –
CXA3268AR
• SLPL
This switches the display system.
D0
0
Display system
NTSC
1
PAL
• SLWD
This switches the display aspect.
D1 Supported aspect
0
1
4:3 display
16:9 display
• SLSH0, SLSH1, SLSH2
These switch the sample-and-hold timing.
SLSH2 SLSH1 SLSH0
Sample-and-hold position
SHS1
D3
D2
D3
0
0
0
0
0
1
SHS2
0
1
0
SHS3
0
1
1
SHS4
1
0
0
SHS5
1
0
1
SHS6
1
1
0
Through (sample-and-hold off)
Through (sample-and-hold off)
1
1
1
• SLRGT
This is the right/left inversion function. This switches the horizontal scan direction of the LCD panel.
D4
0
Scan mode
Normal display (right scan)
1
Right/left inverted display (left scan)
• SLDWN
This is the up/down inversion function. This switches the vertical scan direction of the LCD panel.
D5
0
Scan mode
Normal display (down scan)
Up/down inverted display (up scan)
1
– 35 –
CXA3268AR
• SLEXVD
This switches the external vertical sync signal (VD/Pin 10) input. This is used when not performing sync
separation with the internal sync separation circuit during external separate sync (VD, HD/Pins 10 and 5)
input. Set to "0" during external CSYNC/Pin 5 input.
D6
0
Mode
Other than during external vertical sync signal input
External vertical sync signal input
1
• SLSYP
This switches the input sync polarity. When using the Pin 4 (SYNC OUT) output as the sync signal (when
using the internal sync separation signals), set this to "0".
D7
0
Input polarity
Positive polarity
Negative polarity
1
• SLHDP, SLVDP
These switch the HDO output and VDO output polarity.
D1 Output polarity (VDO)
D0 Output polarity (HDO)
0
1
Positive polarity
Negative polarity
0
1
Positive polarity
Negative polarity
• SLCP1, SLCP2
These switch the clamp position.
D3
0
D2
0
Clamp position
A (Back porch position/when using the internal sync separation signals)
B (Sync position/when using the internal sync separation signals)
C (Back porch position/during external sync signal input)
D (Sync position/during external sync signal input)
0
1
1
0
1
1
2.35µs
2.35µs
SYNC
RPD
2µs
A
2.9µs
2µs
1.3µs
B
C
XCLP
2µs
3.6µs
2µs
1µs
D
Note) When clamp is performed at back porch and sync position, set back porch and sync period of Pins 69,
70, 71 and 72 input signals at pedestal level.
– 36 –
CXA3268AR
• SL4096
This function inverts the output signal polarity every 4096 fields. This further inverts the polarity of the RGB
output that is inverted every 1H for 4096 fields. Normally set to 1H inversion.
D4
0
Mode
1H inversion
1H inversion + 4096 field inversion
1
• SLFR
This function inverts the output signal polarity every field. Normally set to 1H inversion.
D5
0
Mode
1H inversion
1 field inversion
1
• SLFL
This function is used to stop output signal polarity inversion. Normally set to polarity inversion.
D6
0
Mode
Polarity inversion
1
Polarity inversion stopped
• SLTST0, 1, 2, 3, 4
These are the test functions. Set to normal mode.
D0, 1, 2, 3, 4
Mode
Normal mode
Test mode
0
1
• HP1, 2, 3, 4, 5
These set the H position. The horizontal display position is switched by adjusting the HST pulse position using
the input horizontal sync signal as the reference. Adjustment is possible in 1 bit = 2fH increments. (1fH = 1 dot)
Horizontal sync signal
HP: 11111 (LSB)
HP: 10000 (LSB)
HST
HP: 00000 (LSB)
15 steps
(30fH)
16 steps
(32fH)
– 37 –
CXA3268AR
• HDP1, 2, 3, 4, 5
These set the HDO output pulse position. The HDO pulse output position is switched using the input horizontal
sync signal as the reference. Adjustment is possible in 1 bit = 4fH increments. (1fH = 1 dot)
Horizontal sync signal
HDP: 00000 (LSB)
HDO
HDP: 11111 (LSB)
31 steps
(124fH)
– 38 –
CXA3268AR
Application Circuit (RGB input/Y/color difference input, during internal sync separation signal input)
+12V
22k
IN
OUT
To LCD Panel
22k
+12V
Buff
Sample PSIG buffer circuit
+12V
47µ
47µ
1µ
0.68µ
10
47µ
1µ
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
+3V
10
55 VDD
36
G OUT
G DC DET 35
0.68µ
0.01µ
47µ
56
TST11
10
57 OSD B
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
R OUT
R DC DET
B OUT
B DC DET
SIG.C
GND2
TST2
To LCD Panel
0.68µ
3
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
OSD R
OSD G
NC
10
0.68µ
HCK1
HCK2
Vcc1
HST
0.01µ
HDO
To LCD Panel
EN
VDO
0.1µ
VCK
XCLR
RPD
VST
RGT
Vss
1µ
FIL IN
B/B-Y
CKI
0.01µ
0.01µ
0.01µ
1k
B/B-Y
CKO
3.3µ 1000p 33k
G/Y
G/Y
VDD
+12V
10k
30p
2
R/R-Y
10k
VDD
R/R-Y
3.3µ
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
47k
0.01µ 6800p
+3V
1
1
1µ
0.01µ
1k
33k
15k
47µ
0.01µ
+3V
270
To LCD Panel
To Serial Controller
47µ
1µ
1 Resistance value tolerance: ±2%, temperature coefficient: ±200ppm or less
Locate this resistor as close to the IC pin as possible to reduce the effects of external signals.
2 Varicap diode: 1T369 (SONY)
3 Connect to GND when not using OSD input.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 39 –
CXA3268AR
Application Circuit (RGB input/Y/color difference input, during external sync signal input)
+12V
22k
IN
OUT
To LCD Panel
22k
+12V
Buff
Sample PSIG buffer circuit
+12V
47µ
47µ
1µ
0.68µ
10
47µ
1µ
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
+3V
10
55 VDD
36
G OUT
G DC DET 35
0.68µ
0.01µ
47µ
56
TST11
10
57 OSD B
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
To LCD Panel
R OUT
R DC DET
B OUT
B DC DET
SIG.C
GND2
TST2
0.68µ
3
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
OSD R
OSD G
NC
10
0.68µ
HCK1
HCK2
Vcc1
HST
0.01µ
HDO
To LCD Panel
EN
VDO
0.1µ
VCK
XCLR
RPD
VST
RGT
Vss
FIL IN
B/B-Y
CKI
0.01µ
0.01µ
0.01µ
1k
B/B-Y
CKO
3.3µ 1000p 33k
G/Y
G/Y
VDD
+12V
10k
30p
2
R/R-Y
10k
VDD
R/R-Y
3.3µ
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
47k
0.01µ 6800p
+3V
0.01µ
1
1
100k
33k
15k
47µ
0.01µ
+3V
To LCD Panel
To Serial Controller
4
47µ
1µ
CSYNC/HD
VD
1 Resistance value tolerance: ±2%, temperature coefficient: ±200ppm or less
Locate this resistor as close to the IC pin as possible to reduce the effects of external signals.
2 Varicap diode: 1T369 (SONY)
3 Connect to GND when not using OSD input.
4 During CSYNC input, input to Pin 5 only (leave Pin 10 open). During separate sync (HD, VD) input, input to Pins 5 and 10.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 40 –
CXA3268AR
Notes on Operation
(1) This IC contains digital circuits, so the set board pattern must be designed in consideration of undesired
radiation, interference to analog circuits, etc. Care should also be taken for the following items when
designing the pattern.
• The digital and analog IC power supplies should be separated, but the GND and VSS should not be
separated and should use a plain GND (VSS) pattern in order to reduce impedance as much as possible.
The power supplies should also use a plain pattern.
• Use ceramic capacitors for the by-pass capacitors between the power supplies and GND, and connect
these capacitors as close to the pins as possible.
• The resistor connected to Pin 8 should be connected as close to the pin as possible, and the wiring from
the pin to GND should be as short as possible. Also, do not pass other signal lines close to this pin or the
connected resistor.
• The resistor connected to Pin 17 should be located as close to the pin as possible. Also, do not pass
other signal lines close to this pin.
• The capacitors connected to Pins 7 and 42 should be located as close to the LCD panel as possible.
• The PLL block (LPF/VCO) should be compact and located near the IC.
(2) The R/R-Y (Pin 72), G/Y (Pin 71), B/B-Y (Pin 70) and FIL IN (Pin 69) pin input signals are clamped at the
inputs using the capacitors connected to each pin, so these signals should be input at sufficiently low
impedance.
(Input at an impedance of 1kΩ (max.) or less.)
(3) The smoothing capacitor of the DC level control feedback circuit in the capacitor block connected to the
RGB output pins should have a leak current with a small absolute value and variance. Also, when using the
pulse elimination (PAL display, WIDE display) function, the picture quality should be thoroughly evaluated
before deciding the capacitance value of the capacitor.
(4) A thorough study of whether the capacitor connected to the COM output pin satisfies the LCD panel
specifications should be made before deciding the capacitance value.
(5) If this IC is used in connection with a circuit other than an LCD, it may cause that circuit to malfunction
depending on the order in which power is supplied to the circuits. Thoroughly study the consequences of
using this IC with other circuits before deciding on its use.
(6) Since this IC utilizes a C-MOS structure, it may latch up due to excessive noise or power surge greater than
the maximum rating of the I/O pins, or due to interface with the power supply of another circuit, or due to
the order in which power is supplied to circuits. Be sure to take measures against the possibility of latch up.
(7) Be sure to observe the power supply and power saving sequence specifications specified for this IC.
(8) Do not apply a voltage higher than VDD or lower than VSS to I/O pins.
(9) Do not use this IC under operating conditions other than those given.
(10) Absolute maximum rating values should not be exceeded even momentarily. Exceeding ratings may
damage the device, leading to eventual breakdown.
(11) This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should
be taken to prevent electrostatic discharge.
(12) Always connect the VSS, GND1 and GND2/3 pins to the lowest potential applied to this IC; do not leave
these pins open. The voltages applied to the power supply pins should be as follows.
VSS = GND1 = GND2/3 ≤ VDD = VCC1 ≤ VCC2 = VCC3.
– 41 –
CXA3268AR
Package Outline
Unit: mm
72PIN LQFP (PLASTIC)
12.0 ± 0.3
10.0 ± 0.2
14.5 ± 0.2
0.65 ± 0.2
54
39
55
38
72
19
1
18
0.5
A
0.2 ± 0.08
0.15 ± 0.05
0.1
0.08
M
0.1 ± 0.1
0° to 10°
DETAIL A
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
42 ALLOY
SONY CODE
EIAJ CODE
LQFP-72P-L111
P-LQFP72-10X10-0.5
JEDEC CODE
PACKAGE MASS
0.3g
– 42 –
相关型号：
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