CXA3266Q_技术文档

CXA3266Q

PLL IC for LCD Monitor/Projector

Description

48 pin QFP (Plastic)

The CXA3266Q is a PLL IC for LCD monitors/

projectors with built-in phase detector, charge pump,

VCO and counter.

The various internal settings are performed by

serial data via a 3-line bus.

Applicable LCD monitor/projector resolution are

NTSC, PAL, VGA, SVGA, XGA, SXGA and UXGA

etc.

The CXA3266Q is the same package as the

previous CXA3106Q and CXA3106AQ. They have

the same pin configuration excluding Pin 38.

Functions

• Phase detector enable

• UNLOCK output

• Output TTL disable function

• Power saving function (2 steps)

Features

• Supply voltage: 5 ± 0.25V single power supply

• Package: 48-pin QFP

• Power consumption: 328mW

• Sync input frequency: 10 to 120kHz

• Clock output signal frequency: 10 to 203MHz

• Clock delay: 8/32 to 48/32 CLK

• Sync delay: 8/32 to 48/32 CLK

• I/O level: TTL, PECL (complementary)

• Low clock jitter

Applications

• CRT displays

• LCD projectors

• LCD monitors

• Multi-media

• Digital TV

• 1/2 clock output

• TTL output high level control function

Pin Configuration (Top View)

35

32 31

30 29 28 27 26 25

36

34 33

IOGND

VOCLP

PLLVCC

PLLGND

VCOVCC

VCOGND

VCOHGND

IREF

DSYNC

CLK

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

CLKN

CLK/2

CLK/2N

19 DGND

DVCC

18

17

16

15

14

13

UNLOCK

DIVOUT

SEROUT

CS

RC2

RC1

IRGND

IRVCC

TLOAD

9

10 11 12

1

2

3

4

5

6

7

8

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E99426-PS

CXA3266Q

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage

IOVCC, DVCC, TTLVCC, PECLVCC, PLLVCC,

VCOVCC, IRVCC,

–0.5 to +7.0

–0.5 to +0.5

V

IOGND, DGND, TTLGND, VCOHGND, PLLGND,

VCOGND, IRGND

• Input voltage

VCOH, VCOL, SYNCH, SYNCL, VCO, HOLD,

SYNC, SENABLE, SCLK, SDATA, TLOAD, CS, VOCLP IOGND – 0.5 to IOVCC + 0.5 V

RC2

IRGND – 0.5 to IRVCC + 0.5 V

• Output current

SEROUT, DIVOUT, UNLOCK, CLK/2N, CLK/2,

CLKN, CLK, DSYNC, CLK/2L, CLK/2H, CLKL,

CLKH, DSYNCH, DSYNCL, VBB

IREF, RC1

–30 to +30

–2 to +2

mA

°C

• Storage temperature Tstg

• Allowable power dissipation

PD

–65 to +150

860

mW

Recommended Operating Conditions

Min.

4.75

Typ.

Max.

5.25

• Supply voltage

IOV^CC, DVCC, TTLVCC, PECLVCC,

PLLVCC, VCOVCC, IRVCC

IOGND, DGND, TTLGND, VCOHGND,

PLLGND, VCOGND, IRGND

DIN (PECL) ¹H level

5.00

0

V

–0.05

0.05

• Digital input

IOVCC – 1.1

DIN (PECL) ¹L level

DIN (TTL) ²H level

IOVCC – 1.5

V

2.0

DIN (TTL) ²L level

0.8

V

VOCLP (clamp voltage)

TTLGND + 2.4

TTLVCC

V

• SYNC, SYNCH, SYNCL input jitter

• Operating ambient temperature

Ta

ns

–20

+75

°C

1

VCOH, VCOL, SYNCH, SYNCL

2

VCO, HOLD, SYNC, SENABLE, SCLK, SDATA, TLOAD, CS

– 2 –

CXA3266Q

– 3 –

CXA3266Q

Pin No.

1

Symbol

IOV^CC

Description

Reference voltage level

Digital power supply

Digital GND

5V

2

IOGND

VCOH

0V

3

External VCO input

PECL

TTL

4

VCOL

External inverted VCO input

External VCO input

5

VCO

6

HOLD

Phase detector disable signal input

Sync input

TTL

7

SYNCH

SYNCL

SYNC

PECL

TTL

8

Inverted sync input

9

Sync input

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

SENABLE

SCLK

Control signal (enable)

Control signal (clock)

Control signal (data)

Programmable counter test input

Chip select

TTL

SDATA

TLOAD

CS

TTL

SEROUT

DIVOUT

UNLOCK

DV^CC

Register read output

Programmable counter test output

Unlock signal output

Digital power supply

Digital GND

TTL

5V

DGND

CLK/2N

CLK/2

0V

Inverted 1/2 clock output

1/2 clock output

TTL

CLKN

Inverted clock output

Clock output

TTL

CLK

TTL

DSYNC

TTLGND

TTLV^CC

IOGND

PECLV^CC

CLK/2L

CLK/2H

CLKL

Delay sync signal output

TTL output GND

TTL

0V

TTL output power supply

Digital GND

5V

0V

PECL output power supply

Inverted 1/2 clock output

1/2 clock output

5V

PECL

PECLV^CC– 1.7V

5V

Inverted clock output

Clock output

CLKH

DSYNCL

DSYNCH

VBB

Delay sync signal output

Inverted delay sync signal output

PECL reference voltage

PECL output power supply

Digital GND

PECLVCC

IOGND

VOCLP

PLLVCC

PLLGND

VCOVCC

VCOGND

VCOHGND

IREF

0V

TTL high level clamp

PLL circuit analog power supply

PLL circuit analog GND

VCO circuit analog power supply

VCO circuit analog GND

VCO SUB analog GND

Charge pump current preparation

External pin for LPF

IREF analog GND

Clamp voltage

5V

0V

5V

0V

1.2V

2.0 to 4.4V

2.1V

0V

RC2

RC1

IRGND

IRV^CC

IREF analog power supply

5V

– 4 –

CXA3266Q

Pin Description and I/O Pin Equivalent Circuit

No.

Reference

voltage level

Symbol

I/O

Equivalent circuit

Description

Digital power supply.

Ground this pin to the ground pattern

with a 0.1µF ceramic chip capacitor as

close to the pin as possible.

1

IOVCC

—

5V

2

IOGND

DVCC

—

0V

5V

0V

Digital GND.

18

19

25

Digital power supply.

Digital GND.

DGND

TTLGND

TTL output GND.

TTL output power supply.

Ground this pin to the ground pattern

with a 0.1µF ceramic chip capacitor as

close to the pin as possible.

26

27

28

TTLVCC

IOGND

—

5V

0V

5V

Digital GND.

PECL output power supply.

Ground this pin to the ground pattern

with a 0.1µF ceramic chip capacitor as

close to the pin as possible.

PECLVCC

PECL output power supply.

Ground this pin to the ground pattern

with a 0.1µF ceramic chip capacitor as

close to the pin as possible.

36

37

39

40

41

PECLVCC

IOGND

—

5V

0V

5V

0V

5V

Digital GND.

PLL circuit analog power supply.

Ground this pin to the ground pattern

with a 0.1µF ceramic chip capacitor as

close to the pin as possible.

PLLVCC

PLLGND

VCOVCC

PLL circuit analog GND.

VCO circuit analog power supply.

Ground this pin to the ground pattern

with a 0.1µF ceramic chip capacitor as

close to the pin as possible.

42

43

47

VCOGND

VCOHGND

IRGND

—

0V

VCO circuit analog GND.

VCO SUB analog GND.

IREF analog GND.

IREF analog power supply.

Ground this pin to the ground pattern

with a 0.1µF ceramic chip capacitor as

close to the pin as possible.

48

IRVCC

—

5V

– 5 –

CXA3266Q

No.

Reference

voltage level

Symbol

VCOH

I/O

I

Equivalent circuit

Description

External VCO input.

Programmable counter test input

(switchable by a control register).

When using the VCO PECL input,

open the Pin 5 VCO TTL input.

3

PECL

External inverted VCO input.

When open, this pin goes to the PECL

threshold voltage (IOVcc – 1.3V).

Only the Pin 3 VCOH input with VCOL

input open can be also operated but

complementary input is recommended

in order to realize stable high-speed

operation.

IOVCC

4

VCOL

I

14k

500

14k

3

4

7

8

Sync input.

500

When using the SYNCH PECL input,

open the Pin 9 SYNC TTL input.

The sync signal can be switched

between positive/negative polarity by

an internal register.

7

8

SYNCH

SYNCL

PECL

IOGND

Inverted sync input.

When open, this pin goes to the PECL

threshold voltage (IOVcc – 1.3V).

Only the Pin 7 SYNCH input with

SYNCL input open can be also

operated but complementary

input is recommended in order to

realize stable high-speed operation.

– 6 –

CXA3266Q

No.

Reference

voltage level

Symbol

VCO

I/O

I

Equivalent circuit

Description

External VCO input.

Programmable counter test input

(controlled by a control register).

When using the VCO TTL input, open

the Pin 3 VCOH and Pin 4 VCOL

PECL inputs.

5

6

9

TTL

Phase detector disable signal.

Active high. When this pin is high, the

phase detector output is held. This pin

goes to high level when open.

HOLD

SYNC

I

(See the HOLD Timing Chart.)

Sync input.

When using the SYNC TTL input,

open the Pin 7 SYNCH and Pin 8

SYNCL PECL inputs.

The sync signal can be switched

between positive/negative polarity by

an internal register.

IOVCC

40k

192

Control signal (enable) for setting the

internal registers.

When SENABLE is low, registers can

be written; when high, registers can be

read.

5

6

9

10

11

12

13

10

SENABLE

I

TTL

(See the Control Register Table and

Control Timing Chart.)

1.5V

Control signal (clock) for setting the

internal registers.

IOGND

When SENABLE is low, SDATA is

loaded to the registers at the rising

edge of SCLK.

When SENABLE is high, the register

contents are output from SEROUT at

the falling edge of SCLK.

11

SCLK

I

TTL

(See the Control Register Table and

Control Timing Chart.)

Control signal (data) for setting the

internal registers.

(See the Control Register Table and

Control Timing Chart.)

12

13

SDATA

TLOAD

I

TTL

Programmable counter test input.

This pin is normally open status and

high. Register contents can be loaded

immediately to programmable counter

by setting TLOAD low during the

programmable counter test mode.

– 7 –

CXA3266Q

No.

Reference

voltage level

Symbol

I/O

Equivalent circuit

Description

IOVCC

40k

192

Chip select.

When low, all circuits including the

register circuit are set to the power

saving mode.

14

CS

I

TTL

14

When high, all circuits are set to

operating mode.

IOGND

TTLVCC

TTL output high level clamp.

The TTL high level voltage is clamped

at the almost same value with the

voltage applied to this pin.

When this pin is open, TTL output

high level is approximately 2.7V by

dividing the internal resistor.

3k

Clamp

voltage

38

VOCLP

I

38

3.5k

TTLGND

– 8 –

CXA3266Q

No.

Reference

voltage level

Symbol

I/O

O

Equivalent circuit

Description

Register read output.

When SENABLE is high, the register

contents are output from SEROUT at

the falling edge of SCLK.

15

SEROUT

TTL

(See the Control Register Timing

Chart.)

TTL output can be turned ON/OFF

(high impedance) by a control register.

Programmable counter test output.

(See the I/O Timing Chart.)

TTL output can be turned ON/OFF

(high impedance) by a control register.

16

20

21

22

23

DIVOUT

CLK/2N

CLK/2

CLKN

O

TTL

Inverted 1/2 clock output.

(See the I/O Timing Chart.)

TTL output can be turned ON/OFF

(high impedance) by a control register.

IOVCC

TTLVCC

100k

15 22

16 23

1/2 clock output.

(See the I/O Timing Chart.)

TTL output can be turned ON/OFF

(high impedance) by a control register.

20

21

24

TTLGND

Inverted clock output.

(See the I/O Timing Chart.)

TTL output can be turned ON/OFF

(high impedance) by a control register.

IOGND

Clock output.

(See the I/O Timing Chart.)

TTL output can be turned ON/OFF

(high impedance) by a control register.

CLK

Delay sync signal output.

(See the I/O Timing Chart.)

TTL output can be turned ON/OFF

(high impedance) and switched

between positive/negative polarity by

a control register.

24

DSYNC

O

TTL

Unlock signal output.

This pin is an open collector output,

and pulls in the current when a phase

difference occurs. The UNLOCK

sensitivity can be adjusted by

connecting a capacitor and resistors

to this output appropriately.

TTLVCC

17

UNLOCK

O

TTL

17

(See the UNLOCK Timing Chart.)

TTL output can be turned ON/OFF

(high impedance) by a control register.

TTLGND

IOGND

– 9 –

CXA3266Q

No.

Reference

voltage level

Symbol

CLK/2L

I/O

O

Equivalent circuit

Description

Inverted 1/2 clock output.

(See the I/O Timing Chart.)

This pin requires an external pull-

down resistor.

29

30

31

32

33

34

PECL

When not used, connect to PECLVCC

without connecting a pull-down

resistor.

1/2 clock output.

(See the I/O Timing Chart.)

This pin requires an external pull-

down resistor.

When not used, connect to PECLVCC

without connecting a pull-down

resistor.

CLK/2H

O

Inverted clock output.

(See the I/O Timing Chart.)

This pin requires an external pull-

down resistor.

When not used, connect to PECLVCC

without connecting a pull-down

resistor.

IOVCC

PECLV^CC

CLKL

Clock output.

30 32 34

33

(See the I/O Timing Chart.)

This pin requires an external pull-

down resistor.

When not used, connect to PECLVCC

without connecting a pull-down

resistor.

29 31

CLKH

IOGND

Delay sync signal output.

(See the I/O Timing Chart.)

This pin requires an external pull-

down resistor.

When not used, connect to PECLVCC

without connecting a pull-down

resistor.

DSYNCL

DSYNCH

Inverted delay sync signal output.

(See the I/O Timing Chart.)

This pin requires an external pull-

down resistor.

When not used, connect to PECLVCC

without connecting a pull-down

resistor.

– 10 –

CXA3266Q

No.

Reference

voltage level

Symbol

I/O

Equivalent circuit

Description

PECLVCC

PECL reference voltage.

When used, ground this pin to the

ground pattern with a 0.1µF ceramic

chip capacitor as close to the pin as

possible.

PECLV^CC

–1.7V

35

VBB

O

35

IOGND

IRVCC

Charge pump current preparation.

Connect to GND via an external

resistor (3.0kΩ).

Ground this pin to the ground pattern

with a 0.1µF ceramic chip capacitor

as close to the pin as possible.

44

IREF

—

1.2V

44

IRGND

IOGND

External pin for LPF.

See the Recommended Operating

Circuit for the external circuits. Note

that external resistors and capacitors

should be metal film resistors and

temperature compensation capacitors

which are relatively unaffected by

temperature change.

IRV^CC

2.0

to

4.4V

RC2

RC1

45

46

—

46

45

External pin for LPF.

See the Recommended Operating

Circuit for the external circuits.

IRGND

IOGND

2.1V

– 11 –

CXA3266Q

– 12 –

CXA3266Q

Electrical Characteristics

(Ta = 25°C, VCC = 5V, GND = 0V)

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

Current consumption (excluding output current)

Current consumption 1

Current consumption 2

Current consumption 3

Digital input

ICC1

ICC2

ICC3

CS = H, Synth Power = 1

CS = H, Synth Power = 0

CS = L

51.0

9.0

65.5

13.0

1.5

79.0

16.0

1.8

mA

1.2

Digital high level input

voltage (PECL)

IOV^CC

–1.15

VIH1

VIL1

VIO

V

Digital low level input

voltage (PECL)

IOVCC

–1.5

VCOL, SYNCL input open

voltage (PECL)

IOVCC

–1.3

V

Digital high level input

current (PECL)

IIH1

I^IL1

VIH = IOVCC – 0.8V

V^IL= IOVCC – 1.6V

–100

–200

2.0

100

0

µA

V

Digital low level input

current (PECL)

Digital high level input

voltage (TTL)

VIH2

VIL2

IIH2

IIL2

Digital low level input

voltage (TTL)

0.8

–5

0

V

Digital high level input

current (TTL)

VIH = 3.5V

VIL = 0.2V

–10

–20

µA

Digital low level input

current (TTL)

HOLD characteristics

RC1 input pin leak current Ileak

1.00

nA

ns

HOLD signal set-up time

HOLD signal hold time

Digital output

Ths

Thh

20

Digital high level output

voltage (PECL)

PECLV^CC

–1.6

VOH1

V^OL1

VBB

VOH2

VOL2

RL = 330Ω

CL = 10pF

V

Digital low level output

voltage (PECL)

PECLVCC

–1.8

PECL output reference

voltage

PECLVCC

–1.7

Digital high level output

voltage (TTL)

2.4

Digital low level output

voltage (TTL)

0.5

– 13 –

CXA3266Q

Item

Symbol

Iunlock

Fin

Conditions

Min.

–30

10

Typ.

Max.

120

Unit

mA

UNLOCK output

UNLOCK output current

SYNC input

SYNC input frequency range

DSYNC output

kHz

DSYNC output coarse

delay time setting

resolution (upper)

Rdsync1

Td1

2

6

bit

CLK

bit

DSYNC output coarse

delay time (upper)

2

5

DSYNC output fine delay

time setting resolution

(lower)

Rdsync2

DSYNC output fine delay

time (lower)

Td2

Td9

8/32

4

48/32

5

CLK

DSYNC output DIVOUT

output delay time

VCO characteristics

DIV output frequency

operation range 1

FVCO1

FVCO2

FVCO3

FVCO4

DIV = 1/1

40

20

10

5

203

100

50

MHz

DIV output frequency

operation range 2

DIV = 1/2

DIV = 1/4

DIV = 1/8

DIV output frequency

operation range 3

DIV output frequency

operation range 4

25

VCO lock range

VCO gain 1

VCO gain 2

VCO gain 3

VCO gain 4

Vlock

KVCO1

KVCO2

KVCO3

KVCO4

2.0

300

150

75

4.4

700

350

175

87.5

V

DIV = 1/1

DIV = 1/2

DIV = 1/4

DIV = 1/8

480

240

120

60

Mrad/sv

37.5

C.Pump Bit = 00,

IREF = 3.0kΩ

Charge pump current 1

Charge pump current 2

Charge pump current 3

Kpd1

Kpd2

Kpd3

62.5

125

250

500

100

200

400

137.5

275

µA

C.Pump Bit = 01,

IREF = 3.0kΩ

C.Pump Bit = 10,

IREF = 3.0kΩ

550

µA

bit

C.Pump Bit = 11,

IREF = 3.0kΩ

Change pump current 4

VCO counter bits

Kpd4

Rdiv2

800

12

1100

– 14 –

CXA3266Q

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

CLK (CLK, CLK/2) output

CLK output (PECL)

frequency range 1

Fclk1PECL DIV = 1/1

Fclk2PECL DIV = 1/2

Fclk3PECL DIV = 1/4

Fclk4PECL DIV = 1/8

40

20

10

5

203

100

50

MHz

ns

CLK output (PECL)

frequency range 2

CLK output (PECL)

frequency range 3

CLK output (PECL)

frequency range 4

25

CLK, CLK/2 output (PECL)

rise time

10% to 90%,

RL = 330Ω

TrPECL

TfPECL

1.0

40

20

10

5

2.0

3.0

100

50

CLK, CLK/2 output (PECL)

fall time

10% to 90%,

RL = 330Ω

ns

CLK output (TTL)

frequency range 1

Fclk1TTL DIV = 1/1

Fclk2TTL DIV = 1/2

Fclk3TTL DIV = 1/4

Fclk4TTL DIV = 1/8

MHz

ns

CLK output (TTL)

frequency range 2

CLK output (TTL)

frequency range 3

CLK output (TTL)

frequency range 4

25

CLK, CLK/2 output (TTL)

rise time

10% to 90%,

CL = 10pF

TrTTL

TfTTL

Dclk2

0.8

40

1.1

50

1.6

60

CLK, CLK/2 output (TTL)

fall time

10% to 90%,

CL = 10pF

ns

CLK output (PECL, TTL)

duty

CL = 10pF

%

SYNC input (PECL) and

CLK output (PECL) delay

offset

Td3

Td4

Td5

Td8

1.0

0.3

1.8

1.6

2.0

0.7

2.5

2.2

3.0

1.1

3.2

ns

CLK output (PECL) and

DSYNC output (PECL)

phase difference

CL = 10pF

CLK output (PECL) and

CLK/2 output (PECL)

phase difference

DSYNC, CLK, CLK/2

output (PECL) and TTL

output phase difference

– 15 –

CXA3266Q

Item

Symbol

Tj1p-p

Tj2p-p

Tj3p-p

Tj4p-p

Tj5p-p

Conditions

Min.

1.8

1.2

1.0

0.9

0.7

0.5

Typ.

2.5

1.5

1.4

1.3

1.0

0.8

Max.

4.0

1.9

1.7

1.6

1.4

Unit

CLK (CLK, CLK/2) output

triggered at SYNC

Fsync = 15.73kHz

Fclk = 12.27MHz

N = 780

CLK vs. SYNC output jitter

(NTSC)

ns

triggered at SYNC

Fsync = 31.47kHz

Fclk = 25.18MHz

N = 800

CLK vs. SYNC output jitter

(VGA)

triggered at SYNC

Fsync = 48.08kHz

Fclk = 50.00MHz

N = 1040

CLK vs. SYNC output jitter

(SVGA)

triggered at SYNC

Fsync = 56.48kHz

Fclk = 75.00MHz

N = 1328

CLK vs. SYNC output jitter

(XGA)

triggered at SYNC

Fsync = 80kHz

Fclk = 136.00MHz

N = 1700

CLK vs. SYNC output jitter

(SXGA)

triggered at SYNC

Fsync = 93.75kHz

Fclk = 202.50MHz

N = 2160

CLK vs. SYNC output jitter

(UXGA)

Tj6p-p

Tj7p-p

1.0

0.1

12

ns

CLK vs. DSYNC output jitter

Control registers

triggered at DSYNC

SCLK frequency

SCLK

TENS

TENH

TDS

in write/read mode

in write mode

in read mode

MHz

ns

SENABLE set-up time

SENABLE hold time

SDATA set-up time

SDATA hold time

3

0

3

0

3

0

ns

TDH

ns

SENABLE set-up time

SENABLE hold time

TNENS

TNENH

ns

– 16 –

CXA3266Q

Description of Block Diagram

Sync Input

Sync signals in the range of 10 to 120kHz can be input. Input supports both positive and negative polarity.

PECL input can also be a single input.

When SYNC is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal.

When SYNC is negative polarity, the clock is regenerated in synchronization with the falling edge of the sync signal.

VCO oscillation stops when there is no sync input.

0

1

Register: SYNC POL

SYNC input polarity

Negative

Positive

Phase Detector

The phase detector operates at the sync input frequency of 10 to 120kHz. The PD input polarity should be

set to the default PD POL = 1. Phase comparison is performed at the edges.

The input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped

at the front end of the CXA3266Q when inputting a noisy signal.

The phase detector HOLD signal is supplied by TTL. (See the HOLD Timing Chart.)

The PLL UNLOCK signal is output by an open collector.

(See the UNLOCK Timing Chart.)

Charge Pump

The gain (I, I/2, I/4, I/8) can be varied by changing the charge pump current using 2 bits of control register.

0

1

Register: C.Pump bit 1

Register: C.Pump bit 0

Charge pump current

1

0

1

400µA

800µA

100µA

200µA

LPF

This is a loop filter comprised of the external capacitors and resistor.

Be sure to use metal film resistors with little temperature variation and a temperature-compensated capacitor.

In particular, the 0.068µF capacitor should be equivalent to high dielectric constant series capacitor type B or

better. (electrostatic capacitance change ratio ±10%: T = –25 to +85°C)

VCO

The VCO oscillator frequency covers from 40 to 203MHz.

VCO Rear-end Counter

The VCO output is frequency divided to 1/1, 1/2, 1/4 or 1/8 by switching 2 bits of control register.

The operating range can be expanded to 5 to 203MHz by combining the counter with a VCO frequency divider.

0

Register: DIV 1, 2, 4, 8 bit 1

Register: DIV 1, 2, 4, 8 bit 0

Counter frequency divisions

0

1

0

1

1/2

1/4

1/8

1/1

– 17 –

CXA3266Q

Feedback Programmable Counter

This counter can be set as desired from 256 to 4096 using 12 bits.

Frequency divisions = (m + 1) × 8 + n, n: 3 bits (VCO DIV bits 0 to 2), m: 9 bits (VCO DIV bits 3 to 11)

When the register value is changed, the new setting is actually loaded to the counter when the counter value

becomes "all 0".

Clock Output

When SYNC input is positive polarity, the clock is regenerated in synchronization with the rising edge of the

sync signal.

The clock output delay time can be changed in the range of 8/32 to 48/32 CLK using 6 bits of control register.

(See the I/O Timing Chart.)

Output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL

output can also be turned off independently.

0

1

Register: Clock Enable

Clock output status

OFF

ON

1/2 Clock Output

Reset is performed at the delay sync timing and the clock output is frequency divided by 1/2. (See the I/O

Timing Chart.)

Both odd and even output are TTL and PECL output. TTL output can also be turned off independently.

0

1

Register: Clock Enable

Clock output status

OFF

ON

Delay Sync Output

The front edge of the delay sync pulse is latched by the pulse obtained by frequency dividing the CLK

regenerated by the PLL, so there is almost no jitter with respect to CLK. This front edge can be used as the

reset signal for the system timing circuit.

The rear edge of the delay sync pulse is latched by the CLK regenerated by the PLL. This relationship is

undefined for one clock as shown in the Timing Chart.

The delay sync output delay time can be varied in two stages. First, the delay time can be varied in the range

of 8/32 to 48/32 CLK using 6 bits of control register, and then in the range of 2 to 5 CLK using 2 bits of

control register. In other words, the total delay time is ((8/32 to 48/32) + (2 to 5)) CLK. (See the I/O Timing

Chart.)

DSYNC output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock

TTL output can also be turned off.

0

1

Register: Clock Enable

Clock output status

OFF

ON

Lower delay line

FINE DELAY bits 0 to 5

000111

001000

· · · · · · · · · · · ·

101111

Delay time

9/32CLK

48/32CLK

8/32CLK

Upper delay line

COARSE DELAY bits 0 to 1

00

01

10

11

Delay time

3CLK

4CLK

5CLK

2CLK

0

1

Register: DSYNC POL

DSYNC output polarity

Negative

Positive

– 18 –

CXA3266Q

Programmable Counter TTL Output Switching

Output (PECL, TTL) from DSYNC output is possible by switching of control register.

1

0

Register: DSYNC By-pass

Output status from DSYNC

DSYNC output

DIVOUT output

Delay Sync Output Width (DSYNC By-pass = 0)

Delay sync output pulse width can be varied to 1, 2, 4, or 8CLK by switching 2 bits of control register.

01

10

11

00

Register: DSYNC WIDTH

DSYNC width

2CLK

4CLK

8CLK

1CLK

Delay Sync Output Delay (DSYNC By-pass = 0)

DIVOUT output delay from delay sync output can be varied to 4 or 5CLK by switching of control register.

1

0

Register: DSYNC DELAY

Delay time

5CLK

4CLK

DSYNC Output Switching during HOLD

By switching with a control register, DSYNC output during HOLD period is controlled. Its output status is

different according to DSYNC By-pass, DSYNC POL and HOLD signals of the register. The output for each

setting is shown below.

Output from

DSYNC (Pin 24) and

DSYNCH (Pin 34)

Register

DSYNC POL

Register

DSYNC Hold DSYNC By-pass

Register

Pin 6 HOLD

H

L

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H

DIVOUT

L

H

L

DIVOUT

H

L

DSYNC

L

H

L

DSYNC

DIVOUT

DSYNC

H

L

H

L

H

L

H

L

– 19 –

CXA3266Q

Control Circuit (3-bit address, 8-bit data)

The timing and input methods are described hereafter.

Feedback programmable counter control

VCO rear-end counter control

Fine delay line control

REGISTER1, 2 12bit VCODIV Bit0 to 11

REGISTER3

REGISTER4

REGISTER5

2bit DIV1, 2, 4, 8 Bit0, Bit1

6bit FINE DELAY Bit0 to 5

2bit COARSE DELAY Bit0, Bit1

2bit C.Pump Bit0, Bit1

1bit PD POL

Coarse delay line control

Charge pump current DAC control

Phase detector input positive/negative polarity control REGISTER5

Delay sync output width control

REGISTER5

REGISTER6

REGISTER7

2bit DSYNC WIDTH

1bit DSYNC DELAY

1bit SYNC POL

Delay sync output delay control

Sync input positive/negative polarity control

Delay sync output positive/negative polarity control

Clock TTL output OFF function

1bit DSYNC POL

1bit CLK Enable

Inverted clock TTL output OFF function

1/2 clock TTL output OFF function

1bit NCLK Enable

1bit CLK/2 Enable

1bit NCLK/2 Enable

1bit DSYNC Enable

1bit UNLOCK Enable

1bit VCO By-pass

1bit Synth power

Inverted 1/2 clock TTL output OFF function

Delay sync TTL output OFF function

UNLOCK output OFF function

Programmable counter input switching

Power save with register contents held

Register read function power ON/OFF

Programmable counter TTL output OFF function

Programmable counter TTL output switching

Delay sync output hold function

1bit Read out power

1bit DIVOUT Enable

1bit DSYNC By-pass

1bit DSYNC Hold

Power Save

The CXA3266Q realizes 2-step power saving (all OFF, control registers only ON). This is controlled by a

control register and the chip selector.

Step 1: Chip selector control

L

H

CS

Power saving status

All OFF

Power ON

Step 2: Control register control

0

1

Register: Synth power

Power saving status

Control registers only ON

Power ON

Readout Circuit (during test mode)

The control register contents can be read by serial data from SEROUT.

(See the Control Register Timing Chart.)

Register: Read out power

Readout status

1

0

Function OFF

Function ON

– 20 –

CXA3266Q

Programmable Counter Output (during test mode)

The programmable counter output is TTL output from the DIVOUT pin.

(See the I/O Timing Chart.)

This output is normally not used.

Register: DIVOUT Enable

DIVOUT output status

1

0

ON

OFF

TLOAD input (during test mode)

This control signal forcibly loads the control register contents to the programmable counter.

This signal is normally not used.

TLOAD

L

H

Forced load control status

Function OFF

Function ON

VCO input (during test mode)

This is the programmable counter test signal input pin.

This pin can be switched internally by the MUX circuit.

TTL and PECL input are possible.

This pin is normally not used.

Register: VCO By-pass

Input status

0

1

Internal VCO External input

– 21 –

CXA3266Q

Control Register Timing

1) Write mode

Many functions of the CXA3266Q can be controlled via a program. Characteristics are changed by setting the

internal control register values via a serial interface comprised of three pins: SENABLE (Pin 10), SCLK (Pin

11) and SDATA (Pin 12). The write timing diagram is shown below.

Input the 8-bit data and 3-bit register address MSB first to the SDATA pin. Some registers are not 8 bits, but

the data is input aligned with the LSB side in these cases. (See the Register Table.)

SENABLE is the enable signal and is active low. SCLK is the transfer clock signal, and data is loaded to the

IC at the rising edge. When SENABLE rises, SCLK must be high. (Registers are set at the rising edge of

SENABLE.) When SENABLE falls, SCLK may be either high or low.

SENABLE

8bit

3bit

SDATA

SCLK

DATA

ADDRESS

Enlarged

TENS

TENH

SENABLE

SDATA

SCLK

TDS TDH

For example, when inputting a 16-bit signal, the initial 5 bits are invalid and the latter 11 bits are valid. This is

to say that the latter 11 bits are loaded to the register.

SENABLE

5bit

8bit

3bit

SDATA

SCLK

Invalid DATA

DATA

address

– 22 –

CXA3266Q

The settings of the frequency divider (2 bits, DIV1, 2, 4, 8) and programmable counter (12 bits, VCODIV) at

the rear end of the VCO are transferred in the order shown below. (The data will be set when the three

registers are transferred.)

First DIVREG2, CENFREREG and DIVREG1 are set, and then the data is transferred independently at the

timings shown below.

DIVREG2 (upper 4 bits of VCODIV)

↓

CENFREREG (2 bits of DIV1, 2, 4, 8)

↓

DIVREG1 (lower 8 bits of VCODIV)

All three of the above registers must be changed even when changing only (2 bits of DIV1, 2, 4, 8). This is

the same when changing only (12 bits of VCODIV).

SENABLE

SDATA

SCLK

DIVREG2

CENFREREG

DIVREG1

– 23 –

CXA3266Q

2) Read mode

Data can be transferred from the shift register to the data register only when SENABLE is high.

Binary data can be read from the data register by inputting SCLK when SENABLE is high. Data is loaded

from the data register to the SCAN PATH circuit each time one clock is input to SCLK, and is output

sequentially from the register read no. 1 data (VCODIV bit 7) through the SEROUT pin. When the 42nd

SCLK clock pulse is input, the register read no. 42 data (VCO By-pass) is output. Then, when the 43rd clock

pulse is input to SCLK, the output returns to the register read no. 1 data (VCODIV bit 7) and the data output

is repeated. Also, the data output from the SCAN PATH circuit is automatically reloaded even when the shift

register data is changed during data output.

Note) Since all registers do not have 8 bits, only the valid bits of each register are loaded to the SCAN PATH

circuit. (See the Control Register Table for the actual register read no.)

SCLK

CLK

NEN

I/P SHIFT REGISTER, 11 BITS

8 BIT DATA 3 BIT ADDRESS

7 DATA REGISTERS (42 LATCHES).

REGISTERS ARE DIFFERENT LENGTHS

UP TO 8 BIT

TR

SENABLE

EN

SEROUT

CLK

SCAN PATH, 1 ELEMENT PER REGISTER BIT

Block Diagram during Read Mode

TNENS

TNENH

SENA

READ NO. 1

READ NO. 2

2

READ NO. N

SEROUT

1

N

SCLK

Timing Chart during Read Mode

– 24 –

CXA3266Q

– 25 –

CXA3266Q

– 26 –

CXA3266Q

– 27 –

CXA3266Q

– 28 –

CXA3266Q

2. HOLD timing

SYNC input

(SYNC POL = 1)

SYNC input

(SYNC POL = 0)

DIVOUT output

(TTL)

Thh Ths

Thold

HOLD input

(TTL)

The phase comparison output is held and fixed VCO output frequency is output.

CLK output

HOLD signal set-up time (Ths) is a time from the rising edge of HOLD signal to the falling edge of DIVOUT.

Or, when SYNC POL = 1, it is a time from the falling edge of HOLD signal to the rising edge of SYNC; when

SYNC POL = 0, it is the time from the falling edge of HOLD signal to the falling edge of SYNC.

HOLD signal hold time (Thh) is the time from the falling edge of DIVOUT to falling edge of HOLD signal. Or,

when SYNC POL = 1, it is the time from the rising edge of SYNC to the rising edge of HOLD signal; when

SYNC POL = 0, it is the time from the falling edge of SYNC to the rising edge of HOLD signal.

When the HOLD input is held, the CLK frequency fluctuation can be calculated as follows.

∆V

+Q –Q

I

C

SW

∆f

VCO

Ileak

SW

I

C · ∆V = Q = Ileak · Thold

C:

Loop filter capacitance

Voltage variation due to leak current

∆V:

Ileak: Internal amplifier leak current

Thold: Hold time

∆V = Ileak · Thold/C

∆f = ∆V · KVCO = Ileak · Thold/C · KVCO

For example, assuming f = 100MHz, Ileak = 1nA, Thold = 1ms, C = 0.068µF, and KVCO = 2π · 75MHz, then:

∆V = 1 × 10^–9· 1 × 10^–3/(0.068 × 10^–6) = 15 × 10^–6[V]

∆f = 1 × 10^–9· 1 × 10^–3/(0.068 × 10^–6) · 75 × 10⁶= 1125 [Hz]

– 29 –

CXA3266Q

3. Relationship between SYNC input and DSYNC output during HOLD

DSYNC

internal signal

SYNC

internal signal

J

Q

DIVOUTN

internal signal

K

CK

CLK

When the above SYNC internal and DIVOUTN internal signals are input, the DSYNC internal signal is output

as shown in the table below.

1. DSYNC = L when SYNC = L and DIVOUTN = L.

2. DSYNC = H or L (unchanged with the previous data) when SYNC = H and DIVOUTN = L.

3. DSYNC = H when DIVOUTN = H (SYNC = H or L)

SYNC

DIVOUTN

J

L

H

L

K

L

Q

L

Q

L

DSYNC

L

(1)

(2)

(3)

(4)

(5)

(6)

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

( ) is unchanged with the previous data.

SYNC

internal signal

DIVOUTN

internal signal

DSYNC

internal signal

(1)

(5)

(6)

(4) (2)

(3)

– 30 –

CXA3266Q

During HOLD, the output from DSYNC can be controlled by register DSYNC hold. Its output status differs

according to the DSYNC polarity or DSYNC By-pass switching. The below diagrams show the relationship with

DSYNC output for each SYNC input.

(DSYNC POL = 1 for all of CASE1 to CASE3.)

CASE1

HSYNC

(SYNC POL = 1)

HOLD input

(1) During DSYNC

HOLD ON

(DSYNC Hold = 1)

DSYNC By-pass = 1

DSYNC By-pass = 0

(2) During DSYNC

HOLD OFF

(DSYNC Hold = 0)

DSYNC By-pass = 1

DSYNC By-pass = 0

CASE2

HSYNC

(SYNC POL = 1)

HOLD input

(1) During DSYNC

HOLD ON

(DSYNC Hold = 1)

DSYNC By-pass = 1

DSYNC By-pass = 0

(2) During DSYNC

HOLD OFF

(DSYNC Hold = 0)

DSYNC By-pass = 1

DSYNC By-pass = 0

– 31 –

CXA3266Q

CASE3

HSYNC

(SYNC POL = 1)

HOLD input

(1) During DSYNC

HOLD ON

(DSYNC Hold = 1)

DSYNC By-pass = 1

DSYNC By-pass = 0

(2) During DSYNC

HOLD OFF

(DSYNC Hold = 0)

DSYNC By-pass = 1

DSYNC By-pass = 0

– 32 –

CXA3266Q

4. UNLOCK timing

Inside the IC Outside the IC

VCC

I2

R2

C

R1

I1

UNLOCK

S2

S1

unlock

detect

Signal from phase

comparator

The unlock detect output is an open collector. When unlock detect output S1 goes high, the current I1 is pulled in.

The UNLOCK sensitivity can be adjusted by connecting external resistors (R1, R2) and a capacitor (C) to this output

pin appropriately and changing these values. Operation during three modes is described below.

CASE 1: When there is no phase difference, that is to say, when the PLL is locked.

The S1 signal is low and the S2 signal is high.

The UNLOCK output remains low.

S1

S2

threshold

level

UNLOCK

CASE 2: When there is a phase difference, that is to say, when the S1 signal goes high and low as shown in

the figure below, the fall slew rate of the S2 signal is determined by the current I1 flowing into that

open collector. Therefore, increasing the resistance R1 causes the S2 signal fall slew rate to

become slower. Also, since the S2 signal rise slew rate is determined by the current I2, reducing

the resistance R2 causes the S2 signal rise slew rate to become faster. If this integrated S2 signal

does not fall below the threshold level of the next inverter, the UNLOCK signal stays low, and the

PLL is said to be locked.

S1

S2

threshold

level

UNLOCK

CASE 3: However, even if a phase difference exists as shown above, if the resistance R1 is reduced, the

current I1 flowing into the open collector increases, and the S2 signal fall slew rate becomes faster.

Also, if the resistance R2 is increased, the S2 signal rise slew rate becomes slower. If this

integrated S2 signal falls below the threshold level of the next inverter, the UNLOCK signal goes

from low to high, and the PLL is said to be unlocked.

S1

threshold

level

S2

UNLOCK

– 33 –

CXA3266Q

Charge Pump and Loop Filter Settings

The CXA3266Q's charge pump is a constant-current output type as shown below.

When a constant-current output charge pump circuit is used inside the PLL,

the phase detector output acts as a current source, and the dimension of its

transmittance KPD is A/rad. Also, when considering the VCO input as a

voltage, the LPF transmittance dimension must be expressed in ohms (Ω =

V/A).

VCC

S1

S2

To LPF

Therefore, the PLL transmittance when a constant-current output charge

pump circuit is used is as follows.

LPF

VCO

PD

ω

0

θr

r

KPD

(A/rad)

F (S)

(Ω)

KVCO

(rad/sV)

1/S

+

–

θo

N

counter

1/N

1/S

ω /N

0

The PLL closed loop transmittance is obtained by the following formula.

θo/N

θr

KPD · F (S) · KVCO · 1/N · 1/S

1 + KPD · F (S) · KVCO · 1/N · 1/S

=

... (1)

Here, KPD, F (S), and KVCO are:

KPD: Phase comparator gain (A/rad)

F (S): Loop filter transmittance (Ω)

KVCO: VCO gain

(rad/sV)

¹The reason for the 1/S inside the phase detector is as follows.

t

θo (t)/N = o ω0 (t)/Ndt + θo (t = 0)/N ... (a)

∫

If θo (t = 0) = 0,

t

θo (t)/N =

∫

o ω0 (t)/Ndt ... (b)

Performing Laplace conversion:

1

s

θo (S)/N =

W0 (S)/N ... (c)

– 34 –

CXA3266Q

The loop filter F (s) is described below.

The loop filter smoothes the output pulse from the phase comparator and inputs it as the DC component to the

VCO. In addition to this, however, the loop filter also plays an important element in determining the PLL

response characteristics.

Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the CXA3266Q's

LPF is a current input type active filter as shown below, so the following calculations show an actual example

of deriving the PLL closed loop transmittance when using this type of filter and then using this transmittance to

create a formula for setting the filter constants.

Current input type active filter

C

R

ii

Vo

–A

–1

–Vo

The filter transmittance is as follows.

The Bode diagram for formula (2) is as follows.

VO

A

1

SC

+ VO = (R +

)

1

τ

1 + SRC

A

1 + A

F (S) =

=

·

SC

log w

1 + Sτ

SC

A

1 + A

·

log w

τ = RC

0

Here, assuming A > 1, then:

–45deg

1 + Sτ

SC

...........................

F (S) =

(2)

–90

Next, substituting (2) into (1) and obtaining the overall closed loop transmittance for the PLL:

KPD · KVCO · τ

KPD · KVCO

NC

· S +

NC

θo/N

θr

...

=

(3)

KPD · KVCO · τ

KPD · KVCO

S²+

· S +

NC

2ζωnS + ωn²

S²+ 2ζωnS + ωn²

............................................

(4)

(5)

(6)

KPD · KVCO

......................................................

ωn =

√

NC

1

2

.................................................................

– 35 –

ζ =

ωnτ

CXA3266Q

Here, ωn and ζ are as follows.

ωn characteristic angular frequency:

The oscillatory angular frequency when PLL oscillation is assumed to have been maintained by the loop filter

and individual loop gains is called the characteristic angular frequency: ωn.

ζ damping factor:

This is the PLL transient response characteristic, and serves as a measure of the PLL stability. It is

determined by the loop gain and the loop filter.

A capacitor C2 is added to the actual loop filter.

This added capacitor C2 is used to reduce the R noise, and a value of around 1/10 to 1/1000 of C1 should be

selected as necessary.

Current input type active filter with added capacitor C2

C2

C1

R

ii

Vo

–A

–1

–Vo

The filter transmittance is as follows.

The Bode diagram for formula (7) is as follows.

1 + C1 · R · S

F (S) =

S ((C1 + C2) + C1 · C2 · R · S)

1

1 + τ1 · S

S (C1 + C2) (1 + τ2 · S)

..................

=

(7)

τ1

τ2

log w

τ1 = C1 · R

C1 · C2 · R

τ2 =

C1 + C2

log w

0

–45deg

Here, assuming C2 = C1/100, then:

C1 · C1/100 · R

τ2 =

–90

C1 + C1/100

1

101

=

C1 · R

1

101

τ1

– 36 –

CXA3266Q

Next, the various parameters inside an actual CXA3266Q are obtained.

The CXA3266Q's charge pump output block and the LPF circuit are as follows.

C2

R1 C1

46

45

CXA3266Q

To VCO

VCC

333

100µA

or 200µA

or 400µA

or 800µA

S1

S2

100µA

or 200µA

or 400µA

or 800µA

20k

100

First, KPD is as follows.

KPD = 100µ/2π or 200µ/2π or 400µ/2π or 800µ/2 π (A/rad)

Typical KVCO characteristics curves for the CXA3266Q's internal VCO are as follows.

250

VCO DIV = 1/1

200

150

VCO DIV = 1/2

100

50

0

VCO DIV = 1/4

VCO DIV = 1/8

2

3

4

VCO input voltage [V]

Therefore, KVCO is as follows.

KVCO = 2π · 75M or 2π · 37.5M or 2π · 18.75M or 2π · 9.375M (rad/sV)

– 37 –

CXA3266Q

ωn and ζ calculated for various types of computer signals are shown below.

Here, the various parameters are as follows.

FSYNC: Input H sync frequency

FCLK: Output clock frequency

KPD × 2π: Phase comparator gain × 2π (KPD × 2π = +100 or 200 or 400 or 800)

KVCO/2π: VCO gain

(when VCO DIV = 1/1, KVCO/2π = 75)

(when VCO DIV = 1/2, KVCO/2π = 75/2)

(when VCO DIV = 1/4, KVCO/2π = 75/4)

(when VCO DIV = 1/8, KVCO/2π = 75/8)

N: Counter value

C1: Loop filter capacitance value

R1: Loop filter resistance value

KPD C.Pump

× 2π setting

DIV1, 2, 4, 8

setting setting

N

KVCO/2π

C1 R1

ωn

µF kΩ kHzrad kHz

fn

ζ

MODE Resolution HSYNC FCLK

kHz

MHz µA Bit1 Bit0 M/(S × V) Bit1 Bit0

NTSC

PAL

15.73 12.27 400

15.73 18.41 400

15.73 24.55 800

15.63 14.69 400

15.63 22.03 800

15.63 29.38 400

1

0

1

0

1

0

1

75/8

75/4

75/8

75/4

75/2

75/1

1

0

1

0

1

0

1

0

780 0.068 3.0 8.41 1.34 0.86

1170 0.068 3.0 6.87 1.09 0.70

1560 0.068 3.0 8.41 1.34 0.86

940 0.068 3.0 7.66 1.22 0.78

1410 0.068 3.0 8.84 1.41 0.90

1880 0.068 3.0 7.66 1.22 0.78

848 0.068 3.0 8.06 1.28 0.82

800 0.068 3.0 8.30 1.32 0.85

864 0.068 3.0 11.30 1.80 1.15

832 0.068 3.0 11.51 1.83 1.17

1024 0.068 3.0 10.38 1.65 1.06

1056 0.068 3.0 10.22 1.63 1.04

1040 0.068 3.0 10.30 1.64 1.05

1048 0.068 3.0 14.51 2.31 1.48

1152 0.068 3.0 13.84 2.20 1.41

1344 0.068 3.0 12.81 2.04 1.31

1328 0.068 3.0 12.89 2.05 1.31

1312 0.068 3.0 12.97 2.06 1.32

1328 0.068 3.0 12.89 2.05 1.31

1376 0.068 3.0 12.66 2.02 1.29

1696 0.068 3.0 11.40 1.82 1.16

1688 0.068 3.0 16.17 2.57 1.65

1722 0.068 3.0 16.01 2.55 1.63

2160 0.068 3.0 20.21 3.22 2.06

PAL

PC-98 640 × 400 24.82 21.05 400

VGA 640 × 480 31.47 25.18 400

MAC 640 × 480 35.00 30.24 400

VESA 640 × 480 37.86 31.50 400

SVGA 800 × 600 35.16 36.00 400

SVGA 800 × 600 37.88 40.00 400

SVGA 800 × 600 46.88 49.51 400

SVGA 800 × 600 48.08 50.00 400

SVGA 800 × 600 53.67 56.25 400

MAC 832 × 624 49.72 57.28 400

XGA 1024 × 768 48.36 65.00 400

XGA 1024 × 768 56.48 75.01 400

XGA 1024 × 768 60.02 78.75 400

MAC 1024 × 768 60.24 80.00 400

XGA 1024 × 768 68.68 94.50 400

SXGA 1280 × 1024 46.43 78.75 400

SXGA 1280 × 1024 63.98 108.00 400

SXGA 1280 × 1024 79.98 135.01 400

SXGA 1280 × 1024 91.15 156.96 400

UXGA 1600 × 1200 81.23 175.46 800

UXGA 1600 × 1200 93.72 202.44 800

– 38 –

CXA3266Q

CLK Jitter Evaluation Method

The regenerated CLK is obtained by applying Hsync to the CXA3266Q. Apply this CLK to a digital oscilloscope

and observe the CLK waveform using Hsync as the trigger.

trigger

Digital

Oscillo-

scope

Hsync

H

CLK

Pulse

Generator

CXA3266Q

ch1

Back

Active

Video

Front

Porch

Sync Porch

Computer signal

Hsync

15 to 25% of Tsync

Tsync = 1/fsync

CLK

Enlarged

Trigger

CLK

Tjp-p

The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in

the figure. The CLK jitter size varies according to the difference in the relative position with respect to Hsync.

Therefore, when the observation point is changed, the CLK jitter at that point is observed.

The figure below shows an typical example of the CLK jitter for the CXA3266Q.

The CLK jitter increases slightly at the rising edge of Hsync (in the case of positive polarity), and then settles

down thereafter. However, this is not a problem as the active pixels start after about 20% of the H cycle has

passed from the rising edge of Hsync.

0

1/4 · Tsync

2/4 · Tsync

3/4 · Tsync

Tsync

Observation points

– 39 –

CXA3266Q

Example of Representative Characteristics

KVCO characteristics

KVCO temperature characteristics

250

200

Ta = +75°C

Ta = +25°C

Ta = –25°C

DIV = 1/1

200

150

100

50

DIV = 1/2

100

DIV = 1/4

50

DIV = 1/8

0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

1.5

2.0

2.5

3.0

3.5

4.0

4.5

VCO control voltage [V]

Fine delay Td2 vs. Fine delay bit

48

40

32

24

16

8

Ta = +75°C

Ta = +25°C

Ta = –25°C

8

16

24

32

40

48

Fine delay bit

Jitter peak-peak vs. Output frequency

2.5

NTSC, DIV = 1/8, CP = 10, 11

VGA, DIV = 1/8, 1/4, CP = 10

SVGA, DIV = 1/4, CP = 10

XGA, DIV = 1/2, CP = 10

SXGA, DIV = 1/1, CP = 10

UXGA, DIV = 1/1, CP = 11

2.0

1.5

1.0

0.5

0

20

40

60

80 100 120 140 160 180 200 220

Output frequency [MHz]

– 40 –

CXA3266Q

Notes on Operation

• Be sure not to separate the analog and digital power supplies, and the analog and digital GND.

• The ground pattern should be as wide as possible. Using a multi-layer substrate with a mat ground is

recommended.

• Ground the power supply pins of the IC with a 0.1µF or larger ceramic chip capacitor as close to each pin as

possible.

• Be sure to accurately match the I/O characteristic impedance in order to ensure sufficient performance during

high-speed operation.

• Design the set so that the loop filter (external) is located at the minimum distance. (See the CXA3266Q

PWB.)

• The voltage applied to VOCLP pin must be supplied from the stabilized power supplies (3-pin regulator etc.)

because of the construction of internal circuit.

– 41 –

CXA3266Q

(1) Recommended PECL I/O circuit

The peripheral circuits mainly use PECL for digital input and output. Of course, PECL and TTL can also be

mixed. In this case, disable the TTL outputs with the control registers.

PECL level output pins

330Ω

GND

35

32

36

34

33

31

30

29

28

27

26

25

37 IOGND

DSYNC 24

VOCLP

PLLV^CC

38

39

CLK 23

CLKN 22

40 PLLGND

CLK/2

21

VCOV^CC

VCOGND

VCOHGND

IREF

41

42

43

44

45

CLK/2N 20

DGND

DV^CC

19

18

V^CC

100kΩ

100pF

2

3.0kΩ

100Ω

UNLOCK output

0.068µF

3

UNLOCK 17

DIVOUT 16

10nF

GND

RC2

680pF

46 RC1

SEROUT

CS 14

TLOAD

15

3.0kΩ

4

IRGND

47

48

Loop Filter

IRV^CC

13

1

2

3

4

5

6

7

8

9

10

11

12

GND

VCC (+5.0V)

Control

Register

Notes)

¹Unless otherwise specified, all capacitors are 0.1µF.

²Vary the external resistor and capacitor values of the

UNLOCK output as necessary.

SYNCH, SYNCL: PECL level

complementary input

HOLD

³This external resistor (3.0kΩ) should be a metal film

resistor in consideration of temperature characteristics.

⁴The loop filter's capacitors and resistor should also be

temperature compensated.

– 42 –

CXA3266Q

(2) Recommended TTL I/O circuit

The peripheral circuits mainly use TTL for digital input and output. Of course, PECL and TTL can also be

mixed.

35

32

36

34

33

31

30

29

28

27

26

25

TTL level output pins

37 IOGND

DSYNC 24

VOCLP

PLLV^CC

38

39

CLK 23

CLKN 22

40 PLLGND

CLK/2

21

VCOV^CC

VCOGND

VCOHGND

IREF

41

42

43

44

45

CLK/2N 20

DGND

DV^CC

19

18

V^CC

100kΩ

100pF

2

3.0kΩ

100Ω

UNLOCK output

0.068µF

3

UNLOCK 17

DIVOUT 16

10nF

GND

RC2

680pF

46 RC1

SEROUT

CS 14

TLOAD

15

3.0kΩ

IRGND

4

47

48

Loop Filter

IRV^CC

13

1

2

3

4

5

6

7

8

9

10

11

12

GND

VCC (+5.0V)

Control

Notes)

¹Unless otherwise specified, all capacitors are 0.1µF.

²Vary the external resistor and capacitor values of the

UNLOCK output as necessary.

Register

HOLD

SYNC: TTL level input

³This external resistor (3.0kΩ) should be a metal film

resistor in consideration of temperature characteristics.

⁴The loop filter's capacitors and resistor should also be

temperature compensated.

– 43 –

CXA3266Q

Connecting the CXA3266Q with Sony ADC (Demultiplex Mode)

When connecting the PLL output to A/D converters with built-in demultiplex function such as the

CXA3246Q/CXA3276Q/CXA3256R/CXA3286R (Sony), a simple system can be configured by connecting the

CLK (PECL) and CLKN (PECL) outputs of the CXA3266Q to the CLK (PECL) and CLKN (PECL) inputs of

each A/D converter, respectively, and the 1/2 CLK (PECL) and 1/2 CLKN (PECL) outputs of the CXA3266Q

to the RESETN (PECL) and RESET (PECL) inputs of each A/D converter, respectively (when the PLL

counter value N is an even number).

Wiring Diagram

8

R

G

B

VIN

ADC

CLK (PECL)

TTL

8

CXA3246Q

CXA3276Q

CXA3256R

CXA3286R

CLKN (PECL)

RESETN (PECL)

RESET (PECL)

TTL

8

VIN

ADC

CLK (PECL)

TTL

8

CXA3246Q

CXA3276Q

CXA3256R

CXA3286R

CLKN (PECL)

RESETN (PECL)

RESET (PECL)

TTL

8

VIN

ADC

CXA3246Q

CXA3276Q

CXA3256R

CXA3286R

CLK (PECL)

TTL

8

CLKN (PECL)

RESETN (PECL)

RESET (PECL)

TTL

• CXA3246Q 8-bit 120MSPS ADC

• CXA3276Q 8-bit 160MSPS ADC

• CXA3256R

• CXA3286R

8-bit 120MSPS ADC

8-bit 160MSPS ADC

PLL

CXA3266Q

– 44 –

CXA3266Q

CXA3266Q and Sony ADC (Demultiplex Mode) Timing: 120MHz specification

The CXA3266Q and CXA3246Q/CXA3256R timings are shown below.

Here, the important timings are as follows.

(The clock cycle is labeled as T.)

• For the A/D converters

Clock input vs. reset input

The set-up time is T–1.1ns and the hold time is 0.3ns, satisfying the A/D converter specifications.

• For the CMOS LOGIC at the rear end of the A/D converters

A/D converter data output vs. 1/2 clock output timing

The set-up time is T–4.5ns and the hold time is T–3.5ns. (These timings also include combinations of

three A/D converters from different lots, and are defined for all operating temperatures and all operating

supply voltages. See the CXA3246Q/CXA3256R data sheets for a detailed description.)

• For the CMOS LOGIC at the rear end of the A/D converters

DSYNC signal from CXA3266Q vs. A/D converter 1/2 clock output

The set-up time is T–3.2ns and the hold time is T–4.2ns.

CXA3266Q

T

CLK (PECL)

out

2.8 to 6.2ns

DSYNC (TTL)

out

0.3 to 1.1ns

1/2CLK (PECL)

out

See the CXA3246Q and

CXA3256R data sheets.

CXA3246Q

CXA3256R

Tsetup min. Thold min.

T–4.5ns T–3.5ns

Tsetup min.

T–3.2ns

Thold min.

T–4.2ns

3.0 to 7.0ns

1/2CLK (TTL)

out

DATA (TTL)

out

– 45 –

CXA3266Q

CXA3266Q and Sony ADC (Demultiplex Mode) Timing: 160MHz specification

The CXA3266Q and CXA3276Q/CXA3286R timings are shown below.

Here, the important timings are as follows.

(The clock cycle is labeled as T.)

• For the A/D converters

Clock input vs. reset input

The set-up time is T–1.1ns and the hold time is 0.3ns, satisfying the A/D converter specifications.

• For the CMOS LOGIC at the rear end of the A/D converters

A/D converter data output vs. 1/2 clock output timing

The set-up time is T–4.0ns and the hold time is T–3.0ns. (These timings also include combinations of

three A/D converters from different lots, and are defined for all operating temperatures and all operating

supply voltages. See the CXA3276Q/CXA3286R data sheets for a detailed description.)

• For the CMOS LOGIC at the rear end of the A/D converters

DSYNC signal from CXA3266Q vs. 1/2 clock output of A/D converter

The set-up time is T–3.2ns and the hold time is T–3.7ns.

CXA3266Q

T

CLK (PECL)

out

2.8 to 6.2ns

DSYNC (TTL)

out

0.3 to 1.1ns

1/2CLK (PECL)

out

See the CXA3276Q and

CXA3286R data sheets.

CXA3276Q

CXA3286R

Tsetup min. Thold min.

Tsetup min.

T–3.2ns

Thold min.

T–3.7ns

T–4.0ns

T–3.0ns

3.0 to 6.5ns

1/2CLK (TTL)

out

DATA (TTL)

out

– 46 –

CXA3266Q

Connecting the CXA3266Q with Sony ADC (Straight Mode)

When connecting the PLL output to A/D converters such as the CXA3246Q/CXA3276Q/CXA3256R/CXA3286R

(Sony), a simple system can be configured as shown below.

Wiring Diagram

8

R

G

B

VIN

CLK (PECL)

TTL

CLKN (PECL)

ADC

CXA3246Q

CXA3276Q

CXA3256R

CXA3286R

8

VIN

CLK (PECL)

TTL

CLKN (PECL)

ADC

CXA3246Q

CXA3276Q

CXA3256R

CXA3286R

8

VIN

CLK (PECL)

TTL

CLKN (PECL)

ADC

CXA3246Q

CXA3276Q

CXA3256R

CXA3286R

• CXA3246Q 8-bit 120MSPS ADC

• CXA3276Q 8-bit 160MSPS ADC

• CXA3256R

• CXA3286R

8-bit 120MSPS ADC

8-bit 160MSPS ADC

PLL

CXA3266Q

– 47 –

CXA3266Q

CXA3266Q and Sony ADC (Straight Mode) Timing: 100MHz specification

The CXA3266Q and CXA3246Q/CXA3256R timings are shown below.

Here, the important timings are as follows.

(The clock cycle is labeled as T.)

• For the CMOS LOGIC at the rear end of the A/D converters

A/D converter data output vs. clock output from CXA3266Q

The set-up time is T–5.7ns and the hold time is 0.3ns. (These timings also include combinations of three

A/D converters from different lots, and are defined for all operating temperatures and all operating supply

voltages. See the CXA3246Q/CXA3256R data sheets for a detailed description.)

• For the CMOS LOGIC at the rear end of the A/D converters

DSYNC signal from CXA3266Q vs. A/D converter clock output

The set-up time is T–3.0ns and the hold time is T–1.0ns.

CXA3266Q

T

CLK (PECL)

out

1.8 to 3.2ns

CLK (TTL)

out

1.0 to 3.0ns

DSYNC (TTL)

out

Thold min.

1.0ns

Tsetup min.

T–3.0ns

CXA3246Q

CXA3256R

Tsetup min.

T–5.7ns

Thold min.

0.3ns

3.5ns min.

7.5ns max.

DATA (TTL)

out

– 48 –

CXA3266Q

CXA3266Q and Sony ADC (Straight Mode) Timing: 100MHz specification

The CXA3266Q and CXA3276Q/CXA3286R timings are shown below.

Here, the important timings are as follows.

(The clock cycle is labeled as T.)

• For the CMOS LOGIC at the rear end of the A/D converters

A/D converter data output vs. clock output from CXA3266Q

The set-up time is T–5.2ns and the hold time is 0.3ns. (These timings also include combinations of three

A/D converters from different lots, and are defined for all operating temperatures and all operating supply

voltages. See the CXA3276Q/CXA3286R data sheets for a detailed description.)

• For the CMOS LOGIC at the rear end of the A/D converters

DSYNC signal from CXA3266Q vs. A/D converter clock output

The set-up time is T–3.0ns and the hold time is T–1.0ns.

CXA3266Q

T

CLK (PECL)

out

1.8 to 3.2ns

CLK (TTL)

out

1.0 to 3.0ns

DSYNC (TTL)

out

Thold min.

1.0ns

Tsetup min.

T–3.0ns

CXA3276Q

CXA3286R

Tsetup min.

T–5.2ns

Thold min.

0.3ns

3.5ns min.

7.0ns max.

DATA (TTL)

out

– 49 –

CXA3266Q

CXA3266Q-PWB (CXA3266Q Evaluation Board)

The CXA3266Q-PWB is an evaluation board for the CXA3266Q PLL-IC. This board makes it possible to easily

evaluate the CXA3266Q's performance using the supplied control program (Note: IBM PC/AT, MS-DOS 5.0 or

newer US mode specifications).

Features

• Two input level (TTL and PECL) SYNC input

• Two output level (TTL and PECL) CLK, CLK2 and DSYNC output

• Supply voltage: +5.0V

Absolute Maximum Ratings (Ta = 25°C)

Supply voltage

VCC

–0.5 to +7.0

V

Recommended Operating Conditions

• Supply voltage

• Digital input

VCC

4.75 to 5.25

0

V

GND

(PECL)

V

DIN (High)

DIN (Low)

DIN (High)

DIN (Low)

V^CC– 1.1

VCC – 1.5

V (Min.)

V (Max.)

(TTL)

GND + 2.0 V (Min.)

GND + 0.8 V (Max.)

• Operating ambient temperature

Ta

–20 to +75

°C

Block Diagram

Loop Filter

VCO input

(PECL/TTL)

DSYNC output

(PECL/TTL)

CLK output

(PECL/TTL)

CXA3266Q

48pin QFP

SYNC input

(PECL/TTL)

CLK/2 output

(PECL/TTL)

VBB (PECL)

SEROUT (TTL)

DIVOUT (TTL)

UNLOCK (TTL)

3

CONTROL BUS (TTL)

SENABLE, SCLK, SDATA

– 50 –

CXA3266Q

Setting Methods and Notes on Operation

Input pins

This PWB supports TTL single and PECL complementary input.

Input pins: SYNC: TTL level input, 10 to 120kHz

SYNCL: PECL low level input, 10 to 120kHz

SYNCH: PECL high level input, 10 to 120kHz

VCO:

TTL level input. This is a test pin and is therefore normally not used.

VCOL: PECL low level input. This is a test pin and is therefore normally not used.

VCOH: PECL high level input. This is a test pin and is therefore normally not used.

Output pins

This PWB supports TTL single and PECL complementary output.

DSYNCH,

DSYNCL: PECL level complementary delay SYNC outputs. The output range is 10 to 120kHz.

DSYNC:

TTL level delay SYNC output. The output range is 10 to 120kHz.

CLKH,

CLKL:

PECL level complementary CLK outputs. The output range is 10 to 203MHz.

TTL level complementary CLK outputs. The output range is 10 to 100MHz.

PECL level complementary 1/2 CLK outputs. The output range is 5 to 100MHz.

CLK,

CLKN:

CLK/2H,

CLK/2L:

CLK/2,

CLK/2N:

TTL level complementary CLK outputs. The output range is 5 to 100MHz.

Outputs the PECL amplitude threshold voltage.

VBB:

SEROUT: TTL level control register serial data output.

DIVOUT: TTL level internal programmable counter test output.

UNLOCK: TTL level UNLOCK output. This pin requires external circuits such as appropriate capacitors and

resistors.

See the IC specifications for a detailed description.

PECL outputs (VBB, DSYNCH, DSYNCL, CLKH, CLKL, CLK/2H, CLK/2L) are output constantly, but TTL

outputs (DSYNC, CLK, CLKN, CLK/2, CLK/2N, SEROUT, DIVOUT, UNLOCK) are controlled by the respective

control registers. Therefore, the enable/disable settings should be made in accordance with the application.

See the following pages for the setting method.

– 51 –

CXA3266Q

Jumper Wire Settings

S1, S2: These enable/disable HOLD (Pin 6). HOLD is active high, so the jumper wire should be connected to

S2 (HOLD = low) for normal use. When using HOLD, connect the jumper wire to S1 (HOLD = high).

(For the initial setting, the jumper wire is connected to S2.)

S3, S4: These enable/disable TLOAD (Pin 13). Connect the jumper wire to S4 (TLOAD = high) for normal use.

When using TLOAD, connect the jumper wire to S3 (TLOAD = low). (For the initial setting, the jumper

wire is connected to S4.)

S5, S6: These enable/disable CS (Pin 14). Connect the jumper wire to S6 (CS = high) for normal use. When

using Power Save, connect the jumper wire to S5 (CS = low). (For the initial setting, the jumper wire is

connected to S6.)

Supplied Program

This PWB has a control program that facilitates evaluation of the CXA3266Q. Operation methods and precautions

are as follows.

1) Compatible personal computers

Use an IBM PC/AT or compatible machine equipped with a 25-pin D-SUB parallel port (printer port). Also,

operating systems which support the program are MS-DOS 5.0 or newer and MS-Windows 3.1 or newer.

(When using Windows, start the program from the DOS window.)

2) Connection of the supplied cable

Connect the supplied cable to the parallel port of the personal computer and the DBUS1 connector of the

CXA3266Q-PWB.

D-SUB 25-pin parallel connector pin arrangement

1

13

Pin 2 : SCLK

Pin 3 : SDATA

Pin 4 : SENABLE

Pin 11 : SERIN

Pin 19 : GND

14

25

3) Connect the power cable and supply power to the CXA3266Q-PWB.

4) Start the program

A) Boot the personal computer and then shift to the directory containing the program.

B) Set MS-DOS to US mode. → US Return or Enter

C) Input the program name. → CXA3266Q Return or Enter → Move to the program screen.

– 52 –

CXA3266Q

5) Description of program screen

A) Setting of each function

When the program is started, the following initial screen is displayed.

A3266 PLL REGISTERS

Divisor 1672

Divider 2

Coarse Delay 00

Polarity

Fine Delay

Charge Pump 00

0

Power

SYNC DSYNC

PD

0

SCAN SYNTH

VCO Bypass

ON

0

ON

O/P Enable

DIVOUT

ON

UNLOCK

ON

DSYNC

ON

CLK2

ON

NCLK2

ON

CLK1

ON

NCLK1

ON

DSYNC Functions

DELAY

ON

WIDTH

00

HOLD

ON

BYPASS

ON

Use arrow keys to select data bit. Press ENTER to toggle and load data.

Use Pg Up and Pg Dn to increment/decrement divisor and fine delay registers.

Press a to abort, s to scan registers MIXED SIGNAL SYSTEMS AUG 1998

– 53 –

CXA3266Q

Divisor

This is used to input the frequency division ratio of the program counter. The value can be changed as

desired from 9 to 4111 by moving the cursor to the position of the number and pressing the Return or Enter

key. (Note: The operating range of the CXA3266Q is from 256 to 4096.) The value can also be incremented

or decremented by one step by pressing the Page Up or Page Down key, respectively.

The internal VCO has an oscillator frequency of 40 to 203MHz, so the output frequency and Divider (VCO

frequency divider) setting range are as follows.

40

Divider = 1

203

1/1

1/2

1/4

1/8

20

Divider = 2

50

100

Divider = 4

10

Divider = 8

25

5

50

100

O/P frequency [MHz]

150

200

Divider

This sets the VCO output frequency division ratio to 1/1, 1/2, 1/4 or 1/8. The frequency division ratio changes

repeatedly in the order of 1/1 → 1/2 → 1/4 → 1/8 → 1/1 each time the cursor is moved to the position of the

number and the Return or Enter key is pressed.

Coarse Delay

This is the DSYNC upper delay time setting. The value can be changed by moving the cursor to the position

of the number and pressing the Return or Enter key. The delay time variable range settings are "00" (2 CLK),

"01" (3 CLK), "10" (4 CLK) or "11" (5 CLK).

Fine Delay

This is the DSYNC lower delay time setting. The value can be changed by moving the cursor to the position

of the number and pressing the Return or Enter key. The value can also be incremented or decremented by

one step by pressing the Page Up or Page Down key, respectively. The delay time can be varied from 1/32

CLK to 64/32 CLK by setting "0" to "63", respectively.

Charge Pump

This is the charge pump circuit KI setting. The value can be changed by moving the cursor to the position of the

number and pressing the Return or Enter key. KI can be set to "00" (approximately 100µA), "01" (approximately

200µA), "10" (approximately 400µA) or "11" (approximately 800µA).

Polarity

These are the SYNC, DSYNC and PD (Phase Detector) polarity inversion settings, and should be set as

necessary such as when inverting the SYNC input and DSYNC output waveforms. The setting value "1" is

positive polarity, and "0" is negative polarity. These should normally all be set to "1". (Fix PD to "1" other than

during test mode.)

– 54 –

CXA3266Q

Power

SCAN:

This is the control register read setting. When this is ON, the control register serial data is

output from SEROUT (Pin 15). This should normally be set to OFF.

SYNTH:

This is the enable/disable setting for this IC. This should normally be set to ON.

VCO By-pass: This is set to OFF when testing the program counter. This should normally be set to ON.

O/P Enable

These are the enable/disable settings for each TTL output (DIVOUT, UNLOCK, DSYNC, CLK2, NCLK2,

CLK1 and NCLK1). Set to ON when performing evaluation using TTL output.

DSYNC Functions

DELAY:

WIDTH:

When DIVOUT is output from DSYNC output, its delay is set. 4 CLK for OFF; 5 CLK for ON.

When DIVOUT is output from DSYNC output, its pulse width is changed. Their settings are

1 CLK for "00", 2 CLK for "01", 4 CLK for "10", and 8 CLK for "11".

HOLD:

DSYNC output status is set during HOLD. Output OFF status for OFF (H or L fixed according

to DSYNC POL polarity); DSYNC or DIVOUT are output for ON.

BYPASS:

DSYNC/DIVOUT output switching from DSYNC output is performed. DSYNC is output for ON;

DIVOUT for OFF.

– 55 –

CXA3266Q

B) Description of readout mode

This program has a function (readout mode) that reads the contents written to the control registers from the

CXA3266Q SEROUT (Pin 15) and displays these contents on the screen. This function is described below.

1) Set SCAN to ON at the function setting screen.

2) Press the S key.

The following screen appears.

SCAN RESULT, CXA3266 PLL REGISTERS

Register 1 DIVREG1

Register 2 DIVREG2

Register 3 CENFREREG

Register 4 DELAYREG

Register 5 CPREG

00111000

0101

01

00100000

100110

11111111

111111

Register 6 TTLPOLREG

Register 7 TESTPOWREG

Press r to return to PLL REGISTERS MENU.

Press a to abort

MIXED SIGNAL SYSTEMS AUG 1998

This screen conforms to the Control Register Table listed in the CXA3266Q data sheet.

3) Press the R key to return to the original function setting screen.

C) Quit the program

Press the A key to quit the program.

– 56 –

CXA3266Q

Substrate Pattern (parts surface)

Substrate Pattern (solder surface)

– 57 –

CXA3266Q

VCC

GND

VCO

VCOL

VCOH

C21

33µ

+

BNC3

BNC2

BNC1

PR10

VBB

R1

R8

CXA3266Q PWB

BNC4

SYNCH

PR8

DSYNCL

PR9

DSYNCH

R3

R2

R9

R10

S1

S2

BNC5

SYNCL

PR6

CLKL

PR7

CLKH

R7

R4

IC1

R14

R11

BNC6

PR1

CLK/2L

PR5

CLK/2H

SYNC

R6

R5

R13

R12

PR2

SEROUT

PR3

DIVOUT

PR4

UNLOCK

PR11

CLK/2N

PR12

CLK/2

PR13

CLKN

PR14

CLK

PR15

DSYNC

Silk Screen (parts surface)

2 1 C

9 1 C

0 2 C

0 1 C

8 C

1 1 C

7 C

9 C

Silk Screen (solder surface)

– 58 –

CXA3266Q

D N G O I

P L C O V

^{C C}V L L P

D N G L L P

^{C C}V O C V

D N G O C V

D N G H O C V

F E R I

C N Y S D

K L C

N K L C

2 / K L C

N 2 / K L C

D N G D

^{C C}V D

K C O L N U

T U O V I D

T U O R E S

S C

2 C R

1 C R

D N G R I

^{C C}V R I

D A O L T

r e t s i g e R l o r t n o C

– 59 –

CXA3266Q

Package Outline

Unit: mm

48PIN QFP (PLASTIC)

15.3 ± 0.4

+ 0.1

0.15 – 0.05

+ 0.4

12.0 – 0.1

0.15

36

25

24

37

+ 0.2

0.1 – 0.1

48

13

1

12

+ 0.15

0.3 – 0.1

0.8

0.24

M

+ 0.35

2.2 – 0.15

PACKAGE STRUCTURE

EPOXY RESIN

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

SOLDER / PALLADIUM

PLATING

SONY CODE

EIAJ CODE

QFP-48P-L04

QFP048-P-1212

42/COPPER ALLOY

0.7g

JEDEC CODE

PACKAGE MASS

NOTE : PALLADIUM PLATING

This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

– 60 –


型号：	CXA3266Q
厂家：	SONY CORPORATION
描述：	PLL IC for LCD Monitor/Projector PLL IC为液晶显示器/投影仪显示器 CD
文件：	总60页 (文件大小：762K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXA3266Q [SONY]

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