TS4100 [SILICON]
Precision Measurement;
| 型号： | TS4100 |
| 厂家： | 
SILICON |
| 描述： | Precision Measurement |
| 文件： | 总24页 (文件大小：1778K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS4100/01/02 Data Sheet
"Rail-to-Rail Plus"™, 1% RON Flatness, 0.8 V to 5.25 V Analog
Switches/Multiplexers
KEY FEATURES
• Low Supply Voltage Operation: 0.8 V to
5.25 V
The TS410x family of analog switches and multiplexers consists of the TS4100 8-chan-
nel analog multiplexer, the TS4101 dual 4-channel analog multiplexer, and the TS4102
triple single-pole/double-throw (SPDT) switch. These switches are unique because they
can operate at supply voltages as low as 0.8 V while accepting input signal swings
above the supply voltage up to 5.25 V ("Rail-to-Rail Plus"™). The on-resistance variation
over the entire signal swing range is less than 1%, exhibiting excellent linearity and con-
sistency in dynamic and measurement applications. With a supply current of only 675
nA, the TS4100-TS4102 family input and output leakage is less than 0.5 nA, both when
off and when on.
• On-resistance of 80 Ω
• "Rail to Rail Plus"™ input/output voltages
can exceed the supply rails
• Guaranteed Low Off and On Leakage: ±0.5
nA
• Guaranteed Match Between Channels: 9 Ω
• Guaranteed <1% On-Resistance Variation
Across Input Voltage
The TS4100-TS4102 are fully specified over the –40 °C to +85 °C temperature range
and is available in a low-profile, thermally-enhanced 16-pin 3.3 mm TQFN package with
an exposed back-side paddle. For best performance, solder exposed back-side paddle
to PCB ground.
• TS4100: 8-Channel Switch/Multiplexer
• TS4101: Two 4-Channel Switches/
Multiplexers
• TS4102: Three Single-Pole/Double-Throw
Switches (SPDT)
Applications
• Supply Current: 675 nA
• Low Voltage Battery-Operated Equipment
• Precision Measurement
• 16-Pin, Low-Profile, Thermally Enhanced 3
mm x 3 mm TQFN Package
• Analog Signal Processing
• Communication Circuits
• Audio Signal Routing
• Low-Voltage Data-Acquisition Systems
Functional Block Diagrams
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TS4100/01/02 Data Sheet
Ordering Information
1. Ordering Information
Ordering Part Number
TS4100ITQ1633
TS4101ITQ1633
TS4102ITQ1633
Note:
Description
Package
8:1 analog multiplexer
TQFN-16 (3 x 3 mm)
TQFN-16 (3 x 3 mm)
TQFN-16 (3 x 3 mm)
Two 4:1 analog multiplexers
Three 2:1 SPDT analog switches
1. Adding the suffix “T” to the part number (e.g., TS4100ITQ1633T) denotes tape and reel.
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TS4100/01/02 Data Sheet
System Overview
2. System Overview
The TS4100 is an 8-channel multiplexer with inputs NO0-NO7 and output COM. A channel can be selected via address pins ADDA,
ADDB, and ADDC.
The TS4101 is a dual 4-channel switch/multiplexer with two separate input banks: NO0A-NO3A and NO0B-NO3B with dedicated output
COMA and COMB, respectively. A channel can be selected via address pins ADDA and ADDB.
The TS4102 is a triple single-pole/double-throw (SPDT) switch. When ADDA, ADDB, or ADDC is set to a Low state, the output will be
NCA, NCB, or NCC, respectively. When ADDA, ADDB, or ADDC is set to a High state, the output will be NOA, NOB, or NOC, respec-
tively. Refer to XREF DIGITAL I/O SETTINGS TABLE
Unlike similar switch/multiplexer devices, the TS4100-TS4102 input voltage is independent of the supply voltage. This allows the input
voltage to be greater than the supply voltage while maintaining a flat On-resistance vs. the VNO/VCOM curve. Refer to 3.1 Typical
Performance Characteristics for more information.
2.1 Applications Information
2.1.1 AC Performance Considerations
2.1.2 Off Isolation
Like all switch/multiplexer devices, the off-isolation of the device is measured when the device is off (see Figure 2.8 TS4100-TS4102
Charge Injection Test Setup on page 8). During the OFF state, part of the input signal couples to the output load. To maximize the
off-isolation, maximize your capacitive load and minimize your resistive load. The trade-off is that this can increase the insertion loss of
the device so it must be considered when designing a circuit. The insertion loss is measured when the switch/multiplexer is in the ON
state (see Figure 2.9 TS4100-TS4102 Off-Isolation Test Setup on page 9).
At 10 kHz, the off-isolation of the TS4100-TS4102 is approximately –88 dB. Refer to the Off-Isolation vs. Frequency plot in 3.1 Typical
Performance Characteristics.
2.1.3 Total Harmonic Distortion (THD)
In audio and data acquisition applications, signal fidelity is of a concern. As a result, the THD parameter of the analog mux/switch be-
comes an important factor. Many current analog switch/mux devices on the market implement a design that allow for a large variation of
on-resistance as the input signal is changing. With 1% on-resistance variation over the entire signal swing, the TS4100-TS4102 design
minimizes THD. At 10 kHz, the TS4100-TS4102 exhibits a THD of 0.15% over the entire signal swing.
2.1.4 Bandwidth Considerations
The magnitude of the output resistive load and capacitive load has an impact on the bandwidth of the mux/switch. At dc or close to dc
input signals, a resistive load has the greatest impact where the output voltage is determined primarily by the voltage divider consisting
of the switch on-resistance and the output resistive load. To minimize the ON insertion loss, maximize the resistive load.
As the input frequency increases, the ac impedance of the circuit begins to have an impact on bandwidth of the mux/switch. To counter
this effect, minimize the load capacitance and any stray capacitance that may be present on the board. Also, ensure a board layout that
minimizes signal trace lengths.
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TS4100/01/02 Data Sheet
System Overview
2.1.5 Programmable Gain Amplifier (PGA) with the TS4100
Analog signals can vary in amplitude and frequency especially when considering various taypes of sensors such as thermistors, strain
gauges, and photodiodes. To process the analog signals provided by the sensor, a stand-alone ADC such as a TS7001 or TS7003 can
be used. However, to take advantage of the resolution of the ADC, the analog signals must be scaled up to the maximum input voltage
range of the ADC.
One way to achieve this is by designing a 1.5 V non-inverting programmable gain amplifier (PGA) that incorporates a TS1005 opera-
tional amplifier and a TS4100 analog multiplexer as shown in the figure below. The gain can be changed from 2 to 8 via address pins
ADDA, ADDB, and ADDC.
With the TS4100 connected to ground, the on-resistance of the switch becomes part of the gain of the amplifier and needs to be ac-
R1
counted for in the following gain equation: GAIN = 1 +
RGX + RON
where RON is 80 Ω (typ) and RGX is the resistor connected to the TS4100 input. Unlike other analog switches, the TS4100 on-resist-
ance variation over the entire signal swing range is less than 1%. In this circuit, the corresponding gain variation is less than 0.03%
across all channels. This circuit accommodates an input signal bandwidth of 2.5 kHz to 10 kHz. Also, by connecting the TS4100 to
ground, internal switching spikes are minimized. Refer to 2.1.7 Charge Pump Effect Considerations.
Figure 2.1. Non-Inverting Programmable Gain Amplifier (PGA) with TS4100
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TS4100/01/02 Data Sheet
System Overview
2.1.6 Switched-Capacitor Voltage Doubler with the TS4102 and TS3004 Timer
In portable applications, it is a common requirement for a battery to continue to supply power to a circuit when it has discharged to a
voltage unusable by other devices in the system. To address this, a simple voltage doubler can be designed using two SPDT switches
in a single TS4102 device and a TS3004 timer as shown in the figure below.
In this configuration, the TS3003 timer FOUT output provides a 200 Hz (50% Duty Cycle) clock signal to address pin ADDA and ADDB
that switches between 0 V and VDD. When the clock signal to the address pins ADDA and ADDB is 0 V, capacitor C1 is charged to
VSUPPLY. When the clock input is VDD, the charge in C1 is passed to C2 and effectively doubles the voltage at NOB to 2 x VSUPPLY.
Unlike other analog switches, the TS4102 allows the supply voltage to be independent of the common mode input voltage. In this con-
figuration, the TS4102 allows the supply voltage to be independent of the common mode input voltage. In this configuration, the
TS4102 and the TS3004 can operate at a supply voltage range of 1.55 V to 5.25 V while the output voltage is 5 V with VSUPPLY = 2.5
V. With VDD = 1.55 V, the complete circuit consumes only 3 μA of supply current and can drive an output load of up to 48 μA (5% drop
at VOUT).
Figure 2.2. Switched-Capacitor Voltage Doubler with TS4102 and TS3004 Timer
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TS4100/01/02 Data Sheet
System Overview
2.1.7 Charge Pump Effect Considerations
The on-resistance of a MOSFET is inversely proportional to the overdrive voltage in the region where MOSFETS are used as switches.
Conventional analog switch/multiplexers derive their overdrive voltage directly from the supply voltage and common mode input volt-
age; hence, the on-resistance varies with the supply voltage or common mode input voltage.
The TS4100-TS4102 maintains a flat on-resistance that is independent of the supply voltage or common mode input voltage. To ach-
ieve this, a charge pump scheme is implemented where a constant overdrive voltage is applied across the MOSFET. The charge pump
is refreshed at a period of 40 μs with a time period variation of up to 2X.
In applications where input and output impedance is high in the order of MΩs, transients generated by the charge pump can couple to
the input and output of the device. The pulse width of the spikes is 10-s of nanoseconds. The amplitudes of the spikes are independent
of the operating conditions, such as temperature, common mode input voltage and supply voltage.
The figures below show a scope capture of these spikes with an input/output impedance of 1 MΩ and 10 MΩ. With an input/output
impedance of 1 MΩ and 10 MΩ, the amplitude of the spikes is less than 200 μV and 500 μV, respectively.
If these spikes are of a concern in the application, placing a 500 pF capacitor to ground at the input or output will suppress the spikes.
Figure 2.3. Charge Pump Spike (RNO/COM = 1 MΩ)
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TS4100/01/02 Data Sheet
System Overview
Figure 2.4. Charge Pump Spike (RNO/COM = 10 MΩ)
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TS4100/01/02 Data Sheet
System Overview
2.1.8 Power-Up Sequence
To prevent permanent damage to the ADDA, ADDB, ADDC, and INH pin, the power supply voltage should be applied to the device first
followed by the voltage to ADDA, ADDB, ADDC, and/or INH. If it is not possible to follow this power-supply sequence, a 500kΩ resistor
can be placed in series with the digital I/O pins for protection as shown in the figure below. However, if an input voltage is applied be-
fore applying power to the switch/multiplexer, the device will not be damaged as the inputs are independent of the supply voltage.
Figure 2.5. Digital I/O Overvoltage Protection
Figure 2.6. TS4100-TS4102 Address/Enable Turn-On/Off Time Test Setup
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TS4100/01/02 Data Sheet
System Overview
Figure 2.7. TS4100-TS4102 Break-Before-Make Test Setup
Figure 2.8. TS4100-TS4102 Charge Injection Test Setup
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TS4100/01/02 Data Sheet
System Overview
Figure 2.9. TS4100-TS4102 Off-Isolation Test Setup
Figure 2.10. TS4100-TS4102 Insertion Loss Test Setup
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TS4100/01/02 Data Sheet
System Overview
Figure 2.11. TS4101 Crosstalk Test Setup
Figure 2.12. TS4102 Crosstalk Test Setup
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TS4100/01/02 Data Sheet
Electrical Characteristics
3. Electrical Characteristics
Table 3.1. Recommended Operating Conditions1
Conditions
Parameter
Analog Switch
Symbol
Min
Typ
Max
Units
Analog Signal Range
On Resistance
VNO/C, VCOM
RON
0
5.25
105
135
90
V
Ω
Ω
Ω
Ω
%
%
0.8 V ≤ VDD < 1.25 V
ICOM = 1 mA
TA = 25 ºC
TA = 25 ºC
TA = 25 ºC
98
80
1.25 V ≤ VDD ≤ 5.25 V
ICOM = 1 mA
130
1
On Resistance Flat-
ness
RONFLAT
0 V ≤ VNO/C ≤ 5.25 V
ICOM = 1 mA2,3
VDD = 5 V
1.5
On-Resistance Match
Between channels
ΔRON
2.25
9
Ω
VNO/C = 5 V
ICOM = 1 mA4
VDD = 5.25 V
NO/NC Off-Leakage
Current
INO/NC(OFF)
ICOM(OFF)
ICOM(ON)
TA = 25 ºC
TA = 25 ºC
TA = 25 ºC
–0.5
–2
0.5
2
nA
nA
VNO/C = 0 V or 5.25 V
VCOM = 0 V or 5.25 V
INH = 5.25 V5
VDD = 5.25 V
TS4100-TS4102
–0.5
–2
0.5
2
nA
nA
COM Off-Leakage
Current
VNO/C = 0 V or 5.25 V
VCOM = 0 V or 5.25 V
INH = 5.25 V5
COM On-Leakage
Current
VDD = 5.25 V, VNO/C
VCOM = 5.25 V5
=
–0.5
–4
0.5
4
nA
nA
Digital I/O
ADDA/B/C, INH Input
Logic High
VIH
VIL
0.6
–2
V
V
ADDA/B/C, INH Input
Logic Low
0.2
2
ADDA/B/C, INH Input
Leakage Current
IIH, IIL
VINH = VADDA/B/C = 0
or 5.25 V
nA
Switch Dynamic Characteristics
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TS4100/01/02 Data Sheet
Electrical Characteristics
Parameter
Symbol
Conditions
VDD = 5.25 V
Min
Typ
Max
Units
ADDA/B/C, INH Turn-
On Time
tON
7
9
µs
RL = 5 kΩ, CL = 35 pF
ADDA/B/C, INH Turn-
Off Time
tOFF
0.5
6.5
0.8
8.2
µs
µs
See Figure
2.6 TS4100-TS4102
Address/Enable Turn-
On/Off Time Test Set-
up on page 7
Break-Before-Make
Delay
tBBM
VNO/C = 5.25 V
RL = 5 kΩ, CL = 35 pF
See Figure
2.7 TS4100-TS4102
Break-Before-Make
Test Setup on page 86
Charge-Injection
Off-Isolation
Q
VNO/C = 5.25 V, CL = 1 nF
10
pC
dB
See Figure 2.8 TS4100-TS4102 Charge Injec-
tion Test Setup on page 8.
VISO
f = 10 kHz, VNO/C = 1 VRMS, RL = 100 kΩ, CL =
50 pF
–87
See Figure 2.9 TS4100-TS4102 Off-Isolation
Test Setup on page 9.
TS4101,TS4102
Crosstalk
VCT
f = 10 kHz, VNO/C = 1 VRMS, RL = 100 kΩ
–77
dB
%
See Figure 2.11 TS4101 Crosstalk Test Setup
on page 10 and Figure 2.12 TS4102 Crosstalk
Test Setup on page 10.
Total Harmonic Distor-
tion
THD
f = 10 kHz, VNO/C = 400 mVPP (500 mV Offset)
CL = 15 pF, RNO/C = RCOM = 600 Ω
0.16
675
Power Supply
Supply Current
IQ
VDD = 5.25 V
TA = 25 ºC
765
950
5.25
nA
nA
V
VNO/C = 0 or VDD
Supply Voltage
VDD
0.8
Note:
1. VDD = 0.8 V to 5.25 V; INH = GND unless otherwise specified; TA= –40 °C to +85 °C. Typical values are at TA = +25 °C; All
specifications are 100% tested at TA = +85°C. Specification limits over temperature (TA = TMIN to TMAX) are guaranteed by device
characterization, not production tested.
2. On-Resistance Flatness is defined by the following equation: (RON0.5V – RON5.25V / RON0.5V) x 100.
3. Tested at VNO/C = 0.5 V and VNO/C = 5.25 V and guaranteed by design from VNO/C = 0 V to VNO/C = 5.25 V.
4. ΔRON=RONMAX−RONMIN
5. Leakage parameters are guaranteed by correlation at TA = 25 ºC and are 100% tested at the maximum rated hot operating tem-
perature.
6. tBBM = tON − tOFF. Not production tested.
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TS4100/01/02 Data Sheet
Electrical Characteristics
Table 3.2. Absolute Maximum Ratings1
Parameter
Supply Voltage
Symbol
Conditions
Min
–0.3
–0.3
–0.3
Max
+5.5
Units
VDD
VNO/C, VCOM
VADDA/B/C, VINH
INO/C, ICOM
PD
V
V
Analog Signal Voltage
Digital Signal Voltage
Analog Peak Current
Continuous Power Dissipation
+5.5
VDD + 0.3
±15
mA
TA = +70 °C2
1398
mW
Operating Temperature
Storage Temperature
–40
–65
+85
+150
+300
°C
°C
°C
Lead Temperature (Soldering,
10 s)
ESD Tolerance
Human Body Model
Machine Model
Note:
1000
200
V
V
1. Electrical and thermal stresses beyond those listed in this table may cause permanent damage to the device. These are stress
ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sec-
tions of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect
device reliability and lifetime.
2. Derate at 17.5 mW/°C above +70 °C.
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TS4100/01/02 Data Sheet
Electrical Characteristics
3.1 Typical Performance Characteristics
For the following graphs, VDD = 5.25 V, CL = 0 pF, RL = No load, INH = Low, unless otherwise noted. Values are at TA = 25 °C unless
otherwise noted.
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TS4100/01/02 Data Sheet
Electrical Characteristics
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TS4100/01/02 Data Sheet
Electrical Characteristics
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TS4100/01/02 Data Sheet
Pin Descriptions
4. Pin Descriptions
NO6
16
NO2B
16
NCB
16
NO4
15
VDD
14
NO2
13
NO0B VDD NO2A
NOB VDD COMB
15
14
13
15
14
13
12
11
10
9
12
11
10
9
12
11
10
9
1
2
3
4
NO1
NO0
NO3
ADDA
1
2
3
4
NO1A
1
2
3
4
COMC
NOC
COM
NO7
NO5
INH
COMB
NO3B
NO1B
INH
NOA
COMA COMA
TS4100
TS4101
TS4102
NCA
INH
NO0A
NO3A
NCC
ADDA
7
7
7
6
6
6
5
5
5
8
8
8
NC
ADDB
NC
ADDA
NC
ADDB
ADDC
ADDB
ADDC
GND
GND
GND
Table 4.1. Pin Functions
Pin
Pin Name
TS4101
Function
TS4100
TS4102
NOA
1
COM
NO7
NO5
8-channel switch/multiplexer output
COMB
NO3B
4-channel switch/multiplexer "B" output
Single-Pole/Double-Throw Switch (SPDT) "A" normally open input.
8-channel switch/multiplexer input.
2
3
4
4-channel switch/multiplexer "B" input.
COMA
NCA
Single-Pole/Double-Throw Switch (SPDT) "A" output.
8-channel switch/multiplexer input
NO1B
INH
4-channel switch/multiplexer "B" input.
Single-Pole/Double-Throw Switch (SPDT) "A" normally closed input.
Enable digital I/O input. To enable the switch/multiplexer, connect to
GND. To disable, connect to VDD. Refer to the "Digital I/O Overvoltage
Protection" section of the data sheet.
5
6
7
NC
No Connect.
GND
Ground. Connect this pin to the system's clean analog ground plane.
ADDC
ADDC
Address "C" digital I/O input. Refer to the "Digital I/O Overvoltage Protec-
tion" section of the datasheet.
ADDB
ADDA
NO3A
NO0A
Address "B" digital I/O input. Refer to the "Digital I/O Overvoltage Protec-
tion" section of the datasheet.
8
9
ADDB
ADDA
NO3
ADDB
ADDA
Address "A" digital I/O input. Refer to the "Digital I/O Overvoltage Protec-
tion" section of the datasheet.
4-channel switch/multiplexer "A" input.
10
8-channel switch/multiplexer input.
4-channel switch/multiplexer "A" input.
NCC
Single-Pole/Double-Throw Switch (SPDT) "C" normally closed input.
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TS4100/01/02 Data Sheet
Pin Descriptions
Pin
Pin Name
TS4101
Function
TS4100
TS4102
NOC
11
NO0
8-channel switch/multiplexer input.
4-channel switch/multiplexer "A" output.
COMA
NO1A
Single-Pole/Double-Throw Switch (SPDT) "C" normally open input.
8-channel switch/multiplexer input.
12
13
NO1
NO2
4-channel switch/multiplexer "A" input
COMC
COMB
Single-Pole/Double-Throw Switch (SPDT) "C" output.
8-channel switch/multiplexer input.
NO2A
VDD
4-channel switch/multiplexer "A" input.
Single-Pole/Double-Throw Switch (SPDT) "B" output.
14
15
Power Supply Voltage Input. Bypass this pin with a 1μF cerarnic coupling
capacitor in close proximity to the TS4100-TS4102.
NO4
NO6
—
8-channel switch/multiplexer input.
NO0B
4-channel switch/multiplexer "B' input.
NOB
Single-Pole/Double-Throw Switch (SPDT) "B" normally open input.
8-channel switch/multiplexer input
16
NO2B
—
4-channel switch/multiplexer "B" input.
NCB
—
Single-Pole/Double-Throw Switch (SPDT) "B" normally closed input.
EP
For best electrical and thermal performance, solder exposed paddle to
GND.
4.1 Digital I/O Settings
Table 4.2. Digital I/O Settings
INH
Address Bits
ADDB
TS4100
COM
TS4101
TS4102
ADDC
(TS4100 and
ADDA
COMA
COMB
Output
COMA
Output
COMB
Output
COMC
Output
Output
Output
TS4102 Only)
1
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
Switch Open
NO0
NO1
NO2
NO3
NO4
NO5
NO6
NO7
NO0A
NO1A
NO2A
NO3A
NO0A
NO1A
NO2A
NO3A
NO0B
NO1B
NO2B
NO3B
NO0B
NO1B
NO2B
NO3B
NCA
NOA
NCA
NOA
NCA
NOA
NCA
NOA
NCB
NCB
NOB
NOB
NCB
NCB
NOB
NOB
NCC
NCC
NCC
NCC
NOC
NOC
NOC
NOC
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TS4100/01/02 Data Sheet
Packaging
5. Packaging
5.1 TS410x Package Dimensions
Figure 5.1. 3x3 mm 16-QFN Package Diagram
Dimension
Min
0.70
0.00
0.20
Nom
0.75
Max
0.85
0.05
0.30
A
A1
—
b
0.25
D
3.00 BSC.
1.80
D2
1.75
1.85
e
0.50 BSC.
3.00 BSC.
1.80
E
E2
1.75
0.30
—
1.85
0.40
0.05
0.05
0.05
0.10
L
0.35
aaa
—
bbb
—
—
ccc
—
—
ddd
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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TS4100/01/02 Data Sheet
Packaging
5.2 TS410x Top Marking
TS4100 Top Marking
Table 5.1. TS4100 Top Marking Explanation
Mark Method:
Pin 1 Mark:
Laser
Circle = 0.5 mm Diameter (Low-
er-Left Corner)
Font Size:
0.50 mm (20 mils)
Product ID
Line 1 Mark Format:
Line 2 Mark Format:
Line 3 Mark Format:
e.g., "T4100"
TTTT = Mfg Code
YY = Year
Manufacturing Code from the Assembly Purchase Order Form.
Assigned by the Assembly House. Corresponds to the year and
work week of the assembly release.
WW = Work Week
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Rev. 1.0 | 20
TS4100/01/02 Data Sheet
Revision History
6. Revision History
Revision 1.0
February 24, 2016
• Initial external release.
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Rev. 1.0 | 21
Table of Contents
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.1 AC Performance Considerations . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.2 Off Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.3 Total Harmonic Distortion (THD) . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.4 Bandwidth Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1.5 Programmable Gain Amplifier (PGA) with the TS4100. . . . . . . . . . . . . . . . 3
2.1.6 Switched-Capacitor Voltage Doubler with the TS4102 and TS3004 Timer . . . . . . . . . 4
2.1.7 Charge Pump Effect Considerations. . . . . . . . . . . . . . . . . . . . . . 5
2.1.8 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . .14
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Digital I/O Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 TS410x Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .19
5.2 TS410x Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table of Contents 22
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