SC644 [SEMTECH]
Light Management Unit with 4 LDOs and SemPulse®Interface; 有4个LDO和SemPulse®Interface照明管理单元
| 型号： | SC644 |
| 厂家： | 
SEMTECH CORPORATION |
| 描述： | Light Management Unit with 4 LDOs and SemPulse®Interface |
| 文件： | 总26页 (文件大小：589K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SC644
Light Management Unit with
4 LDOs and SemPulse® Interface
POWER MANAGEMENT
Features
Description
Input supply voltage range — 2.9V to 5.5V
Very high efficiency charge pump driver system with
three modes — ꢀx, ꢀ.5x, and 2x
Six programmable current sinks with 29 increments
from 0mA to 25mA
The SC644 is a high efficiency charge pump LED driver
using Semtech’s proprietary charge pump technology.
Performance is optimized for use in single cell Li-ion
battery applications.
Display backlighting is provided through six matched
current sinks with integrated fade-in and fade-out con-
trols. The LEDs can be driven as a single set or as two
different sets (for main and sub displays) with indepen-
dent controls. Four low noise, low dropout (LDO) regulators
are provided to supply power for camera module I/O and
other peripheral circuits.
Four programmable 200mA low-noise LDO regulators
Programmable driver configurations for main and
sub-display backlight
Fade-in/fade-out feature for main and sub display
backlight
SemPulse single wire interface
Backlight current accuracy — ꢀ.5% typical
Backlight current matching — 0.5% typical
Automatic sleep mode with LEDs off
Shutdown current — 0.ꢀµA typical
Ultra-thin package — 3 x 3 x 0.6 (mm)
Lead free and halogen free
The SC644 uses the proprietary SemPulse single wire
®
interface. This interface controls all functions of the device,
including backlight currents and LDO voltage outputs.
The single wire interface minimizes microcontroller and
interface pin counts.
WEEE and RoHS compliant
Applications
The SC644 enters sleep mode when all the LED drivers are
disabled. In this mode, the quiescent current is reduced
while the device continues to monitor the SemPulse inter-
face. Any combination of LDOs may be enabled when in
sleep mode.
Cellular phones, smart phones, and PDAs
LCD display modules
Portable media players
Digital cameras and GPS units
Display backlighting and LED indicators
Typical Application Circuit
Sub
Backlight
SC644
Main Backlight
VBAT = 2.9V to 5.5V
IN
OUT
SemPulse
Interface
4.7µF
SPIF
4.7µF
BL1
BL2
BYP
BL3
BL4
22nF
BL5
BL6
AGND
PGND
LDO1
LDO2
LDO3
LDO4
VLDO1 = 1.5V to 3.3V
VLDO2 = 1.2V to 1.8V
VLDO3 = 1.5V to 3.3V
Motor
1.0µF
1.0µF
1.0µF
1.0µF
2.2µF
2.2µF
US Patents: 6,504,422; 6,794,926
ꢀ
October 8, 2009
© 2009 Semtech Corporation
SC644
Pin Configuration
Ordering Information
Device
Package
SC644ULTRT(ꢀ)(2)
MLPQ-UT-20 3×3
Evaluation Board
20
19
18
17
16
SC644EVB
Notes:
IN
PGND
BL3
1
2
3
15
14
13
12
11
LDO1
LDO2
BYP
(ꢀ) Available in tape and reel only. A reel contains 3,000 devices.
(2) Lead-free packaging only. Device is WEEE and RoHS compliant,
and halogen free.
TOP VIEW
BL2
4
5
SPIF
T
8
LDO3
BL1
6
7
9
10
MLPQ-UT-20; 3x3, 20 LEAD
θJA = 35°C/W
Marking Information
644
yyww
xxxx
yyww = Date Code
xxxx = Semtech Lot No.
2
SC644
Absolute Maximum Ratings
Recommended Operating Conditions
IN, OUT (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
Cꢀ+, C2+ (V) . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VOUT + 0.3)
Pin Voltage — All Other Pins (V) . . . . . . . . . -0.3 to (VIN + 0.3)
OUT, LDOn(ꢀ) Short Circuit Duration. . . . . . . . . .Continuous
ESD Protection Level(2) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ambient Temperature Range (°C). . . . . . . . -40 ≤ TA ≤ +85
InputVoltage (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 ≤ VIN ≤ 5.5
Output Voltage (V). . . . . . . . . . . . . . . . . . . . . . 2.5 ≤ VOUT ≤ 5.25
Voltage difference between any two LEDs (V) . . . ∆VF ≤ ꢀ.0
Thermal Information
Thermal Resistance, Junction to Ambient(3) (°C/W) . . . . 35
Maximum Junction Temperature (°C) . . . . . . . . . . . . . . +ꢀ50
Storage Temperature Range (°C). . . . . . . . . . . . -65 to +ꢀ50
Peak IR Reflow Temperature (ꢀ0s to 30s) (°C) . . . . . . +260
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(ꢀ) subscript n = ꢀ, 2, 3, and 4.
(2) Tested according to JEDEC standard JESD22-Aꢀꢀ4-B.
(3) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD5ꢀ standards.
Electrical Characteristics
Unless otherwise noted, TA = +25°C for Typ, -40ºC to +85°C for Min and Max, TJ(MAX) = ꢀ25ºC, VIN = 3.7V, Cꢀ= C2 = 2.2µF, CIN = COUT = 4.7µF,
(ESR = 0.03Ω)(ꢀ)
Parameter
Symbol
Conditions
Min
Typ
Max Units
Supply Specifications
Input Supply Voltage
Shutdown Current
VIN
2.9
5.5
2.0
V
IQ(OFF)
Shutdown, VIN = 4.2V
Sleep (all LDOs off), SPIF = VIN
Sleep (all LDOs on), SPIF = VIN
0.ꢀ
90
µA
(2)
(2)
ꢀ35
450
µA
300
2.6
4.8
5.6
Total Quiescent Current
IQ
ꢀx mode, IOUT = 3.0 mA, IBLn(3) = 0.5mA, 6 LEDs on
ꢀx mode, IOUT = ꢀ50mA, IBLn = 25mA, 6 LEDs on
ꢀ.5x or 2x mode, IOUT = ꢀ50mA, IBLn = 25mA, 6 LEDs on
mA
Charge Pump Electrical Specifications
Sum of all active LED currents,
VOUT ≤ 4.2V
Maximum Total Output Current
IOUT(MAX)
ꢀ50
mA
Backlight Current Setting Range
Backlight Current Accuracy
Backlight Current Matching(4)
IBL
Nominal setting for BLꢀ – BL6
IBLn = ꢀ2mA
0
-8
25
8
mA
%
IBL_ACC
IBL-BL
ꢀ.5
0.5
IBLn = ꢀ2mA
-3.5
+3.5
%
ꢀx Mode to ꢀ.5x Mode
Falling Transition Voltage
VTRANSꢀx
VHYSTꢀx
IOUT = 50mA, IBLn = ꢀ0mA, VOUT = 3.2V
IOUT = 50mA, IBLn = ꢀ0mA, VOUT = 3.2V
3.22
250
V
ꢀ.5x Mode to ꢀx Mode Hysteresis
mV
3
SC644
Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Min
Typ
Max Units
Charge Pump Electrical Specifications (Cont.)
ꢀ.5x Mode to 2x Mode
VTRANSꢀ.5x
IOUT = 50mA, IBLn = ꢀ0mA, VOUT = 4.2V(5)
IOUT = 50mA, IBLn = ꢀ0mA, VOUT = 4.2V(5)
2.9ꢀ
520
V
Falling Transition Voltage
2x Mode to ꢀ.5x Mode Hysteresis
VHYSTꢀ.5x
mV
Current Sink Off-State
Leakage Current
IBL/FL(OFF)
fPUMP
VIN = VBLn = 4.2V
VIN = 3.2V
0.ꢀ
ꢀ
µA
Pump Frequency
250
kHz
LDO Electrical Specifications
LDOꢀ, LDO3, and LDO4
Voltage Setting Range
(6)
VLDOm
Range of nominal settings
Range of nominal settings
ꢀ.5
ꢀ.2
3.3
ꢀ.8
V
V
LDO2 Voltage Setting Range
Output Voltage Accuracy
VLDO2
ILDO = ꢀmA, TA = 25°C, 2.9V ≤ VIN ≤ 4.2V
ILDO = ꢀmA to ꢀ00mA, 2.9V ≤ VIN ≤ 4.2V
ILDOm = ꢀ50mA, VIN = VLDOm + VDm
-3
ꢀ.0
+3
+3.5
200
%
%
∆VLDO
-3.5
Dropout Voltage(6)(7)
Current Limit
VDm
ILIM
ꢀ50
mV
mA
200
ILDOm = ꢀmA,
VIN = 2.9V to 4.2V, VLDOm = 2.8V
2.ꢀ
ꢀ.3
7.2
4.8
25
Line Regulation
DVLINE
mV
mV
dB
ILDO2 = ꢀmA,
VIN = 2.9V to 4.2V, VLDO2 = ꢀ.8V
VLDOm = 3.3V,
ILDOm = ꢀmA to ꢀ00mA
Load Regulation
DVLOAD
VLDO2 = ꢀ.8V,
ILDO2 = ꢀmA to ꢀ00mA
20
ꢀ.5V < VLDOm < 3.0V, f < ꢀkHz, CBYP = 22nF,
ILDOm = 50mA, with 0.5VP-P supply ripple
PSRRm
PSRR2
50
60
Power Supply Rejection Ratio
ꢀ.2V < VLDO2 < ꢀ.8V, f < ꢀkHz, CBYP = 22nF,
ILDO2 = 50mA, with 0.5VP-P supply ripple
ꢀ0Hz < f < ꢀ00kHz, CBYP = 22nF,
CLDOm = ꢀµF, ILDOm = 50 mA,
ꢀ.5V < VLDOm < 3.0V
en-LDOm
75
50
Output Voltage Noise
µVRMS
ꢀ0Hz < f < ꢀ00kHz, CBYP = 22nF,
CLDO2 = ꢀµF, ILDO2 = 50 mA,
ꢀ.2V < VLDO2 < ꢀ.8V
en-LDO2
Minimum LDO Capacitor (8)
CLDO(MIN)
Nominal value for CLDOn
ꢀ
µF
4
SC644
Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Min
Typ
Max Units
Digital I/O Electrical Specifications (SPIF)
Input High Threshold (9)
VIH
VIL
IIH
VIN = 5.5V
VIN = 2.9V
VIN = 5.5V
VIN = 5.5V
ꢀ.6
V
Input Low Threshold (9)
Input High Current
0.4
+ꢀ
+ꢀ
V
-ꢀ
-ꢀ
µA
µA
Input Low Current
IIL
SemPulse Electrical Specifications (SPIF)
SemPulse Start-up Time(ꢀ0)
Bit Pulse Duration (9)
tSU
tHI
ꢀ
ms
µs
0.75
0.75
500
500
ꢀ0
250
250
Duration Between Bits (9)
tLO
µs
Hold Time - Address (9)
Hold Time - Data (9)
Bus Reset Time (9)
tHOLDA
tHOLDD
tBR
SPIF is held high
SPIF is held high
SPIF is held high
SPIF is pulled low
5000
µs
µs
ms
ms
Shutdown Time(ꢀꢀ)
tSD
ꢀ0
Fault Protection
Output Short Circuit Current Limit
IOUT(SC)
TOTP
OUT pin shorted to GND
Rising threshold
Hysteresis
300
ꢀ65
30
mA
°C
Over-Temperature
THYS
°C
Charge Pump
Over-Voltage Protection
VOVP
OUT pin open circuit, VOUT = VOVP
5.7
6.0
V
VUVLO-OFF
VUVLO-HYS
Increasing VIN
Hysteresis
2.7
V
Under Voltage Lockout
Notes:
800
mV
(ꢀ) Capacitors are MLCC of X5R type. Production tested with higher value capacitors than the application requires.
(2) SPIF is high for more than ꢀ0ms
(3) Subscript for all backlights (BLn), n = ꢀ, 2, 3, 4, 5, and 6. Subscripting for all LDOs (LDOn), n = ꢀ, 2, 3, 4.
(4) Current matching is defined as ꢁIBL(MAX) - IBL(MIN)] / ꢁIBL(MAX) + IBL(MIN)].
(5) Test voltage is VOUT = 4.2V — a relatively extreme LED voltage — to force a transition during test. Typically VOUT = 3.2V for white LEDs.
(6) Subscript m = ꢀ, 3, and 4 and applies only to LDOꢀ, LDO3, and LDO4.
(7) Dropoutisdefinedas(VIN-VLDOm)whenVLDOm dropsꢀ00mVfromnominal. DropoutdoesnotapplytoLDO2sinceithasamaximumoutputvoltage
of ꢀ.8V.
(8) X5R or better “temperature stable”MLCC capacitor.
(9) The source driver used to provide the SemPulse output must meet these limits.
(ꢀ0) The SemPulse start-up time is the minimum time that the SPIF pin must be held high to enable the part before commencing
communication.
(ꢀꢀ) The SemPulse shutdown time is the minimum time that the SPIF pin must be pulled low to shut the part down.
5
SC644
Typical Characteristics
Battery Current (6 LEDs) — 25mA Each
VOUT = 3.50V, IOUT = 150mA, 25°C
Backlight Efficiency (6 LEDs) — 25mA Each
VOUT = 3.50V, IOUT = 150mA, 25°C
300
260
220
180
140
100
100
90
80
70
60
50
2.7
4.2
3.9
3.6
3.3
3
3.6
3.3
3.9
3.0
2.7
4.2
VIN(V�
VIN(V�
Backlight Efficiency (6 LEDs) — 12mA Each
VOUT = 3.37V, IOUT = 72mA, 25°C
Battery Current (6 LEDs) — 12mA Each
VOUT = 3.37V, IOUT = 72mA, 25°C
140
120
100
80
100
90
80
70
60
50
60
40
3.6
3.0
3.9
3.6
2.7
4.2
3.9
3.3
2.7
4.2
3.3
3.0
VIN(V�
VIN(V�
Battery Current (6 LEDs) — 4.0mA Each
VOUT = 3.21V, IOUT = 24mA, 25°C
Backlight Efficiency (6 LEDs) — 4.0mA Each
VOUT = 3.21V, IOUT = 24mA, 25°C
60
50
40
30
100
90
80
70
60
50
20
10
3.6
4.2
3.9
3.0
3.3
2.7
4.2
3.9
3.6
3.3
3.0
2.7
VIN(V�
VIN(V�
6
SC644
Typical Characteristics (continued)
PSRR vs. Frequency — 2.8V
PSRR vs. Frequency — 1.8V
VIN=3.7V, VOUT =1.8V, IOUT = 50mA
0
VIN=3.7V, VOUT =2.8V, IOUT = 50mA
0
-10
-10
-20
-30
-40
-20
-30
-40
-50
-50
-60
-70
-60
-70
10
1000
100
1000
10000
10
10000
100
Frequency (Hz�
Frequency (Hz�
Line Regulation (LDO2)
Line Regulation (LDOm)
ILDO2 = 1mA, VLDO2 = 1.2V and 1.8V, 25°C
ILDOm = 1mA, 25°C, VLDOm = 2.8V, m = 1, 3, or 4
1
3
2
0.75
0.5
1
0.25
1.8V
2.8V
0
0
1.2V
-0.25
-0.5
-1
-2
-0.75
-1
-3
3.3
4.2
3.9
2.7
3.0
2.7
3.6
4.2
3.9
3.3
3.6
3.0
VIN (V�
VIN (V�
LDO Noise vs. Load Current — 1.8V
LDO Noise vs. Load Current — 2.8V
VLDO=1.8V, VIN=3.7V, 25°C, 10Hz < f < 100kHz
VLDO=2.8V, VIN=3.7V, 25°C, 10Hz < f < 100kHz
100
80
60
40
20
0
100
80
60
40
20
0
0
20
40
60
80
100
0
30
60
90
120
150
IOUT (mA�
IOUT (mA�
7
SC644
Typical Characteristics (continued)
Load Regulation (LDO2)
Load Regulation (LDOm)
VIN=3.6V, 25°C, m = 1, 3, or 4
VIN=3.6V, 25°C
0
0
-5
-5
1.5V
1.8V
1.2V
-10
-15
-20
2.5V
-10
1.5V
2.8V
-15
1.8V
3.3V
-20
-25
-30
-25
0
40
80
120
0
40
80
120
160
160
200
200
ILDO (mA�
ILDO (mA�
LDO Load Transient Response (1.8V)
VIN=3.7V, VLDO=ꢀ.8V, ILDO=ꢀ to ꢀ00mA, 25°C
LDO Load Transient Response (3.3V)
VIN=3.7V, VLDO=3.3V, ILDO=ꢀ to ꢀ00mA, 25°C
VLDO (50mV/div)
VLDO (50mV/div)
ILDO (100mA/div)
ILDO (100mA/div)
Time (20µꢁꢂꢀiꢃ�
Time (20µꢁꢂꢀiꢃ�
LDO Load Transient Response (1.2V)
Output Short Circuit Current Limit
VIN=3.7V, VLDO=ꢀ.2V, ILDO=ꢀ to ꢀ00mA, 25°C
VOUT=0V, VIN=4.2V, 25°C
VOUT (ꢀV/div)
VLDO (50mV/div)
ILDO (100mA/div)
IOUT (200mA/div)
Time (20µꢁꢂꢀiꢃ�
Time (1mꢁꢂꢀiꢃ�
8
SC644
Typical Characteristics (continued)
Ripple — 1X Mode
Ripple — 1.5X Mode
VIN=3.8V, 6 Backlights — ꢀ5 mA each, 25°C
VIN=3.6V, 6 Backlights — ꢀ5 mA each, 25°C
VIN (ꢀ00mV/div)
VIN (ꢀ00mV/div)
VOUT (ꢀ00mV/div)
IBL (20mA/div)
VOUT (ꢀ00mV/div)
IBL (20mA/div)
Time (20µꢁꢂꢀiꢃ�
Time (20µꢁꢂꢀiꢃ�
Output Open Circuit Protection
Ripple — 2X Mode
VIN=2.9V, 6 Backlights — ꢀ5 mA each, 25°C
VIN=3.7V, 25°C
VBL (500mV/div)
VOUT (1V/div)
VIN (ꢀ00mV/div)
5.42V
VOUT (ꢀ00mV/div)
IBL (20mA/div)
IBL (20mA/div)
Time (20µꢁꢂꢀiꢃ�
Time (200µꢁꢂꢀiꢃ�
9
SC644
Pin Descriptions
Pin #
Pin Name
Pin Function
ꢀ
2
3
4
5
6
7
8
9
IN
PGND
BL3
Battery voltage input
Ground pin for high current charge pump
Current sink output for backlight LED 3 — leave this pin open if unused
Current sink output for backlight LED 2 — leave this pin open if unused
Current sink output for backlight LED ꢀ — leave this pin open if unused
Current sink output for backlight LED 4 — leave this pin open if unused
Current sink output for backlight LED 5 — leave this pin open if unused
Current sink output for backlight LED 6 — leave this pin open if unused
Analog ground pin — connect to ground and separate from PGND current
BL2
BLꢀ
BL4
BL5
BL6
AGND
ꢀ0
ꢀꢀ
ꢀ2
LDO4
LDO3
SPIF
Output of LDO4
Output of LDO3
SemPulse single wire interface pin — used to enable/disable the device and to configure all regis-
ters (refer to Register Map and SemPulse Interface sections)
ꢀ3
ꢀ4
ꢀ5
ꢀ6
ꢀ7
ꢀ8
ꢀ9
20
BYP
LDO2
LDOꢀ
OUT
C2+
Cꢀ+
Cꢀ-
Bypass pin for LDO reference — connect a 22nF ceramic capacitor to AGND
Output of LDO2
Output of LDOꢀ
Charge pump output — all LED anode pins should be connected to this pin
Positive connection to bucket capacitor 2
Positive connection to bucket capacitor ꢀ
Negative connection to bucket capacitor ꢀ
Negative connection to bucket capacitor 2
C2-
Thermal pad for heatsinking purposes — connect to ground plane using multiple vias — not con-
nected internally
T
THERMAL PAD
ꢀ0
SC644
Block Diagram
C2+
17
C1+
18
C1-
19
C2-
20
VIN
Fractional Charge Pump
(1x, 1.5x, 2x)
IN
1
16
OUT
SPIF 12
Oscillator
SemPulse
Digital
5
4
3
6
7
8
BL1
BL2
BL3
BL4
BL5
Interface
and Logic
Control
Current
Setting
DAC
LDO
Voltage
Reference
BYP 13
BL6
Voltage
Setting
DAC
VIN
2
9
PGND
AGND
LDO1
15
14
11
10
LDO1
LDO2
LDO3
LDO4
VIN
LDO2
VIN
LDO3
VIN
LDO4
ꢀꢀ
SC644
Applications Information
and support the output drive requirements. Capacitors
with X7R or X5R ceramic dielectric are strongly recom-
mended for their low ESR and superior temperature and
voltage characteristics. Y5V capacitors should not be
used as their temperature coefficients make them unsuit-
able for this application.
General Description
This design is optimized for handheld applications sup-
plied from a single cell Li-Ion and includes the following
key features:
• A high efficiency fractional charge pump that
supplies power to all LEDs
• Six matched current sinks that control LED back-
lighting current, with 0mA to 25mA per LED.
• Four adjustable LDOs. LDOꢀ , LDO3, and LDO4
are adjustable with ꢀ5 settings from ꢀ.5V to 3.3V.
LDO2 is adjustable with 7 settings from ꢀ.2V to
ꢀ.8V.
LED Backlight Current Sinks
The backlight current is set via the SemPulse interface.
The current is regulated to one of 29 values between
0mA and 25mA. The step size varies depending upon the
current setting. Between 0mA and 5mA, the step size is
0.5mA. The step size increases to ꢀmA for settings
between 5mA and 2ꢀmA. Steps are 2mA between 2ꢀmA
and 25mA. The variation in step size allows finer adjust-
ment for dimming functions in the low current setting
range and coarse adjustment at higher current settings
where small current changes are not visibly noticeable in
LED brightness. A zero setting is also included to allow
the current sink to be disabled by writing to either the
enable bit or the current setting register for maximum
flexibility.
High Current Fractional Charge Pump
The backlight outputs are supported by a high efficiency,
high current fractional charge pump output. The charge
pump multiplies the input voltage by ꢀ, ꢀ.5 or 2 times. The
charge pump switches at a fixed frequency of 250kHz in
ꢀ.5x and 2x modes and is disabled in ꢀx mode to save
power and improve efficiency.
The mode selection circuit automatically selects the mode
as ꢀx, ꢀ.5x, or 2x based on circuit conditions such as LED
voltage, input voltage, and load current. The ꢀx mode is
the most efficient of the three modes, followed by ꢀ.5x
and 2x modes. Circuit conditions such as low input voltage,
high output current, or high LED voltage place a higher
demand on the charge pump output. A higher numerical
mode (ꢀ.5x or 2x) may be needed momentarily to main-
tain regulation at the OUT pin during intervals of high
demand. The charge pump responds to momentary high
demands, setting the charge pump to the optimum mode
to deliver the output voltage and load current while opti-
mizing efficiency. Hysteresis is provided to prevent mode
toggling.
All backlight current sinks have matched currents, even
when there is variation in the forward voltages (∆VF ) of
the LEDs. A minimum ∆VF of ꢀ.2V is supported when the
input voltage (VIN) is at 3.0V. Higher ∆VF LED mis-match is
supported when VIN is higher than 3.0V. All current sink
outputs are compared and the lowest output is used for
setting the voltage regulation at the OUT pin. This is
done to ensure that sufficient bias exists for all LEDs.
The backlight LEDs default to the off state upon power-
up. For backlight applications using fewer than six LEDs,
any unused output must be left open and the unused
LED must remain disabled. When writing to the backlight
enable register, a zero (0) must be written to the corre-
sponding bit of any unused output.
The charge pump requires two bucket capacitors for
proper operation. One capacitor must be connected
between the Cꢀ+ and Cꢀ- pins and the other must be con-
nected between the C2+ and C2- pins as shown in the
typical application circuit diagram. These capacitors
should be equal in value, with a nominal capacitance of
2.2µF to support the charge pump current requirements.
The device also requires a 4.7µF capacitor on the IN pin
and a 4.7µF capacitor on the OUT pin to minimize noise
Backlight Quiescent Current
The quiescent current required to operate all five back-
lights is reduced when backlight current is set to 4.0mA
or less. This feature results in higher efficiency under
light-load conditions. Further reduction in quiescent
current will result from using fewer than six LEDs.
ꢀ2
SC644
Applications Information (continued)
Main and Sub Backlight Bank Configuration
The six LED backlight drivers can be configured as a single
bank or as two independent banks — one dedicated for
a main display and the other for a sub display. This feature
allows the device to drive two sets of LEDs with different
settings so different current and fade settings can be
used.
Immeꢀiate
change to new
bright leꢃel
No change
FADE=0
Write new
bright leꢃel
Write FADE=0
FADE=0
Write
FADE=1
Immeꢀiate
change to
new bright
leꢃel
Write
FADE=0
FADE=1
The Register Map contains two separate control registers
for main and sub currents. Register 0ꢀh contains the
current setting code for the main bank, and register 02h
contains the setting code for the sub bank. There are also
three bits in register 0Ah that control which drivers are
assigned to each display. The default setting assigns all
six LED drivers to the main display control register. In this
scenario, the current control settings for each LED driver
come from register 0ꢀh. Other settings are available that
allow the groupings to be defined so that any number
from ꢀ to 6 drivers can be grouped as the main display
backlight drivers, with the remaining drivers assigned to
the sub display backlight by default. See Table 8 of the
Register Map section for more details.
No
change
FADE=1
Write
FADE=1
Write new
bright
Faꢀe=0
leꢃel
Faꢀe
beginꢁ
Faꢀe
enꢀꢁ
Faꢀe iꢁ reꢀirecteꢀ
towarꢀ the new
ꢃalue from current
ꢁtate
Faꢀe
proceꢁꢁing(1�
No
change
Write new
bright leꢃel
Write
Faꢀe=1
Write
Continue
faꢀe uꢁing
new rate
new faꢀe
rate
Note:
(1� When the ꢀata in backlight
enable regiꢁter 00h iꢁ not 00h
Backlight Fade-in and Fade-out Function
Register 09h contains bits that control the fade state of
each display (main and sub). When enabled, the fade
function causes the backlight settings to step from their
current state to the next programmed state as soon as
the new state is stored in its register. For example, if the
backlight is set at 25mA and the next setting is the off
state, the backlight will step from 25mA down to 0mA
using all 29 settings at the fade rate specified by the bits
in register 09h. The same is true when turning on or
increasing the backlight current — the backlight current
will step from the present level to the new level at the
step rate defined in register 09h. This process applies for
both the main and the sub displays. The state diagram in
Figure ꢀ describes all possible conditions for a fade opera-
tion. More details can be found in the Register Map
section.
Figure 1 — State Diagram for Fade Function
Fade-In from Off State
When the initial state of the main or sub backlight current
register is 00h (the data value for 0mA), fading to an on
state is accomplished by following the steps listed in
Table ꢀ. Following these steps explicitly will ensure that
the fade-in operation will proceed with no interruption at
the rate specified in the Main/Sub Backlight Fade register
(09h). This procedure must be followed regardless of
which backlight grouping configuration is being used.
Note that it is only necessary to set the BLEN bits for the
main or sub display that is required to fade.
ꢀ3
SC644
Applications Information (continued)
Table 1 — Fade-In from Off State
dure must be followed regardless of the backlight
grouping configuration.
Command
Sequence
Action
Data
Table 3 — Fading between Different On States
Binary value
xx0xxx, xxxxx0,
or xx0xx0
ꢀ. Disable fade for
the bank
Command
Sequence
Write to register 09h
Action
Data
Any value from 0ꢀh
through 3Fh
2. Set Main and/or
Sub backlights to
0.5mA
ꢀ. Enable fade
Write to register 09h
Write to register 0ꢀh
and or 02h(ꢀ)
04h
2. Set new value of Write to register 0ꢀh Any value from 05h
backlight current and/or 02h through ꢀFh
Binary value
xxꢀxx0 , xxꢀxxꢀ,
or xx0xxꢀ
3. Enable fade for
the bank
Write to register 09h
Write to register 00h
Additional Information
For more details about the Fade-in/Fade-out function,
refer to the SC644 Backlight Driver Software User’s Guide
and SemPulse Interface Specification document and to the
associated software drivers available for this device
(contact your sales office for more details).
Any value from 0ꢀh
through 3Fh
4. Set BLEN bits
5. Set new value of
backlight current
for the bank
Write to register 0ꢀh Any value from 05h
and/or 02h through ꢀFh
Notes:
(ꢀ) Write only to the banks which will fade
Programmable LDO Outputs
Four low dropout (LDO) regulators are included to supply
power to peripheral circuits. Each LDO output voltage
setting has 3.5% accuracy over the operating tempera-
ture range. Output current greater than specification is
possible at somewhat reduced accuracy (refer to the
typical characteristic section of this datasheet for load
regulation examples). LDOꢀ, LDO3, and LDO4 have iden-
tical specifications, with a programmable output ranging
from ꢀ.5V to 3.3V. LDO2 is specified to operate with pro-
grammable output ranging from ꢀ.2V to ꢀ.8V. LDO2 also
has lower noise specifications so that it can be used with
noise sensitive circuits.
Fade-Out from any On State to Off State
Fading the backlight LEDs from any active state to the off
state follows a simple procedure. The sequence of com-
mands for this action is shown in Table 2. Following these
steps explicitly will ensure that the fade-out operation will
proceed with no interruption at the rate specified in the
Main/Sub Backlight Fade register (09h). This procedure
must be followed regardless of the backlight grouping
configuration.
Table 2 — Fade-Out from any On State to Off State
Command
Sequence
Action
Data
Shutdown Mode
Any value from 0ꢀh
through 3Fh
ꢀ. Enable fade
Write to register 09h
The device is disabled when the SPIF pin is held low for
the shutdown time specified in the electrical characteris-
tics section. All registers are reset to default condition at
shutdown. Typical current consumption is this mode is
0.ꢀµA
2. Set Main and/or
Sub backlights to
0mA
Write to register 0ꢀh
and/or 02h
00h
Fading Between Different On States
Sleep Mode
Fading from one backlight level to another (up or down)
also follows a simple procedure. The sequence of com-
mands for this action is shown in Table 3. Following these
steps explicitly will ensure that the fade-in/fade-out oper-
ation will proceed with no interruption at the rate specified
in the Main/Sub Backlight Fade register (09h). This proce-
When all backlights are off the charge pump is disabled,
and sleep mode is activated. This is a reduced current
mode that helps minimize overall current consumption.
In sleep mode, the SemPulse interface continues to
monitor its input for commands from the host. Typical
current consumption in this mode is 90µA.
ꢀ4
SC644
Applications Information (continued)
Charge Pump Output Current Limit
Protection Features
The SC644 provides several protection features to safe-
guard the device from catastrophic failures. These features
include:
The device limits the charge pump current at the OUT pin.
When OUT is shorted to ground, the output current will
typically equal 300mA. The output current is also limited
to 300mA when over loaded resistively.
• Output Open Circuit Protection
• Over-Temperature Protection
• Charge Pump Output Current Limit
• LDO Current Limit
LDO Current Limit
The device limits the current at all LDO output pins. The
minimum limit is 200mA, so load current of greater than
the rated current can be used (with degraded accuracy)
without tripping the current limit.
• LED Float Detection
Output Open Circuit Protection
Over-Voltage Protection (OVP) at the OUT pin prevents
the charge pump from producing an excessively high
output voltage. In the event of an open circuit between
the OUT pin and all current sinks (no loads connected),
the charge pump runs in open loop and the voltage rises
up to the OVP limit. OVP operation is hysteretic, meaning
the charge pump will momentarily turn off until VOUT is
sufficiently reduced. The maximum OVP threshold is 6.0V,
allowing the use of a ceramic output capacitor rated at
6.3V with no concern of over-voltage damage. Typical OVP
voltage is 5.7V.
LED Float Detection
Float detect is a fault detection feature of the LED back-
light outputs. If an output is programmed to be enabled
and an open circuit fault occurs at any backlight output,
that output will be disabled to prevent a sustained output
OVP condition from occurring due to the resulting open
loop. Float detect ensures device protection but does not
ensure optimum performance. Unused LED outputs must
be disabled to prevent an open circuit fault from
occurring.
Thermal Management
Over-Temperature Protection
The device has the potential for peak power dissipation
equal to 2.75W when all outputs are simultaneously oper-
ating at maximum rated current and powered by a fully
charged Li-Ion cell equal to 4.2V. A calculation of the
maximum power dissipation of the device should be done
to identify if power management measures are needed to
prevent overheating. The MLP package is capable of dis-
sipating ꢀ.85W when proper layout techniques are used.
The Over-Temperature (OT) protection circuit prevents the
device from overheating and experiencing a catastrophic
failure. When the junction temperature exceeds ꢀ65°C, the
device goes into thermal shutdown with all outputs dis-
abled until the junction temperature is reduced. All
register information is retained during thermal shutdown.
Hysteresis of 30°C is provided to ensure that the device
cools sufficiently before re-enabling.
ꢀ5
SC644
Applications Information (continued)
• Figure 3 shows the pads that should be con-
PCB Layout Considerations
nected to the ground plane with multiple vias.
Make all ground connections to a solid ground
plane as shown in Figure 4.
The layout diagram in Figure 2 illustrates a proper two-
layer PCB layout for the SC644 and supporting
components. Following fundamental layout rules is
critical for achieving the performance specified in the
Electrical Characteristics table. The following guidelines
are recommended when developing a PCB layout:
• If a ground layer is not feasible, the following
groupings should be connected:
PGND — CIN, COUT
AGND — Ground Pad, CLDOꢀ, CLDO2,
CLDO3, CLDO4, CBYP
• Place all bypass and decoupling capacitors —
Cꢀ, C2, CIN, COUT, CLDOꢀ, CLDO2, CLDO3,
CLDO4, and CBYP as close to the device as
possible.
• All charge pump current passes through IN,
OUT, and the bucket capacitor connection pins.
Ensure that all connections to these pins make
use of wide traces so that the resistive drop on
each connection is minimized.
• If no ground plane is available, PGND and AGND
should be routed back to the negative battery
terminal, separately, using thick traces. Joining
the two ground returns at the terminal prevents
large pulsed return currents from mixing with
the low-noise return currents of the LDOs.
• All LDO output traces should be made as wide
as possible to minimize resistive losses.
• The thermal pad should be connected to the
ground plane using multiple vias to ensure
proper thermal connection for optimal heat
transfer.
• The following capacitors — CLDOꢀ, CLDO2,
CLDO3, CLDO4, and CBYP should be grounded
together. Connect these capacitors to the
ground plane at one point near the AGND pin
as shown in Figure 2.
Ground Plane
PGND
VOUT
C2
C1
COUT
VIN
Figure 3 — Layer 1
CLDO1
CIN
IN
LDO1
LDO2
BYP
CLDO2
CBYP
PGND
PGND
BL3
BL2
BL1
SC644
PGND
SPIF
LDO3
CLDO3
CLDO4
AGND
Figure 4 — Layer 2
Figure 2 — Recommended PCB Layout
ꢀ6
SC644
SemPulse Interface
Introduction
®
tHOLDD when the pulse train is completed. If the proper
hold time is not received, the interface will keep counting
pulses until the hold time is detected. If the total exceeds
63 pulses, the write will be ignored and the bus will reset
after the next valid hold time is detected. After the bus
has been held high for tHOLDD, the bus will expect the next
pulse set to be an address write. Note that this is the same
effect as the bus reset that occurs when tHOLDA exceeds its
maximum specification. For this reason, there is no
maximum limit on tHOLDD — the bus simply waits for the
next valid address to be transmitted.
SemPulse is a write-only single wire interface. It provides
access to up to 32 registers that control device functional-
ity. Two sets of pulse trains are transmitted to generate a
complete SemPulse command. The first pulse set is used
to set the desired address. After the bus is held high for
the address hold period, the next pulse set is used to write
the data value. After the data pulses are transmitted, the
bus is held high again for the data hold period to signify
the data write is complete. At this point the device latches
the data into the address that was selected by the first set
of pulses. See the SemPulse Timing Diagrams for descrip-
tions of all timing parameters.
Multiple Writes
It is important to note that this single-wire interface
requires the address to be paired with its corresponding
data. If it is desired to write multiple times to the same
address, the address must always be re-transmitted prior
to the corresponding data. If it is only transmitted one
time and followed by multiple data transmissions, every
other block of data will be treated like a new address. The
result will be invalid data writes to incorrect addresses.
Note that multiple writes only need to be separated by
the minimum tHOLDD for the slave to interpret them cor-
rectly. As long as tHOLDA between the address pulse set and
the data pulse set is less than its maximum specification
but greater than its minimum, multiple pairs of address
and data pulse counts can be made with no detrimental
effects.
Chip Enable/Disable
The device is enabled when the SemPulse interface pin
(SPIF) is pulled high for greater than tSU. If the SPIF pin is
pulled low again for more than tSD, the device will be
disabled.
Address Writes
The first set of pulses can range between 0 and 3ꢀ (or ꢀ to
32 rising edges) to set the desired address. After the
pulses are transmitted, the SPIF pin must be held high for
tHOLDA to signal to the slave device that the address write is
finished. If the pulse count is between 0 and 3ꢀ and the
line is held high for tHOLDA, the address is latched as the
destination for the data word. If the SPIF pin is not held
high for tHOLDA, the slave device will continue to count
pulses. If the total exceeds 3ꢀ pulses, the write will be
ignored and the bus will reset after the next valid hold
time is detected. Note that if tHOLDA exceeds its maximum
specification, the bus will reset. This means that the com-
munication is ignored and the bus resumes monitoring
the pin, expecting the next pulse set to be an address.
Standby Mode
Once data transfer is completed, the SPIF line must be
returned to the high state for at least ꢀ0ms to return to the
standby mode. In this mode, the SPIF line remains idle
while monitoring for the next command. This mode
allows the device to minimize current consumption
between commands. Once the device has returned to
standby mode, the bus is automatically reset to accept the
address pulses as the next data block. This safeguard is
intended to reset the bus to a known state (waiting for the
beginning of a write sequence) if the delay exceeds the
reset threshold.
Data Writes
After the bus has been held high for the minimum address
hold period, the next set of pulses are used to write the
data value. The total number of pulses can range from 0
to 63 (or ꢀ to 64 rising edges) since there are a total of 6
register bits per register. Just like with the address write,
the data write is only accepted if the bus is held high for
ꢀ7
SC644
SemPulse Interface (continued)
®
SemPulse Timing Diagrams
The SemPulse single wire interface is used to enable or disable the device and configure all registers (see Figure 5). The
timing parameters refer to the digital I/O electrical specifications.
Address is set
Up to 32 rising edges
(0 to 31 pulses)
Up to 64 rising edges
(0 to 63 pulses)
Data is written
SPIF
t = tSU
t = tHOLDA
t = tHOLDD
tHI
tLO
Figure 5 — Uniform Timing Diagram for SemPulse Communication
Timing Example 1
In this example (see Figure 6), the slave chip receives a sequence of pulses to set the address and data, and the pulses
experience interrupts that cause the pulse width to be non-uniform. Note that as long as the maximum high and low
times are satisfied and the hold times are within specification, the data transfer is completed regardless of the number
of interrupts that delay the transmission.
Address is set to
register 02h
Data written is
000011
SPIF
tLO
t = tSU
tHI
t = tHOLDA
t = tHOLDD
t < tHImax
t < tLOmax
Figure 6 — SemPulseData Write with Non-Uniform Pulse Widths
Timing Example 2
In this example (see Figure 7), the slave chip receives a sequence of pulses to set the address and data, but an interrupt
occurs during a pulse that causes it to exceed the minimum address hold time. The write is meant to be the value 03h
in register 05h, but instead it is interpreted as the value 02h written to register 02h. The extended pulse that is delayed
by the interrupt triggers a false address detection, causing the next pulse set to be interpreted as the data set. To avoid
any problems with timing, make sure that all pulse widths comply with their timing requirements as outlined in this
datasheet.
Address is set to register
03h (address and data are
now out of order)
Address is set to
register 02h
Data written is
000010
SPIF
Interrupt
duration
t > tHImax
t = tHOLDA
t = tHOLDD
Figure 7 — Faulty SemPulse Data Write Due to Extended Interrupt Duration
ꢀ8
SC644
Register Map(1)
Reset
Value
Address(2)
D5
D4
D3
D2
D1
D0
Description
00h
0ꢀh
02h
05h
06h
07h
08h
09h
0Ah
BL6EN
0(3)
BL5EN
MBL4
SBL4
0(3)
BL4EN
MBL3
SBL3
BL3EN
MBL2
BL2EN
MBLꢀ
BLꢀEN
MBL0
00h
00h
00h
00h
00h
00h
00h
00h
00h
Backlight Enable
Main Backlight Current
Sub Backlight Current
LDOꢀ
0(3)
SBL2
SBLꢀ
SBL0
0(3)
LDOꢀV3
0(3)
LDOꢀV2
LDO2V2
LDO3V2
LDO4V2
MFADEꢀ
MB2
LDOꢀVꢀ
LDO2Vꢀ
LDO3Vꢀ
LDO4Vꢀ
MFADE0
MBꢀ
LDOꢀV0
LDO2V0
LDO3V0
LDO4V0
MFADE
MB0
0(3)
0(3)
LDO2
0(3)
0(3)
LDO3V3
LDO4V3
SFADE
0(3)
LDO3
0(3)
0(3)
LDO4
SFADEꢀ
0(3)
SFADE0
0(3)
Main/Sub Backlight Fade
Main/Sub Bank Select
Notes:
(ꢀ) all registers are write-only
(2) Addresses 03h and 04h are not used
(3) 0 = always write a 0 to these bits
Definition of Registers and Bits
BL Enable Control Register (00h)
This register enables the backlight current sinks.
BL6EN through BL1EN [D5:D0]
These bits are used to enable current sinks. These current
sinks will then sink whatever current is set in the corre-
sponding current control register.
Main Backlight Current Control Register (01h)
This register is used to set the currents for the LED drivers
designated as main backlight current sinks. Note these
current sinks can be disabled using register 00h or by
writing the 0mA value into this register.
Bit D5
This bit is unused and is always a zero.
ꢀ9
SC644
Register Map (continued)
MBL4 through MBL0 [D4:D0]
Sub Backlight Current Control Register (02h)
These bits are used to set the current for the main back-
light current sinks. All enabled current sinks will sink the
same current as shown in Table 4.
This register is used to set the currents for the LED drivers
designated as sub backlight current sinks. Note these
current sinks can be disabled using register 00h or by
writing the 0mA value into this register.
Table 4 — Main Backlight Current Settings
Bit D5
Backlight
MBL4 MBL3 MBL2 MBL1 MBL0
Current (mA)
This bit is unused and is always a zero.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
See note ꢀ
See note ꢀ
See note ꢀ
0.5
ꢀ
ꢀ.5
2
2.5
3
3.5
4
4.5
5
6
7
8
9
ꢀ0
ꢀꢀ
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
ꢀ7
ꢀ8
ꢀ9
20
2ꢀ
23
25
(ꢀ) Reserved for future use.
20
SC644
Register Map (continued)
SBL4 through SBL0 [D4:D0]
LDO1 Control Register (05h)
These bits are used to set the current for the sub backlight
current sinks. All enabled current sinks will sink the same
current as shown in Table 5.
This register is used to enable LDOꢀ and set its output
voltage level.
Bits [D5:D4]
These bits are unused and are always zeroes.
Table 5 — Sub Backlight Current Settings
Backlight
SBL4 SBL3 SBL2 SBL1 SBL0
Current (mA)
LDO1V3 through LDO1V0 [D3:D0]
These bits set the output voltage of LDOꢀ as shown in
Table 6.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
See note ꢀ
See note ꢀ
Table 6 — LDO1 Control Codes
See note ꢀ
LDO1V3 LDO1V2 LDO1V1 LDO1V0
VLDO1
0.5
ꢀ
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
OFF
3.3V
3.2V
3.ꢀV
3.0V
2.9V
2.8V
2.7V
2.6V
2.5V
2.4V
2.2V
ꢀ.8V
ꢀ.7V
ꢀ.6V
ꢀ.5V
ꢀ.5
2
2.5
3
3.5
4
4.5
5
6
7
8
9
ꢀ0
ꢀꢀ
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
ꢀ7
ꢀ8
ꢀ9
20
2ꢀ
23
25
(ꢀ) Reserved for future use.
2ꢀ
SC644
Register Map (continued)
LDO3V3 through LDO3V0 [D3:D0]
These bits are used to set the output voltage of LDO3 as
shown in Table 8.
LDO2 Control Register (06h)
This register is used to enable LDO2 and set its output
voltage level.
Table 8 — LDO3 Control Codes
Bits [D5:D3]
These bits are unused and are always zeroes.
LDO3V3 LDO3V2 LDO3V1 LDO3V0
VLDO3
LDO2V2 through LDO2V0 [D2:D0]
These bits are used to set the output voltage of LDO2 in
accordance with Table 7.
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
OFF
3.3V
3.2V
3.ꢀV
3.0V
2.9V
2.8V
2.7V
2.6V
2.5V
2.4V
2.2v
ꢀ.8V
ꢀ.7V
ꢀ.6V
ꢀ.5V
Table 7 — LDO2 Control Codes
LDO2V2
LDO2V1
LDO2V0
VLDO2
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
OFF
ꢀ.8V
ꢀ.7V
ꢀ.6V
ꢀ.5V
ꢀ.4V
ꢀ.3V
ꢀ.2V
LDO3 Control Register (07h)
This register is used to enable LDO3 and set its output
voltage level.
Bits [D5:D4]
These bits are unused and are always zeroes.
22
SC644
Register Map (continued)
MFADE1 and MFADE0 [D2:D1]
LDO4 Control Register (08h)
This register is used to enable LDO4 and set its output
voltage level.
These bits are used to set the rise/fall rate between two
backlight currents for the main display as show in Table
ꢀ0. For the fade feature to be active, the MFADE bit must
be set. The number of steps required to change the back-
light current will be equal to the change in binary count
of bits MBL4 through MBL0.
Bits [D5:D4]
These bits are unused and are always zeroes.
LDO4V3 through LDO4V0 [D3:D0]
These bits are used to set the output voltage of LDO4 as
shown in Table 9.
Table 10 — Main Display Fade Control Bits
Fade Feature Rise/
Fall Rate (ms/step)
MFADE1
MFADE0
Table 9 — LDO4 Control Codes
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
32
24
ꢀ6
8
LDO4V3 LDO4V2 LDO4V1 LDO4V0
VLDO4
0
0
0
0
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
ꢀ
ꢀ
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
0
ꢀ
OFF
3.3V
3.2V
3.ꢀV
3.0V
2.9V
2.8V
2.7V
2.6V
2.5V
2.4V
2.2V
ꢀ.8V
ꢀ.7V
ꢀ.6V
ꢀ.5V
MFADE [D0]
This bit is used to enable or disable the fade feature.
When MFADE is enabled and a new main backlight
current is set, this current will change from its existing
value to the new value written in MBLꢁ4:0] at the rate
determined by MFADEꢀ and MFADE0 (in ms/step). A new
setting cannot be written during an ongoing fade opera-
tion, but an on-going fade operation may be cancelled by
writing 0 to the MFADE bit. Clearing the MFADE bit during
an ongoing fade operation changes the current immedi-
ately to the value of MBLꢁ4:0]. The number of counts to
complete a fade operation equals the difference between
the old and new MBLꢁ4:0] settings. If MFADE is cleared,
the current level will change immediately without the
fade delay. The rate of fade may be changed dynamically
by writing new values to the MFADEꢀ and MFADE0 bits.
The total fade time is given by the number of steps
between old and new backlight values (see Table 4), mul-
tiplied by the rate of fade in ms/step.
Fade Control Register (09h)
This register contains the fade enables and rate controls
for both the main display and sub display LED driver
banks.
23
SC644
Register Map (continued)
SFADE1 and SFADE0 [D5:D4]
Bank Selection Register (0Ah)
These bits are used to set the rise/fall rate between two
backlight currents for the sub display as show in Table ꢀꢀ.
For the fade feature to be active, the SFADE bit must be
set. The number of steps required to change the backlight
current will be equal to the change in binary count of bits
SBL4 through SBL0.
This register contains the bits that determine which LED
drivers are assigned to the main display and which are
part of the sub display bank.
Bits [D5:D3]
These bits are unused and are always zeroes.
Table 11 — Sub Display Fade Control Bits
MB2, MB1, and MB0 [D2:D0]
These bits are used to set the number of LED drivers dedi-
cated to a main backlight function. This allows the device
to drive two different sets of LEDs with different settings
for use in products like clamshell-style mobile phones that
have a main display and a sub display with different light-
ing requirements. Note that any driver not selected for
the main display will automatically be assigned to the sub
display set. The code set by these three bits determines
which LED drivers are dedicated to the main display
according to the assignments listed in Table ꢀ2.
Fade Feature Rise/
Fall Rate (ms/step)
SFADE1
SFADE0
0
0
ꢀ
ꢀ
0
ꢀ
0
ꢀ
32
24
ꢀ6
8
SFADE [D3]
This bit is used to enable or disable the fade feature. When
SFADE is enabled and a new main backlight current is set,
the current will change from its existing setting to the new
setting written in SBLꢁ4:0] at the rate determined by
SFADEꢀ and SFADE0 (in ms/step). A new setting cannot
be written during an ongoing fade operation, but an on-
going fade operation may be cancelled by writing 0 to the
SFADE bit. Clearing the SFADE bit during an ongoing fade
operation changes the current immediately to the value
of SBLꢁ4:0]. The number of counts to complete a fade
operation equals the difference between the old and new
SBLꢁ4:0] settings. If SFADE is cleared, the current level will
change immediately without the fade delay. The rate of
fade may be changed dynamically by writing new values
to the SFADEꢀ and SFADE0 bits. The total fade time is
given by the number of steps between old and new back-
light values (see Table 5), multiplied by the rate of fade in
ms/step.
Table 12 — Main Display Driver Assignment Codes
Main Display Sub Display
Led Drivers LED Drivers
MB2
MB1
MB0
0
0
0
0
ꢀ
ꢀ
0
0
ꢀ
ꢀ
0
0
0
ꢀ
0
ꢀ
0
ꢀ
BLꢀ - BL6
BLꢀ - BL5
BLꢀ - BL4
BLꢀ - BL3
BLꢀ - BL2
BLꢀ
none
BL6
BL5-BL6
BL4 - BL6
BL3 - BL6
BL2 - BL6
BLꢀ - BL6
(default)
ꢀꢀ0 through ꢀꢀꢀ
none
24
SC644
Outline Drawing — MLPQ-UT-20 3x3
B
E
DIMENSIONS
INCHES MILLIMETERS
MIN NOM MAX MIN NOM MAX
A
D
DIM
A
-
-
-
.020
A1 .000
A2
.024 0.50
.002 0.00
0.60
0.05
-
(.006)
(0.152)
PIN 1
INDICATOR
(LASER MARK)
b
D
.006 .008 .010 0.15 0.20 0.25
.114 .118 .122 2.90 3.00 3.10
D1 .061 .067 .071 1.55 1.70 1.80
.114 .118 .122 2.90 3.00 3.10
E1 .061 .067 .071 1.55 1.70 1.80
E
e
L
N
aaa
bbb
.016 BSC
.012 .016 .020 0.30 0.40 0.50
0.40 BSC
A2
C
20
.003
.004
20
0.08
0.10
A
SEATING
PLANE
aaa C
A1
D1
e
LxN
E/2
E1
2
1
N
D/2
bxN
bbb
C A B
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
3.
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
DAP IS 1.90 x 1.90mm.
25
SC644
Land Pattern — MLPQ-UT-20 3x3
K
DIMENSIONS
INCHES MILLIMETERS
R
DIM
(.114)
.083
.067
.067
.016
.004
.008
.031
.146
(2.90)
2.10
1.70
1.70
0.40
0.10
0.20
0.80
3.70
C
G
H
K
P
R
X
Y
Z
Z
(C)
H
G
Y
X
P
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 930ꢀ2
Phone: (805) 498-2ꢀꢀꢀ Fax: (805) 498-3804
www.semtech.com
26
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