SED1351F0B [SEIKO]
IC,LCD CONTROLLER,CMOS,QFP,100PIN;
| 型号： | SED1351F0B |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | IC,LCD CONTROLLER,CMOS,QFP,100PIN CD |
| 文件： | 总18页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SED1351
GRAPHICS LCD CONTROLLER
■ DESCRIPTION
The SED1351F is a graphics LCD controller capable of controlling medium to large resolution displays. It
transfers data from MPU to external frame buffer RAM and converts this data to display signals for LCD
drivers. The SED1351F can display images with 4 gray shades and support display duty cycle as high as 1/
1024.
The SED1351F is designed to achieve high efficiency and data throughput to the LCD. It has a cycle steal
mode which allows MPU to access frame buffer RAM without interfering with the display operation. The
SED1351F can directly interface with up to eight 64K-bit SRAMs or two 256K-bit SRAMs.
The SED1351F can operate with either 5V or 3V power supply. The 5V version chip is the SED1351F0A and
the 3V version chip is the SED1351FLB.
■ FEATURES
Low-power CMOS technology
Maximum number of rows
•
•
•
•
•
•
•
•
•
•
•
8-bit or 16-bit MPU data interface
Directinterfacewith80xx,Z80and68xxxMPU
Binary mode ............ 2048
Gray mode .............. 1024
Maximum number of rows:
4- or 8-bit panel data bus for single panel and
4-bit bus for dual panel
Single panel ............ 1024
Dual panel ...............2048
SupportlogicalORoflayersandpaneldivision
Smooth vertical scrolling
Maximumdisplaysizeswhen64K-byteSRAMs
are used:
Virtual screen display up to 1024
Binary mode ............ 2048 × 256 / 1024 × 512
Gray mode .............. 1024 × 256 / 512 × 512
Binary mode (on/off only) generates black &
white images
Available models:
•
Gray mode (on/off and two gray steps) gener-
ates images with 4 gray shades
•
SED1351F0A ............ 5V, QFP5-100 pin
SED1351FLB ............ 3V,QFP15-100 pin
■ SYSTEM BLOCK DIAGRAM
CLOCK
DATA
CONTROL
ADDRESS
MONO LCD
SED1351F
MPU
80xx
Z80
68xxx
SRAM
8 of 8K × 8 or
2 of 32K × 8
197
SED1351
■ INTERFACE WITH 8-BIT MPU (Z-80) AND 64K-BIT SRAM (8 of 8K x 8)
Z80
SED1351F
UD0~UD3,LD0~LD3
A0~A15
A0~A15
YD
LP
MONO LCD
IOCS
DECODER
XSCL
FR
MPUSEL
MMU
VA0~VA12
VD0~VD7
VCS0~VCS7
VWE
A0~A12
DECODER
MEMCS
I/O1~I/O8
CS(0)
WE
8K × 8
MEMRQ
IOREQ
A0~A12
I/O1~I/O8
CS(1)
WE
A0~A12
I/O1~I/O8
CS(2)
WE
A0~A12
I/O1~I/O8
CS(3)
DB0~DB7
D0~D7
WE
RD
IORD
A0~A12
I/O1~I/O8
CS(4)
WR
IOWR
WE
MEMRD
MEMWR
A0~A12
I/O1~I/O8
CS(5)
WE
A0~A12
I/O1~I/O8
CS(6)
WAIT
RESET
CLK
READY
RESET
MPULCK
WE
A0~A12
I/O1~I/O8
CS(7)
WE
Note: Example implementation, actual may vary.
198
SED1351
■ INTERFACE WITH 16-BIT MPU (8086) AND 64K-BIT SRAM (8 of 8K x 8)
8086
(Maximum Mode)
8288
SED1351
UD0~UD3,LD0~LD3
YD
LP
XSCL
FR
MPUCLK
MEMRD
MEMWR
IORD
CLK
CLK
S2
MRDC
AMWC
IORC
MONO LCD
S2
S1
S0
8284A
S1
CLK
S0
AIOWC
IOWR
VA0~VA12
VD0~VD7
VCS0
A0~A12
+5V
READY
RESET
READY
RESET
DEN
DT/R
ALE
I/O1~I/O8
CS(0)
WE
8K × 8
MPUSEL
MEMCS
BHE
WE
RDY
A0~A12
I/O1~I/O8
CS(2)
VCS2
VCS4
VCS6
Decoder
WE
8282
A0~A12
I/O1~I/O8
CS(4)
M/IO
BHE
WE
BHE
A16~A19
A0~A12
I/O1~I/O8
CS(6)
A16~A19
A0~A15
AD0~AD15
AB0~AB15
IOCS
WE
STB
OE
Decoder
A0~A12
I/O1~I/O8
CS(1)
VD8~VD15
VCS1
WE
8286
A0~A12
I/O1~I/O8
CS(3)
VCS3
VCS5
DB0~DB15
D0~D15
WE
T
A0~A12
I/O1~I/O8
CS(5)
MIN/MAX
OE
WE
A0~A12
I/O1~I/O8
CS(7)
RESET
READY
VCS7
WE
Note: Example implementation, actual may vary.
199
SED1351
■ INTERFACE WITH 16-BIT MPU (68000) AND 256K-BIT SRAM (2 of 32K x 8)
68000
UD0~UD3,LD0~LD3
DACK
READY
YD
Q
D
LP
MONO LCD
XSCL
FR
CK
VA1~VA15
VD0~VD7
VCS0
A0~A14
FC0,1,2
I/O1~I/O8
IOCS
32K × 8
A[16–23]
Decoder
CS(0)
MEMCS
WE
VWE
AS
MEMRD
IORD
R/W
A0~A14
I/O1~I/O8
VD8~VD15
VCS1
MEMWR
IOWR
32K × 8
CS(1)
WE
A[1–15]
LDS
AB1–AB15
AB0
UDS
BHE
Note: Example implementation, actual may vary.
200
SED1351
■ SUPPORTED RESOLUTIONS
Maximum Display Size
Monochrome 4 Grayscale
Display
RAM
SRAM
Type
CPU
Interface
SRAM
Interface
X
Y
X
Y
8K
256
512
×
×
256
256
256
256
×
×
128
256
1 of 8K × 8
2 of 8K × 8
8 bit
8 bit
16K
8 bit
8 bit
16 bit
16 bit
24K
32K
512
512
×
×
384
512
384
512
×
×
256
256
3 of 8K × 8
4 of 8K × 8
8 bit
8 bit
8 bit
8 bit
16 bit
16 bit
1 of 32K × 8
6 of 8K × 8
8 bit
8 bit
48K
768
×
512
512
×
384
8 bit
8 bit
16 bit
16 bit
56K
64K
896
×
×
512
512
512
512
×
×
448
512
7 of 8K × 8
8 of 8K × 8
8 bit
8 bit
1024
8 bit
8 bit
16 bit
16 bit
2 of 32K × 8
8 bit
8 bit
16 bit
16 bit
■ BLOCK DIAGRAM
RESET
READY
MPUSEL, MPUCLK
IOCS,LOWR, IORD
MEMCS, MEMWR, MEMRD
R1 to
R15
Control Register
I/O Control
Address Buffer
Data Buffer
LCDENB
XSCL
LP
YD
AB0 ~ AB15
BHE
Display Timing
Control
WF
16 Bits
DB0 ~ DB15
Refresh
Address
Counter
VRAM
Control
Basic Training
Generation
Display Data
Control
UD0 ~ UD3
LD0 ~ LD3
Oscillator
MPX
MPX
OSC1
OSC2
VA0 ~ VA15
VWE
VD0 ~ VD15
VCS0 ~ VCS4
201
SED1351
■ ELECTRICAL CHARACTERISTICS
SED1351F0A
Absolute Maximum Ratings
•
•
(VSS = 0V)
Parameter
Supply voltage
Symbol
VDD
VI
Ratings
VSS–0.3 to 7.0
VSS–0.3 to VDD+0.3
VSS–0.3 to VDD+0.3
±10
Unit
V
Input voltage
V
Output voltage
VO
V
Output current/pin
Power dissipation
Supply current
IO
mA
mW
mA
°C
—
PD
200
IDD/ISS
Tstg
Tsol
±40
Storage temperature
Soldering temperature and time
–65 to 150
260°C, 10s (at lead)
Recommended Operating Conditions
•
(VSS = 0V)
Parameter
Supply voltage
Symbol
Condition
Min
4.5
Typ
5.0
—
Max
Unit
V
VDD
VI
5.5
VDD
75
Input voltage
VSS
–20
V
Operating temperature
Topr
—
°C
202
SED1351
DC Characteristics (F0A)
°
(Ta = –20 to 75°C)
Parameter
Symbol
Condition
Min
—
Typ
—
Max
100
Unit
Static current
IDDS
VIN = VDD, VDD = Max,
VSS, IOH = IOL = 0
µA
VDD = 5.5V,
VIH = VDD,
VIL = VSS
Input leakage current (Type 1)
ILI
–10
—
10
µA
High level input voltage 1 (OSC1)
Low level input voltage 1 (OSC1)
High level input voltage 2 (Type 2)
Low level input voltage 2 (Type 2)
High level input voltage 3 (Type 3)
Low level input voltage 3 (Type 3)
Hysteresis voltage (Type 3)
VIH1
VIL1
VIH2
VIL2
VT+
VT–
VH
VDD = 5.5V
VDD = 4.5V
VDD = 5.5V
VDD = 4.5V
VDD = 5.5V
VDD = 4.5V
VDD = 5V
3.5
—
—
—
—
—
—
—
—
—
—
1.0
—
V
V
V
V
V
V
V
V
2.0
—
0.8
—
4.0
—
0.8
—
0.3
High level output voltage 1 (Type 4)
VOH1
VDD = 4.5V
IOH = –2mA
IOL = 6mA
VDD
– 0.4
—
Low level output voltage 1 (Type 4)
High level output voltage 2 (OSC2)
Low level output voltage 2 (OSC2)
VOL1
VOH2
VOL2
—
—
—
—
VSS
+ 0.4
V
V
V
VDD = 4.5V
IOH = –50µA
IOL = 50µA
VDD
– 0.4
—
—
VSS
+ 0.4
Note:
Type 1. MEMCS, MEMWR, MEMRD, IOCS, IOWR, IORD, MPUCLK, AB0 ~ AB15, BHE, MPUSEL, RESET, OSC
Type 2. MEMCS, MEMWR, MEMRD, IOCS, IOWR, IORD, MPUCLK, AB0 ~ AB15, BHE, DB0 ~ DB15, VD0 ~ VD15
Type 3. MPUSEL, RESET
Type 4. DB0 ~ DB15, READY, VA0 ~ VA15, VCS0 ~ VCS4, VD0 ~ VD15, VWE, XSCL, LP, WF, YD, UD0 ~ UD3, LD0 ~ LD3,
LCDENB
203
SED1351
SED1351FLA
Absolute Maximum Ratings
•
•
(VSS = 0V)
Parameter
Supply voltage
Symbol
VDD
VI
Ratings
VSS–0.3 to 7.0
VSS–0.3 to VDD+0.5
VSS–0.3 to VDD+0.5
±24
Unit
V
Input voltage
V
Output voltage
VO
V
Output current/pin
Power dissipation
Supply current
IO
mA
mW
mA
°C
PD
200
IDD/ISS
Tstg
±40
Storage temperature
–65 to 150
Recommended Operating Conditions
•
(VSS = 0V)
Parameter
Supply voltage
Symbol
Condition
Min
2.7
Typ
—
Max
Unit
V
VDD
VI
3.6
VDD
75
Input voltage
VSS
–20
—
V
Operating temperature
Topr
—
°C
204
SED1351
DC Characteristics (FLB)
°
(Ta = –20 to 75°C)
Parameter
Symbol
Condition
Min
—
Typ
—
Max
30
Unit
Static current
IDDS
VIN = VDD or VSS,
µA
VDD = MAX, IOH = IOL = 0
VDD = MAX,
VIH = VDD,
VIL = VSS
Input leakage current (Type 1)
IL
–1
—
1
µA
High level input voltage 1 (OSC1)
Low level input voltage 1 (OSC1)
High level input voltage 2 (Type 2)
Low level input voltage 2 (Type 2)
High level input voltage 3 (Type 3)
Low level input voltage 3 (Type 3)
Hysteresis voltage (Type 3)
VIH1
VIL1
VIH2
VIL2
VT+
VT–
VH
VDD = MAX
VDD = MIN
VDD = MAX
VDD = MIN
VDD = MAX
VDD = MIN
VDD = TYP
0.7VDD
—
—
—
—
—
—
—
—
—
—
0.2VDD
—
V
V
V
V
V
V
V
V
0.7VDD
—
0.2VDD
—
0.8VDD
—
0.2VDD
—
0.3
High level output voltage 1 (Type 4)
VOH1
VDD = MIN
IOH = –1.5mA
IOL = 3mA
VDD
– 0.3
—
Low level output voltage 1 (Type 4)
High level output voltage 2 (OSC2)
Low level output voltage 2 (OSC2)
VOL1
VOH2
VOL2
—
—
—
—
VSS
+ 0.3
V
V
V
VDD = MIN
IOH = –50µA
IOL = 50µA
VDD
– 0.4
—
—
VSS
+ 0.4
Note:
Type 1. MEMCS, MEMWR, MEMRD, IOCS, IOWR, IORD, MPUCLK, AB0 ~ AB15, BHE, MPUSEL, RESET, OSC
Type 2. MEMCS, MEMWR, MEMRD, IOCS, IOWR, IORD, MPUCLK, AB0 ~ AB15, BHE, DB0 ~ DB15, VD0 ~ VD15
Type 3. MPUSEL, RESET
Type 4. DB0 ~ DB15, READY, VA0 ~ VA15, VCS0 ~ VCS4, VD0 ~ VD15, VWE, XSCL, LP, WF, YD, UD0 ~ UD3, LD0 ~ LD3,
LCDENB
205
SED1351
■ PIN CONFIGURATION (F0A)
80
81
51
50
VA3
VD11
VD12
VD13
VD14
VD15
LCDENB
XSCL
LP
VA2
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
VA1
VA0
VWE
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
WF
YD
SED1351FOA
UD0
UD1
UD2
UD3
LD0
LD1
LD2
LD3
OSC1
OSC2
31
30
100
1
■ PIN CONFIGURATION (FLB)
75
51
76
50
VD8
V
SS
VA4
77
VD9
VD10
VD11
VD12
VD13
VD14
VD15
LCDENB
XSCL
LP
49
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
VA3
VA2
VA1
VA0
VWE
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AB15
AB14
WF
SED1351FLB
YD
UD0
UD1
UD2
UD3
LD0
LD1
LD2
LD3
OSC1
OSC2
V
SS
DD
V
26
100
1
25
206
SED1351
■ PIN DESCRIPTION
1. System Connector Terminals (at MPU)
F0A
Pin No.
FLB
Pin No.
Pin Name
Type
I/O
Drv
Description
DB0 to DB15
30 to 45
28 to 43
These pins are interfaced with the MPU data bus.
When using an 8-bit MPU, connect DB8 to DB15 to
VDD.
AB0 to AB15
I
14 to 29
12 to 27
These pins are interfaced with the MPU address bus.
If multiplexed address signals are used, connect them
via latch circuits. A control register is selected by AB0
to AB3. Correspondence of the MPU address bus to
the VRAM address bus is such that ABi = VAi (where
i is a pin number).
BHE
I
13
11
This signal is a bus high enable signal where a 16-bit
MPU is used. It goes “L” (low) when an odd address is
encountered. When using an 8-bit MPU configuration,
connect the BHE pin to VDD.
IOCS
I
I
3
4
1
2
This pin selects a control register contained in the
SED1351. It is “L” active, and must be assigned to
MPU I/O space.
IOWR
This signal is used for writing data into a control
register contained in the SED1351. It is “L” active, and
must go “L” when it encounters an OUT instruction
from the MPU.
IORD
I
5
3
This signal is used for reading data from a control
register contained in the SED1351. It is “L” active, and
must go “L” when it encounters an IN instruction from
the MPU.
MEMCS
MEMWR
I
I
6
7
4
5
This signal is used for selecting VRAM. It is “L” active,
and must be assigned to MPU memory space.
ThissignalisusedforwritingdatatotheVRAM. Itis“L”
active, and must go “L” when it encounters a memory
write instruction from the MPU.
MEMRD
READY
I
8
9
6
7
This signal is used for reading data from the VRAM. It
is “L” active, and must go “L” when it encounters a
memory read instruction from the MPU.
O
This signal requests the MPU to wait. It goes “L” by the
falling edge of IOCS or MEMCS. It goes “H” by the
rising edge of MPUCLK after completion of the
SED1351 internal processing. Since READY is not a
tri-state pin, it needed not be pulled up and must be
connected directly to the READY (WAIT) terminal of
the MPU.
MPUCLK
MPUSEL
I
I
10
12
8
This pin accepts an MPU clock. The MPU wait state is
cleared by the rising edge of MPUCLK.
10
This signal is connected to either VDD or VSS for
selection of an MPU.
MPUSEL = VSS 8-bitMPU(e.g.,Z80,V20,i8088)
MPUSEL = VDD 16-bit MPU (e.g., V30, i8086)
RESET
I
11
9
The MPU reset signal comes to this pin. It is “H” active,
and initializes a control register.
207
SED1351
Combinations of Control Pins
IOCS
IOWR
IORD
MEMCS
MEMWR
MEMRD
Operation
1
0
0
1
1
*
*
1
1
1
0
0
*
*
Invalid
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
Write to control register
Read from control register
Write to VRAM
Read from VRAM
Note: Any combination other than those listed above will cause a system error.
1
0
*
=
=
=
“H” (high)
“L” (low)
Don’t care
2. VRAM Connector Terminals
F0A
Pin No.
FLB
Pin No.
Pin Name
Type
I/O
Drv
Description
VD0 to VD15
68 to 78,
81 to 85
68 to 83
These pins are interfaced with the VRAM data bus.
For a 16-bit MPU configuration, VD0 to VD7 must be
connected to even addresses, and VD8 to VD15 to
odd addresses. For an 8-bit configuration, VD8 to
VD15 must be connected to VDD.
VA0 to VA12
O
O
O
O
47 to 59 45 to 49,
52 to 59
These pins are interfaced with the VRAM address
bus and chip select pins.
VA13/VCS7 to
VA15/VCS5
60 to 62
67 to 63
46
60 to 62
67 to 63
44
The SED1351 has chip select pins that can directly
control eight 64K SRAMs (8K bytes each) or two
256K SRAMs (32K bytes) in the 64K VRAM space.
See Technical Manual for details.
VCS0 to VCS4
VWE
ThissignalisusedforwritingdatatotheVRAM. Itis“L”
active, and must be connected to the WE pin of the
VRAM.
3. Oscillator Terminals
F0A
Pin No.
FLB
Pin No.
Pin Name
OSC1
OSC2
Type
Drv
Description
I
99
97
98
The OSC1 (input) and OSC2 (output) pins gener-
ate clocks for internal operation. They allow crystal
oscillation and external clock input.
O
100
4. Power Terminals
F0A
Pin No.
FLB
Pin No.
Pin Name
VDD
Type
Drv
Description
—
—
2, 79
1, 80
51, 100
50, 99
The power supply pins include two VDDs and two
VSSs. Apply +5V or +3V to VDD and 0V to VSS. A
capacitor (4.7 µF or more) must be connected near
each pair of VDD/VSS pins.
SS
V
208
SED1351
5. LCD Connector Terminals
F0A
Pin No.
FLB
Pin No.
Pin Name
Type
Drv
Description
UD0 to UD3
I/O
O
91 to 94
95 to 98
89 to 92
93 to 96
LCD display data. UD0 to UD3 are the upper panel
display data in the signal panel or double panel
drive panel mode. LD0/UD4 to LD3/UD7 are the lower
panel display data in the double panel drive mode.
UD0 to UD3, and LD0/UD4 to LD3/UD7 are used for 8-
bit data transfer in the single panel drive mode.
LD0/UD4 to
LD3/UD7
XSCL
LP
O
O
87
88
85
86
This single is a shift clock for display data transfer.
Take the UD0 to UD3, LD0/UD4 to LD3/UD7 display
data into LCDs by the falling edge of XSCL.
This pin provides both a display data latch pulse and
a scan signal transfer clock. Upon completion of trans-
ferring the LCD data on one line, display data can be
latched or a scan signal transferred by the falling edge
of LP.
WF
YD
O
O
89
90
87
88
This pin provides a frame signal used for LCD AC
driving.
This pin provides a scanning line start pulse. The
signal is “H” active. Allow the scanning line drive IC to
take in YD by the falling edge of LP.
The SED1351 has two lines of retracing; if two scan-
ning line drive ICs are cascade-connected for the
upper and lower panels in the double panel drive
mode, two lines must be provided between the upper
and lower scanning line drive outputs.
LCDENB
O
86
84
This pin provides the data which is set in bit 1 (D1) of
the mode register (R1). LCDENB goes “L” when the
system is reset; it can be effectively used for LCD
power control.
209
SED1351
Illustrated below are the display data which are output from the UD0 to UD3, LD0/UD4 to LD3/UD7 and the
display on the panel:
UD3 UD2 UD1 UD0 . . .
UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 . . .
Dual Panel — Top
8-bit Single Panel
LD3 LD2 LD1 LD0 . . .
Dual Panel — Bottom
. . .
UD3 UD2 UD1 UD0 UD3 UD2 UD1 UD0
4-bit Single Panel
■ LCD PANEL PIXELS
640 DOTS
1 - 1
2 - 1
1 - 2
2 - 2
1 - 639 1 - 640
2 - 639 2 - 640
240 LINES
UPPER LCD PANEL
240 - 1 240 - 2
241 - 1 241 - 2
240- 639 240- 640
241- 639 241- 640
(TOP VIEW)
240 LINES
LOWER LCD PANEL
480 - 1 480 - 2
480- 639 480- 640
210
SED1351
■ MONOCHROME LCD PANEL INTERFACE
8-Bit Dual Monochrome Panel (i.e. 640 × 480)
LP : 242 PULSES
YD
LP
WF
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241 LINE 2/242
UD[3:0], LD[3:0]
LP
WF
XSCL: 160 CLOCKS
XSCL
1–1
1–2
1–5
1–6
1–637
1–638
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
1–3
1–7
1–639
1–4
1–8
1–640
241–1
241–2
241–3
241–4
241–5
241–6
241–7
241–8
241–637
241–638
241–639
241–640
211
SED1351
■ MONOCHROME LCD PANEL INTERFACE
4-Bit Single Monochrome Panel (i.e. 320 × 480)
LP : 482 PULSES
YD
LP
WF
LINE 1
LINE 2
LINE 3
LINE 4
LINE 479 LINE 480
LINE 1
LINE 2
UD[3:0]
LP
WF
XSCL: 80 CLOCKS
XSCL
1–1
1–2
1–3
1–4
1–5
1–317
1–318
1–319
1–320
UD3
UD2
UD1
UD0
1–6
1–7
1–8
8-Bit Single Monochrome Panel (i.e. 640 × 480)
LP : 482 PULSES
YD
LP
WF
LINE 1
LINE 2
LINE 3
LINE 4
LINE 479 LINE 480
LINE 1
LINE 2
UD[3:0], LD[3:0]
LP
WF
XSCL: 80 CLOCKS
XSCL
1–1
1–2
1–3
1–4
1–5
1–6
1–7
1–8
1–9
1–633
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
1–10
1–11
1–12
1–13
1–14
1–15
1–16
1–634
1–635
1–636
1–637
1–638
1–639
1–640
212
SED1351
■ PACKAGE DIMENSIONS
SED1351F0A
•
QFP5-100pin
Unit: mm
0.4
25.6 ±
0.1
20 ±
80
51
81
50
Index
100
31
1
30
0.1
0.1
0.30 ±
0.65 ±
0 ~12°
2.8
Actual Size
SED1351FLB
•
QFP15-100pin
Unit: mm
0.4
16.0 ±
0.1
14.0 ±
75
51
76
50
Index
26
100
1
25
0.1
0.1
0.18 ±
0.5 ±
0 ~ 12°
Actual Size
1.0
213
THIS PAGE INTENTIONALLY BLANK
214
相关型号：
©2020 ICPDF网 联系我们和版权申明