SED1353 [EPSON]
SED1353 GRAPHICS LCD CONTROLLER; SED1353图形液晶显示控制器
| 型号： | SED1353 |
| 厂家： | 
EPSON COMPANY |
| 描述： | SED1353 GRAPHICS LCD CONTROLLER |
| 文件： | 总30页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GRAPHICS
SED1353
October 1998
SED1353 GRAPHICS LCD CONTROLLER
■ DESCRIPTION
The SED1353 is a dot matrix graphic LCD controller supporting resolutions up to 1024x1024. It is
capable of displaying a maximum of 256 simultaneous colors out of a possible 4096 or 16 gray shades.
Design flexibility allows the SED1353 to interface to either an MC68000 family microprocessor or an
8/16-bit MPU/bus with minimum external logic. The Static RAM (SRAM) interface used for the display buffer
is optimized for speed and performance, supporting up to 128K bytes.
Two power save modes, combined with operating voltages of 2.7 volts through 5.5 volts, allow for a wide
range of applications while providing minimum power consumption.
■ FEATURES
• pin compatible with the SED1352
• low power consumption
• 16-bit 16 MHz MC68xxx MPU interface
• 8/16-bit MPU interface controlled by a READY
(or WAIT#) signal
• display memory interface:
128K bytes using one 64Kx16 SRAMs
128K bytes using two 64Kx8 SRAMs
64K bytes using two 32Kx8 SRAMs
40K bytes using one 8Kx8 and one 32Kx8
SRAM
• option to use built-in index register or direct-map-
ping to access one of sixteen internal registers
• 2-terminal crystal or external oscillator support
• 8/16-bit SRAM interface configurations
• split screen display support allowing two different
images to be simultaneously displayed
32K bytes using one 32Kx8 SRAM
16K bytes using two 8Kx8 SRAMs
8K bytes using one 8Kx8 SRAM
• LCD panel configurations:
single-panel, single-drive passive display
dual-panel, dual-drive passive display
• virtual display support (displays images larger
than the panel size through the use of panning)
• maximum number of vertical lines:
• display modes:
1,024 lines (single-panel, single-drive display)
2,048 lines (dual-panel, dual-drive display)
black-and-white display
2/4 bits per pixel, 4/16-level gray-scale display
2/4/8 bits per pixel, 4/16/256-level color display
QFP5-100-S2 package (F0A)
•
•
• two software power-save modes
■ SYSTEM BLOCK DIAGRAM
CLOCK
QFP15-100-STD package (F1A)
DATA
CONTROL
LCD PANEL
MPU
SED1353
SRAM
ADDRESS
80xx
Z80
68xxx
1
X18A-C-001-08
GRAPHICS
SED1353
■ INTERFACE OPTIONS
Interface with 16-Bit MC68xxx MPU and 16K bytes SRAM (2 of 8K x 8)
MC68xxx
SED1353
A20 to A23
FC0 to FC1
MEMCS#
Decoder
Decoder
A14 to A16
A10 to A19
VD8-15
VD0-7
VWE#
IOCS#
A1 to A19
D0 to D15
AB1 to AB19
DB0 to DB15
READY
WE#
WE#
64 Kbit
CS#
64 Kbit
CS#
DTACK#
UDS#
AB0
LDS#
BHE#
VCS0#
VCS1#
VA0-12
AS#
R/W#
IOR#
IOW#
Note: Example implementation, actual may vary.
Interface with 8-Bit Z80 MPU and 16K bytes SRAM (2 of 8K x 8)
Z80
Decoder
SED1353
MEMCS#
MREQ#
MI#
A10 to A15
VD0-7
VWE#
Decoder
IOCS#
IORQ#
A0 to A15
D0 to D7
WAIT#
WE#
WE#
AB0 to AB15
DB0 to DB7
READY
64 Kbit
CS#
64 Kbit
CS#
MEMW#
MEMR#
WR#
RD#
VCS0#
VCS1#
VA0-12
IOR#
IOW#
RESET#
RESET
Note: Example implementation, actual may vary.
X18A-C-001-08
2
GRAPHICS
SED1353
Interface with 16-Bit 8086 MPU and 64K bytes SRAM (2 of 32K x 8)
8086
(Maximum mode)
8288
SED1353
CLK
CLK
MEMR#
MRDC#
CLK
READY
RESET#
S2#
S2#
S1#
S0#
VD0-7
VWE#
MEMW#
IOR#
AMWC#
IORC#
READY
RESET#
S1#
S0#
RDY
AIOWC#
IOW#
DEN
WE#
8284A
DT/R
ALE
256 Kbit
CS#
A16 to A19
AB16 to AB19
Decoder
A16
VCS0#
VA0-14
M/IO#
AB0 to AB15
BHE#
BHE#
BHE#
AD0 to AD15
MEMCS#
IOCS#
A0 to A16
STB
WE#
256 Kbit
CS#
D0 to D15
DB0 to DB15
T
OE
VCS1#
Transceiver
RESET
VD8-15
READY
Note: Example implementation, actual may vary.
Interface with 8-Bit ISA Bus and 40K bytes SRAM (1 of 8K x 8 and 1 of 32K x 8)
8-Bit ISA Bus
SED1353
REFRESH
VD0-7
VWE#
SA13 to SA16
MEMCS#
MEMW#
MEMR#
Decoder
SMEMW#
SMEMR#
WE#
READY
IOCHRDY
SD0 to SD7
SA0 to SA19
64 Kbit
CS#
DB0 to DB7
AB0 to AB19
VCS0#
VA0-14
SA(1 or 4) to SA9
SA10 to SA15
Decoder
IOCS#
AEN
IOW#
IOW#
IOR#
RESET
IOR#
WE#
RESET#
256 Kbit
CS#
optional
Decoder
0WS#
VCS1#
Note: Example implementation, actual may vary.
3
X18A-C-001-08
GRAPHICS
SED1353
Interface with 16-Bit ISA Bus and 128K bytes SRAM (1 of 128K x 8)
16-bit ISA Bus
SED1353
REFRESH
SA14 to SA16
MEMCS#
MEMW#
MEMR#
READY
Decoder
SMEMW#
SMEMR#
VWE#
WE#
IOCHRDY
SD0 to SD15
SA0 to SA19
DB0 to DB15
AB0 to AB19
1 Mbit
SA(1 or 4) to SA9
SA10 to SA15
VCS0#
LB#
UB#
Decoder
IOCS#
IOW#
AEN
VCS1#
IOW#
IOR#
IOR#
SBHE#
BHE#
RESET
VA0-15
A0-15
RESET#
VD0-7
I/O 1-8
IOCS16#
Decoder
VD8-15
I/O 9-16
LA17 to LA23
MEMCS16#
Decoder
Note: Example implementation, actual may vary.
■ SUPPORTED RESOLUTIONS
Example Display Size
Display
RAM
SRAM
Type
CPU
Interface
SRAM
Interface
4 Grays/
Colors
16 Grays/
Colors
Monochrome
256 Colorsa
X
Y
X
Y
X
Y
X
Y
8K byte
320 x 200
256 x 128
128 x 128
—
1 of 8Kx8
2 of 8Kx8
1 of 32Kx8
8-bit
8-bit
8-bit
8-bit/16-bit
16-bit
16K byte
512 x 256
320 x 200
200 x 160
160 x 100a
16-bit
8-bit
32K byte
40K byte
512 x 512
512 x 256
512 x 320
256 x 256
320 x 256
192 x 100a
320 x 128a
8-bit
1 of 8Kx8 and
1 of 32Kx8
1024 x 320
8-bit
8-bit
8-bit
16-bit
16-bit
16-bit
8-bit/16-bit
16-bit
64K byte
1024 x 512
512 x 512
512 x 256
512 x 512
256 x 256a
512 x 256a
2 of 32Kx8
1 of 64Kx16
2 of 64Kx8
16-bit
128K byte 1024 x 1024
1024 x 512
16-bit
a. 256 colors must use 16-bit SRAM interface
The above listed display sizes are examples based on bits/pixel and available memory.
X18A-C-001-08
4
GRAPHICS
SED1353
■ BLOCK DIAGRAM
Control Registers
IOR#, IOW#, IOCS#,
MEMCS#, MEMR#,
MEMW#, BHE#,
AB[19:0]
Port
Bus
Sequence
Controller
Decoder
Signal
Translation
LCDENB
UD[3:0]
LD[3:0]
LP, YD,
Memory
Decoder
Lookup
Table
LCD
Panel
Interface
READY
XSCL,
WF(XSCL2)
Data Bus
Conversion
Address
Generator
DB[15:0]
Display
Data
Formatter
MPU/CRT
Selector
Timing Generator
Power Save
Oscillator
SRAM Interface
5
X18A-C-001-08
GRAPHICS
SED1353
■ FUNCTIONAL BLOCK DESCRIPTION
Bus Signal Translation
Data Bus Conversion
According to configuration setting VD2, Bus Sig-
nal Translation translates either MC68000 type
MPU signals or Ready type MPU signals to
internal bus interface signals.
According to configuration setting VD0, Data
Bus Conversion maps the external data bus,
either 8-bit or 16-bit, into the internal odd and
even data bus.
Control Registers
Address Generator
The Control Register contains 16 internal control
and configuration registers. These registers can
be accessed by either direct-mapping or using
the built-in internal index register.
The Address Generator generates display
refresh addresses to be used to access display
memory.
MPU / CRT Selector
Sequence Controller
The MPU / CRT Selector grants access to the
display memory from either the MPU or the dis-
play refresh circuitry.
The Sequence Controller generates horizontal
and vertical display timings according to the
configuration registers settings.
Display Data Formatter
LCD Panel Interface
The Display Data Formatter reads in the display
data from the display memory and outputs the
correct format for all supported gray shade and
color selections.
The LCD Panel Interface performs frame rate
modulation and output data pattern formatting
for both passive monochrome and passive color
LCD panels.
Clock Inputs / Timing
Look-Up Table
Clock Inputs / Timing generates the internal
master clock according to gray-level / color
selected and display memory interface.The
master clock (MCLK) can be:
- MCLK = input clock
The Look-Up Table contains three 16x4-bit wide
palettes. In gray shade modes, the “green” pal-
ette can be configured for the re-mapping of 16
possible shades of gray. In color modes, all
three palettes can be configured for the re-map-
ping of 4096 possible colors.
- MCLK = 1/2 input clock
- MCLK = 1/4 input clock.
Pixel clock = input clock = f
OSC.
Port Decoder
According to configuration settings VD1, VD12 -
VD4, IOCS# and address lines AB9-1, the Port
Decoder validates a given I/O cycle.
SRAM Interface
The SRAM Interface generates the necessary
signals to interface to the Display Memory
(SRAM).
Memory Decoder
According to configuration settings VD15 -
VD13, MEMCS# and address lines AB19-17,
the Memory Decoder validates a given memory
cycle.
6
X18A-C-001-08
GRAPHICS
SED1353
■ DC SPECIFICATIONS
Absolute Maximum Ratings
Symbol
VDD
Parameter
Rating
Units
VSS - 0.3 to + 6.0
V
V
Supply Voltage
VIN
VSS - 0.3 to VDD + 0.5
VSS - 0.3 to VDD + 0.5
-65 to 150
Input Voltage
VOUT
TSTG
TSOL
V
Output Voltage
° C
° C
Storage Temperature
Solder Temperature/Time
260 for 10 sec. max at lead
Recommended Operating Conditions
Symbol
VDD
Parameter
Supply Voltage
Condition
Min
2.7
Typ
Max
5.5
Units
V
VSS = 0 V
3.0/3.3/5.0
--
VIN
VSS
VDD
V
Input Voltage
f
f
OSC = 6 MHz
256 colors
IOPR
TOPR
PTYP
4.5/5.0/11
25
mA
° C
Operating Current
-40
85
Operating Temperature
Typical Active Power Consumption
OSC = 6 MHz
256 colors
13.5/16.5/55
mW
7
X18A-C-001-08
GRAPHICS
SED1353
Input Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Units
VDD = 4.5V
VDD = 3.0V
VDD = 2.7V
0.8
0.4
0.3
VIL
VIH
VT+
VT-
VH
V
Low Level Input Voltage
VDD = 5.5V
VDD = 3.6V
VDD = 3.3V
2.0
1.3
1.2
V
V
V
V
High Level Input Voltage
Positive-going Threshold
Negative-going Threshold
Hysteresis Voltage
VDD = 5.0
VDD = 3.3
VDD = 3.0
2.4
1.4
1.3
VDD = 5.0
VDD = 3.3
VDD = 3.0
0.6
0.5
0.4
VDD = 5.0
VDD = 3.3
VDD = 3.0
0.1
0.1
0.1
IIZ
--
-1
1
µA
Input Leakage Current
Input Pin Capacitance
f =1 MHz,
VDD= 0V
CIN
12
pF
VDD = 5.0V
VI = VDD
RPD
RPD
RPD
50
90
100
180
200
200
360
400
kΩ
kΩ
kΩ
Pull Down Resistance
Pull Down Resistance
Pull Down Resistance
VDD = 3.3V
VI = VDD
VDD = 3.0V
VI = VDD
100
X18A-C-001-08
8
GRAPHICS
SED1353
Output Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Units
VDD = Min
Low Level Output Voltage
I
OL = 4 mA
Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S
VOL (5.0V)
VOL (3.3V)
VOL (3.0V)
VOH (5.0V)
VOH (3.3V)
VOH (3.0V)
0.4
V
IOL = 8 mA
IOL = 12 mA
VDD = Min
Low Level Output Voltage
I
OL = 2 mA
Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S
0.3
0.3
V
V
V
V
V
IOL = 4 mA
IOL = 6 mA
VDD = Min
Low Level Output Voltage
I
OL = 1.8 mA
IOL = 3.5 mA
IOL = 5 mA
Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S
VDD = Min
High Level Output Voltage
I
OH = -4 mA
Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S
VDD-0.4
IOH = -8mA
IOH = -12 mA
VDD = Min
Low Level Output Voltage
I
OL = -2 mA
Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S
VDD-0.3
IOL = -4 mA
IOL = -6 mA
VDD = Min
High Level Output Voltage
I
OH = -1.8 mA
IOH = -3.5 mA
IOH = -5 mA
Type 1 - TS1D2, CO1
Type 2 - TS2, CO2
Type 3 - TS3, CO3, CO3S
VDD-0.3
IOZ
--
-1
1
µA
Output Leakage Current
Output Pin Capacitance
f =1 MHz,
VDD= 0V
COUT
12
pF
f =1 MHz,
VDD= 0V
CBID
12
pF
Bidirectional Pin Capacitance
9
X18A-C-001-08
GRAPHICS
SED1353
■
1353F0A PIN OUT
SED
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VD6
VD5
VD4
VD3
VD2
VD1
VD0
VA10
VA9
VA8
VA7
VA6
VA5
VA4
VA3
VA2
VA1
VA0
RESET
AB19
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
XSCL
LCDENB
VOE#
IOCS#
IOW#
IOR#
MEMCS#
MEMW#
MEMR#
READY
BHE#
OSC1
OSC2
DB0
DB1
DB2
DB3
DB4
DB5
DB6
SED1353F0A
* Pin 80 = WF in all display modes except format 1 for 8-bit single color panel.
* Pin 80 = XSCL2 in format 1 for 8-bit single color panel.
X18A-C-001-08
10
GRAPHICS
SED1353
■
1353F1A PIN OUT
SED
76
50
LP
V
V
DD
SS
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
WF/XSCL2*
XSCL
LCDENB
VOE#
IOCS#
IOW#
IOR#
MEMCS#
MEMW#
MEMR#
READY
BHE#
OSC1
OSC2
DB0
VD7
VD6
VD5
VD4
VD3
VD2
VD1
VD0
VA 10
VA9
VA8
VA7
VA6
VA5
VA4
VA3
VA2
VA1
SED1353F1A
DB1
DB2
DB3
DB4
DB5
DB6
30
29
28
27
VA0
RESET
AB19
AB18
AB17
DB7
VSS
26
V
DD
* Pin 77 = WF in all display modes except format 1 for 8-bit single color panel.
* Pin 77 = XSCL2 in format 1 for 8-bit single color panel.
11
X18A-C-001-08
GRAPHICS
SED1353
■
1353D0A PIN OUT
SED
Dummy Pad
VD7
90
80
70
WF/XSCL2*
XSCL
LCDENB
VOE#
100
110
120
VD6
VD5
VD4
VD3
VD2
60
50
40
IOCS#
IOW#
VD1
VD0
IOR#
MEMCS#
MEMW#
MEMR#
VA10
VA9
VA8
VA7
READY
BHE#
SED1353D0A
VA6
VA5
OSC1
OSC2
VA4
VA3
DB0
DB1
VA2
VA1
VA0
RESET
AB19
DB2
DB3
DB4
DB5
DB6
DB7
1
10
20
30
Dummy Pad
=
=
Chip Size
Chip Thickness
Pad Size
5.030 mm x 5.030 mm
0.400 mm
= 0.090 mm x 0.090 mm
= 0.126 mm (Min.)
Pad Pitch
* Pad 97 = WF in all display modes except format 1 for 8-bit single color panel.
* Pad 97 = XSCL2 in format 1 for 8-bit single color panel.
X18A-C-001-08
12
GRAPHICS
SED1353
PAD Coordinates
Pad
Pad Center
Coordinate
Pad Center
Coordinate
Pin
Pad
No.
Pin
Name
No.
Name
X
Y
X
Y
1
VSS
---
-2.165
-2.000
-1.840
-1.685
-1.535
-1.388
-1.246
-1.106
-0.969
-0.835
-0.703
-0.573
-0.444
-0.317
-0.190
-0.063
0.063
0.190
0.317
0.444
0.573
0.703
0.835
0.969
1.106
1.246
1.388
1.535
1.685
1.840
2.000
2.165
2.390
2.390
2.390
2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.340
-2.000
-1.840
-1.685
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
RESET
VA0
VA1
VA2
---
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.165
2.000
1.840
1.685
1.535
1.388
1.246
1.106
-1.535
-1.388
-1.246
-1.106
-0.969
-0.835
-0.703
-0.573
-0.444
-0.317
-0.190
-0.063
0.063
0.190
0.317
0.444
0.573
0.703
0.835
0.969
1.106
1.246
1.388
1.535
1.685
1.840
2.000
2.165
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2
3
VDD
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
---
4
5
6
VA3
VA4
---
7
8
9
VA5
VA6
---
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VA7
VA8
---
AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
---
VA9
VA10
---
VD0
VD1
---
VD2
VD3
VD4
VD5
VD6
---
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
---
---
VD7
VSS
---
VDD
VD8
VD9
VD10
VD11
VD12
AB17
AB18
---
---
AB19
13
X18A-C-001-08
GRAPHICS
SED1353
Pad Center
Coordinate
Pad Center
Coordinate
Pad
No.
Pin
Name
Pad
No.
Pin
Name
X
Y
X
Y
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
VD13
VD14
VD15
---
0.969
0.835
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.390
2.165
2.000
1.840
1.685
1.535
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VOE#
IOCS#
IOW#
---
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
-2.390
2.390
1.388
1.246
1.106
0.969
0.835
0.703
0.573
0.444
0.317
0.190
0.063
-0.063
-0.190
-0.317
-0.444
-0.573
-0.703
-0.835
-0.969
-1.106
-1.246
-1.388
-1.535
-1.685
-1.840
-2.000
-2.165
2.390
-2.390
0.703
0.573
VA11
VA12
VA13
VA14
VA15
VWE#
VCS0#
VCS1#
---
0.444
IOR#
MEMCS#
---
0.317
0.190
0.063
MEMW#
MEMR#
---
-0.063
-0.190
-0.317
-0.444
-0.573
-0.703
-0.835
-0.969
-1.106
-1.246
-1.388
-1.535
-1.685
-1.840
-2.000
-2.340
-2.390
-2.390
-2.390
-2.390
-2.390
READY
BHE#
---
UD3
OSC1
OSC2
---
UD2
UD1
UD0
DB0
LD3
DB1
LD2
---
LD1
DB2
LD0
DB3
YD
DB4
---
DB5
LP
DB6
WF/XSCL2
---
---
---
---
DB7
XSCL
LCDENB
129 Dummy Pad
130 Dummy Pad -2.390
X18A-C-001-08
14
GRAPHICS
SED1353
■
PIN DESCRIPTION
Key
I
=
=
=
=
Input
Output
Bidirectional
Power
O
I/O
P
Bus Interface
F0A
Pin #
F1A
Pin #
D0A
Pad #
Pin Name Type
Description
118-119,
94 - 100, 91 - 98, 121-125, These pins are connected to the system data bus. In 8-bit bus mode, DB8-
DB0-DB15 I/O
1, 4 -11 1 - 8
128,
4-11
DB15 must be tied to VDD.
In MC68000 MPU interface, this pin is connected to the Upper Data Strobe
(UDS#) pin of MC68000. In other bus interfaces, this pin is connected to the
system address bus.
AB0
I
12
9
13
14-20,
22-30,
32-33,
36
AB1-AB19 I
13 - 31 10 - 28
These pins are connected to the system address bus.
In MC68000 MPU interface, this pin is connected to the Lower Data Strobe
(LDS#) pin of MC68000. In other bus interfaces, this pin is the Byte High
Enable input for use with 16-bit system. In 8-bit bus mode, tie BHE# input to
BHE#
IOCS#
IOW#
I
I
I
91
84
85
88
81
82
113
103
104
VDD
.
Active low input to select one of fifteen internal registers.
In MC68000 MPU interface, this pin is connected to the R/W# pin of
MC68000. This input pin will define whether the data transfer is a read
(active high) or write (active low) cycle. In other bus interfaces, this is the
active low input to write data into an internal register.
In MC68000 MPU interface, this pin is connected to the AS# pin of
MC68000. This input pin will indicate a valid address is available on the
address bus. In other bus interfaces, this is the active low input to read data
from an internal register.
IOR#
I
86
83
106
MEMCS#
MEMW#
I
I
87
88
84
85
107
109
Active low input to indicate the attempt to access the display memory.
Active low input to write data to the display memory. This pin should be tied
to VDD in an MC68000 MPU interface.
Active low input to read data from the display memory. This pin should be
tied to VDD in an MC68000 MPU interface.
MEMR#
I
89
86
110
For MC68000 MPU interface, this pin is connected to the DTACK# pin of
MC68000 and will be driven low when ever a data transfer is complete. In
other bus interfaces, this output is driven low to force the system to insert
wait states when needed.
READY
RESET
O
I
90
32
87
29
112
37
READY is placed in a high-impedance (Hi-Z) state after the transfer is
completed.
Active high input to force all signals to their inactive states.
15
X18A-C-001-08
GRAPHICS
SED1353
Display Memory Interface
F0A
F1A
Pin #
D0A
Pin Name Type
Description
Pin #
Pad #
These pins are connected to the display memory data bus. For 16-bit interface,
VD0-VD7 are connected to the display memory data bus of even byte addresses
and VD8-VD15 are connected to the display memory data bus of odd byte
addresses. The output drivers of these pins are tri-stated when RESET is high.
54-55,
44 - 51, 41 - 48, 57-61,
54 - 61 51 - 58 64,
68-75
VD0-VD15 I/O
On the falling edge of RESET the values of VD0-VD15 are latched into the chip
to configure various hardware options.
38-40,
42-43,
33 - 43, 30 - 40 45-46,
62 - 66 59 - 63 48-49,
51-52,
VA0-VA15 O
These pins are connected to the display memory address bus.
77-81
VCS1#
VCS0#
O
O
69
68
66
65
84
83
Active low chip-select output to the second or odd byte address SRAM.
Active low chip-select output to the first or even byte address SRAM.
Active low output used for writing data to the display memory. This pin is
connected to the WE# input of the SRAMs.
VWE#
VOE#
O
O
67
83
64
80
82
Active low output to enable reading of data from the display memory. This pin is
connected to the OE# input of the SRAMs.
102
LCD Interface
FPDI-1TM
Pin Namea
F0A
F1A
Pin #
D0A
Pin Name
Type
Description
Pad #
Pin #
Panel display data bus. The data format depends on the specific
panel connected. For 4-bit single panels, these bits are driven 0
(low state).
UD3-UD0 UD3-UD0
LD3-LD0 LD3-LD0
70 - 73 67 - 70 86 - 89
74 - 77 71 - 74 90 - 93
O
O
O
Display data shift clock. Data is shifted into the LCD X-drivers on
the falling edge of this signal.
XSCL
LP
FPSHIFT
FPLINE
81
79
78
76
100
96
Display data latch clock. The falling edge of this signal is used to
latch a row of display data in the LCD X-drivers and to turn on the
row driver (Y driver).
For format 1 of 8-bit single color panels this is the second shift
clock. For all other modes,this is the LCD backplane BIAS signal.
This output toggles once every n LP periods, as programmed in
AUX[05]
MOD
WF/XSCL2
YD
O
80
77
97
FPSHIFT2
Vertical scanning start pulse. A logic ‘1’ on this signal, sampled
by the LCD module on the falling edge of LP, is used by the panel
row driver (Y driver) to indicate the start of the vertical frame.
FPFRAME
O
O
78
82
75
79
94
LCD enable signal output. It can be used externally to turn off the
panel supply voltage and backlight.
LCDENB ---
101
a. VESA Flat Panel Display Interface Standard (FPDI-1TM
)
X18A-C-001-08
16
GRAPHICS
SED1353
Clock Inputs
F0A
Pin #
F1A
Pin #
D0A
Pad #
Pin Name Type
Description
This pin, along with OSC2 is the 2-terminal crystal interface when using a
2-terminal crystal as the clock input. If an external oscillator is used as a
clock source, then this pin is the clock input.
OSC1
OSC2
I
92
93
89
90
115
116
This pin, along with OSC1 is the 2-terminal crystal interface when using a
2-terminal crystal as the clock input. If an external oscillator is used as a
clock source, then this pin should be left unconnected.
O
Power Supply
F0A
Pin #
F1A
Pin #
D0A
Pad #
Pin Name Type
Description
VDD
VSS
P
P
3, 53
2, 52
50, 100 3, 67
49, 99 1, 65
Voltage supply.
Voltage Ground.
■ SUMMARY OF CONFIGURATION OPTIONS
(1/0)
Pin Name
value on this pin at falling edge of RESET is used to configure:
1
0
VD0
VD1
16-bit host bus interface
8-bit host bus interface
Use direct-mapping for I/O accesses
Use indexed mapping for I/O accesses
MPU / Bus interface with memory accesses controlled
by a READY (WAIT#) signal
VD2
VD3
MC68000 MPU interface
No byte swap of high and low data bytes in 16-bit bus
interface
Swap of high and low data bytes in 16-bit bus interface
Select I/O mapping address bits [9:1].
These nine bits are latched on power-up and are compared to the MPU address bits [9-1]. A valid I/O cycle
combined with a valid address will enable the internal I/O decoder. Therefore, both types of I/O mapping are
limited to even address boundaries to determine either the absolute or indexed I/O address of the first register.
Note that a “valid I/O cycle” includes IOCS# being toggled low.
VD12-VD4
Select memory mapping address bits [3:1]
These three bits are latched on power-up and are compared to the MPU address bits [19-17]. A valid memory
cycle combined with a valid address will enable the internal memory decoder. As only the three most significant
VD15-VD13 bits of the address are compared, the maximum amount of memory supported is 128K bytes. Note that a “valid
memory cycle” includes MEMCS# being toggled low.
When using 128K byte memory it must be mapped at an even address such that all 128K bytes is available without
a change in state on A17, as this would invalidate the internal compare logic.
17
X18A-C-001-08
GRAPHICS
SED1353
Example: If an ISA bus (no byte swap) with memory segment “A” and I/O location 300h are used, the
corresponding settings of VD15-VD0 would be:
8-Bit ISA Bus
16-Bit ISA Bus
Index
Register
Index
Register
Pin Name
Direct Mapping
Direct Mapping
VD0
VD1
0
0
1
1
0
1
0
1
VD2
0
0
0
0
VD3
0
0
0
0
VD12-VD4
VD15-VD13
11 0000 000
101
11 0000 xxx
101
11 0000 000
101
11 0000 xxx
101
Where x = don’t care; 1 = connected to pull-up resistor; 0 = not connected to pull-up resistor
X18A-C-001-08
18
GRAPHICS
SED1353
■ MONOCHROME PASSIVE STN LCD PANEL INTERFACE
4-Bit Single Panel
LP : 240 PULSES
LP: 4 PULSES
YD
LP
WF
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
LINE1
LINE2
UD[3:0]
LP
WF
XSCL: 80 CLOCK PERIODS
XSCL
1-317
1-318
1-319
1-320
1-1
1-2
1-3
1-4
1-5
UD3
UD2
UD1
UD0
1-6
1-7
1-8
Example Timing for a 320x240 single panel
19
X18A-C-001-08
GRAPHICS
SED1353
■ MONOCHROME PASSIVE STN LCD PANEL INTERFACE
8-Bit Single Panel
LP: 4 PULSES
LP : 480 PULSES
YD
LP
WF
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
UD[3:0], LD[3:0]
LP
WF
XSCL:80 CLOCK PERIODS
XSCL
1-633
1-634
1-635
1-636
1-637
1-638
1-639
1-640
1-1
1-2
1-3
1-4
1-5
1-9
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
1-10
1-11
1-12
1-13
1-6
1-7
1-14
1-15
1-8
1-16
Example timing for a 640x480 panel
X18A-C-001-08
20
GRAPHICS
SED1353
■ MONOCHROME PASSIVE STN LCD PANEL INTERFACE
8-Bit Dual Panel
LP: 2 PULSES
LP : 240 PULSES
YD
LP
WF
LINE1/241 LINE2/242 LINE3/243 LINE4/244
LINE 239/479 LINE240/480
LINE1/241 LINE2/242
UD[3:0], LD[3:0]
LP
WF
XSCL: 160 CLOCK PERIODS
XSCL
1-637
1-638
1-1
1-2
1-3
1-4
1-5
1-6
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
1-639
1-7
1-8
1-640
241-1 241-5
241-2 241-6
241-3 241-7
241-4 241-8
241-637
241-638
241-639
241-640
Example timing for a 640x480 panel
21
X18A-C-001-08
GRAPHICS
SED1353
■ COLOR PASSIVE STN LCD PANEL INTERFACE
4-Bit Single Panel
LP: 4 PULSES
LP : 240 PULSES
YD
LP
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
LINE1
LINE2
UD[3:0]
LP
WF
XSCL: 240 CLOCK PERIODS
XSCL
1-B319
1-R320
1-G320
1-B320
1-R1
1-G1
1-B1
1-R2
1-G2
1-B3
UD3
UD2
UD1
UD0
1-B2
1-R4
1-R3
1-G3
1-G4
1-B4
Example timing for a 320x240 panel
X18A-C-001-08
22
GRAPHICS
SED1353
■ COLOR PASSIVE STN LCD PANEL INTERFACE
8-Bit Single Panel - Format 1
LP: 480 PULSES
LP: 4 PULSES
YD
LP
UD[3:0]
LD[3:0]
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
LP
XSCL2: 120 CLOCK PERIODS
XSCL: 120 CLOCK PERIODS
XSCL2
XSCL
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
1-R1
1-B1
1-G2
1-R3
1-B3
1-G4
1-R5
1-B5
1-G1 1-G6
1-B6
1-G7
1-R8
1-B8
1-G9
1-B11 1-R12
1-G12 1-B12
1-R13 1-G13
1-B13 1-R14
1-G14 1-B14
1-B635 1-R636
1-G636 1-B636
1-R637 1-G637
1-B637 1-R638
1-G638 1-B638
1-R639 1-G639
1-B639 1-R640
1-G640 1-B640
1-R2 1-R7
1-B2 1-B7
1-G3 1-G8
1-R4 1-R9
1-B4 1-B9
1-R10 1-R15 1-G15
1-G5 1-G10 1-B10 1-B15 1-R16
1-R6 1-R11 1-G11 1-G16 1-B16
Example timing for a 640x480 panel
23
X18A-C-001-08
GRAPHICS
SED1353
■ COLOR PASSIVE STN LCD PANEL INTERFACE
8-Bit Single Panel - Format 2
LP: 4 PULSES
LP : 240 PULSES
YD
LP
UD[3:0]
LD[3:0]
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
LINE1
LINE2
LP
WF
XSCL: 120 CLOCK PERIODS
XSCL
1-G318
1-B318
1-R319
1-G319
1-R1
1-G1
1-B1
1-R2
1-B3
1-G6
UD3
UD2
UD1
UD0
1-R4
1-B6
1-G4
1-B4
1-R7
1-G7
1-B319
1-R320
1-G320
1-B320
1-G2
1-B2
1-R3
1-G3
1-R5
1-G5
1-B7
1-R8
LD3
LD2
LD1
LD0
1-B5
1-R6
1-G8
1-B8
Example timing for a 320x240 panel
X18A-C-001-08
24
GRAPHICS
SED1353
■ COLOR PASSIVE STN LCD PANEL INTERFACE
8-Bit Dual Panel
LP: 2 PULSES
LP: 240 PULSES
YD
LP
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
LINE479 LINE480
LINE1
LINE2
UD[3:0]
LD[3:0]
LINE241 LINE242 LINE243 LINE244
LINE241 LINE242
LP
WF
XSCL: 480 CLOCK PERIODS
XSCL
1-R1
1-G1
1-G2
1-B2
1-B3
1-R4
1-R637
1-G637
1-B637
1-R638
1-G638
1-B638
1-R639
1-G639
1-B639
1-R640
1-G640
1-B640
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
1-B1
1-R3
1-G4
1-R2
1-G3
1-B4
241-R1
241-G1
241-B1
241-R2
241-G2
241-B2
241-R3
241-G3
241-B3
241-R4
241-G4
241-B4
241-R637 241-G638 241-B639
241-G637 241-B638 241-R640
241-B637 241-R639 241-G640
241-R638 241-G639 241-B640
Example timing for a 640x480 panel
25
X18A-C-001-08
GRAPHICS
SED1353
■ COLOR PASSIVE STN LCD PANEL INTERFACE
16-Bit Single Panel With External Circuit
LP : 480 PULSES
LP: 4 PULSES
YD
LP
LINE1
LINE2
LINE3
LINE4
LINE479
LINE480
LINE1
LINE2
Pixel Data
LP
WF
XSCL: 120 CLOCKS
XSCL
1-R1
1-B3
1-G4
1-R5
1-B5
1-B635 1-G638
UD3
UD2
UD1
UD0
1-G636 1-R639
1-R637 1-B639
1-B637 1-G640
1-B1
1-G2
1-R3
1-G1
1-R2
1-R4
1-B4
1-R636 1-B638
1-B636 1-G639
1-G637 1-R640
1-R638 1-B640
LD3
LD2
LD1
LD0
1-G5
1-B2
1-G3
1-R6
1-R1
1-B1
1-G2
1-R3
1-B635
1-G636
1-R637
1-B637
UD7
UD6
UD5
UD4
1-G638
1-B3
1-G4
1-R5
1-B5
UD3
UD2
UD1
UD0
1-R639
1-B639
1-G640
1-G1
1-R636
1-B636
1-G637
1-R638
LD7
LD6
LD5
LD4
1-R2
1-B2
1-G3
1-B638
1-R4
1-B4
1-G5
1-R6
LD3
LD2
LD1
LD0
1-G639
1-R640
1-B640
Example timing for a 640x480 panel
X18A-C-001-08
26
GRAPHICS
SED1353
■ COLOR PASSIVE STN LCD PANEL INTERFACE
16-Bit Dual Panel With External Circuit
LP: 2 PULSES
LP : 240 PULSES
YD
LP
LINE1/241
LINE2/242
LINE3/243
LINE4/244
LINE239/479 LINE240/480
LINE1/241
LINE2/242
Pixel Data
LP
WF
XSCL: 240 CLOCKS
XSCL
1-R1
1-G1
1-B1
1-R2
1-G638 1-B639
1-G2
1-B3
1-R4
1-G4
1-B4
UD3
UD2
UD1
UD0
1-B2
1-R3
1-G3
1-B638 1-R640
1-R639 1-G640
1-G639 1-B640
241-
241-
241-R1 241-G2 241-B3
241-G1 241-B2 241-R4
241-B1 241-R3 241-B4
241-R2 241-G3 241-B4
LD3
LD2
LD1
LD0
G638
B639
241-
241-
B638
R640
241-
241-
R639
G640
241-
G639
241-
B640
1-R1
1-G1
1-B1
1-R2
1-G638
1-B638
1-R639
1-G639
UD7
UD6
UD5
UD4
1-B639
1-G2
1-B2
1-R3
1-G3
UD3
UD2
UD1
UD0
1-R640
1-G640
1-B640
241-R1
241-G638
241-B638
241-R639
241-G639
LD7
LD6
LD5
LD4
241-G1
241-B1
241-R2
241-
241-G2
241-B2
LD3
LD2
LD1
LD0
B639
241-
R640
241-
241-R3
241-G3
G640
241-
B640
Example timing for a 640x480 panel
27
X18A-C-001-08
GRAPHICS
SED1353
■ PACKAGE DIMENSIONS: SED1353F0A
QFP5-100PIN-S2
(SED1353F0A)
± 0.04
23.2
± 0.1
20.0
80
51
81
50
Index
100
31
± 0.1
± 0.1
1
30
0.65
0.30
0~12°
± 0.1
0.8
1.6
All dimensions in mm
Actual Size
X18A-C-001-08
28
GRAPHICS
SED1353
■ PACKAGE DIMENSIONS: SED1353F1A
QFP15-100PIN-STD
(SED1353F1A)
± 0.4
± 0.1
16.0
14.0
75
51
76
50
Index
100
26
1
25
± 0.1
0.168
0.5
0.5
0~12°
± 0.2
1
All dimensions in mm
Actual Size
29
X18A-C-001-08
GRAPHICS
SED1353
■ COMPREHENSIVE SUPPORT TOOLS
Seiko Epson Corp. provides the designer and manufacturer a complete set of resources and tools for the develop-
ment of LCD Graphics Systems.
Documentation
Technical Manuals
•
•
Evaluation/Demonstration Board Manual
Evaluation/Demonstration Board
Assembled and Fully Tested Graphics Evaluation/Demonstration Board
Schematic of Evaluation/Demonstration Board
Parts List
•
•
•
•
•
•
•
Installation Guide
CPU Independent Software Utilities
Evaluation Software
Windows CE Display Driver
■ APPLICATION ENGINEERING SUPPORT
Seiko Epson Corp. offers the following services through their Sales and Marketing Network:
Sales Technical Support
Customer Training
•
•
CONTACT YOUR SALES REPRESENTATIVE FOR THESE
COMPREHENSIVE DESIGN TOOLS:
• SED1353 Technical Manual
• SDU1353 Evaluation Boards
• CPU Independent Software Utilities
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: 042-587-5812
Fax: 042-587-5564
http://www.epson.co.jp
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: (408) 922-0200
Fax: (408) 922-0238
http://www.eea.epson.com
Taiwan, R.O.C.
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan, R.O.C.
Tel: 02-2717-7360
Fax: 02-2712-9164
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Hong Kong
Europe
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
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