SED1345F0A [SEIKO]
CRT to LCD Converter, 640 X 480 Dots, CMOS, PQFP80;
| 型号： | SED1345F0A |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | CRT to LCD Converter, 640 X 480 Dots, CMOS, PQFP80 CD 外围集成电路 |
| 文件： | 总12页 (文件大小：45K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SED1345
CMOS VIDEO - LCD INTERFACE (VLI)
8 Levels of Gray Scale
•
■ DESCRIPTION
The SED1345 is a video-LCD interface (VLI) developed for a dot matrix LCD display system. It converts
separate video signals for CRT display into signals for LCD.
The SED1345 can use a conventional LCD driver to display data at eight gradation levels corresponding to
digital video signal data I, R, G and B. The on-chip color pallet for gradation display allows setting of any
gradation level for each of the 16 colors on the CRT display.
A 640 × 480 dot panel with eight gradation levels can be driven using only 256K bits of frame buffer memory.
This leads to a significant reduction in system memory cost.
With the SED1345, the user can select not only a display size but a display area to configure a display panel
of flexible size from 640 × 200 dots to 640 × 480 dots (maximum). These LCD display sizes are compatible
with various display modes such as CGA® and EGA®.
■ FEATURES
Low-power CMOS technology
TTL-compatible signal input
LCD display size:
Register programming by 4 bits
•
•
•
•
•
•
•
•
•
•
Maximum dot clock: ......................... 30 MHz
Supports 40KB SRAM frame buffer
Duty cycle: ............................. 1/200 to 1/480
Power-on clear function
Horizontal: ..................................... 640 dots
Vertical: .................200, 350, 400, 480 lines
Supports 8 levels of gray shade
Single power supply: ...................... 5V ± 5%
Package:....................... QFP5-80 pin (FOA)
•
•
•
Supports single panel and dual panel
LCD driver interface:4 bits bus and 4 bits × 2 bus
■ SYSTEM BLOCK DIAGRAM
DIGITAL R
DIGITAL G
DIGITAL B
SED1345
MONO LCD
PC
HSYNC
VSYNC
SRAM
185
SED1345
■ BLOCK DIAGRAM
A0 D0
A4 D3
CS, WR
SEL
Gradation
Color
Pallet
I. R. G. B.
MPU Interface
Signal
Generator
CK
HSC
VSC
Timing
Generator
UD0~UD3
LD0~LD3
Video
Signal
Interface
Address
Counter
(WR)
Address
Counter
(RD)
XSCL
LP
XECL
LCD
Driver
Control
WF
TD
YSCL
S/P Convertor
M
P
X
MD0
MD7
MA0
WE OE
MA15
■ PIN OUT
M A 0
I
R
G
B
NU
NU
NU
NU
LD3
LD2
LD1
LD0
UD3
UD2
UD1
UD0
60
55
50
45
40
35
65
70
M A 1
M A 2
M A 3
M A 4
M A 5
M A 6
M A 7
M A 8
M A 9
SED1345
M A 1 0
30
25
75
80
M A 1 1
M A 1 2
M A 1 3
M A 1 4
M A 1 5
5
10
15
20
186
SED1345
■ PIN OUT
No.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
OE
No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
NU
VDD
VSS
D3
No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
VSC
VSS
VDD
CK
No.
1
Name
NU
2
VDD
VSS
NU
VSS
VDD
WE
3
4
MA15
MA14
MA13
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
D2
I
5
NU
6
XECL
XSCL
LP
D1
R
7
D0
G
CS
B
8
WR
A4
NU
9
WF
10
11
12
13
14
15
16
17
18
19
20
YD
NU
YSCL
NU
A3
NU
A2
NU
A1
LD3
LD2
LD1
LD0
UD3
UD2
UD1
UD0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
A0
NU
SEL
RES
NU
NU
HSC
Note: NU
=
Pin is Not Used
The NU pin is wired to the IC chip inside the package, and must be held open.
■ PIN DESCRIPTION
Pin Name
VDD
Pin No.
Function
2, 23, 42, 63
+5V power
VSS
3, 22, 43, 62
GND
UD0 to UD3
LD0 to LD3
XSCL
80 to 77
Data bus output to X-driver
Data bus output to X-driver
Shift clock output to X-driver
Latch pulse output
76 to 73
7
LP
8
6
XECL
Enable shift clock output to X-driver
LCD AC signal output
WF
9
YD
10
Scanning start data output to Y-driver
Shift clock output to Y-driver
Video data input
YSCL
11
I, R, G, B
CK
65 to 68
64
Dot clock input
HSC
60
Horizontal sync signal input
Vertical sync signal input
VSC
61
MA0 to MA15
MD0 to MD7
WE
40 to 25
20 to 13
24
Address bus output to frame buffer memory
Data bus input/output to frame buffer memory
Write enable signal output
OE
21
Output enable signal output
D0 to D3
A0 to A4
CS
47 to 44
54 to 50
48
Data bus input for writing registers
Address bus input/output for writing registers
Chip select signal input
WR
49
Write signal input
SEL
56
Register write mode selection input (ROM/MPU)
Reset signal input
RES
57
187
SED1345
■ ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = 0V)
•
Parameter
Supply Voltage
Symbol
VDD
VI
Condition
Ratings
–0.3 to 7.0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–10 to 10
Unit
V
Based on VSS
Input Voltage
V
Output Voltage
VD
V
I/O Voltage
VI/O
IO
V
Output Current/Pin
Power Dissipation
Operating Temperature
Storage Temperature
Soldering Temperature and Time
mA
mW
°C
°C
PD
250
Topr
Tstg
Tsol
0 to 70
–65 to 150
260°C, 10s (at lead)
—
Recommended Operating Conditions
•
•
(VSS = 0V)
Parameter
Supply Voltage
Symbol
Condition
Min
Typ
Max
5.25
Unit
V
VDD
4.75
5.00
DC Characteristics
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Average Operating
Symbol
Condition
Min
—
Typ
—
Max
40
Unit
mA
Iopr
fck=24MHz
Current Consumption
High Voltage Input Voltage 1
Low Level Input Voltage 1
High Level Input Voltage 2
Low Level Input Voltage 2
High Level Input Voltage 3
Low Level Input Voltage 3
High Level Output Voltage
Low Level Output Voltage
Input Current Leakage
I/O Current Leakage
VIH1
VIL1
VIH2
VIL2
VIH3
VIL3
VOH
VOL
ILI
*1
*2
*3
2.0
–0.3
4.0
—
—
—
—
—
—
—
—
—
—
VDD+0.3
V
V
0.8
VDD+0.3
0.8
V
–0.3
3.0
V
VDD+0.3
0.6
V
–3.0
4.35
—
V
IOH = –2mA
IOL = 6mA
—
V
0.4
V
VI = 0V to VDD
VI/O = 0V to VDD
–1
1
µA
µA
ILI/O
–1
1
*1 Pad: I, R, G, B, CK, HSC, VSC, MD0 to MD7, A0 to A4, CS, WR
*2 Pad: D0 to D3, SEL
*3 Pad: RES
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Output Rise Time
Output Fall Time
Symbol
Condition
CL = 150pF
CL = 150pF
Min
—
Typ
—
Max
50
Unit
ns
tri
tfl
—
—
50
ns
188
SED1345
AC CHARACTERISTICS
LCD Interface Timing Chart
•
°
WF
YD
Data Output of 1st Line
LP
t CLP
LP
64 Dots
XECL
XSCL
UD0-UD3
LD0-LD3
159
160
1
8
152
159
160
1
WF
tr1
tf1
tDFR
YD
LP
tSUYD1
tHYD1
tHYD2
tWLPH
tSUYD2
tSULP
tWECH
tHLP
LP
XECL
tES1
tSL3
tES2
tSL2
tCSC
tSL1
tLS2
tLS3
tLS1
XSCL
tHXD
tSUXD
tWSCL
tWSCH
UD0-UD3
LD0-LD3
Output Signal Reference Level:
“H” = VDD × 0.8V
“L” = VDD × 0.2V
189
SED1345
X Driver
°
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
S6 = “H”
S6 = “L”
S6 = “H”
S6 = “L”
S6 = “H”
S6 = “L”
S6 = “H”
S6 = “L”
S6 = “H”
S6 = “L”
Min
2t1
Typ
—
Max
—
Unit
ns
XSCL Cycle Time
tCSC
4t1
t1–20
2t1–20
t1–20
2t1–20
t1–30
2t1–30
21–30
2t1–30
XSCL “H” Pulse Width
XSCL “L” Pulse Width
tWSCH
tWSCL
tSUXD
tHXD
tSL1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UD0–3, LD0–3 Setup Time
before XSCL
UD0–3, LD0–3 Hold Time
after XSCL
S6 = “H” 0.5t1–30
XSCL to LP Time
XSCL to LP Time
LP to XSCL Time
LP to XSCL Time
XSCL to LP Time
LP to XSCL Time
LP Cycle Time
S6 = “L”
S6 = “H”
S6 = “L”
t1–30
t1–20
tSL2
2t1–20
S5 = “H”
S6 = “H” 1.5t1–50
tLS1
S6 = “L”
S6 = “H”
S6 = “L”
3t1–50
t1–20
tLS2
2t1–20
S6 = “H” 0.5t1–40
S6 = “L” t1–40
S6 = “H” 0.5t1–40
tSL3
S5 = “L”
tLS3
S6 = “L”
S0 = “H”
S0 = “L”
t1–40
320t1
640t1
tCLP
—
—
—
—
ns
ns
S6 = “H” 1.5t1–50
S5 = “H”
S5 = “L”
S6 = “L”
S6 = “H”
S6 = “L”
3t1–50
t1–40
LP, YSCL “H” Pulse Width
tWLPH
—
—
ns
2t1–40
t1–50
LP Setup Time before XECL
LP Hold Time after XECL
XSCL to XECL Time
tSULP
tHLP
S5 = “H”, S6 = “H”
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
S5 = “H”, S6 = “H”
S5 = “H”, S6 = “H”
S5 = “H”, S6 = “H”
S5 = “H”, S6 = “H”
S5 = “H”, S6 = “H”
0.5t1–40
0.5t1–30
0.5t1–40
1.5t1–50
—
tES1
—
XECL to XSCL Time
tES2
—
XECL “H” Pulse Width
tWECH
tDFR
—
WF Output Delay Time After LP, YSCL
100
t1 = 2tCCK (tCCK = dot clock cycle)
190
SED1345
Y Driver
°
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
S0 = “H”
Min*
Typ
—
Max
—
Unit
ns
YD Setup Time
before LP, YSCL
YD Hold Time
after LP, YSCL
142t1–100
302t1–100
18t1–100
18t1–100
tSUYD1
S0 = “L”
S0 = “H”
S0 = “L”
S5 = “H”
thYD1
—
—
—
—
ns
ns
S6 = “H” 141.5t1–100
S6 = “L” 141t1–100
S6 = “H” 301.5t1–100
S6 = “L” 301t1–100
S6 = “H” 17.5t1–100
S6 = “L” 17t1–100
S6 = “H” 17.5t1–100
S6 = “L” 17t1–100
S0 = “H”
S0 = “L”
S0 = “H”
S0 = “L”
YD Setup Time
tSUYD2
before LP, YSCL
S5 = “L”
YD Hold Time
after LP, YSCL
tHYD2
—
—
ns
t1=2tCCK (tCCK = dot clock cycle)
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
CK Cycle Time
Symbol
tCCK
Condition
Min
33
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK “H” Pulse Width
tWCKW
tWCKL
tr2
12
CK “L” Pulse Width
12
Input Rise Time
—
Input Fall Time
tf2
—
5
VD Setup Time Before CK
VD Hold Time After CK
CK Setup Time Before HSC
CK Hold Time After HSC
HSC Setup Time Before VSC
HSC Hold Time After VSC
Active Pulse Width HSC
Non-Active Pulse Width HSC
tSUVD
tHVD
16
—
—
—
—
—
—
—
—
2
tSUCK
tHCK
20
0
tSUVH
tHVM
tWH1
tWH2
80
0
8tCCK
64tCCK
191
SED1345
Memory Interface
Read Cycle
•
°
SRAM Read Cycle
t
RC1
MA0 to MA15
MD0 to MD7
VALID
t
OH
t
ACC
VALID
→
(Memory VLI)
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Symbol
tRC1
Condition
Min
4tCCK
—
Typ
—
Max
—
Unit
ns
Read Cycle Time
Address Access Time
Output Hold Time
tACC
—
4tCCK–17
—
ns
tOH
10
—
ns
192
SED1345
Write Cycle
°
Write Cycle
tWC1
tAS
tWR
MA0 to MA15
WE
VALID
tWP1
tDW
tDH
MD0 to MD7
←
VALID
(VLI Memory)
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Write Cycle Time
Symbol
tWC1
tWP1
tAS
Condition
Min*
4tCCK
Typ
—
—
—
—
—
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
Write Pulse Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
3tCCK–13
0.5tCCK–14
0.5tCCK–14
3tCCK–38
5
—
—
tWR
—
tDW
—
tDH
—
Input/Output Signal Reference Level: “H” = 2.0V “L” = 0.8V
*tCCK is the cycle time of dot clock (tCCK = 1/fCK).
193
SED1345
Register Program
Write Data Using MPU
•
°
tHCS
tSUCS
CS
tSUA
tHA
A0 to A4
VALID
tSUD
tHD
D0 to D3
WR
tWWR
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
CS Setup Time
Symbol
tSUCS
tHCSH
tSUA
Condition
Min
50
Typ
—
—
—
—
—
—
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
CS Hold Time
50
—
A0–A4 Setup Time
A0–A4 Hold Time
D0–D3 Setup Time
D0–D3 Hold Time
WR Pulse Width
50
—
tHA
50
—
tSUD
100
50
—
tHD
—
tWWR
50
—
194
SED1345
Write Data Using ROM
•
0 1 2 3
3031
0 1 2 3
A0
A1
A2
A3
A4
tRC2
VALID
VALID
VALID
A0
tHRM
tSURM
D0 to D3
VALID
VALID
VALID
Input/output signal level identification voltages:
“H” level – 2.0V
“L” level – 0.8V
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
ROM Read Cycle Time
D0 to D3 Setup Time
D0 to D3 Hold Time
Symbol
Condition
Min*
8t1–100
100
Typ
—
Max
—
Unit
ns
tRC2
tSURM
tHRM
—
—
ns
10
—
—
ns
* t1=2tCCK (tCCK is a cycle time of dot clock)
195
SED1345
Reset Input
•
t
WRES
RES
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
RES Pulse Width
Symbol
twRES
Condition
Min
1.0
Typ
—
Max
—
Unit
ns
Input signal reference level: “H” = 2.0V “L” = 0.8V
tCCK is a cycle time of dot clock (tCCK = 1/fCK)
System Configuration
•
MPU/ROM
+5V
66
R
R
71
67
68
65
61
60
64
TEST
G
G
B
B
LP
WF
5
4
Personal
Computer
I
I
VSC
HSC
CK
VSC
HSC
CK
YSCL 11
YD 10
XSCL
XECL
7
6
SED1345
640 × 480
UD0 80
UD1 79
UD2 78
UD3 77
LD0 76
LD1 75
LD2 74
LD3 73
2
23
42
63
LCD
V
DD
3
22
43
62
V
SS
10
19
19
10
9
A0
I/O0
A0
I/O0
9
8
7
6
5
4
3
25
24
21
23
2
18
17
16
15
14
13
12
11
28
14
18
17
16
15
14
13
12
11
8
7
6
5
4
3
25
24
21
23
2
I/O8
VDD
VSS
I/O8
VDD
28
14
A12 VSS
26
1
20
A14
CS
OE 22
27
20
26
22
27
CS1 OE
CS2 CE
CE
SRM20256M
SRM2264M
196
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