SED1341F0E [SEIKO]
CRT to LCD Converter, 720 X 400 Dots, CMOS, PQFP80;
| 型号： | SED1341F0E |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | CRT to LCD Converter, 720 X 400 Dots, CMOS, PQFP80 CD 外围集成电路 |
| 文件： | 总20页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SED1341
CMOS VIDEO – LCD INTERFACE (VLI)
■ DESCRIPTION
The SED1341 is a VLI (video-LCD interface) for converting previously separated video signals, intended for
a CRT display, into signals compatible with dot-matrix liquid-crystal displays (LCDs). When sync and data
separators are added, composite video signals can also be processed. Using the SED1341, a compact LCD
monitor can replace a monochrome CRT display without including additional software or hardware.
The frame-buffer memory controlled by the VLI accurately matches the high-frequency video signals to the
low-frequencyoperationoftheLCDunit.Ascreenalignmentfunctionfortheadjustmentofthedisplayposition
makes it easy to implement an LCD module that is compatible with CRT display.
IndividualselectionofthevideodatascreenandLCDpanelsizesandaverticaldoublelinedisplaymodeallow
the SED1341 to interface LCDs with the video outputs of a variety of personal computers (PCs).
■ FEATURES
Low-power CMOS technology
TTL-compatible signal input
Built-in PLL to generate dot clock
Supports single panel and dual panel
•
•
•
•
•
•
•
•
Supports 4-bit, 8-bit dual panel and 8-bit single
panel
Supports 40KB SRAM frame buffer
Screen alignment adjustment via 4-bit bus or
hardware
•
•
•
•
•
•
Supports screen size from 640 × 200 to 720 × 400
Duty cycle ............................. 1/100 to 1/496
Power-on clear function
Horizontal and vertical back porch register
Internal oscillator to optimize the frame frequency
to match the LCD timing
Single power supply ............. 5V ± 5%
Package................................ QFP5-80 pin (FOE)
Supports vertical flyback time
•
■ AVAILABLE MODELS
SED1341FOC and SED1341FOE. See the functional comparison table at the end of this data sheet.
■ SYSTEM BLOCK DIAGRAM
DIGITAL R
DIGITAL G
VD
DIGITAL B
SED1341
MONO LCD
HSYC
VSYC
PC
SRAM
165
SED1341
■ BLOCK DIAGRAM
CU, CD
PCO
OSC1 OSC2 SEL1-SEL13
Timing Generator
PLL Program
Counter/Phase
Comparator
D0-D3
A0/S5-A2/S3
CS/S1, WR/S2
VDD
VSS
Scanning Signal
Generator
S0
RES
Address Counter
(Write)
Address Counter
(Read)
VD, CK
UD0-UD3
HSC, VSC
LD0-LD3
XSCL
LP, YD, WF, YSCL
PL0-PL3
S/P
Converter
MPX
MD0-MD7
WE
MA0-MA15
■ SED1341F0C/SED1341F0E Pin Comparison
M A 2
M A 3
M A 4
M A 5
M A 6
M A 7
M A 8
M A 9
PL0
SEL3
PL1
PL2
SEL5
SEL6
SEL7
SEL8
60
55
50
45
40
35
65
70
75
80
M A 1 0
SED1341FOE
TEST/LD3
TEST/LD2
TEST/LD1
TEST/LD0
TEST
SEL1
SEL2
OSC1
M A 1 1
M A 1 2
M A 1 3
M A 1 4
M A 1 5
S E L 1 2
S E L 1 1
30
25
5
10
15
20
166
SED1341
■ PINOUT
Pin
Pin
Pin
Pin
Number
1
Name
OSC2
UD3
UD2
UD1
UD0
SEL13
XSCL
LP
Number
21
Name
SEL14
WE
Number
41
Name
MA1
MA0
SEL9
D3
Number
61
Name
VSC
HSC
CK
22
2
42
62
23
TEST
SEL4
SEL11
SEL12
MA15
MA14
MA13
MA12
MA11
MA10
MA9
3
43
63
24
4
44
64
VD
25
5
45
D2
65
PL0
26
6
46
D1
66
SEL3
PL1
27
7
47
D0
67
28
8
48
CS/S1
WR/S2
A2/S3
A1/S4
A0/S5
VDD
68
PL2
29
9
WF
49
69
SEL5
SEL6
SEL7
SEL8
30
10
11
12
13
14
15
16
17
18
19
20
YD
50
70
31
YSCL
VSS
51
71
32
52
72
33
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
53
73
TEST/LD3
TEST/LD2
TEST/LD1
TEST/LD0
TEST
34
MA8
54
TEST/S0
RES
SEL10
PCO
CU
74
35
MA7
55
75
36
MA6
56
76
37
MA5
57
77
38
MA4
58
78
SEL1
39
MA3
59
CD
79
SEL2
40
MA2
60
PL3
80
OSC1
Note: TEST pins must be left open as they are wired to individual IC chips inside the package.
167
SED1341
■ PIN DESCRIPTION
Pin
Description
Name
Number
VDD
VSS
53
12
Supply voltage (+5V)
GND
OSC1
OSC2
80
1
Oscillator pin (input)
Oscillator pin (output)
UD0 to UD3
TEST/LD0 to TEST/LD3 76 to 73
XSCL
LP
5 to 2
X-driver data bus output (upper)
X-driver data bus output (lower)
X-driver shift clock output
7
8
Latch pulse output
WF
YD
YSCL
9
10
11
AC waveform output for LCD
Row scanning start data output for Y-driver
Y-driver shift clock output
VD
CK
HSC
VSC
64
63
62
61
Video data input
Dot clock input
Horizontal sync signal input
Vertical sync signal input
MA0 to MA15
MD0 to MD7
WE
42 to 27
20 to 13
22
Address bus output to frame buffer memory
Data bus I/O to frame buffer memory
Write enable signal output
D0 to D3
47 to 44
Data input for screen position input
SEL5 = LOW
SEL5 = HIGH
TEST/S0
A0/S5 to A2/S3
CS/S1
54
52 to 50
48
TEST
Scan signal output for digital switch
Scan signal output for digital switch
Scan signal output for digital switch
Scan signal output for digital switch
Address bus input
Chip select input
Write signal input
WR/S2
49
RES
55
Reset signal input
SEL1
SEL2
SEL3
SEL4
SEL5
SEL6
SEL7
SEL8
SEL9
SEL10
SEL11
SEL12
SEL13
SEL14
78
79
66
24
69
70
71
72
43
56
25
26
6
LCD drive mode select input (single/dual)
LCD panel line number select input
LCD panel line number select input
LCD panel line length select input
Screen alignment method select input (SW/MPU) (disable/enable)
LCD panel vertical flyback time select input
Latch pulse output timing select input (edge/level)
X-driver interface data bus select input (4-bit, 4 × 2-bit, 8-bit)
LCD panel vertical flyback line number select input
Video data vertical line number select input
Video data vertical line number select input
Video data line length select input
Vertical doubleline display select input (enable/disable)
Horizontal back porch range select input (normal/high)
21
PL0
PL1
PL2
PL3
65
67
68
60
Polarity select input for video signal VD
Polarity select input for video signal HSC
Polarity select input for video signal VSC
Polarity select input for video signal CK
PCO
CU, CD
57
58, 59
Program counter output from PLL section
Phase comparator output from PLL section
168
SED1341
■ ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = 0V)
•
Parameter
Supply voltage
Symbol
VDD
VI
Ratings
–0.3 to 7.0
Unit
V
Input voltage
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–10 to 10
V
Output voltage
VD
V
I/O voltage
VI/O
IO
V
Output current
mA
mW
°C
°C
—
Power dissipation
Operating temperature
Storage temperature
Soldering temperature and time
PD
250
Topr
Tstg
Tsol
0 to 70
–65 to 150
260°C, 10s (at lead)
RECOMMENDED OPERATING CONDITIONS
•
•
Parameter
Supply voltage
Symbol
VDD
Condition
Min
4.75
—
Typ
5.00
0
Max
5.25
—
Unit
V
Supply voltage
VSS
V
DC CHARACTERISTICS
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Min Typ Max Unit
fck = 14.3MHz (640×200) fck/3.6 4.5 fck/2.28 MHz
Parameter
Symbol
Condition
Oscillation Frequency
fOSC
fck = 16MHz (640×350)
fck = 21MHz (640×400)
fck/3.6
fck/3.6
7
9
and
MHz
MHz
MHz
11.2
fck = 24MHz (640×480) fck=3.6 10
Average Operating
fck = 32MHz
Iopr
—
—
40
mA
Current Consumption
fosc = 12MHz
*1
High Level Input Voltage 1
Low Level Input Voltage 1
High Level Input Voltage 2
Low Level Input Voltage 2
High Level Input Voltage 3
Low Level Input Voltage 3
High Level Output Voltage
Low Level Output Voltage
Input Current Leakage
I/O Current Leakage
VIH1
VIL1
VIH2
VIL2
VIH3
VIL3
VOH
VOL
IL1
2.0
–0.3
4.0
—
—
—
—
—
—
—
—
—
—
VDD+0.3
0.8
V
V
*2
*3
VDD+0.3
0.8
V
–0.3
3.0
V
VDD+0.3
0.6
V
–0.3
4.35
—
V
IOH = –2mA *4
IOL = 6mA *4
—
V
0.4
V
VI–0V to VDD
VI/O = 0V to VDD
–1
1
mA
mA
ILI/O
–1
1
Notes:
*1. VD, CK, HSC, VSC, MD0 to MD7, A0 to A2, CS, WR, SEL9, SEL10
*2. PL0 to PL3, SEL1 to SEL8, SEL11 to SEL13, D0 to D3
*3. RES
*4. Except OSC2 Pin
169
SED1341
Power-On Clear Function
•
VLI has an internal power-on clear function which prevents unusual display after power-on and random data
display of buffer memory outside the display area.
The reset input makes the power-on clear function enable, and VLI performs as follows:
Clearing the frame buffer memory
Blanking the LCD display data
Whentheverticalsyncsignal, VSC, isinputafterthefourtofive-frametimefollowingtheresetrelease, thepower-
on clear function is released, and ordinary display operation starts.
4 to 5 Frames
RES
WF
XD0-7
LCD Display Data
Transmission Starts
VSC
VD
Video Data Input Status
Memory Clear Sequence
Blanking LCD Display Data
Power-on Waveforms
No video data, VD, is input during the memory clear sequence.
LCD-associated signals, such as shift clock, XSCL, and latch pulse LP are output during reset input.
170
SED1341
AC CHARACTERISTICS
LCD Interface Timing Chart
•
°
1st Frame
WF
YD
Data Output
of 1st Line
LP
tCLP
LP
XSCL
XD0-3
160
1
2
7
151
160
1
WF
YD
LP
tDFR
tf1
tr1
tsuYD1
thYD1
tWLPH
thYD2
tsuYD2
tSL3
tSL2
tLS1
tLS2
tSL1
tCSC
tLS3
XSCL
XD0-3
tWSCH
tsuXD
thYD
tWSCL
Note: “H” = VDD × 0.8V
“L” = VDD × 0.2V
Output Signal Reference Level
171
SED1341
Oscillation, Output Rise Time, Output Fall Time
°
Parameter
Symbol
t1
Condition
Min
2.28•tcck
and 89.2
—
Typ
—
Max
Unit
ns
3.6•tcck
Oscillation
Output Rise Time
Output Fall Time
tr1
tf1
C=150pF
C=150pF
—
—
50
50
ns
ns
—
Note: tcck is a cycle time of dot clock (tcck = 1/fck)
X Driver
°
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
XSCL Cycle Time
Symbol
Condition
SEL8 = “H”
SEL8 = “L”
SEL8 = “H”
SEL8 = “L”
SEL8 = “H”
SEL8 = “L”
SEL8 = “H”
SEL8 = “L”
SEL8 = “H”
SEL8 = “L”
Min*
2t1
Typ
—
Max
—
Unit
ns
tCSC
tWSCH
tWSCL
tSUXD
4t1
t1–20
2t1–20
t1–20
2t1–20
t1–30
2t1–30
t1–30
2t1–30
XSCL “H” Pulse Width
XSCL “L” Pulse Width
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UD0–3, UD0–3 Setup Time
before XSCL
UD0–3, UD0–3 Setup Time
after XSCL
SEL8 = “H” 0.5t1–30
SEL8 = “L” t1–30
SEL8 = “H” t1–20
SEL8 = “L” 2t1–20
SEL8 = “H” 1.5t1–50
SEL8 = “L” 3t1–50
SEL8 = “H” t1–20
SEL8 = “L” 2t1–20
SEL8 = “H” 0.5t1–40
SEL8 = “L” t1–40
SEL8 = “H” 0.5t1–40
SEL8 = “L” t1–40
XSCL to LP Time
XSCL to LP Time
LP to XSCL Time
LP to XSCL Time
XSCL to LP Time
LP to XSCL Time
LP Cycle Time
tSL1
tSL2
tLS1
tLS2
tSL3
tLS3
tCLP
SEL7 = “H”
SEL7 = “L”
SEL1 = “H”
SEL1 = “L”
320t1
640t1
—
—
—
—
ns
ns
SEL8 = “H” 1.5t1–50
SEL8 = “L” 3t1–50
SEL8 = “H” t1–40
SEL8 = “L” 2t1–40
—
SEL7 = “H”
SEL7 = “L”
LP “H” Pulse Width
tWLPW
tDFR
—
—
—
ns
ns
WF Output Delay Time After LP1, LP2
—
100
*t1 is an oscillation frequency of X’tal oscillation circuit (t1 = 1/fosc)
172
SED1341
Y Driver
°
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
SEL1 = “H”
Min*
Typ
—
Max
—
Unit
ns
YD Setup Time
before LP, YSCL
YD Hold Time
after LP, YSCL
142t1–100
302t1–100
18t1–100
18t1–10
tSUYD1
SEL1 = “L”
SEL1 = “H”
SEL1 = “L”
SEL7 = “H”
thYD1
—
—
—
—
ns
ns
SEL8 = “H”141.5t1–100
SEL8 = “L” 141t1–100
SEL8 = “H”301.5t1–100
SEL8 = “L” 301t1–100
SEL8 = “H” 17.5t1–100
SEL8 = “L” 17t1–100
SEL8 = “H” 17.5t1–100
SEL8 = “L” 17t1–100
SEL1 = “H”
SEL1 = “L”
SEL1 = “H”
SEL1 = “L”
YD Setup Time
tSUYD2
before LP, YSCL
SEL7 = “L”
YD Hold Time
after LP, YSCL
thYD2
—
—
ns
*t1 is an oscillation frequency of X’tal oscillation circuit (t1 = 1/fosc)
Video Signal Interface
°
(When PL1 = “L”, PL2 = “L”, PL3 = “L”)
thVH
tSUVM
VSC
Vertical Back Porch
HSC
VD
INVALID
VALID
INVALID
HSC
CK
VD
INVALID
tf2
1
2
640
INVALID
tr2
HSC
CK
thCK
tCCK
tSUCK
thVD
tWCKH
tSUVD
tWCKL
VD
ITS
173
SED1341
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
CK Cycle Timer
Symbol
tCCK
twCKw
twCKL
tr2
Condition
Min
29.4
12
12
—
—
16
2
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK “H” Pulse Width
CK “L” Pulse Width
Input Rise Time
Input Fall Time
tf2
5
VD Setup Time Before CK
VD Hold Time After CK
CK Setup Time Before HSC
CK Hold Time After HSC
HSC Setup Time Before VSC
HSC Hold Time After VSC
tSUVD
thVD
—
—
—
—
—
—
tSUCK
thCK
20
0
tSUVW
thUM
80
0
Memory Interface
Read Cycle
•
°
t
RC1
MA0 ~ MA15
VALID
t
OH
t
ACC
MD0 ~ MD7
(Memory –VLI)
VALID
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Read Cycle Time
Symbol
tRC1
Condition
Min
4tCCK
—
Typ
—
Max
—
Unit
ns
Address Access Time
Output Hold Time
tACC
—
4tCCK–17
—
ns
tOH
10
—
ns
174
SED1341
Write Cycle
°
tRC1
tAS
tWR
MA0 to MA15
WE
VALID
tWP1
tDH
tDW
MD0 ~ MD7
(Memory VLI)
←
VALID
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Write Cycle Time
Symbol
tWC1
tWD1
TAS
Condition
Min*
4tCCK
Typ
—
—
—
—
—
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
Write Pulse Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
3tCCK–13
0.5tCCK–14
0.5tCCK–14
3tCCK–38
5
—
—
tWR
—
tDW
—
tDH
—
Input, Output Signal Reference Level; “H” = 2.0V “L” = 0.8V
*tCCK is a cycle time of Dot Clock (tCCK = 1/fCK).
175
SED1341
Register Program
Write Method of MPU
•
°
tSUCS
thCS
CS
thA
tsuA
A0-A2
VALID
tsuD
VALID
thD
D0-D3
WR
tWWR
Input, Signal Reference Level; “H” = 2.0V “L” = 0.8V
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
CS Setup Time
Symbol
tsUCS
thCS
tsuA
Condition
Min
10
10
10
10
50
10
50
Typ
—
—
—
—
—
—
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
CS Hold Time
—
A0–A2 Setup Time
A0–A2 Hold Time
D0–D3 Setup Time
D0–D3 Hold Time
Pulse Width
—
thA
—
tsuD
—
thD
—
twWR
—
176
SED1341
Data Set Method By Digital Switch
•
1 Frame Time (LCD)
S0
S1
S2
S3
S4
S5
tWSH
S0
tWSL
S1
tSUDS
thDS
D0 ~ D3
VALID
* Input Signal Reference Level; “H” = 2.0V “L” = 0.8V
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Scanning Signal “H” Pulse Width
Scanning Signal “OFF” Width
D0–D3 Setup Time
Symbol
tWSH
Condition
Min*
8t1–150
8t1–150
100
Typ
—
Max
—
Unit
ns
tWSL
—
—
ns
tSUDS
thDS
—
—
ns
D0–D3 Hold Time
0
—
—
ns
*t1 is an oscillation frequency of X’tal oscillation circuit (t1 = 1/fosc)
177
SED1341
PLL Interface
•
CK
PCO
HSC
CU
CD
CD
PCO
HSC
tWPCO
tCU
tHU
CU
CD
tHD
tCD
Input Signal Reference Level; “H” = 2.0V “L” = 0.8V
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
Symbol
tHU
Condition
CL = 20pF
CL = 20pF
CL = 20pF
CL = 20pF
CL = 20pF
CL = 20pF
Min
—
Typ
22
22
22
22
—
Max
40
40
40
40
35
—
Unit
ns
ns
ns
ns
ns
ns
CU “ON” Delay Time After HSC
CU “OFF” Delay Time After CK
CU “ON” Delay Time After CK
CD “OFF” Delay Time After HSC
PCO Delay Time After CK
PCO Pulse Width
tCU
—
tCD
—
tHD
—
tCPCD
tWPCO
—
tCCK–25
—
178
SED1341
Reset Input
•
t
WRES
RES
(VDD = 5V±5%, VSS = 0V, Ta = 0 to 70°C)
Parameter
RES Pulse Width
Symbol
Condition
Min
1.0
Typ
—
Max
—
Unit
ns
tWRES
Input Signal Reference Level; “H” = 2.0V “L” = 0.8V
179
SED1341
■ EXAMPLE OF APPLICATION: 640 × 200 Dots, 4 bit 2-Bus, 2-Screen Operation
MPU
4
CU CD
CK
CS/S1
WR/S2
D0-D3
A0/S5
OSC1
3
OSC2
4
4
UD0-UD3
XSCL
LP
-A2/S3
Ck
VD
HSC
VSC
VD
HSC
VSC
VLI
WF
YD
EQ
EQ
X Driver
LD0-LD3
E1
E1
X Driver
X Driver
D1
YSCL
FR
13
8
L
AT DO
Dot Matrix LCD Panel
(640 x 200)
D1
YSCL
FR
SRAM2064C
SRAM2064C
X Driver
EQ
X Driver
X Driver
E1
E1
64K SRAM x 2
Recommended X Driver: SED1600F
Recommended Y Driver: SED1610F
4
640 × 400 Dots/640 × 350 Dots Connecting to Memory
•
15
8
256K SRAM
SRM20256 (32k x 8)
640 × 400 Dots/640 × 350 Dots Application Circuit
180
SED1341
640 × 480 Dots Connecting to Memory
•
VLI
8
13 (MAO-MA12)
(MAO-MA14)
15
64K SRAM 1 piece
and 256K SRAM 1 piece
SRM20256 (32k x 8)
SRM2264 (8k x 8)
640 × 480 Application Circuit
Example of LCD Module
•
EG-8001 (640 x 400 Dots)
53
1
2
VDD
VDD
VSS
VLCD
LP
12
VSS
3
4
VLCD
8
LP
9
5
WF
FR
SEL 1 = "L"
SEL 2 = "L"
6
7
VDD
YDIS
LCD Panel (EG-8001)
640 x 400 dots
NC
SEL 3 = "L"
VLI
10
8
YD
DIN
SEL 8 = "L"
4bit x 2bus
7
9
XSCL
XSCL
NC
2 screen drive
10
4
4
5~2
11~14
15~18
19
UD0-UD3
UD0-UD3
LD0-LD3
EI
76~73
LD0-LD3
VDD
20
EO
LCD Interface Circuit
181
SED1341
Example of PLL Circuit
•
V.C.O.
Phase Detector
MC4044 (MOTOROLA)
Charge Pump
Low Pass
Filter
13
1
C828
100K
U1 R1
1.8µ
C1
2P-30P
7P
0.002µ
R
30K
CV
2
3
HC125
D1 V1
HCU04
680
330
C2
+
–
0.33µ
to produce
high speed
and high
accuracy
clock
fCK
CK
CD
CU
to use built-in
phase detector
VLI
HSC
HSC
PCO
fCK
CU
C1
C2
R
14.3 MHz
21 MHz
1SV73(JRC)
22pF
10pF
30pF
15pF
330 Ω
510 Ω
1S2267 (Toshiba)
182
SED1341
■ DIFFERENCES BETWEEN SED1341F0C and SED1341F0E
Name
Name
No.
No.
D1341F0C
OSC2
UD3
D1341F0E
OSC2
UD3
D1341F0C
MA1
D1341F0E
MA1
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1
MA0
MA0
2
NU/SEL9
D3
SEL9
D3
3
UD2
UD2
4
UD1
UD1
D2
D2
5
UD0
UD0
D1
D1
6
XECL
XSCL
LP1
SEL13
XSCL
LP
D0
D0
7
CS/S1
WR/S2
A2/S3
A1/S4
A0/S5
VDD
CS/S1
WR/S2
A2/S3
A1/S4
A0/S5
VDD
NU/S0
RES
8
9
WF
WF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
YD
YD
NU/LP2
VSS
YSCL
VSS
MD7
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
NU
NU/S0
RES
MD6
MD5
NU/ITS
PCO
SEL10
PCO
CU
MD4
MD3
CU
MD2
CD
CD
MD1
PL3
PL3
MD0
VSC
VSC
CAS
HSC
HSC
CK
WE
WE
CK
NU
NU
VD
VD
SEL4
RAS2
RAS1
MA14/MA15
MA14
MA13
MA12
MA11
MA10
MA9
SEL4
SEL11
SEL12
MA15
MA14
MA13
MA12
MA11
MA10
MA9
MA8
MA7
MA6
MD5
MA4
MA3
MA2
PL0
PL0
SEL3
PL1
SEL3
PL1
PL2
PL2
SEL5
NU/SEL6
NU/SEL7
NU/SEL8
NU/LD3
NU/LD2
NU/LD1
NU/LD0
SEL
SEL5
SEL6
SEL7
SEL8
NU/LD3
NU/LD2
NU/LD1
NU/LD0
NU
MA8
MA7
MA6
MD5
SEL1
SEL2
OSC1
SEL1
SEL2
OSC1
MA4
MA3
MA2
NU = Not Used. NU terminals must be open since they are wired to individual IC chips in the package.
183
SED1341
Functional Comparison Table
•
Item
640 × 200
SED1341FOC
SED1341FOE
O
O
640 × 350
O
O
640 × 400
O
O
640 × 480
O
O
720 × 350
X
O
720 × 400
X
O
Automatic Centering Display
Automatic Horizontal Line Blanking
PLL Counter Dividing Ratio
Frame Buffer Memory
ITS (Half Tone) Display
XECL (X-Driver Enable Clock) (output)
X
O
X
O
1/706 to 1/961
1/514 to 1/1025
SRAM/DRAM
SRAM
O
O
X
X
O: Possible
X: Not Possible
184
相关型号：
©2020 ICPDF网 联系我们和版权申明