LA72700V [SANYO]
US MTS (Multi Channel Television Sound) Decoder; 美国MTS （多频道电视声音）解码器
| 型号： | LA72700V |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | US MTS (Multi Channel Television Sound) Decoder |
| 文件： | 总16页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0015
Monolithic Linear IC
US MTS (Multi Channel
Television Sound) Decoder
LA72700V
Overview
LA72700V is a US MTS (Multi Channel Television Sound) decoder.
Features
• With SIF circuit, STEREO channel separation is alignment-free.
• Built-in filters are adjustment free.
• SAP output level is selectable 2 levels.
• Included control function for STEREO and SAP detection sensitivity.
Functions
• SIF FM-Demodulator.
• STEREO decoder.
• ALC function is included.
• dbx Noise Reduction system.
• SAP demodulator.
• STEREO detection.
• SAP detection.
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
9.6
Unit
V
Maximum power supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
V
max
CC
Pd max
Ta≤70°C *
810
-10 to +70
-55 to +150
mW
°C
Topr
Tstg
°C
* ON board (114.3 × 76.1 × 1.6 mm Glass Epoxy resin board)
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
N2206 / O2505 MS OT B8-8873 No.A0015-1/16
LA72700V
Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
9.0
Unit
V
Recommended operating
voltage
V
CC
Operating voltage range
V
op
8.5 to 9.5
V
CC
Electrical Characteristics at Ta = 25°C, V
= 9.0V
CC
Ratings
typ
Parameter
Current dissipation
Symbol
Conditions
Unit
min
50
max
70
I
No signal Inflow current at pin 31
60
mA
CC
* Default condition
SIF input level
(Reference)
VILIM
fc = 4.5MHz
(80)
(90)
(100)
dBµV
Deviation
MONO (300Hz, Mod = 100%, Pre-emphasis ON) Æ
±25kHz
Base band input level
(Reference)
VILIMB
100% Modulation
MONO(L+R): 530mVp-p (300Hz, Pre-emphasis ON)
SUB(L-R):
SAP:
380mVp-p (300Hz, dbx-NR ON), Pilot: 110mVp-p
300mVp-p (300Hz, dbx-NR ON)
MONO output level
VOMON
THDMON
FCM1
Input: fm = 1kHz, 100% Mod, MONORAL
Measure OUT (L), OUT (R)
-7.0
-6.0
0.15
0
-5.0
0.6
2
dBV
%
MONO distortion
Input: fm = 1kHz, 100% Mod, MONORAL
Measure OUT (L), OUT (R)
MONO frequency characteristics
Input: fm = 8kHz, 30% Mod, MONORAL
Measure OUT(L), OUT(R),
-2
55
dB
Ratio from fm = 1kHz level.
MONO S/N ratio
SNM
S = VOMON, N = 0% Mod
65
dB
Measure OUT (L), OUT (R)
With 15kHz LPF, JIS-A
STEREO output level
STEREO distortion
VOST
THDS
FCS1
Input: fm = 1kHz, 100% Mod, STEREO
Measure OUT (L), OUT(R)
-7.0
-6.0
1.0
0
-5.0
2.5
3
dBV
%
Input: fm = 1kHz, 100% Mod, STEREO
Measure OUT (L), OUT (R)
STEREO frequency
characteristics
fm = 8kHz, 30% Mod, STEREO
Measure OUT (L), OUT (R),
-3
dB
Ratio from fm = 1kHz level.
STEREO S/N ratio
SNS
S = VOST, N = 0% Mod
50
60
dB
Measure OUT (L), OUT (R)
With 15kHz LPF, JIS-A
STEREO separation 1
STEREO separation 2
STEREO Detection level-1
STEREO Detection level-2
STSE1
STSE2
VINSD1
VINSD2
f = 300Hz (R/L), 30% Mod
20
20
52
62
25
25
57
67
dB
dB
%
Measure ratio OUT (L) with OUT (R)
f = 3kHz (R/L), 30% Mod
Measure ratio OUT (L) with OUT (R)
Except Stereo Detection Æ Stereo Detection
Measure PILOT level, at STERO det.
Except Stereo Detection Æ Stereo Detection
* Insert Resistor pin 14 to GND (ex. 51kΩ)
Measure PILOT level, at STERO det.
62
72
%
Continued on next page.
No.A0015-2/16
LA72700V
Continued from preceding page.
Parameter
Ratings
typ
Symbol
HYST
Conditions
Unit
%
min
10
max
25
STEREO detection hysteresis
Input Mod. Difference at Stereo /Except Stereo Det.
* at default condition
15
SAP output level-1
SAP output level-2
VOSA
Fm = 1kHz, 100% Mod, SAP
Measure OUT (L), OUT
* at bit6 = 0
-7.5
-5.5
-6.5
-4.5
-5.5
-3.5
3.5
dBV
dBV
VOSA2
Fm = 1kHz, 100% Mod, SAP
Measure OUT (L), OUT
* at bit6 = 1
SAP distortion
SAP S/N ratio
THDSA
SNSA
Fm = 1kHz, 100% Mod, SAP
Measure OUT (L), OUT
S = VOSA, N = 0% Mod,
Measure OUT (L), OUT (R)
With 15kHz LPF, JIS-A
Measure SAP carrier level,
when SAP det
1.5
65
%
55
13
dB
SAP detection level-1
VINSA1
VINSA2
VINSA3
18
(10)
(25)
23
(15)
(30)
%
%
%
* Default condition
SAP detection level-2
(Reference)
Measure SAP carrier level,
when SAP det
(5)
* pin15 to GND (ex 33kΩ)
Measure SAP carrier level,
when SAP det
SAP detection level-3
(Reference)
(20)
* pin15 to GND (ex 8.2kΩ)
Input Mod. Difference at SAP/Except SAP Det.
* at default condition
SAP detection hysteresis
MODE output MONO
MODE output SAP
HYSA
2
0.7
1.7
2.7
3.5
5
1
10
1.3
2.3
3.3
4.2
%
V
V
V
V
MODMO
MODSA
MODST
MODSS
Input = MONO: f = 1kHz, 0% Mod
Measure pin32
Input = SAP: Carrier
2
Measure pin32
MODE output STEREO
MODE output ST + SAP
Input = STEREO: Pilot
Measure pin32
3
Input = STEREO: Pilot,
SAP: Carrier
3.8
Measure pin32
Distortion
THDALC
MONO 1kHz Mod 100%
* ALC on Measure OUT (L), OUT (R)
0.3
0.5
%
* Normally measurement condition is Input = SIF mode (-90dBµV), ALC = OFF
* " Reference " Items are reference levels, their specs are no-guarantee.
Package Dimensions
unit : mm
3247B
No.A0015-3/16
LA72700V
Block Diagram and Application Circuit Example
No.A0015-4/16
LA72700V
00p-1 ( Normally use : group-1 only )
D8
D7
D6
D5
D4
D3
D2
D1
Condition
*
0
0
Stereo
SAP
0
1
1
1
0
1
Both
Prohibit
*
*
*
*
*
*
0
Normal (Auto det)
Forced Mono
Normal (MUTE off)
MUTE
1
0
1
0
ALC off (Through)
ALC on
1
0
SAP LEVEL-1
SAP LEVEL-2
SIF mode
1
0
1
Base Band mode
Fix
0
1
Prohibit (TEST MODE)
*: Initial condition
Read out data
D8
D7
D6
D5
D4
D3
D2
D1
Condition
0
0
0
0
0
0
Fixed
Normal
0
1
SAP det
Normal
0
1
Stereo det
Test mode condition
When STOP condition transform at Grp-1 data-end, controlled NORMAL mode.
Grp-2(Only test condition: Normally, this data is no-need)
D8
D7
D6
D5
D4
D3
D2
D1
Condition/Monitor position
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Normal (Usually, Fixed)
TEST-1 SIF output
TEST-2 SAP BPF
TEST-3 SAP VCO
TEST-4 ST VCO
TEST-5 ADJ VCO
TEST-6 dbx input
TEST-7 L-R Demod output
TEST-8 Pilot cancel
TEST-9 dbx 2.19k LPF
TEST-10 dbx 408 LPF
TEST-11 dbx DET 10k LPF
TEST-12 dbx SPEC 7.6k LPF
TEST-13 dbx SPEC output
TEST-14 (No operation)
TEST-15 (No operation)
No.A0015-5/16
LA72700V
Pin Functions
DC voltage
AC level
No.
1
Pin function
PC_DC_IN
Input/output form
Reference
DC: 3.8V
AC coupling (Input)
AC: 2.4Vp-p
2
PC_DCOUT
DC: 3.8V
AC coupling (Output)
AC: 2.4Vp-p
3
PCSTFILT
DC: 3.8V
Stereo VCO PLL filter
4
PCPLDET
DC: 3.8V
Pilot level detect
5
PISIF
DC: 3.7V
Signal input
Continued on next page.
No.A0015-6/16
LA72700V
Continued from preceding page.
DC voltage
AC level
No.
6
Pin function
Input/output form
Reference
GND
CSAPDET
DC: 2.8V
SAP carrier level detect
8
9
NC
No connect
PC FIL
DC: 2.9V
SIF offset cancel
10
MUTE
DC: 0V
MUTE = 5V
11
SDA
Serial data input
12
SCL
Serial clock input
Continued on next page.
No.A0015-7/16
LA72700V
Continued from preceding page.
DC voltage
AC level
No.
13
Pin function
PC DBXIN
Input/output form
Reference
DC: 2.5V
Offset cancel filter
14
PSTSENS
DC: 3.1V
Stereo det sensitivity change
OPEN = default
Insert resistor(30k or over) = Low sensitivity
15
PSAPSENS
DC: 3.1V
SAP detect sensitivity control
OPEN = default
controlled by insert resistor
* see electrical reference
16
PCTNWID
DC: 4.0V
dbx RMS detect(wide band)
17
PCDETWID
DC: 3.8V
dbx wide detect
Continued on next page.
No.A0015-8/16
LA72700V
Continued from preceding page.
DC voltage
AC level
No.
18
Pin function
PCTIMSPE
Input/output form
Reference
DC: 3.8V
dbx spectral detect
18
5kΩ
OMP05019
19
PCDETSPE
DC: 3.8V
dbx RMS detect (Spectral band)
20
PCSPECIN
DC: 3.8V
dbx main signal V/I convert filter
21
PCDOSPE
DC: 3.8V
Offset cancel filter
AC: 220mVp-p
22
PCDBXOUT
DC: 3.8V
AC coupling (Output)
AC: 220mVp-p
23
PCDBX_IN
AC coupling (Input)
Continued on next page.
No.A0015-9/16
LA72700V
Continued from preceding page.
DC voltage
AC level
No.
24
Pin function
PCALCFIL
Input/output form
Reference
DC: 0.6V
ALC filter
* When ALC function no-use, this terminal is open.
25
26
27
PORCH
POLCH
PCREG
DC: 3.8V
Line out R
AC: 1.4mVp-p
DC: 3.8V
Line out L
AC: 1.4mVp-p
DC: 3.8V
Reference Voltage
Continued on next page.
No.A0015-10/16
LA72700V
Continued from preceding page.
DC voltage
AC level
No.
28
Pin function
PMAIN_IN
Input/output form
Reference
DC: 3.5V
AC coupling (Input)
AC coupling (Output)
Regulator
AC: 220mVp-p
29
PMAINOUT
DC: 3.8V
AC: 220mVp-p
30
PCREG76
DC: 1.2V
31
32
V
CC
POLED
DC*
Mode out
* See Mode
table
MONO = 0.9V
SAP = 2.0V
STEREO = 3.0V
STEREO+SAP = 3.8V
33
PICLKFSC
DC: 0V
Fsc input
AC*
3.579545MHz, 200mVp-p
* 200mVp-p
Recommend
Continued on next page.
No.A0015-11/16
LA72700V
Continued from preceding page.
DC voltage
AC level
No.
34
Pin function
PCDJFIL
Input/output form
Reference
Filter adjustment signal detect
DC: 2.5V
35
PCPLC
DC: 6.3V
Pilot canceller reference-1
36
PCPLC2
DC: 6.3V
Pilot canceller reference-2
No.A0015-12/16
LA72700V
Serial Control (I2C)
(1) Data Transfer Manual
This LSI adopts control method (I2C -BUS) with serial data, and controlled by two terminals which called SCL (serial
clock) and SDA (serial data). At first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to
SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit),
and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this LSI pull down
the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition,
thus the transfer comes to close.
*1 Defined by SCL rise down SDA during ‘H’ period.
*2 Defined by SCL rise up SDA during ‘H’ period.
(2) Transfer Data Format
After transfer start condition, transfers slave address (1000000*) to SDA terminal, control data, then, stop condition
(See figure 1).
Slave address is made up of 7bits, *3 8th bit shows the direction of transferring data, if it is “L”, takes write mode (As
this LSI side, this is input operation mode), and in case of ‘H’, reading mode (As this LSI side, this is output operation
mode).
Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled
the transfer dates.
*3 It is called R/W bit.
Fig.1 DATA STRUCTURE " WRITE " mode
R/W
START Condition
Slave Address
ACK
ACK
Control data
ACK
ACK
STOP condition
STOP condition
L
Fig.2 DATA STRUCTURE " READ " mode
R/W
START condition
Slave Address
Internal Data*
H
* Output 5bits data as follows;
bit8 is result of STERO DET (H: STEREO)
bit7 is result of SAP DET (H: SAP)
bit6 to bit1 are fixed to “L”
No.A0015-13/16
LA72700V
(3) Initialize
This LSI is initialized for circuit protection. Initial condition is “0 (all bits)”.
Parameter
Symbol
Min
-0.5
3.0
Max
1.5
Unit
V
LOW level input voltage
HIGH level input voltage
LOW level output current
SCL clock frequency
V
IL
VI
IH
5.5
V
I
3.0
mA
kHz
µs
OL
f
0
100
SCL
Set-up time for a repeated START condition
t
4.7
SU: STA
Hold time START condition. After this period, the first clock pulse is
generated
t
4.0
µs
HD: STA
LOW period of the SCL clock
Rise time of both SDA and SDL signals
HIGH period of the SCL clock
Fall time of both SDA and SDL signals
Data hold time
t
4.7
0
µs
µs
µs
µs
µs
ns
µs
µs
LOW
t
1.0
1.0
R
t
4.0
0
HIGH
t
F
t
0
HD: DAT
Data set-up time
t
250
4.0
4.7
SU: DAT
t
SU: STO
Set-up time for STOP condition
BUS free time between a STOP and START condition
t
BUF
Timing Chart
No.A0015-14/16
LA72700V
Measurement Circuit
No.A0015-15/16
LA72700V
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
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In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
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reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
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This catalog provides information as of October, 2005. Specifications and information herein are subject
to change without notice.
PS No.8340-16/16
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