LA72702NV [SANYO]
Monolithic Linear IC For US TV BTSC Decoder; 单片线性IC对于美国电视BTSC解码器
| 型号： | LA72702NV |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Monolithic Linear IC For US TV BTSC Decoder |
| 文件： | 总10页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENA0979
Monolithic Linear IC
For US TV
LA72702NV
BTSC Decoder
Overview
The LA72702NV is a US TV BTSC Decoder.
Features
• With SIF circuit, alignment-free* STEREO channel separation.
* When base band signal input, separation is adjusted by input level.
• Dual slave address(80h, 84h).
Functions
• SIF FM-Demodulator • STEREO detection
• SAP detection
• STEREO decoder
• dbx Noise Reduction • SAP demodulator
• STEREO detection sensitivity change function • SAP output select 2-levels
• SAP detection sensitivity change function
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
V
Maximum power supply voltage
Allowable power dissipation
Operating temperature
Storage temperature
V
H max
7.0
290
CC
Pd max
Ta≤85°C, Mounted on a specified board*
mW
°C
Topr
Tstg
-20 to +85
-55 to +150
°C
* Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy board
Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Recommended operating voltage
Allowable operating voltage range
vacate
5.0
V
V
V
H op
CC
4.5 to 5.5
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
N2807 TI IM 20070112-S00005 No.A0979-1/10
LA72702NV
Electrical Characteristics at Ta = 25°C, V
= 5.0V
DD
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
30
(80)
max
50
Current dissipation
I
No signal Inflow current at pin 19, default condition
40
mA
CC
SIF input level (Reference)
V LIM
I
fc = 4.5MHz
(90)
(100)
dBμV
Deviation
MONO (300Hz, Mod = 100%, Pre-emphasis ON)
Æ ±25kHz
Base band input level (Reference)
V LIMB
I
100% Modulation
MONO(L+R) : 530mVp-p (300Hz, Pre-emphasis ON)
SUB(L-R)
SAP
: 380mVp-p (300Hz, dbx-NR ON), Pilot : 110mVp-p
: 300mVp-p (300Hz, dbx-NR ON)
MONO output level
V
MON
fm=1kHz, 100% Mod, 15kHz LPF
fm=1kHz, 100% Mod, 15kHz LPF
-7.0
-5.5
0.15
0
-4.5
0.6
2
dBV
%
O
MONO distortion
THDMON
FCM1
MONO frequency characteristics
fm=3kHz, 30% Mod, Pre-emphasis ON
* Measure ratio from fm=1kHz level.
-2
dB
MONO S/N ratio
SNM
S=V MON, N=0% Mod, 15kHz LPF
O
55
65
-5.5
0.5
0
dB
dBV
%
STEREO output level
STEREO distortion
V
ST
fm=1kHz, 100% Mod, 15kHz LPF
fm=1kHz, 100% Mod, 15kHz LPF
-7.0
-4.5
1.0
2
O
THDS
FCS1
STEREO frequency characteristics
fm=3kHz, 30% Mod, 15kHz LPF
-2
dB
* Measure ratio from fm=1kHz level.
STEREO S/N ratio
SNS
S=V ST, N=0% Mod, 15kHz LPF
O
50
20
20
30
60
25
25
38
dB
dB
dB
%
STEREO separation 1
STEREO separation 2
STEREO Detection level-1
STSE1
STSE2
f=300Hz (R/L), 30% Mod, 15kHz LPF
f=3kHz (R/L), 30% Mod, 15kHz LPF
V
SD1
Except Stereo Detection Æ Stereo Detection
* Serial control “SENS HI” Pilot (fH)=15.73kHz
* Measure pilot level.
45
IN
STEREO Detection level-2
STEREO Detection hysteresis
SAP output level-1
V
SD2
Except Stereo Detection Æ Stereo Detection
* Serial control “SENS LO”
38
10
47
20
53
30
%
%
IN
HYST
Input Mod. Difference at Stereo/Except Stereo Det.
* Serial control “SENS HI”
V
SA1
fm=1kHz, 100% Mod, 15kHz LPF
* SAP-1 (serial control)
-14.0
-7.5
-11.0
-5.5
-8.0
-3.5
1.5
dBV
dBV
O
O
SAP output level-2
V
SA2
fm=1kHz, 100% Mod, 15kHz LPF
* SAP-2 (serial control)
SAP distortion
THDSA
SNSA
fm=1kHz, 100% Mod, 15kHz LPF
0.7
60
17
%
dB
%
SAP S/N ratio
S=V SA2, N=0% Mod, 15kHz LPF
O
50
10
SAP detection level-1
V
SA1
Except SAP → SAP Det.
24
31
10
IN
* Serial control “SENS HI” SAP Carrier=5fH only
* Measure output level.
SAP detection level-2
V
SA2
Except SAP → SAP Det.
17
2
24
5
%
%
IN
* Serial control “SENS LO”
* Measure output level.
SAP detection hysteresis
HYSA
Input Mod. Difference at SAP/Except SAP Det.
* SAP carrier only.
* Serial control “SENS HI”
MODE output MONO
MODMO
MODSA
MODST
MODSS
STDT
Input=MONO : f=1kHz, 0% Mod
0.7
1.6
2.5
3.5
1
1.9
1.3
2.2
V
V
MODE output SAP
Input=SAP : Carrier
MODE output STEREO
MODE output ST + SAP
Stereo detect speed (Reference )
Input=STEREO : Pilot
2.8
3.1
V
Input=STEREO : Pilot, SAP : Carrier
3.8
4.2
V
Input=STEREO : Pilot
(480)
(1000)
ms
I2C data no-send
Measure pin 20 voltage change to 2.8V timing from
Power ON
SAP detect speed (Reference )
SAPDT
SAP : Carrier
I2C data no-send
(350)
(1000)
ms
Measure pin 20 voltage change to 1.9V timing from
Power ON
* Normally measurement condition is Input = SIF mode (90dBμV)
* " Reference " Items are reference levels, their specs are no-guarantee.
No.A0979-2/10
LA72702NV
Package Dimensions
unit : mm (typ)
3175C
7.8
24
13
12
1
0.65
0.15
(0.33)
0.22
SANYO : SSOP24(275mil)
Mode Condition
I2C data in
Output mode
I2C out
D8 D7 Mode pin20
1 1 3.8V
Signal
D8
D7
(0)
D6
∗
0
1
0
1
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
0
1
0
1
∗
∗
∗
∗
∗
D5
(0)
D4
(0)
D3
0
0
0
0
0
1
1
1
∗
D2
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
0
1
1
1
0
0
1
1
D1
0
1
1
0
0
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
0
1
0
1
0
1
Lch pin18
L
Rch pin17
R
Mode condition
Stereo
+ SAP
(0)
Stereo
SAP-1
FIX
SIF
STEREO
SENS
Lo
SAP
SENS
Lo
SAP
SAP
(1)
SAP
L+R
L+R
L+R
L+R
L+R
Off
SAP
SAP
SAP
L+R
L+R
L+R
Off
SAP-2
BASE
band
MULTI-1
MULTI-2
F-MONO
F-MONO
F-MONO
MUTE
(1)
(1)
Hi
Hi
Stereo
0
0
0
1
1
1
∗
L
R
Stereo
1
0
2.8V
L
R
Stereo
L
R
Stereo
L+R
L+R
L+R
Off
L+R
L+R
L+R
Off
F-MONO
F-MONO
F-MONO
MUTE
Mono
∗
L+R
SAP
SAP
L+R
L+R
Off
L+R
SAP
SAP
SAP
SAP
Off
MONO
SAP-1
0
1
1.9V
+ SAP
0
0
0
0
∗
SAP-2
MULTI-1
MULTI-2
MUTE
MONO
∗
L+R
L+R
L+R
Off
L+R
L+R
L+R
Off
MONO
MONO
MONO
MUTE
0
0
1.0V
∗
∗
∗
* : no care
No.A0979-3/10
LA72702NV
I2C Control Table
Grp-1 (Normally use : group-1 only)
D8
D7
D6
D5
D4
D3
D2
D1
Condition
*
0
0
1
1
0
1
0
1
Stereo
SAP
Both
MUTE
*
*
*
*
*
*
0
1
Normal (Auto DET)
Forced Mono
SAP SENS LO
SAP SENS HI
Stereo SENS LO
Stereo SENS HI
SAP Level-1
SAP Level-2
SIF mode
0
1
0
1
0
1
0
1
Base Band mode
Fix
0
1
Prohibit (TEST MODE)
* : Shows Initial condition
Read out data
D8
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
Condition
Fixed
Normal
0
1
SAP det
Normal
0
1
Stereo det
Test mode condition(Reference)
When STOP condition transform at Grp-1 data-end, controlled NORMAL mode.
Grp-2 is only test condition. Usually, these data are no-need. Their data are no guarantee, except all L condition.
D8
D7
D6
D5
D4
D3
D2
D1
Condition/Monitor position
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Normal (Usually, Fixed)
TEST-1 SIF output
TEST-2 SAP BPF
TEST-3 (reserved)
TEST-4 ST VCO
TEST-5 (reserved)
TEST-6 SAP monitor
TEST-7 ST monitor
TEST-8 Pilot cancel monitor
TEST-9 dbx 2.19k LPF
TEST-10 dbx 408 LPF
TEST-11 dbx DET 10k LPF
TEST-12 dbx SPEC 7.6k LPF
TEST-13 dbx SPEC output
TEST-14 L+R/lL-R monitor
TEST-15 dbx 2.09k LPF
Blank Bits are no-care
Slave addresses are 80h (1000 000*, at pin8 Open/GND) and 84h (1000 010*, at pin8 H).
No.A0979-4/10
LA72702NV
Block Diagram and Application
S p e c t r a l R M S D E T
S p e c t r a l D E T
d e W R i M S D E T
S p e c t r a l I n
O f f s e t C a n c e l
No.A0979-5/10
LA72702NV
Pin Functions
DC: voltage
AC: level
DC : 2.4V
Pin No.
1
Pin Name
PCPLDET
Function
Equivalent Circuit
Pilot level detect for stero detection
40kΩ
1
40kΩ
1kΩ
160kΩ
2
3
4
PC_DC_IN
PC_DCOUT
PC FIL
AC coupling (Input)
AC coupling (Output)
SIF offset cancel
DC : 2.4V
AC : 2.4Vp-p
3
2
DC : 2.4V
500Ω
1kΩ
AC : 2.4Vp-p
DC : 2.6V
1kΩ
1kΩ
4
5
PISIF
Signal input
DC : 3.7V
Common input at SIF, Base band
5
10kΩ
500Ω
1kΩ
6
7
GND
CSAPDET
SAP carrier level detect for SAP detection
DC : 2.8V
70kΩ
1kΩ
1kΩ
2kΩ
1kΩ
7
8
ADDSEL
Slave address change control
OPEN/GND : 80h
DC : 0V
8
5V
: 84h
1kΩ
100kΩ
Continued on next page.
No.A0979-6/10
LA72702NV
Continued from preceding page.
DC: voltage
AC: level
5V
Pin No.
9
Pin Name
SDA
Function
Equivalent Circuit
Serial data input
9
1kΩ
0V
5V
10
11
SCL
Serial clock input
10
1kΩ
0V
PC DBXIN
Offset cancel feedback filter
DC: 2.4V
11
5kΩ
12
PCDETSPE
Spectral band RMS detect
DC: 2.3V
1kΩ
200Ω
12
13
PCTIMSPE
dbx spectral detect
DC: 2.4V
13
5kΩ
14
PCTNWID
Wide band RMS detect
DC: 2.4V
1kΩ
200Ω
14
15
PCSPECIN
dbx main signal V/I convert filter
DC: 2.4V
15
10kΩ
16
PC KE6B
Offset cancel feedback filter
DC: 2.4V
AC: 220mVp-p
250Ω
16
500Ω
500Ω
Continued on next page.
No.A0979-7/10
LA72702NV
Continued from preceding page.
DC: voltage
AC: level
DC: 2.4V
Pin No.
17
Pin Name
PORCH
Function
Equivalent Circuit
Line out R
AC: 1.4Vp-p
50kΩ
17
300Ω
50kΩ
300Ω
18
POLCH
Line out L
DC: 2.4V
AC: 1.4Vp-p
50kΩ
300Ω
18
300Ω
50kΩ
19
20
V
CC
POLED
Mode out
MONO
SAP
DC: See Right
AC: Test only
= 0.9V
= 2.0V
= 3.0V
STEREO
20
1kΩ
STEREO + SAP = 3.8V
21
22
23
PCREG
Reference voltage
DC: 2.4V
DC: 1.6V
DC: 2.4V
10kΩ
500Ω
9.6kΩ
21
1kΩ
PMAINOUT
Offset cancel feedback filter
450kΩ
22
500Ω
PCPLC
Pilot level detect for pilot canceller
40kΩ
40kΩ
1kΩ
160kΩ
23
Continued on next page.
No.A0979-8/10
LA72702NV
Continued from preceding page.
DC: voltage
AC: level
DC: 2.4V
Pin No.
24
Pin Name
PCPTFILT
Function
Equivalent Circuit
Pilot level detect for ST PLL filter
40kΩ
40kΩ
1kΩ
160kΩ
24
I2C BUS Serial Interface Specification
(1) Data transfer manual
This IC adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL (serial
clock) and SDA (serial data).At first, set up*1 the condition of starting data transfer, and after that, input 8 bit data to
SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit),
and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this IC pull down the
SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition,
thus the transfer comes to close.
*1 Defined by SCL rise down SDA during ‘H’ period.
*2 Defined by SCL rise up SDA during ‘H’ period.
(2) Transfer data format
After transfer start condition, transfers slave address (1000 000 ) to SDA terminal, control data, then, stop condition
*
(See figure 1).
Slave address is made up of 7bits, *38th bit shows the direction of transferring data, if it is ‘L’ takes write mode (As this
IC side, this is input operation mode), and in case of ‘H’ reading mode (As this IC side, this is output operation mode).
Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled
the transfer dates.
*3 It is called R/W bit.
Fig.1 DATA STRUCTURE “WRITE” mode
R/W
START Condition
Slave Address
ACK
Control data
ACK
STOP condition
L
Fig.2 DATA STRUCTURE “READ” mode
R/W
H
START condition
Slave Address
ACK
Internal Data *
ACK
STOP condition
∗ The output data synchronizes with the clock of SCL pin. Then, the ACK output is made after the output data.
bit8 is result of STERO DET (H : STEREO)
bit7 is result of SAP DET (H : SAP)
bit6 to bit1 are fixed to ‘L’
(3) Initialize
This IC is initialized for circuit protection. Initial condition is “0 (All bits) ”.
No.A0979-9/10
LA72702NV
Reference
Parameter
Symbol
min
max
unit
V
LOW level input voltage
V
-0.5
2.5
1.5
IL
HIGH level input voltage
LOW level output current
SCL clock frequency
V
5.5
3.0
V
mA
kHz
μs
μs
μs
μs
μs
μs
μs
ns
μs
μs
IH
I
OL
f
0
4.7
4.0
4.7
0
100
SCL
Set-up time for a repeated START condition
t
SU : STA
t
HD : STA
Hold time START condition. After this period, the first clock pulse is generated
LOW period of the SCL clock
t
LOW
Rise time of both SDA and SDL signals
HIGH period of the SCL clock
t
1.0
1.0
R
t
4.0
0
HIGH
Fall time of both SDA and SDL signals
Data hold time
t
F
t
0
HD : DAT
Data set-up time
t
250
4.0
4.7
SU : DAT
t
SU : STO
Set-up time for STOP condition
BUS free time between a STOP and START condition
t
BUF
Definition of timing
t
t
t
F
R
HIGH
SCL
SDA
t
t
t
t
t
t
t
HD:STA
SU:STA
LOW
HD:DATA
SU:DAT
SU:STO
BUF
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of November, 2007. Specifications and information herein are subject
to change without notice.
PS No.A0979-10/10
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