S6A0075_技术文档

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

June. 2000.

Ver. 0.0

Contents in this document are subject to change without notice. No part of this document may be reproduced

or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express

written permission of LCD Driver IC Team.

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

INTRODUCTION

S6A0075 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can

display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format.

FUNCTIONS

·

Character type dot matrix LCD driver & controller

Internal driver: 34 common and 100 segment signal output

Easy interface with 4-bit or 8-bit MPU

Clock synchronized serial interface

5 x 8 dot matrix / 6 x 8 dot matrix possible

Bi-directional shift function

All character reverse display

Display shift per line

Voltage converter for LCD drive voltage: 13V max. (2 times/3 times)

Various instruction functions

Automatic power on reset

FEATURES

·

Internal memory

- Character Generator ROM (CGROM): 9,600 bits (240 characters x 5 x 8 dot)

- Character Generator RAM (CGRAM): 64 x 8 bits (8 characters x 5 x 8 dot)

- Segment Icon RAM (SEGRAM): 16 x 8 bits (96 icons max.)

- Display Data RAM (DDRAM): 80 x 8 bits (80 characters max.)

Low power operation

- Power supply voltage range: 2.7 - 5.5V (VDD)

- LCD Drive voltage range: 3.0 - 13.0V (VDD - V5)

·

CMOS process

Programmable duty cycle: 1/17, 1/33

Internal oscillator with an external resistor

Bare chip available

2

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

PROGRAMMABLE DUTY CYCLES

5-dot Font Width

Single-chip Operation

Display Line

Numbers

Duty Ratio

Displayable Characters

1 line of 40 characters

2 lines of 40 characters

4 line of 20 characters

Possible Icons

1

2

4

1/17

1/33

80

6-dot Font Width

Single-chip Operation

Display Line

Numbers

Duty Ratio

Displayable Characters

1 line of 32 characters

2 lines of 32 characters

4 line of 16 characters

Possible Icons

1

2

4

1/17

1/33

96

3

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

BLOCK DIAGRAM

IE OSC1 OSC2

Oscillator

Power on Reset

(POR)

Timing Generator

RESET

IM

RS/CS

E/SCLK

RW/SID

Instruction

Register

(IR)

7

8

Instruction

Decoder

System

Interface

Serial

4-bit

8-bit

COM0-

34-bit

Shift

Common

Driver

Display Data

RAM (DDRAM)

96 x 8-bit

COM33

Register

Address

Counter

7

8

Data

Register

(DR)

8

COM1-

COM100

100-bit 100-bit

Segment

Driver

Shift

Latch

Input/

Output

Buffer

Register Circuit

DB4-DB7

DB3-DB1

DB0-SOD

8

Busy Flag

LCD Driver

Voltage Selector

3

7

8

Character

Generator

RAM

(CGRAM)

64 bytes

Character

Generator

ROM

(CGROM)

9600 bits

Segment

RAM

(SEGRAM)

16 bytes

V1 - V5

Cursor and

Blink

Vci

Controller

C1

C2

Voltage Converter

5

V5OUT2

V5OUT3

5/6

Parallel/Serial Converter and

Smooth Scroll Circuit

VDD

GND(VSS)

4

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

PAD CONFIGURATION

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

1

2

3

4

5

6

7

8

9

129 SEG33

128 SEG32

127 SEG31

126 SEG30

125 SEG29

124 SEG28

123 SEG27

122 SEG26

121 SEG25

120 SEG24

119 SEG23

118 SEG22

117 SEG21

116 SEG20

115 SEG19

114 SEG18

113 SEG17

112 SEG16

111 SEG15

110 SEG14

109 SEG13

108 SEG12

107 SEG11

106 SEG10

105 SEG9

104 SEG8

103 SEG7

102 SEG6

101 SEG5

100 SEG4

99 SEG3

98 SEG2

97 SEG1

96 COM0

95 COM1

94 COM2

93 COM3

92 COM4

91 COM5

90 COM6

89 COM7

88 COM8

87 COM17

86 COM18

85 COM19

84 COM20

83 COM21

82 COM22

81 COM23

80 COM24

SEG77 10

SEG78 11

SEG79 12

SEG80 13

SEG81 14

SEG82 15

SEG83 16

SEG84 17

SEG85 18

SEG86 19

SEG87 20

SEG88 21

SEG89 22

SEG90 23

SEG91 24

SEG92 25

SEG93 26

SEG94 27

SEG95 28

SEG96 29

SEG97 30

SEG98 31

SEG99 32

SEG100 33

COM9 34

COM10 35

COM11 36

COM12 37

COM13 38

COM14 39

COM15 40

COM16 41

COM25 42

COM26 43

COM27 44

COM28 45

COM29 46

COM30 47

COM31 48

COM32 49

COM33 50

(0, 0)

Y

X

Chip size: 7450 x 5340

´

PAD size: 100 100

Unit:

m

S6A0075

5

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

PAD CENTER COORDINATES

Table 1. Pad Location

Coordinate

Pad

No.

Pad

Name

Pad

No.

Pad

Name

Pad

No.

Pad

Name

X

Y

X

Y

X

Y

1

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

SEG92

SEG93

SEG94

SEG95

SEG96

SEG97

SEG98

SEG99

-2975

-2850

-2725

-2600

-2475

-2350

-2225

-2100

-1975

-1850

-1725

-1600

-1475

-1350

-1225

-1100

-975

-850

-725

-600

-475

-350

-225

-100

24

-2504

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

SEG100

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

VDD

1024

1262

1387

1512

1637

1762

1887

2012

2137

2262

2387

2512

2637

2762

2887

3012

3137

3262

3559

-2504

-1750

-1625

-1500

-1375

-1250

-1125

-1000

-875

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

DB4

DB5

3559

3262

3137

3012

2887

2762

2637

2512

2387

2262

2137

2012

1887

1762

1637

1512

1387

1262

0

2

125

3

DB6

250

4

DB7

375

5

VCI

500

6

C2

625

7

C1

750

8

VSS2

V5OUT2

V5OUT3

V5

875

9

1000

1125

1250

1375

1500

1625

1750

2504

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

V4

V3

V2

V1

COM24

COM23

COM22

COM21

COM20

COM19

COM18

COM17

COM8

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

OSCC

OSC1

RESET

IM

IE

VSS1

149

RS/CS

RW/SID

E/SCLK

DB0/SOD

DB1

274

-750

399

-625

524

-500

649

-375

774

DB2

-250

899

DB3

-125

Table 1. Pad Location (Continued)

6

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

Coordinate

Pad

No.

Pad

Name

Pad

No.

Pad

Name

Pad

No.

Pad

Name

X

Y

X

Y

X

Y

97

SEG1

SEG2

1024

899

2504

2062

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

-3559

1937

1812

1687

1562

1437

1312

1187

1062

937

98

99

SEG3

774

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

SEG4

649

SEG5

524

SEG6

399

SEG7

274

SEG8

149

SEG9

24

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

-100

-225

-350

-475

-600

-725

-850

-975

-1100

-1225

-1350

-1475

-1600

-1725

-1850

-1975

-2100

-2225

-2350

-2475

-2600

-2725

-2850

-2975

-3559

812

687

562

437

312

187

62

-62

-187

-312

-437

-562

-687

-812

-937

-1062

-1187

-1312

-1437

-1562

-1687

-1812

-1937

-2062

7

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

PAD DESCRIPTION

Table 2. Pad Description

Input/

Output

Pad (No)

VDD (51)

Name

Description

for logical circuit (+3V, +5V)

0V (GND)

Interface

VSS1, VSS2

(57,72)

-

Power supply

V1 - V5

(79 - 75)

Bias voltage level for LCD driving.

Input voltage to the voltage converter to

generate LCD drive voltage

(Vci = 2.5 - 4.5V).

Vci (69)

Input

SEG1 - SEG100

(97- 33)

Output

Segment output Segment signal output for LCD drive.

LCD

COM0 - COM33

(80 - 96, 34 - 50)

Common output Common signal output for LCD drive.

When use internal oscillator, connect

Input

External

resistor/oscillator

(OSC1)

OSC1, OSC2

(53, 52)

(OSC1),

Output

(OSC2)

external Rf resistor.

If external clock is used, connect it to

Oscillator

OSC1.

External

capacitance

input

To use the voltage converter (2 times /3

times), these pins must be connected to

the external capacitance.

C1, C2

(71, 70)

External

capacitance

Input

RESET (54)

IE (56)

Reset pin

Initialized to low

-

When IE = "High", Instruction set is

selected as Table 6. When IE = "Low",

Instruction set is selected as Table 10.

Select pin of

instruction set

The value of Vci is converted two times.

To use three times converter, the same

converter output capacitance as that of C1-C2 should be

connected here.

Two times

V5OUT2 (73)

V5 capacitance

Output

Input

Three times

The value of Vci is converted three

converter output times.

V5OUT3 (74)

IM (55)

V5

Select Interface mode with the MPU.

When IM = "Low": Serial mode,

When IM = "High": 4-bit/8-bit bus mode.

Interface mode

selection

-

8

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

Table 2. Pad Description (Continued)

Input/

Output

Pad (No)

Name

Description

Interface

When bus mode, used as register

selection input.

When RS/CS = "High", data register is

selected.

When RS/CS = "Low", instruction

register is selected.

When serial mode, used as chip

selection input.

Register select/

chip select

RS/CS (58)

Input

MPU

When RS/CS = "Low", selected.

When RS/CS = "High", not elected.

(low access enable)

When bus mode, used as read/write

selection input.

When RW/SID = "High", read operation.

When RW/SID = "Low", write operation.

When serial mode, used for data input

pin.

Read/Write/

RW/SID (59)

E/SCLK (60)

DB0/SOD (61)

Input

MPU

Serial input

data

When bus mode, used as read/write

enable signal.

When serial mode, used as serial clock

input pin.

Read/Write

Enable/Serial

clock

When 8-bit bus mode, used as lowest bi-

directional data bit. During 4-bit bus

mode, open this pin.

When serial mode, used as serial data

output pin. If not in read operation, open

this pin.

Data bus 0

bit/serial output

data

Input.Output/

Output

When 8-bit bus mode, used as low order

bi-directional data bus.

During 4-bit bus mode or serial mode,

open these pins.

DB1 - DB3

(62 - 64)

Data bus 1-7

MPU

Input.Output

When 8-bit bus mode, used as high

order bi-directional data bus. In case of

4-bit bus mode, used as both high and

low order. DB7 used for busy flag output.

During serial mode, open these pins.

DB4 - DB7

(65 - 68)

9

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

FUNCTION DESCRIPTION

SYSTEM INTERFACE

This chip has all three kinds interface type with MPU: serial, 4-bit bus and 8-bit bus. Serial and bus (4-bit/8-bit) is

selected by IM input, and 4-bit bus and 8-bit bus is selected by DL bit in the instruction register. During read or

write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register (IR). The

data register (DR) is used as temporary data storage place for being written into or read from

DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation,

reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the

next DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR,

the data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register (IR) is used

only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select

register, use RS/CS input pin in 4-bit/8-bit bus mode (IM = "High") or RS bit in serial mode (IM = "Low").

RS

0

R/W

Operation

0

1

0

1

Instruction write operation (MPU writes Instruction code into IR)

Read busy flag (DB7) and address counter (DB0 - DB6)

Data write operation (MPU writes data into DR)

0

1

Data read operation (MPU reads data from DR)

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

BUSY FLAG (BF)

S6A0075

When BF = "High", it indicates that the internal operation is being processed. So during this time the next

instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),

through DB7. Before executing the next instruction, be sure that BF is not high.

DISPLAY DATA RAM (DDRAM)

DDRAM stores display data of maximum 80 x 8 bits (80 characters). DDRAM address is set in the address

counter (AC) as a hexadecimal number. (refer to Figure 1.)

MSB

LSB

AC6 AC5 AC4 AC3 AC2 AC1 AC0

Figure 1. DDRAM Address

Display of 5-Dot Font Width Character

5-dot 1-line Display

In case of 1-line display with 5-dot font, the address range of DDRAM is 00H-4FH. (refer to Figure 2)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

COM1

COM8

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

SEG1

SEG100

S6A0075

Display Position

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27

COM9

COM16

SEG1

SEG100

DDRAM Address

S6A0075

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

COM1

COM8

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 1F 10 11 12 13 14

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28

COM9

COM16

(After Shift Left)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

COM1

COM8

4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 1F 10 11 12

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

COM9

COM16

13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26

(After Shift Right)

Figure 2. 1-line x 40ch. Display

11

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

5-dot 2-line Display

In case of 2-line display with 5-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 3).

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

COM1

COM8

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

COM17

COM24

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

SEG1

SEG100

S6A0075

Display Position

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27

COM9

COM16

COM25

COM32

54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67

SEG1

SEG100

DDRAM Address

S6A0075

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

COM1

COM8

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14

COM17

COM24

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 00

COM9

COM16

COM25

COM32

55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 40

(After Shift Left)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

COM1

COM8

27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12

COM17

COM24

67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

COM9

13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26

COM16

COM25

COM32

53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66

(After Shift Right)

Figure 3. 2-line x 40ch. Display (5-dot Font Width)

12

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

5-dot 4-line Display

S6A0075

In case of 4-line display with 5-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H -53H, 60H-73H

(refer to Figure 4).

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

Display Position

DDRAM Address

COM1

COM8

COM9

COM16

COM17

COM24

COM25

COM32

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73

SEG1

SEG100

S6A0075

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20

COM1

COM8

COM9

COM16

COM17

COM24

COM25

COM32

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 00

21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 20

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 40

61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 60

(After Shift Left)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20

COM1

COM8

COM9

COM16

COM17

COM24

COM25

COM32

13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12

33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32

53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52

73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72

(After Shift Right)

Figure 4. 4-line x 20ch. Display (5-dot Font Width)

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S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

DISPLAY OF 6-DOT FONT WIDTH CHARACTER

When this device is used in 6-dot font width mode, SEG97, SEG98, SEG99 and SEG100 must be open.

6-dot 1-line Display

In case of 1-line display with 6-dot font, the address range of DDRAM is 00H-4FH (refer to Figure 5).

Display Position

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

COM1

COM8

COM9

COM16

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

SEG1

SEG96 SEG1

SEG96

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DDRAM Address

S6A0075

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

COM1

COM8

COM9

COM16

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20

(After Shift Left)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

COM1

COM8

COM9

COM16

4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E

(After Shift Right)

Figure 5. 1-line ´ 32ch. Display

6-dot 2-line Display

In case of 2-line display with 6-dot font, the address range of DDRAM is 00H-27H, 40H-67H (refer to Figure 6).

Display Position

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

COM1

COM8

COM17

COM24

COM9

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F

COM16

COM25

COM32

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F

SEG1

SEG96

SEG96 SEG1

DDRAM Address

S6A0075

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

COM1

COM8

COM17

COM24

COM9

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20

COM16

COM25

COM32

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60

(After Shift Left)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

COM1

COM8

COM17

COM24

COM9

27 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E

COM16

COM25

COM32

67 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E

(After Shift Right)

Figure 6. 2-line ´ 32ch. Display (6-dot font width)

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

6-dot 4-line Display

S6A0075

In case of 4-line display with 6-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H

(refer to Figure 7).

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

Display Position

DDRAM Address

COM1

COM8

COM9

COM16

COM17

COM24

COM25

COM32

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F

SEG1

SEG96

S6A0075

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

COM1

COM8

COM9

COM16

COM17

COM24

COM25

COM32

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10

21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50

61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70

(After Shift Left)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

COM1

COM8

COM9

COM16

COM17

COM24

COM25

COM32

13 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E

33 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E

53 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E

73 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E

(After Shift Right)

Figure 7. 4-line ´ 16ch. Display (6-dot Font Width)

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S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

TIMING GENERATION CIRCUIT

Timing generation circuit generates clock signals for the internal operations.

ADDRESS COUNTER (AC)

Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading

from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W =

"High", AC can be read through DB0-DB6

CURSOR/BLINK CONTROL CIRCUIT

It controls cursor/blink ON/OFF and black/white inversion at cursor position.

LCD DRIVER CIRCUIT

LCD Driver circuit has 34 common and 100 segment signals for LCD driving. Data from

SEGRAM/CGRAM/CGROM is transferred to 100-bit segment latch serially, and then it is stored to 100-bit shift

latch. When each com is selected by 34-bit common register, segment data also output through segment driver

from 100-bit segment latch. In case of 1-line display mode, COM0-COM17 have 1/17 duty, and in 2-line or 4-line

mode, COM0-COM33 have 1/33 duty ratio.

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

CGROM (CHARACTER GENERATOR ROM)

CGROM has 5 ´ 8 dots 240 Character Pattern.

CGRAM (CHARACTER GENERATOR RAM)

CGRAM has up to 5 ´ 8 dots 8 characters. By writing font data to CGRAM, user defined character can be used

(refer to Table 4).

5 ´ 8 dots Character Pattern

Table 4. Relationship between Character Code(DDRAM) and Character Pattern(CGRAM)

Character Code (DDRAM data)

CGRAM Address

CGRAM Data

Pattern

Number

D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0

0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Pattern 1

.

0

x

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

x

1

0

1

0

1

0

1

0

1

0

Pattern 8

.

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S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

6 x 8 Dots Character Pattern

Character Code (DDRAM data)

CGRAM Address

CGRAM Data

Pattern

Number

D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0

0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Pattern 1

.

0

x

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

0

1

0

1

0

1

0

1

0

1

0

Pattern 8

.

1. When BE (Blink Enable bit) = "High", blink is controlled by B1 and B0 bit.

In case of 5-dot font width, when B1 = "1", enabled dots of P0-P4 will blink, and when B1 = "0" and B0 = "1", enabled

dots in P4 will blink, when B1 = "0" and B0 = "0", blink will not happen.

In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and when B1 = "0" and B0 = "1", enabled

dots of P5 will blink, when B1 = "0" and B0 = "0", blink will not happen.

2

"X": Don't care

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

SEGRAM (SEGMENT ICON RAM)

S6A0075

SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0 (COM17)

makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0 (COM33) does

that. Its higher 2-bit are blinking control data, and lower 6-bits are pattern data (refer to Table 5 and Figure 8).

Table 5. Relationship between SEGRAM Address and Display Pattern

SEGRAM Data Display Pattern

SEGRAM Address

5-dot Font Width

6-dot Font Width

A3 A2 A1 A0 D7 D6 D5 D4

D3

S2

S7

D2

D1 D0 D7

S4 S5 B1

S9 S10 B1

D6

B0

D5

S1

S7

D4

S2

S8

D3

S3

D2

S4

D1

S5

D0

S6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

X

S1

S6

S3

S8

S9 S10 S11 S12

S11 S12 S13 S14 S15 B1

S16 S17 S18 S19 S20 B1

S21 S22 S23 S24 S25 B1

S26 S27 S28 S29 S30 B1

S31 S32 S33 S34 S35 B1

S36 S37 S38 S39 S40 B1

S41 S42 S43 S44 S45 B1

S46 S47 S48 S49 S50 B1

S51 S52 S53 S54 S55 B1

S56 S57 S58 S59 S60 B1

S61 S62 S63 S64 S65 B1

S66 S67 S68 S69 S70 B1

S71 S72 S73 S74 S75 B1

S76 S77 S78 S79 S80 B1

B0 S13 S14 S15 S16 S17 S18

B0 S19 S20 S21 S22 S23 S24

B0 S25 S26 S27 S28 S29 S30

B0 S31 S32 S33 S34 S35 S36

B0 S37 S38 S39 S40 S41 S42

B0 S43 S44 S45 S46 S47 S48

B0 S49 S50 S51 S52 S53 S54

B0 S55 S56 S57 S58 S59 S60

B0 S61 S62 S63 S64 S65 S66

B0 S67 S68 S69 S70 S71 S72

B0 S73 S74 S75 S76 S77 S78

B0 S79 S80 S81 S82 S83 S84

B0 S85 S86 S87 S88 S89 S90

B0 S91 S92 S93 S94 S95 S96

1. B1, B0: Blinking control bit

Control Bit

BE B1 B0

0 X X

Blinking Port

5-dot font width

No blink

D4

6-dot font width

No blink

D5

1 0 0

1 0 1

1 1 X

D4 - D0

D5 - D0

1. S1-S80 : Icon pattern ON/OFF in 5-dot font width

S1-S96 : Icon pattern ON/OFF in 6-dot font width

2. "X": Don't care.

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S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

5-Dot Font Width (FW = 0)

S76 S77 S78 S79 S80

S81 S82 S83 S84 S85

S96 S97 S98 S99 S100

S1 S2 S3 S4 S5

S6 S7 S8 S9 S10

. . .

6-Dot Font Width (FW = 1)

S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96

S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12

. . .

Figure 8. Relationship between SEGRAM and Segment Display

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

INSTRUCTION DESCRIPTION

OUTLINE

To overcome the speed difference between internal clock of S6A0075 and MPU clock, S6A0075 performs

internal operation by storing control information to IR or DR. The internal operation is determined according to the

signal from MPU, composed of read/write and data bus. (refer to Table 6/10) Instruction can be divided largely

four kinds,

·

S6A0075 function set instructions (set display methods, set data length, etc.)

Address set instructions to internal RAM

Data transfer instructions with internal RAM

Others .

The address of internal RAM is automatically increased or decreased by 1.

When IE = "High", S6A0075 is operated according to instruction set 1 (Table 6) and when IE = "Low", S6A0075 is

operated according to instruction set 2 (Table 10).

NOTE: During internal operation, busy flag (DB7) is read high. Busy flag check must precede the next instruction. When an

MPU program with Busy Flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction by

the falling edge of the “E” signal after the Busy Flag (DB7) goes to “Low”.

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S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

INSTRUCTION DESCRIPTION 1 (IE = "HIGH")

Table 6. Instruction Set 1

Instruction Code

Executi

on Time

(fosc =

Instruction RE

Description

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270kHz)

Write "20H" to DDRAM. and

set DDRAM address to "00H"

from AC.

Clear

X

0

1

x

1.53ms

display

Set DDRAM address to "00H"

from AC and return cursor to its

original position if shifted. The

contents of DDRAM are not

changed.

Return

0

home

Set power down mode bit.

PD = "1":power down mode set,

PD = "0":power down mode

disable

Power

down

mode

1

0

1

PD

39ms

Assign cursor moving direction.

I/D = "1": increment,

I/D = "0": decrement and

display shift enable

bit.

0

1

I/D

S

S = "1": make display shift of

the enabled lines by

the DS4

Entry

mode set

39ms

DS1 bits in the shift enable

instruction.

S = "0": display shift disable

Segment bi-direction function.

BID = "0": Seg1 ® Seg80,

BID = "1": Seg80 ® Seg1.

1

0

1

B/D

Set display/cursor/blink on/off

D = "1": display on,

D = "0": display off,

C = "1": cursor on,

C = "0": cursor off,

B = "1": blink on,

Display

ON/OFF

Control

D

C

B

39ms

B = "0": blink off.

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

Table 6. Instruction Set 1 (Continued)

Instruction Code

Executi

on Time

(fosc =

Instruction RE

Description

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270kHz)

Assign font width, black/white

inverting of cursor, and 4-line

display mode control bit.

FW = "1": 6-dot font width,

FW = "0": 5-dot font width,

B/W = "1": black/white inverting of

cursor enable,

Extended

function

set

1

0

1

FW B/W NW

39ms

B/W = "0": black/white inverting of

cursor disable

NW = "1": 4-line display mode,

NW = "0": 1-line or 2-line display

mode.

Cursor or display shift.

S/C = "1": display shift,

S/C = "0": cursor shift,

R/L = "1": shift to right,

R/L = "0": shift to left.

Cursor or

Display

Shift

0

1

S/C R/L

x

39ms

(when DH = "1")

Determine the line for display shift.

DS1 = "1/0": 1st line display shift

enable/disable

DS2 = "1/0": 2nd line display shift

enable/disable

Shift

Enable

1

0

1

DS4 DS3 DS2 DS1

DS3 = "1/0": 3rd line display shift

enable/disable

DS4 = "1/0": 4th line display shift

enable/disable.

(when DH = "0")

Determine the line for horizontal

smooth scroll.

HS1 = "1/0": 1st line dot scroll

enable/disable

HS4 HS3 HS2 HS1 HS2 = "1/0": 2nd line dot scroll

enable/disable

Scroll

enable

1

0

1

39ms

HS3 = "1/0": 3rd line dot scroll

enable/disable

HS4 = "1/0": 4th line dot scroll

enable/disable.

23

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Table 6. Instruction Set 1 (Continued)

Instruction Code

Executio

n Time

(fosc =

Instruction RE

Description

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270kHz)

Set interface data length

(DL = "1": 8-bit, DL = "0": 4-bit),

numbers of display line when

NW = "0", (N = "1": 2-line, N = "0" :

1-line), extension register, RE("0"),

shift/scroll enable

DH = "1": display shift enable

DH = "0": dot scroll enable. reverse

bit REV = "1": reverse display,

REV = "0": normal display.

RE

(0)

0

1

DL

N

DH

39ms

REV

Function

set

Set DL, N, RE("1") and

CGRAM/SEGRAM blink enable

BE)

BE = " 1/0": CGRAM/SEGRAM

blink enable/disable

RE

(1)

1

0

1

DL

N

BE

0

Set

CGRAM

address

Set CGRAM address in address

counter.

0

1

0

1

AC5 AC4 AC3 AC2 AC1 AC0

39ms

Set

SEGRAM

address

Set SEGRAM address in address

counter.

X

AC3 AC2 AC1 AC0

Set

DDRAM

address

Set DDRAM address in address

counter.

0

1

0

1

AC6 AC5 AC4 AC3 AC2 AC1 AC0

39ms

Set scroll

quantity

QC QC QC QC QC QC Set the quantity of horizontal dot

X

5

4

3

2

1

0

scroll.

Can be known whether during

internal operation or not by

reading BF. The contents of

address counter can also be read.

BF = "1": busy state

Read busy

flag and

address

X

0

1

BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

0ms

BF = "0": ready state

Write data into internal RAM

(DDRAM / CGRAM / SEGRAM).

Write data

X

1

0

1

D7 D6 D5 D4 D3 D2 D1 D0

43ms

Read data from internal RAM

(DDRAM / CGRAM / SEGRAM).

Read data

NOTES:

1. When an MPU program with busy flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next instruction

by the "E" signal after the busy flag (DB7) goes to "Low"

2. "X": Don’t care

24

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Display Clear

S6A0075

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

0

DB0

1

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"

into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first

line of the display. Make entry mode increment (I/D = "1").

Return Home: (RE = 0)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

1

DB0

X

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return

cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.

Power Down Mode Set: (RE = 1)

RS

1

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

1

DB0

PD

Power down mode enable bit set instruction. When PD = "High", it makes S6A0075 suppress current

consumption except the current needed for data storage by executing next three functions.

·

Make the output value of all the COM/SEG ports VDD

Make the COM/SEG output value of extension driver VDD by setting D output to "High" and M output to

"Low"

·

Disable voltage converter to remove the current through the divide resistor of power supply.

You can use this instruction as power sleep mode.

When PD = "Low", power down mode becomes disabled.

25

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Entry Mode Set

(RE = 0)

RS

0

R/W

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

1

DB1

I/D

DB0

S

0

Set the moving direction of cursor and display.

I/D: Increment/decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.

When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.

- CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM.

When S = "High", after DDRAM write, the display of enabled line by DS1 - DS4 bits in the shift enable instruction

is shifted to the right (I/D = "0") or to the left (I/D = "1"). But it will seem as if the cursor does not move. When S =

"Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of display like this function is not

performed.

(RE = 1)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

1

DB1

1

DB0

BID

Set the data shift direction of segment in the application set.

BID: Data shift direction of segment

When BID = "Low", segment data shift direction is set to normal order from SEG1 to SEG100.

When BID = "High", segment data shift direction is set to reverse from SEG100 to SEG1.

By using this instruction, you can raise the efficiency of application board area.

- The BID setting instruction is recommended to be set at the same time level of function set instruction.

- DB1 bit must be set to "1".

26

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Display ON / OFF Control (RE = 0)

S6A0075

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

1

DB2

D

DB1

C

DB0

B

Control display/cursor/blink ON/OFF 1 bit register.

D:

C:

B:

Display ON/OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

Cursor ON/OFF control bit

When C = "High", cursor is turned on.

When C = "Low", cursor is disappeared in current display, but I/D register remains its data.

Cursor Blink ON/OFF control bit

When B = "High", cursor blink is on, that performs alternate between all the high data and display

character at the cursor position. If fosc has 270kHz frequency, blinking has 370 ms interval.

When B = "Low", blink is off.

Extended Function Set (RE = 1)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

1

DB2

FW

DB1

B/W

DB0

NW

FW:

Font Width control

When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5

times than that of 5-dot font width.

The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost

space bit of CGRAM.(refer to Figure 9)

When FW = "Low", 5-dot font width is set.

B/W: Black/White Inversion enable bit

When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display

ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion

has 370 ms intervals.

NW:

4 Line mode enable bit

When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't

care condition.

6-bit

S

p

a

c

CGROM

Characte

Font

CGRAM

Characte

Font

8-bit

(5-dot)

(6-dot)

e

CGROM

CGRAM

Figure 9. 6-dot Font Width CGROM/CGRAM

27

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Cursor or Display Shift (RE = 0)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

S/C

DB2

R/L

DB1

X

DB0

X

Shift right/left cursor position or display, without writing or reading of display data, this instruction is use to correct

or search display data (refer to Table 7). During 2-line mode display, cursor moves to the 2nd line after 40th digit

of 1st line. When 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. Note

that display shift is performed simultaneously in all the line enabled by DS1-DS4 in the shift enable instruction.

When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the

contents of address counter are not changed. During low power consumption mode, display shift may not be

performed normally.

Table 7. Shift Patterns According to S/C and R/L Bits

S/C

0

R/L

0

Operation

Shift cursor to the left, address counter is decreased by 1

Shift cursor to the right, address counter is increased by 1

Shift all the display to the left, cursor moves according to the display

Shift all the display to the right, cursor moves according to the display

0

1

0

1

28

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

Shift/Scroll Enable (RE = 1)

(DH = 0)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

HS4

DB2

HS3

DB1

HS2

DB0

HS1

HS:

Horizontal scroll per line enable

This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to

be dot scrolled, and each scroll is performed individually in each line.

If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and

HS2 to "High".

If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8)

(DH = 1)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

DS4

DB2

DS3

DB1

DS2

DB0

DS1

DS:

Display shift per line enable this instruction selects shifting line to be shifted according to each line

mode in display shift right/left instruction. DS1, DS2, DS3 and DS4 indicate each line to be shifted, and

each shift is performed individually in each line.

If you set DS1 and DS2 to "High" (enable) in 2 line mode, only the 1st line is shifted and the 2nd line is

not shifted. When only DS1 = "High", only the half of the 1st line is shifted. If all the DS bits (DS1 to DS4)

are set to "Low" (disable), no display is shifted.

Table 8. Relationship between DS and COM signal

Enable Bit

Enabled Common Signals

During Shift

Description

HS1/DS1

HS2/DS2

HS3/DS3

HS4/DS4

COM1 - COM8

COM9 - COM16

COM17 - COM24

COM25 - COM32

The part of display line that corresponds to enabled

common signal can be shifted.

29

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Function Set

(RE = 0)

RS

0

R/W

0

DB7

0

DB6

0

DB5

1

DB4

DL

DB3

N

DB2

DB1

DH

DB0

REV

RE(0)

DL:

N:

Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit

bus mode.

When 4-bit bus mode, it needs to transfer 4-bit data by two times.

Display line number control bit

It is variable only when NW bit of extended function set instruction is low.

When N = "Low", it means 1-line display mode.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE:

DH:

Extended function registers enable bit

At this instruction, RE must be "Low".

Display shift enable selection bit.

When DH = "High", display shift per line becomes enable.

When DH = "Low", smooth dot scroll becomes enable.

This bit can be accessed only when IE pin input is "High".

REV: Reverse enable bit

When REV = "High", all the display data are reversed. Namely, all the white dots become black and

black dots become white.

When REV = "Low", the display mode set normal display.

(RE = 1)

RS

0

R/W

0

DB7

0

DB6

0

DB5

1

DB4

DL

DB3

N

DB2

DB1

BE

DB0

0

RE(1)

DL:

N:

Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU.

So to speak, DL is a signal to select 8-bit or 4-bit bus mode.

When 4-bit bus mode, it needs to transfer 4-bit data by two times.

Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", it means 1-line display mode.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE:

BE:

Extended function registers enable bit

When RE = "High", extended function set registers, SEGRAM address set registers, BID bit, HS/DS bits

of shift/scroll enable instruction and BE bits of function set register can be accessed.

CGRAM/SEGRAM data blink enable bit

If BE is "High", It makes user font of CGRAM and segment of SEGRAM blink. The quantity of blink is

assigned the highest 2 bit of CGRAM/SEGRAM.

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Set CGRAM Address (RE = 0)

S6A0075

RS

0

R/W

0

DB7

0

DB6

1

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.

Set SEGRAM Address (RE = 1)

RS

0

R/W

0

DB7

0

DB6

1

DB5

X

DB4

X

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.

Set DDRAM Address (RE = 0)

RS

0

R/W

0

DB7

1

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode

(N = 0, NW = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1, NW = 0), DDRAM

address in the 1st line is from "00H" - "27H", and DDRAM address in the 2nd line is from "40H" - "67H". In 4-line

display mode (NW = 1), DDRAM address is from "00H" - "13H" in the 1st line, from "20H" to "33H" in the 2nd

line, from "40H" - "53H" in the 3rd line and from "60H" - "73H" in the 4th line.

Set Scroll Quantity (RE = 1)

RS

0

R/W

0

DB7

1

DB6

X

DB5

SQ

DB4

SQ4

DB3

SQ3

DB2

SQ2

DB1

SQ1

DB0

SQ0

As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units (Refer to Table 9). In this case

S6A0075 can show hidden areas of DDRAM by executing smooth scroll from 1 to 48 dots.

Table 9. Scroll Quantity According to HDS bits

SQ5

SQ4

SQ3

SQ2

SQ1

SQ0

Function

0

:

0

:

0

:

0

:

0

1

:

0

1

0

1

:

No shift

Shift left by 1-dot

Shift left by 2-dot

Shift left by 3-dot

:

1

0

1

X

1

X

1

X

1

X

Shift left by 47-dot

Shift left by 48-dot

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Read Busy Flag & Address

RS

0

R/W

1

DB7

BF

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

This instruction shows whether S6A0075 is in internal operation or not. If the resultant BF is High, it means the

internal operation is in progress and you have to wait until BF to be Low, and then the next instruction can be

performed. In this instruction you can read also the value of address counter.

Write Data to RAM

RS

1

R/W

0

DB7

D7

DB6

D6

DB5

D5

DB4

D4

DB3

D3

DB2

D2

DB1

D1

DB0

D0

Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or

SEGRAM, is set by the previous address set instruction: DDRAM address set, CGRAM address set, SEGRAM

address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address

is automatically increased/decreased by 1, according to the entry mode.

Read Data From RAM

RS

1

R/W

1

DB7

D7

DB6

D6

DB5

D5

DB4

D4

DB3

D3

DB2

D2

DB1

D1

DB0

D0

Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set

instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is

invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address

set instruction before read operation, you can get correct RAM data from the second, but the first data would be

incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift

instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data

register. After read operation address counter is automatically increased/decreased by 1 according to the entry

mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly. In case of RAM write

operation, after this AC is increased/decreased by 1 like read operation. In this time, AC indicates the next

address position, but you can read only the previous data by read instruction.

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

INSTRUCTION DESCRIPTION 2 (IE = "LOW")

S6A0075

Table 10. Instruction Set 2

Instruction Code

Executi

on Time

(fosc =

Instruction RE

Description

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270kHz)

Write "20H" to DDRAM. and set

DDRAM address to "00H" from

AC.

Clear

display

X

0

1

x

1.53ms

Set DDRAM address to "00H" from

AC and return cursor to its original

position if shifted. The contents of

DDRAM are not changed.

Return

home

Assign cursor moving direction.

I/D = "1": increment,

I/D = "0": decrement. and display

shift enable bit.

S = "1": make entire display shift

of all lines during DDRAM write,

S = "0": display shift disable

Entry

mode set

X

0

1

I/D

S

B

39ms

Set display/cursor/blink on/off

D = "1": display on,

D = "0": display off,

C = "1": cursor on,

C = "0": cursor off,

B = "1": blink on,

Display

ON/OFF

control

0

D

C

B = "0": blink off.

Assign font width, black/white

inverting of cursor, and 4-line

display mode control bit.

FW = "1": 6-dot font width,

FW = "0": 5-dot font width,

B/W = "1": black/white inverting of

cursor enable,

Extended

function

set

1

0

1

FW B/W NW

39ms

B/W = "0": black/white inverting of

cursor disable

NW = "1": 4-line display mode,

NW = "0": 1-line or 2-line display

mode

Cursor or display shift.

S/C = "1": display shift,

S/C = "0": cursor shift,

R/L = "1": shift to right,

R/L = "0": shift to left

Cursor or

display

shift

0

1

S/L R/L

X

39ms

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S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Table 10. Instruction Set 2 (Continued)

Instruction Code

Executi

on Time

(fosc =

Instruction RE

Description

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270kHz)

Determine the line for horizontal

smooth scroll.

HS1 = "1/0": 1st line dot scroll

enable/disable

Scroll

1

HS2 = "1/0": 2nd line dot scroll

enable/disable

0

1

HS4 HS3 HS2 HS1

39ms

Enable

HS3 = "1/0": 3rd line dot scroll

enable/disable

HS4 = "1/0": 4th line dot scroll

enable/disable

Set interface data length

DL = "1": 8-bit,

DL = "0": 4-bit

RE

(0)

numbers of display line when

NW = "0",

N = "1": 2-line,

N = "0": 1-line

extension register, RE("0")

0

1

DL

N

X

0

39ms

Function

Set

Set DL, N, RE("1") and

CGRAM/SEGRAM blink enable

(BE)

BE = " 1/0": CGRAM/SEGRAM

blink enable/disable

RE

(1)

1

BE

Set

CGRAM

address

Set CGRAM address in address

counter.

0

1

0

1

AC5 AC4 AC3 AC2 AC1 AC0

39ms

Set

SEGRAM

address

Set SEGRAM address in address

counter.

X

AC3 AC2 AC1 AC0

Set

DDRAM

address

Set DDRAM address in address

counter.

0

1

0

1

AC6 AC5 AC4 AC3 AC2 AC1 AC0

39ms

Set scroll

quantity

Set the quantity of horizontal dot

scroll.

X

SQ5 SQ4 SQ3 SQ2 SQ1 SQ0

Can be known whether during

internal operation or not by

reading BF. The contents of

address counter can also be read.

BF = "1": busy state,

Read busy

flag and

address

X

0

1

BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

0ms

BF = "0": ready state.

34

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

Table 10. Instruction Set 2 (Continued)

Instruction Code

Execution

Time

(fosc =

270kHz)

Instruction RE

Description

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Write data into internal RAM

(DDRAM / CGRAM / SEGRAM).

Write data

Read data

X

1

0

1

D7 D6 D5 D4 D3 D2 D1 D0

43ms

Read data from internal RAM

(DDRAM / CGRAM / SEGRAM).

Note: 1. When an MPU program with Busy Flag (DB7) checking is made, 1/2 fosc (is necessary) for executing the next

instruction by the falling edge of the “E” signal after the Busy Flag (DB7) goes to “Low”.

2. "X": Don’t care.

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S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Display Clear

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

0

DB0

1

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"

into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first

line of the display. And entry mode is set to increment mode (I/D = "1").

Return Home

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

1

DB0

X

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return

cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.

Entry Mode Set

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

1

DB1

I/D

DB0

S

Set the moving direction of cursor and display.

I/D: Increment/decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.

When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.

- CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM.

When S = "High", after DDRAM write, the entire display of all lines is shifted to the right (I/D = "0") or to the left

(I/D = "1"). But it will seem as if the cursor does not move. When S = "Low", or DDRAM read, or

CGRAM/SEGRAM read/write operation, shift of entire display is not performed.

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Display ON/OFF Control (RE = 0)

S6A0075

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

1

DB2

D

DB1

C

DB0

B

Control display/cursor/blink ON/OFF 1 bit register.

D:

C:

B:

Display ON/OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

Cursor ON/OFF control bit

When C = "High", cursor is turned on.

When C = "Low", cursor is disappeared in current display, but I/D register remains its data.

Cursor Blink ON/OFF control bit

When B = "High", cursor blink is on, that performs alternate between all the high data and display

character at the cursor position. If fosc has 270kHz frequency, blinking has 370 ms interval.

When B = "Low", blink is off.

Extended Function Set (RE = 1)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

1

DB2

FW

DB1

B/W

DB0

NW

FW:

Font width control

When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5

times than that of 5-dot font width.

The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the leftmost

pace bit of CGRAM.(Refer to Fig-10)

When FW = "Low", 5-dot font width is set.

B/W: Black/White Inversion enable bit

When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display

ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion

has 370 ms intervals.

NW:

4 Line mode enable bit

When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't

care condition.

6-bit

S

p

a

c

CGROM

Characte

Font

CGRAM

Characte

Font

8-bit

(5-dot)

(6-dot)

e

CGROM

CGRAM

Figure 10. 6-dot font width CGROM/CGRAM

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S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Cursor or Display Shift (RE = 0)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

S/C

DB2

R/L

DB1

X

DB0

X

Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to

correct

or search display data.(Refer to Table 11) during 2-line mode display, cursor moves to the 2nd line after 40th

digit

of 1st line. When 4-line mode, cursor moves to the next line, only after every 20th digit of the current line. Note

that

display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line

shifted

individually. When display shift is performed, the contents of address counter are not changed.

Table 11. Shift Patterns According to S/C and R/L Bits

S/C

0

R/L

0

Operation

Shift cursor to the left, address counter is decreased by 1

Shift cursor to the right, address counter is increased by 1

Shift all the display to the left, cursor moves according to the display

Shift all the display to the right, cursor moves according to the display

0

1

0

1

Scroll Enable (RE = 1)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

HS4

DB2

HS3

DB1

HS2

DB0

HS1

HS:

Horizontal scroll per line enable

This instruction makes valid dot shift by a display line unit. HS1, HS2, HS3 and HS4 indicate each line to

be dot scrolled, and each scroll is performed individually in each line.

If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and

HS2 to "High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High".

(refer to Table 8)

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

Function Set

(RE = 0)

RS

0

R/W

0

DB7

0

DB6

0

DB5

1

DB4

DL

DB3

N

DB2

DB1

X

DB0

X

RE(0)

DL:

N:

Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit

bus mode.

When 4-bit bus mode, it needs to transfer 4-bit data by two times.

Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", it means 1-line display mode.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE:

Extended function registers enable bit

At this instruction, RE must be "Low".

(RE = 1)

RS

0

R/W

0

DB7

0

DB6

0

DB5

1

DB4

DL

DB3

N

DB2

DB1

BE

DB0

0

RE(1)

DL:

N:

Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit

bus mode.

When 4-bit bus mode, it needs to transfer 4-bit data by two times.

Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", it means 1-line display mode.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE:

BE:

Extended function registers enable bit

When RE = "High", extended function set registers, SEGRAM address set registers, HS bits of scroll

enable instruction and BE bits of function set register can be accessed.

CGRAM/SEGRAM data blink enable bit

If BE is "High", It makes user font of CGRAM and segment of SEGRAM blink. The quantity of blink is

assigned the highest 2 bit of CGRAM/SEGRAM.

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S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Set CGRAM Address (RE = 0)

RS

0

R/W

0

DB7

0

DB6

1

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.

Set SEGRAM Address (RE = 1)

RS

0

R/W

0

DB7

0

DB6

1

DB5

X

DB4

X

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set SEGRAM address to AC. This instruction makes SEGRAM data available from MPU.

Set DDRAM Address (RE = 0)

RS

0

R/W

0

DB7

1

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set DDRAM address to AC.

This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0, NW = 0), DDRAM

address is from "00H" to "4FH". In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from

"00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". In 4-line display mode (NW = 1),

DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "33H" in the 2nd line, from "40H" to "53H" in

the 3rd line and from "60H" to "73H" in the 4th line.

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100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Set Scroll Quantity (RE = 1)

S6A0075

RS

0

R/W

0

DB7

1

DB6

X

DB5

SQ5

DB4

SQ4

DB3

SQ3

DB2

SQ2

DB1

SQ1

DB0

SQ0

As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units (refer to Table 12). In this case

S6A0075 execute dot smooth scroll from 1 to 48 dots.

Table 12. Scroll Quantity According to HDS bits

SQ5

SQ4

SQ3

SQ2

SQ1

SQ0

Function

0

:

0

:

0

:

0

:

0

1

:

0

1

0

1

:

No shift

Shift left by 1-dot

Shift left by 2-dot

Shift left by 3-dot

:

1

0

1

X

1

X

1

X

1

X

Shift left by 47-dot

Shift left by 48-dot

Read Busy Flag & Address

RS

0

R/W

1

DB7

BF

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

This instruction shows whether S6A0075 is in internal operation or not. If the resultant BF is High, it means the

internal operation is in progress and you have to wait until BF to be low, and then the next instruction can be

performed. In this instruction you can read also the value of address counter.

Write Data to RAM

RS

1

R/W

0

DB7

D7

DB6

D6

DB5

D5

DB4

D4

DB3

D3

DB2

D2

DB1

D1

DB0

D0

Write binary 8-bit data to DDRAM/CGRAM/SEGRAM. The selection of RAM from DDRAM, CGRAM, or

SEGRAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, SEGRAM

address set. RAM set instruction can also determines the AC direction to RAM. After write operation, the address

is automatically increased/decreased by 1, according to the entry mode.

41

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Read Data From RAM

RS

1

R/W

1

DB7

D7

DB6

D6

DB5

D5

DB4

D4

DB3

D3

DB2

D2

DB1

D1

DB0

D0

Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. The selection of RAM is set by the previous address set

instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is

invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address

set instruction before read operation, you can get correct RAM data from the second, but the first data would be

incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift

instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output data

register. After read operation address counter is automatically increased/decreased by 1 according to the entry

mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly.

- In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time, AC

indicates the next address position, but you can read only the previous data by read instruction.

42

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

INTERFACE WITH MPU

S6A0075 can transfer data in bus mode (4-bit or 8-bit) or serial mode with MPU. So you can use any type 4 or 8-

bit MPU.

In case of 4-bit bus mode, data transfer is performed by two times to transfer 1 byte data.

·

When interfacing data length are 4-bit, only 4 ports, from DB4 - DB7, are used as data bus.

At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-

bit (in case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by two

times. Busy flag outputs "High" after the second transfer are ended.

·

When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 - DB7.

If IM is set to "Low", serial transfer mode is set.

43

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

INTERFACE WITH MPU IN BUS MODE

Interface with 8-bit MPU

If 8-bit MPU is used, S6A0075 can connect directly with that. In this case, port E, RS, R/W and DB0 - DB7 need

to interface each other. Example of timing sequence is shown below.

RS

R/W

E

Internal Operation

Internal Signal

DB7

No

Bus

y

Data

Busy

Data

Instruction

Busy Flag

Check

Busy Flag

Check

Busy Flag

Check

Figure 11. Example of 8-bit Bus Mode Timing Sequence

Interface with 4-bit MPU

If 4-bit MPU is used, S6A0075 can connect directly with this. In this case, port E, RS, R/W and DB4 - DB7 need

to interface each other. The transfer is performed by two times. Example of timing sequence is shown below.

RS

R/W

E

Internal Signal

DB7

Internal Operation

No

Busy

D7

D3

Busy

AC3

D7 D3

Instruction

Busy Flag Check

Instruction

Figure 12. Example of 4-bit Bus Mode Timing Sequence

44

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

INTERFACE WITH MPU IN SERIAL MODE

S6A0075

When IM port input is "Low", serial interface mode is started. At this time, all three ports, SCLK (synchronizing

transfer clock), SID (serial input data), and SOD (serial output data), are used. If you want to use S6A0075 with

other chips, chip select port (CS) can be used. By setting CS to "Low", S6A0075 can receive SCLK input. If CS is

set to "High", S6A0075 reset the internal transfer counter.

Before transfer real data, start byte has to be transferred. It is composed of succeeding 5 "High" bits, read write

control bit (R/W), register selection bit (RS) and end bit that indicates the end of start byte. Whenever succeeding

5 "High" bits are detected by S6A0075, it makes serial transfer counter reset and ready to receive next

information.

The next input data are register selection bit that determine which register will be used, and read write control bit

that determine the direction of data. Then end bit is transferred, which must have "Low" value to show the end of

start byte. (Refer to Figure 13. Figure 14)

Write Operation (R/W = 0)

After start byte is transferred from MPU to S6A0075, 8-bit data is transferred which is divided into 2 bytes, each

byte has 4 bit's real data and 4 bit's partition token data. For example, if real data is "10110001" (D0 - D7), then

serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe

transfer. To transfer several bytes continuously without changing RS bit and RW bit, start byte transfer is needed

only at first starting time. Namely, after first start byte is transferred, real data can be transferred succeeding.

Read Operation (R/W = 1)

After start byte is transferred to S6A0075, MPU can receive 8-bit data through the SOD port at a time from the

LSB. Wait time is needed to insert between start byte and data reading, because internal reading from RAM

requires some delay. Continuous data reading is possible like serial write operation. It also needs only one start

bytes, only if you insert some delay between reading operations of each byte. During the reading operation,

S6A0075 observes succeeding 5 "High" from MPU. If it is detected, S6A0075 restarts serial operation at once

and ready to receive RS bit. So in continuous reading operation, SID port must be "Low".

45

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

Serial Write Operation

CS (Input)

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SCLK (Input)

SID (Input)

"1" "1" "1" "1" "1" R/WRS 0 D0 D1 D2 D3 "0" "0" "0" "0" D4 D5 D6 D7"0" "0" "0" "0"

Starting Byte

Instruction

Upper Data

Synchronizing

Bit String

Lower Data

1'st Byte

2'nd Byte

Serial Read Operation

CS (Input)

1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SCLK (Input)

SID (Input)

"1" "1" "1" "1" "1"R/W RS "0" "0" "0" "0" "0" "0" "0" "0" "0"

D0 D1 D2 D3 D4 D5 D6 D7

SOD (Output)

Busy Flag/

Read Data

Starting Byte

Lower

Data

Upper

Data

Synchronizing

Bit String

Figure 13. Timing Diagram of Serial Data Transfer

46

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

Continuous Write Operation

SCLK

SID

Wait

Start Byte

1'st Byte 2'nd Byte

Instruction1

1'st Byte

2'nd Byte

1'st Byte

2'nd Byte

Instruction2

Instruction1

Execution Time

Instruction3

Instruction2

Execution Time

Instruction3

Execution Time

Continuous Read Operation

SCLK

SID

Wait

Start

Byte

Data

Data

Data

SOD

Instruction1

Execution Time

Instruction2

Execution Time

Instruction3

Execution Time

Figure 14. Timing Diagram of Continuous Data Transfer

47

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

APPLICATION INFORMATION ACCORDING TO LCD PANEL

LCD Panel: 40 Character x 1-line Format (5-dot Font,1/17 Duty)

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

(COM0)

ª §

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

S6A0075

SEG7

SEG8

SEG9

SEG10

SEG98

SEG99

SEG100

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

LCD Panel: 40 Character x 2-line Format (5-dot Font, 1/33 Duty)

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM33

(COM0)

SEG1

SEG2

SEG3

SEG4

SEG5

S6A0075

SEG98

SEG99

SEG100

COM32

COM31

COM30

COM29

COM28

COM27

COM26

COM25

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

48

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

LCD Panel: 20 Character x 4-line Format (5-dot Font, 1/33 Duty)

S6A0075

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

S6A0075

COM30

COM31

COM32

COM33

(COM0)

SEG1

SEG2

SEG3

SEG4

SEG5

SEG76

SEG77

SEG78

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

SEG98

SEG99

SEG100

49

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

LCD Panel: 16 Character x 4-line Format (6-dot Font, 1/33 Duty)

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

S6A0075

COM28

COM29

COM30

COM31

COM32

COM33

(COM0)

ª §

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG94

SEG95

SEG96

SEG97 Open

SEG98 Open

SEG99 Open

SEG100 Open

50

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

INITIALIZING

INITIALIZING BY INTERNAL RESET CIRCUIT

When the power is turned on, S6A0075 is initialized automatically by power on reset circuit. During the

initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of

initialization.

Display Clear instruction

Write "20H" to all DDRAM

Set Functions instruction

DL = 1: 8-bit bus mode

N = 1: 2-line display mode

RE = 0: Extension register disable

BE = 0: CGRAM/SEGRAM blink OFF

DH = 0: Horizontal scroll enable

REV = 0: Normal display (Not reversed display)

Control Display ON/OFF instruction

D = 0: Display OFF

C = 0: Cursor OFF

B = 0: Blink OFF

Set Entry Mode instruction

I/D = 1: Increment by 1

S = 0: No entire display shift

BID = 0: Normal direction segment port

Set Extension Function instruction

FW = 0: 5-dot font width character display

B/W = 0: Normal cursor (8th line)

NW = 0: Not 4-line display mode, 2-line mode is set because of N("1")

Enable Shift instruction

HS = 0000: Scroll per line disable

DS = 0000: Shift per line disable

Set scroll Quantity instruction

SQ = 000000: Not scroll

INITIALIZING BY HARDWARE RESET INPUT

When RESET pin = "Low", S6A0075 can be initialized like the case of power on reset. During the power on reset

operation, this pin is ignored.

51

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

INITIALIZING BY INSTRUCTION

8-BIT INTERFACE MODE

Power On

Wait for more than 20ms after

V_DDrises to 4.5V

Wait for more than 30ms after

V_DDrises to 2.7V

Condition: fosc = 270kHz

(DL = "1")

0

1

0

1

4-bit interface

8-bit interface

1-line mode

2-line mode

Function Set

DL

N

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DL(1)

0

1

N

0

x

Wait for more than 39 s

m

0

1

0

1

0

1

Display off

Display on

Cursor off

Cursor on

Blink off

D

C

B

Display ON/OFF Control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

D

C

B

Wait for more than 39

Clear Display

ms

Blink on

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

Wait for more than 1.53sms

Entry Mode Set

0

1

0

1

Decrement mode

Increment mode

Entire shift off

I/D

S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

I/D

0

1

S

Entire shift on

Initialization End

52

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

4-BIT INTERFACE MODE

Power On

Wait for more than 20ms after

VDD rises to 4.5V

Wait for more than 30ms after

VDD rises to 2.7V

Condition: fosc = 270kHz

(DL = "0")

0

1

0

1

4-bit interface

8-bit interface

1-line mode

2-line mode

Function Set

DL

N

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

DL(0)

x

Wait for more than 39ms

Function Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

x

1

x

0

x

N

m

Wait for more than 39 s

Display ON/OFF Control

0

1

0

1

0

1

Display off

Display on

Cursor off

Cursor on

Blink off

D

C

B

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

x

D

C

B

Blink on

Wait for more than 39ms

Display Clear

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

x

Wait for more than 1.53ms

Entry Mode Set

0

1

0

1

Decrement mode

Increment mode

Entire shift off

Entire shift on

I/D

S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

x

I/D

SH

Initialization End

53

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

EXAMPLE OF INSTRUCTION AND DISPLAY CORRESPONDENCE

IE = "LOW"

1. Power supply on: Initialized by the internal power on reset circuit

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LCD DISPLAY

2. Function Set: 8-bit, 1-line, RE(0)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

X

3. Display ON/OFF Control: Display/Cursor on

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

_

0

1

0

4. Entry Mode Set: Increment

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

_

0

1

0

5. Write Data to DDRAM: Write S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

S_

SA_

1

0

1

0

1

0

1

6. Write Data to DDRAM: Write A

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

7. Write Data to DDRAM: Write M

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAM_

1

0

1

0

1

0

1

8. Write Data to DDRAM: Write S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMS_

1

0

1

0

1

0

1

54

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

9. Write Data to DDRAM: Write U

LCD DISPLAY

SAMSU_

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

1

0

1

10. Write Data to DDRAM: Write N

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUN_

1

0

1

0

1

0

11. Write Data to DDRAM: Write G

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG_

1

0

1

0

1

12. Cursor or Display Shift: Cursor shift to right

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG _

AMSUNG K_

MSUNG KS_

SUNG KS0_

0

1

0

1

X

13. Entry Mode Set: Entire Display Shift Enable

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

14. Write Data to DDRAM: Write K

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

1

15. Write Data to DDRAM: Write S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

1

16. Write Data to DDRAM: Write 0

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

55

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

17. Write Data to DDRAM: Write 0

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LCD DISPLAY

UNG KS00_

NG KS007_

G KS0073_

G KS0073

KS0075_

1

0

1

0

18. Write Data to DDRAM: Write 7

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

19. Write Data to DDRAM: Write 3

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

20. Cursor or Display Shift: Cursor shift left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

x

21. Write Data to DDRAM: Write 8

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

1

22. Return Home

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG KS0075

0

1

x

23. Clear Display

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

_

0

1

56

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

IE = "HIGH"

S6A0075

1. Power Supply On: Initialized by the internal power on reset circuit

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

2. Function Set: 8-bit, RE(1)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

3. Extended Function Set: 5-font, 4-line

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

4. Function Set: RE(0)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

5. Display ON/OFF Control: Display/Cursor on

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

_

0

1

0

6. Write Data to DDRAM: Write S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

S_

1

0

1

0

1

0

1

57

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

7. Write Data to DDRAM: Write A

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SA_

1

0

1

0

1

12. Write Data to DDRAM: Write G

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG_

1

0

1

0

1

13. Set DDRAM Address 20H

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

_

0

1

0

1

0

14. Write Data to DDRAM: Write K

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

K_

1

0

1

0

1

0

1

19. Write Data to DDRAM: Write 5

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075_

1

0

1

0

1

0

1

20. Set DDRAM Address 40H

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

_

0

1

0

58

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

21. Write Data to DDRAM: Write L

SAMSUNG

KS0075

L_

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

30. Write Data to DDRAM: Write R

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER_

1

0

1

0

1

0

1

0

31. Set DDRAM Address 60H

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

_

0

1

0

43. Write Data to DDRAM: Write R

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER_

1

0

1

0

1

0

1

0

44. Function Set: RE("0"), DH("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER_

0

1

0

1

0

45. Function Set: RE("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER_

0

1

0

59

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

46. Shift/Scroll Enable: DS4("1"), DS3/2/1("0")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER_

0

1

0

47. Function Set: RE("0")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER_

0

1

0

1

0

48. Cursor or Display Shift: Display shift to left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

CONTROLLER_

0

1

0

x

49. Cursor or Display Shift: Display shift to left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

CONTROLLER_

0

1

0

x

50. Cursor or Display Shift: Display shift to left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

ONTROLLER_

0

1

0

x

51. Cursor or Display Shift: Display shift to left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

NTROLLER_

0

1

0

x

60

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

52. Return Home

SAMSUNG

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

KS0075

LCD DRIVER

& CONTROLLER

0

1

x

53. Function Set: RE("0), REV("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER

0

1

0

1

54. Cursor or Display Shift: Display shift to right

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER

0

1

x

55. Cursor or Display Shift: Display shift to right

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER

0

1

x

56. Return Home

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER

0

1

x

57. Function Set: RE("0"), REV("0")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER

0

1

0

61

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

58. Function Set: RE("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0075

LCD DRIVER

& CONTROLLER

0

1

0

59. Entry Mode Set: BID("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

60. Clear Display

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

61. Write Data to DDRAM: Write B

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

1

62. Write Data to DDRAM: Write I

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

63. Write Data for DDRAM: Write D

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

62

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

FRAME FREQUENCY

1/17 DUTY CYCLE

1-line selection period

1

2

3

4

...

16 17

1

2

3

...

16 17

VDD

V1

COM1

V4

V5

1 Frame

Display Font Width

Item

5-Dot Font Width

200 clocks

6-Dot Font Width

240 clocks

1-line selection period

Frame frequency

79.4Hz

66.2Hz

fosc = 270kHz (1 clock = 3.7ms)

1/33 DUTY CYCLE

1-line selection period

1

2

3

4

...

32 33

1

2

3

...

32 33

VDD

V1

COM1

V4

V5

1 Frame

Display Font Width

Item

5-Dot Font Width

100 clocks

6-Dot Font Width

120 clocks

1-line selection period

Frame frequency

81.8Hz

68.2Hz

fosc = 270kHz (1 clock = 3.7ms)

63

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

POWER SUPPLY FOR DRIVING LCD PANEL

WHEN AN EXTERNAL POWER SUPPLY IS USED

VDD

R

VDD

V1

R

R0

R

V2

V3

V4

V5

R

VEE

WHEN AN INTERNAL BOOSTER IS USED

Boosting Twice

Boosting Three Times

VDD

V_CI

VDD

V1

V_CI

VDD

V1

+

R

+

R

-

GND

C1

-

GND

C1

R

V2

-

+

-

+

R0

R

R0

R

1 F

m

1 F

m

C2

V5OUT2

V5OUT3

V3

V4

C2

V5OUT2

V5OUT3

V3

V4

R

V5

-

1mF

+

-

+

-

Can be detached if

not using power

down mode

Can be detached if

not using power

down mode

1m

F

1mF

+

·

Boosted output voltage should not exceed the maximum value (13 V) of the LCD driving voltage.

Especially, a voltage of over 4.3V should not be input to the reference voltage (Vci) when boosting three

times.

·

A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting twice.

The value of resistance, according to the number of lines, duty ratio and the bias, is shown below.

(refer to Table 13)

64

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

Table 13. Duty Ratio and Power Supply for LCD Driving

Item

Data

Number of lines

Duty ratio

Bias

1

1/17

1/5

R

2 or 4

1/33

1/6.7

R

Divided resistance

R0

R

2.7R

MAXIMUM ABSOLUTE RATE

Characteristic

Symbol

Value

Unit

V_DD

Power supply voltage (1)

-0.3 to +7.0

V

V_LCD

V_IN

V_DD-15.0 to V_DD+0.3

Power supply voltage (2)

Input voltage

-0.3 to V_DD+0.3

-30 to +85

V

T_OPR

T_STG

Operating temperature

Storage temperature

°C

-55 to +125

Voltage greater than above may damage to the circuit (V

³ V1 ³ V2 ³ V3 ³ V4 ³ V5)

DD

65

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS (VDD = 2.7V to 5.5V, Ta = -30 to + 85°C)

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

V_DD

Operating voltage

-

2.7

-

5.5

V

Internal oscillation or external

clock.

(V_DD= 3.0V, fosc = 270kHz)

I_DD

Supply current

-

0.15

0.3

mA

-

V_IH1

V_IL1

0.7V_DD

V_DD

-

Input voltage (1)

(Except OSC1)

V_DD= 2.7 - 3.0

V_DD= 3.0 - 5.5

0.2V_DD

-0.3

-

0.6

V_DD

V_IH2

V_IL2

0.7V_DD

-

Input voltage (2)

(Osc1)

V

0.2V_DD

-

V_OH1

V_OL1

V_OH2

V_OL1

Vd_COM

Vd_SEG

I_LKG

I_OH= -0.1mA

I_OL= 0.1mA

0.75V_DD

-

Output voltage (1)

(DB0 - DB7)

0.2V_DD

-

0.8V_DD

I_O= -40mA

I_O= 40mA

-

Output voltage (2)

(Except DB0 - DB7)

0.2V_DD

-

1

I_O= ± 0.1mA

Voltage drop

-

V_IN= 0V - V_DD

Input leakage current

Low input current

-1

-10

-

1

mA

I_IL

V_IN= 0V, V_DD= 3V (pull up)

-50

-120

Internal clock

(external Rf)

f_OSC

f_EC

Rf = 91kW ± 2% (V_DD= 5V)

190

270

350

kHz

125

45

-

270

50

-

410

55

kHz

%

External clock

-

duty

tr, tf

0.2

ms

Voltage converter out2

(Vci = 4.5V)

Ta = 25°C, C = 1mF,

V_OUT2

-3.0

-4.3

-4.2

-5.1

-

I_OUT= 0.25mA,

V

Voltage converter out3

(Vci = 2.7V)

V_OUT3

Vci

f_OSC= 270kHz

-

Voltage converter input

1.0

3.0

-

4.5

1/5 bias

V_DD-V5

13.0

V_LCD

LCD driving voltage

1/6.7 bias

66

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

AC CHARACTERISTICS (VDD = 4.5 to 5.5V, Ta = -30 to +85°C)

Table 14. AC Characteristics

Mode

Item

Symbol

tc

Min

500

-

Typ

Max

Unit

E cycle time

-

E rise/fall time

tr, tf

tw

20

E pulse width (high, low)

R/W and RS setup time

R/W and RS hold time

Data setup time

230

40

10

60

10

500

-

(1) Write mode

tsu1

th1

tsu2

th2

tc

-

ns

(refer to Figure15)

-

Data hold time

-

E cycle time

-

20

-

E rise/fall time

tr, tf

tw

E pulse width (high, low)

R/W and RS setup time

R/W and RS hold time

Data output delay time

230

40

10

-

(2) Read mode

tsu

th

-

ns

(refer to Figure 16)

-

t_D

160

t_DH

Data hold time

5

0.5

-

20

50

-

Serial clock cycle time

Serial clock rise/fall time

Serial clock width (high, low)

Chip select setup time

Chip select hold time

tc

tr, tf

tw

ms

200

60

20

100

-

tsu1

th₁

-

(3) Serial interface

mode

-

ns

Serial input data setup time

Serial input data hold time

Serial output data delay time

tsu2

th2

t_D

-

(refer to Figure 17)

-

160

t_DH

Serial output data hold time

5

-

67

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

TABLE 14. AC CHARACTERISTICS (VDD = 4.5 to 5.5V, Ta = -30 to +85°C)

Mode

Item

Symbol

tc,

Min

1000

-

Typ

Max

Unit

E cycle time

-

E rise / fall time

tr, tf

tw

25

E pulse width (high, low)

R/W and RS setup time

R/W and RS hold time

Data setup time

450

60

-

(4) Write mode

(refer to Fig-15)

tsu1

th1

tsu2

th2

tc

-

ns

20

-

195

10

-

Data hold time

-

E cycle time

1000

-

25

-

E rise/fall time

tr, tf

tw

E pulse width (high, low)

R/W and RS setup time

R/W and RS hold time

Data output delay time

450

60

(5) Read mode

tsu

-

ns

(refer to Figure 16)

th

20

-

t_D

-

360

t_DH

Data hold time

5

1

-

20

50

-

Serial clock cycle time

Serial clock rise/fall time

Serial clock width (high, low)

Chip select setup time

Chip select hold time

tc

tr, tf

tw

ms

-

400

60

20

200

-

tsu1

th1

tsu2

th2

t_D

-

(6) Serial interface

mode

-

ns

Serial input data setup time

Serial input data hold time

Serial output data delay time

-

(refer to Figure 17)

-

360

t_DH

Serial output data hold time

5

-

68

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0075

VIH1

VIL1

RS

th1

tsu1

R/W

VIL1

tw

tf

VIH1

VIL1

VIH1

VIL1

tsu2

E

VIL1

th2

tr

VIH1

VIL1

VIH1

VIL1

DB0 - DB7

Valid Data

tc

Figure 15. Write Mode

VIH1

VIL1

tsu

RS

th

VIH1

R/W

tw

tf

VIH1

VIL1

VIH1

VIL1

E

VIL1

tDH

tr

tD

VOH1

VOL1

VOH1

VOL1

DB0 - DB7

Valid Data

tc

Figure 16. Read Mode

69

S6A0075

100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD

t

C

CS

V_IL1

su1

V_IL1

th1

t

r

t

w

t

w

tf

SCLK

V

IH1

V

IH1

V

IH1

IL1

h2

V

IH1

VIL1

V

VIL1

t

su2

t

SID

t

D

t

DH

V

OH1

SOD

VOL1

Figure 17. Serial Interface Mode

RESET TIMING (VDD = 2.7 to 5.5V, Ta = -30 to +85°C)

Item

Symbol

Min

Typ

Max

Unit

Reset low level width (refer to Figure 18)

t_RES

10

-

ms

t

RES

RESET

VIL1

Figure 18. Reset Timing Diagram

70


型号：	S6A0075
厂家：	SAMSUNG
描述：	100 SEG / 34 COM DRIVER & CONTROLLER FOR DOT MATRIX LCD 100 SEG / 34 COM驱动程序和控制器的点阵LCD 驱动控制器 CD
文件：	总70页 (文件大小：689K)
中文：	中文翻译
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