S6A0093 [SAMSUNG]
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD; 80 SEG / 26 COM驱动程序和控制器的STN LCD
| 型号： | S6A0093 |
| 厂家： | 
SAMSUNG |
| 描述： | 80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD |
| 文件： | 总54页 (文件大小：590K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
june. 2000.
Ver. 0.4
Prepared by:
Won-Sik, Kang
K2w3@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or
transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written
permission of LCD Driver IC Team.
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
S6A0093 Specification Revision History
Content
Version
Date
0.0
Original
Jun.1998
0.1
0.2
0.3
0.4
Miss typed contents changed
RESETB pin VIL,VIH added
Jan.1999
Mar.1999
Nov.1999
Dec.1999
Jun.2000
VDD change (2.4V~5.5V -> 2.4V~3.6V)
VDD change (2.4V~3.6V -> 2.4V~5.5V)
Inspection
1
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
CONTENTS
INTRODUCTION.......................................................................................................................................... 1
FEATURES ................................................................................................................................................. 1
BLOCK DIAGRAM ...................................................................................................................................... 3
PAD CONFIGURATION............................................................................................................................... 4
PAD CENTER COORDINATES................................................................................................................... 5
PIN DESCRIPTION...................................................................................................................................... 6
POWER SUPPLY................................................................................................................................. 6
LCD DRIVER SUPPLY......................................................................................................................... 6
SYSTEM CONTROL............................................................................................................................. 7
MPU INTERFACE ................................................................................................................................ 7
LCD DRIVER OUTPUTS ...................................................................................................................... 8
TEST.................................................................................................................................................... 8
FUNCTION DESCRIPTION.......................................................................................................................... 9
SYSTEM INTERFACE.......................................................................................................................... 9
ADDRESS COUNTER (AC)................................................................................................................ 13
DISPLAY DATA RAM (DDRAM) ......................................................................................................... 13
CHARACTER GENERATOR ROM (CGROM)..................................................................................... 13
CHARACTER GENERATOR RAM (CGRAM) ..................................................................................... 15
SEGMENT ICON RAM (ICONRAM).................................................................................................... 17
LOW POWER CONSUMPTION MODE .............................................................................................. 18
LCD DRIVER CIRCUIT....................................................................................................................... 18
INSTRUCTION DESCRIPTION.................................................................................................................. 19
INITIALIZING & POWER SAVE MODE SETUP......................................................................................... 29
HARDWARE RESET.......................................................................................................................... 29
INITIALIZING AND POWER SAVE SETUP......................................................................................... 30
LCD DRIVING POWER SUPPLY CIRCUIT................................................................................................ 33
VOLTAGE CONVERTER.................................................................................................................... 34
VOLTAGE REGULATOR.................................................................................................................... 35
ELECTRONIC CONTRAST CONTROL (32 STEPS)........................................................................... 36
VOLTAGE GENERATOR CIRCUIT .................................................................................................... 38
MPU INTERFACE...................................................................................................................................... 39
APPLICATION INFORMATION FOR LCD PANEL .................................................................................... 41
FRAME FREQUENCY............................................................................................................................... 43
MAXIMUM ABSOLUTE RATINGS............................................................................................................. 44
ELECTRICAL CHARACTERISTICS.......................................................................................................... 45
DC CHARACTERISTICS.................................................................................................................... 45
AC CHARACTERISTICS .................................................................................................................... 47
2
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
INTRODUCTION
The S6A0093 is an LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can
display 2 or 3 lines of 16 characters with 5 x 8 dots format. It is capable of interfacing various microprocessors,
supporting the 4-bit, 8-bit parallel modes and the clock synchronized serial mode. Voltage converter, oscillator,
voltage regulator, voltage follower and bias circuit are built in the IC. The double height character mode and line
vertical scroll functions are supported.
FEATURES
Driver Outputs
- Common outputs: 26 common
- Segment outputs: 80 segment
Applicable Panel Size
Font
Display
Duty
1 / 17
1 / 25
Contents of outputs
2 x 16 characters + 80 icons
3 x 16 characters + 80 icons
2-line x 16 characters
3-line x 16 characters
5 x 8
Internal Memory
- Character Generator ROM (CGROM): 10,240 bits (256 characters x 5 x 8 dots)
- Character Generator RAM (CGRAM): 320 bits (8 characters x 5 x 8 dots)
- Display Data RAM (DDRAM): 512 bits (16 characters x 4 lines)
- Segment Icon RAM (ICONRAM): 80 bits (80 icons)
MPU Interface
- No busy MPU interface (no busy check or no execution waiting time)
- 8-bit parallel interface mode: 68-series and 80-series are available.
- 4-bit parallel interface mode: 68-series and 80-series are available.
- Serial interface mode: 4 pins clock synchronized serial interface
Function Set
- Various instruction set: display control, power save, power control, etc.
- COM / SEG bi-directional (4-type LCD application available)
- H/W reset (RESETB)
Built-in Analog Circuit
- Internal RC oscillator circuit or external clock
- Electronic volume for contrast control (32 steps)
- Voltage converter / voltage regulator / voltage follower & bias circuit
Low Power Operation
- Sleep mode operation (5mA Max.)
- Normal mode operation (80mA Max.)
1
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Operating Voltage Range
- Power supply voltage (VDD): 2.4V ~ 5.5V
- LCD driving voltage (VLCD = V0 - VSS): 6.0V Max.
Package Type
- Gold bumped chip or TCP
2
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
BLOCK DIAGRAM
RESETB
CK
PS
Oscillator
Timing Generator
IF
M I
CSB
RS
RW_WR
E_RD
Instruction
Register
(IR)
8
Parallel
Interface
4 bit/8 bit
Instruction
Decoder
COM1-
COM24
25 bits
Shift
Common
Driver
Address
Counter
Display
Data RAM
(DDRAM)
512 bits
Register
COM I1
COM I2
DB7
(SI)
Data
Register
(DR)
8
DB6
(SCL)
Serial
7
Interface
DB5-
DB4
8
SEG1-
SEG80
Data Output
Register
(OR)
8
8
80 bits
Shift
Register
80 bits
Latch
Circuit
Segment
Driver
DB3-
DB0
Input Buffer
8
5
8
Character
Generator
RAM
Character
Generator
ROM
Cursor
and
LCD
Driver
Icon
RAM
Blink
Controlle
Voltage
Selector
80 bits
(CGRAM)
320 bits
(CGROM)
10240 bits
5
5
VDD
Segment Data Conversion
GND
LCD Driving Power Circuit
Voltage Converter
Voltage Regulator
Voltage Follower & Bias Resistor
VR V1 V2 V3 V4
CAP1+ CAP1- CAP2+ CAP2- VOUT V0 VEXT REF
Figure 1. Block Diagram
DIRS
3
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
PAD CONFIGURATION
............................
167
179
86
74
Y
X
(0,0)
...........................
DUMMY PAD
PAD
Figure 2. Pad Configuration
Table 1. S6A0093 Pad Dimensions
Size
Item
Pad No.
Unit
X
Y
Chip size
Pad pitch
-
7020
1620
1 ~ 73
90
80
74 ~ 179
1 ~ 73
60
100
50
100
50
mm
74 ~ 86
87 ~ 166
167 ~ 179
All pad
Bumped pad size
100
50
100
Bumped pad height
17
COG Align Key Coordinate
ILB Align Key Coordinate
30 m 30 m 30 m
30 m 30 m 30 m
42 m
m
108 m
108 m
42 m
m
m
m
m
m
m
m
m
m
(+3440, +740)
(-3440, +740)
(-3065, -445)
(-2965, -405)
4
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: mm]
Pad
No.
Pad
name
Pad
No.
Pad
name
Pad
No.
Pad
name
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
RS
VSS
RW_WR
VDD
E_RD
CSB
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VDD
VDD
VDD
VSS
VSS
VSS
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
V0
V0
VR
-3240
-3150
-3060
-2970
-2880
-2790
-2700
-2610
-2520
-2430
-2340
-2250
-2160
-2070
-1980
-1890
-1800
-1710
-1620
-1530
-1440
-1350
-1260
-1170
-1080
-990
-900
-810
-720
-630
-540
-450
-360
-270
-180
-90
0
90
180
270
360
450
540
630
720
810
900
990
1080
1170
1260
1350
1440
1530
1620
1710
1800
1890
1980
2070
-700
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
PS
VDD
IF
VSS
MI
VDD
RESETB
TEST
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
COMI1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM17
COM18
COM19
COM20
SEG1
2160
-700
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
SEG35
440
360
280
200
120
40
-40
-120
-200
-280
-360
-440
-520
-600
-680
-760
-840
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
440
360
280
200
120
40
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
2250
2340
2430
2520
2610
2700
2790
2880
2970
3060
3150
3240
3400
3400
3400
3400
3400
3400
3400
3400
3400
3400
3400
3400
3400
3160
3080
3000
2920
2840
2760
2680
2600
2520
2440
2360
2280
2200
2120
2040
1960
1880
1800
1720
1640
1560
1480
1400
1320
1240
1160
1080
1000
920
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-700
-520
-440
-360
-280
-200
-120
-40
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
COMI2
COM24
COM23
COM22
COM21
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
-920
-1000
-1080
-1160
-1240
-1320
-1400
-1480
-1560
-1640
-1720
-1800
-1880
-1960
-2040
-2120
-2200
-2280
-2360
-2440
-2520
-2600
-2680
-2760
-2840
-2920
-3000
-3080
-3160
-3400
-3400
-3400
-3400
-3400
-3400
-3400
-3400
-3400
-3400
-3400
-3400
-3400
40
120
200
280
360
440
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
94
95
96
97
98
99
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
VR
VOUT
VOUT
CAP2-
CAP2-
CAP2+
CAP2+
CAP1-
CAP1-
CAP1+
CAP1+
VEXT
VSS
VSS
VSS
REF
DIRS
VDD
VDD
VDD
CK
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
-40
-120
-200
-280
-360
-440
-520
840
760
680
600
VSS
520
5
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 3. Pin Description
Name
VDD
I/O
Description
Power supply
Power
Connect to MPU power supply pin.
VSS
0V (GND)
Bias voltage level for LCD driving
Voltages should have the following relationship;
V0 ³ V1 ³ V2 ³ V3 ³ V4 ³ VSS
When the built-in power circuit is active and internal 1/5 bias resistors are
used.
V0
V1
V2
V3
V4
V1
V2
V3
V4
LCD bias
(4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0
I/O
1/5 bias
When the built-in power circuit is active and internal 1/4 bias resistors are
used.
V1
V2
V3
V4
LCD bias
1/4 bias
(3/4) x V0
(2/4) x V0
(1/4) x V0
LCD DRIVER SUPPLY
Table 3. Pin Description (Continued)
Description
Name
I/O
CAP1+
CAP1-
CAP2+
CAP2-
VOUT
O
O
Capacitor + connecting pin for the internal voltage converter
Capacitor - connecting pin for the internal voltage converter
Capacitor + connecting pin for the internal voltage converter
Capacitor - connecting pin for the internal voltage converter
DC/DC voltage converter output (7.2V)
O
O
I/O
Voltage adjust pin
VR
I
I
This pin gives a voltage between V0 and VSS by resistance-division of
voltage.
External reference voltage for internal regulator (instead of the internal
VREF, 2V)
REF = "Low (VSS)": VEXT is not used (open).
REF = "High (VDD)": VEXT is reference input voltage of internal voltage
regulator.
VEXT
Select the input voltage of internal voltage regulator
REF = "Low (VSS)": The input voltage of internal
Voltage regulator is the internal VREF(2V).
REF
I
REF = "High (VDD)": The input voltage of internal
Voltage regulator is the voltage of VEXT.
6
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
SYSTEM CONTROL
Table 3. Pin Description (Continued)
Description
Name
I/O
External clock input. It must be fixed to "High" or "Low" when the internal
oscillation circuit is used. In case of the external clock mode, CK is used as the
clock and OS bit should be OFF.
CK
I
MPU interface selection input
MI = "Low": 80-series MPU
MI = "High": 68-series MPU
MI
I
I
Parallel / serial selection input
When PS = "Low": serial mode
When PS = "High": 4-bit / 8-bit bus mode
PS
Interface data length selection pin for parallel data input
When PS = "Low"
IF = "Low" or "High": serial interface mode
When PS = High
IF
I
I
IF = "Low": 4-bit bus mode
IF = "High": 8-bit bus mode
SEG direction selection input
When DIRS = "Low”
SEG1 ® SEG2 ® SEG79 ® SEG80
When DIRS = "High”
DIRS
SEG80 ® SEG79 ® SEG2 ® SEG1
MPU INTERFACE
Table 3. Pin Description (Continued)
Description
Name
I/O
Reset input
S6A0093 is initialized while RESETB is low.
RESETB
I
Chip selection input
S6A0093 is selected while CSB is low.
CSB
RS
I
I
Register selection input
When RS = "Low", instruction register
When RS = "High", data register.
In 80-series MPU interface mode
This pin is connected to WR pin of MPU and is a active low write signal
In 68-series MPU interface mode
This pin is connected to R/W pin of MPU
When RW_WR = "Low", write mode
RW_WR
E_RD
I
I
When RW_WR = "High", read mode
In 80-series MPU interface mode
This pin is connected to RD pin of MPU and is a active low read signal
In 68-series MPU interface mode
This pin is connected to E pin of MPU and enable read or write command
according to RW_WR signal.
7
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Table 3. Pin Description (Continued)
Name
I/O
Description
I/O
When 8-bit bus mode, used as bi-directional data bus DB0 ~ DB7
During 4-bit bus mode, only DB4 ~ DB7 are used.
DB0 ~ DB3
DB4 ~ DB5
DB6 (SCL),
DB7 (SI)
In this case DB0 ~ DB3 pins are not used.
When serial mode, DB6 (SCL) is used as serial clock input pin and DB7 (SI) is
used as serial data input pin.
LCD DRIVER OUTPUTS
Table 3. Pin Description (Continued)
Name
I/O
Description
O
Common signal output for driving LCD
COM1 ~ COM24
Common signal output for icon display
COMI1, COMI2
SEG1 ~ SEG80
TEST
O
O
These are the same signal but the name is different.
Segment signal output for driving LCD
Table 3. Pin Description (Continued)
Description
Name
I/O
Test pin
TEST
I
This pin is not used for normal operation.
TEST: Open
NOTE: DUMMY – These pins should be opened (floated).
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
FUNCTION DESCRIPTION
SYSTEM INTERFACE
S6A0093 has two kinds of interface type with MPU: bus mode, serial mode. Serial or bus mode is selected by PS pin.
In bus mode, 4-bit bus or 8-bit bus is selected by IF pin, and 68 series MPU or 80 series MPU is selected by MI pin.
Table 4. Various Kinds of MPU Interface according to PS, MI and IF
PS
MI
68 series
(H)
IF
8 bit (H) CSB
4 bit (L) CSB
8 bit (H) CSB
CSB
RS
RS
RS
RS
RS
RW_WR
R/W
E_RD
E
DB0
~
DB3
DB4
~
DB5
DB6
DB6
DB6
DB6
DB6
DB7
DB7
DB7
DB7
DB7
DB0~DB3
DB4~DB5
DB4~DB5
DB4~DB5
DB4~DB5
(1)
R/W
E
*
Bus mode
(H)
WR
RD
RD
DB0~DB3
80 series
(L)
4 bit (L)
CSB
WR
*
Serial
mode
(H)/(L)(2)
(H)/(L)
CSB
RS
(H)/(L)
(H)/(L)
SCL
SI
*
*
(L)
NOTES:
1. Don’ t care (high, low or open)
2. Fixed high (VDD) or low (VSS)
PS: "High" = bus mode, "Low" = serial mode
MI: "High" = 68-series MPU, "Low" = 80-series MPU
IF: "High" = 8 bit mode, "Low" = 4 bit mode (PS: "High")
CSB: "High" = chip is not selected, "Low" = chip is selected
RS: "High" = data register, "Low" = instruction register
RW_WR: Read / Write indicating signal in 68 mode or active low signal for enabling write in 80 mode
E_RD: Active high signal for enabling command is 68 mode or active low signal for enabling read in 80 mode.
SCL (DB6): Serial clock input
SI (DB7): Serial data input
9
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Interface with MPU in Parallel Mode (PS = "High")
During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data
register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM / ICONRAM and one
of these RAMs is selected by RAM address setting instruction. The Instruction register (IR) is used only to store
instruction code transferred from MPU. To select DR or IR register, RS input pin is used.
During reading operation, 8-bit register, output data register (OR) is used. The output data register (OR) is used as
temporary data storage place for being read from DDRAM / CGRAM / ICONRAM and one of these RAMs is selected
by RAM address setting instruction. After RAM address setting, first reading is a dummy cycle in 8-bit bus mode
(figure 3, 4). The valid data comes from second reading. In 4-bit bus mode, after RAM address setting, first and
second reading are dummy cycles (figure 5, 6). The valid data comes from third reading. The dummy read make the
address counter (AC) increased by 1. So it is recommended to set address again before writing. The instruction read
cycle is not supported and it is regarded as a no operation cycle.
In 4-bit bus mode, it is needed to transfer 4-bit data (through DB7~DB4) by two times. The high order bits (for 8-bit
mode DB7~DB4) are written before the low order bits (for 8-bit mode DB3~DB0) in write and low order bits (for 8-bit
mode DB3~DB0) are read before the high order bits (for 8-bit mode DB7~DB4) in read transaction. The DB0~DB3
pins are floated in this 4-bit bus mode. After RESETB resets, S6A0093 considers first 4-bit data from MPU as the
high order bits.
IF
MI
CSB
RS
RW_WR
E_RD
Valid
Data
DB7 DB0
~
Instruction
Write
NOP
Dummy
Read
RAM
Read
Data
Write
Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
10
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
IF
MI
CSB
RS
RW_WR
E_RD
Valid
Data
DB7 DB0
~
Instruction
Write
NOP
Dummy
Read
RAM
Read
Data
Write
Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
IF
MI
CSB
RS
RW_WR
E_RD
upper
4-bit
lower
4-bit
lower
4-bit
upper
4-bit
upper
4-bit
lower
4-bit
DB7 DB4
~
Instruction Write
NOP
Dummy Read
Data Write
Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)
IF
MI
CSB
RS
RW_WR
E_RD
upper
4-bit
lower
4-bit
lower
4-bit
upper
4-bit
upper
4-bit
lower
4-bit
DB7 DB4
~
Instruction Write
NOP
Dummy Read
RAM Read
Data Write
Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Interface with MPU in Serial Mode (PS = "Low")
When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, five ports, RESETB
(reset input), SCL (DB6, synchronizing transfer clock), SI (DB7, serial input data), RS (register selection input) and
CSB(chip selection input) are used.
By setting CSB to "Low", S6A0093 can receive SCL input. If CSB is set to "High", S6A0093 resets the internal 8-bit
shift register and 3-bit counter. Serial data is input in the order of "D7, D6, D5, D4, D3, D2, D1, D0" from the serial
data input pin (SI = DB7) at the rising edge of serial clock (SCL = DB6).
At the rising edge of the 8th serial clock, the serial data (D7-D0) is converted into 8 bit bus mode data. The RS input
of the DR/IR selection is latched at the rising edge of the 8th serial clock (SCL).
C S B
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
D 7
S I (D B 7 )
S C L ( D B 6 )
R S
1
2
3
4
5
6
7
8
9
Figure 7. Timing Diagram of Serial Data Transfer
12
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
ADDRESS COUNTER (AC)
Address Counter (AC) in S6A0093 stores DDRAM/ CGRAM/ ICONRAM address. After writing into or reading from
DDRAM / CGRAM / ICONRAM, AC is automatically increased by 1. The address counter is only one and stores the
address among DDRAM / CGRAM / ICONRAM.
DISPLAY DATA RAM (DDRAM)
DDRAM stores display data of maximum 64 x 8 bits (Max. 64 characters). DDRAM address is set in the address
counter (AC) as a hexadecimal number.
1st Ch.
16th Ch.
~
~
COM1
COM9
COM8
00
10
20
30
01
11
21
31
02
12
22
32
03
13
23
33
04
14
24
34
05
15
25
35
06
16
26
36
07
17
27
37
08
18
28
38
09
19
29
39
0A
1A
2A
3A
0B 0C 0D 0E
1B 1C 1D 1E
2B 2C 2D 2E
3B 3C 3D 3E
0F
1F
2F
3F
COM16
Hidden Line
Hidden Line
SEG1
SEG80
(1) 2 line mode DDRAM Address
~
~
COM1
COM9
COM8
00
10
20
30
01
11
21
31
02
12
22
32
03
13
23
33
04
14
24
34
05
15
25
35
06
16
26
36
07
17
27
37
08
18
28
38
09
19
29
39
0A
1A
2A
3A
0B 0C 0D 0E
1B 1C 1D 1E
2B 2C 2D 2E
3B 3C 3D 3E
0F
1F
2F
3F
COM16
~
COM17 COM24
Hidden Line
SEG1
SEG80
(2) 3 line mode DDRAM Address
Figure 8. DDRAM Address
CHARACTER GENERATOR ROM (CGROM)
CGROM has 5 x 8-dot 256 characters. The CG bit of the instruction table selects the 8 characters (00h ~ 07h) of
CGROM or CGRAM.
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Table 5. CGROM Character Code (00)
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
CHARACTER GENERATOR RAM (CGRAM)
CGRAM has up to 5 x 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used.
CGRAM can be written regardless of CG bit.
Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character code
DD/CGRAM address
CGRAM data
Pattern
number
(DDRAM data)
D7 D6 D5 D4 D3 D2 D1 D0
A6 A5 A4 A3 A2 A1 A0
P7 P6 P5 P4 P3 P2 P1 P0
1 0 0 0 0 0 0
- - - 0 1 0 1 0
- - - 1 0 1 0 1
- - - 0 1 0 1 0
- - - 1 0 1 0 1
- - - 0 1 0 1 0
- - - 1 0 1 0 1
- - - 0 1 0 1 0
- - - 1 0 1 0 1
1 0 0 0 0 0 1
1 0 0 0 0 1 0
1 0 0 0 0 1 1
1 0 0 0 1 0 0
1 0 0 0 1 0 1
1 0 0 0 1 1 0
1 0 0 0 1 1 1
0 0 0 0 0 0 0 0
(00h)
Pattern 1
1 0 0 1 0 0 0
1 0 0 1 0 0 1
1 0 0 1 0 1 0
1 0 0 1 0 1 1
1 0 0 1 1 0 0
1 0 0 1 1 0 1
1 0 0 1 1 1 0
1 0 0 1 1 1 1
- - - 0 0 0 0 0
- - - 1 1 1 1 1
- - - 0 0 0 0 0
- - - 1 1 1 1 1
- - - 0 0 0 0 0
- - - 1 1 1 1 1
- - - 0 0 0 0 0
- - - 1 1 1 1 1
0 0 0 0 0 0 0 1
(01h)
Pattern 2
Pattern 3
Pattern 4
1 0 1 0 0 0 0
1 0 1 0 0 0 1
1 0 1 0 0 1 0
1 0 1 0 0 1 1
1 0 1 0 1 0 0
1 0 1 0 1 0 1
1 0 1 0 1 1 0
1 0 1 0 1 1 1
- - - 0 1 0 1 0
- - - 0 1 0 1 0
- - - 0 1 0 1 0
- - - 0 1 0 1 0
- - - 0 1 0 1 0
- - - 0 1 0 1 0
- - - 0 1 0 1 0
- - - 0 1 0 1 0
0 0 0 0 0 0 1 0
(02h)
1 0 1 1 0 0 0
1 0 1 1 0 0 1
1 0 1 1 0 1 0
1 0 1 1 0 1 1
1 0 1 1 1 0 0
1 0 1 1 1 0 1
1 0 1 1 1 1 0
1 0 1 1 1 1 1
- - - 0 1 1 1 0
- - - 1 0 1 0 1
- - - 1 1 0 1 1
- - - 1 0 1 0 1
- - - 0 1 1 1 0
- - - 1 1 1 1 1
- - - 1 1 1 1 1
- - - 1 1 1 1 1
0 0 0 0 0 0 1 1
(03h)
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) (continued)
Character code
DD/CGRAM address
CGRAM data
Pattern
number
(DDRAM data)
D7 D6 D5 D4 D3 D2 D1 D0
A6 A5 A4 A3 A2 A1 A0
P7 P6 P5 P4 P3 P2 P1 P0
1 1 0 0 0 0 0
1 1 0 0 0 0 1
1 1 0 0 0 1 0
1 1 0 0 0 1 1
1 1 0 0 1 0 0
1 1 0 0 1 0 1
1 1 0 0 1 1 0
1 1 0 0 1 1 1
- - - 1 1 0 1 1
- - - 1 0 0 0 1
- - - 0 0 0 0 0
- - - 1 0 0 0 1
- - - 1 1 0 1 1
- - - 1 1 1 1 1
- - - 1 1 1 1 1
- - - 1 1 1 1 1
0 0 0 0 0 1 0 0
(04h)
Pattern 5
Pattern 6
Pattern 7
Pattern 8
1 1 0 1 0 0 0
1 1 0 1 0 0 1
1 1 0 1 0 1 0
1 1 0 1 0 1 1
1 1 0 1 1 0 0
1 1 0 1 1 0 1
1 1 0 1 1 1 0
1 1 0 1 1 1 1
- - - 1 1 1 1 1
- - - 1 1 1 1 1
- - - 0 0 0 0 0
- - - 0 0 0 0 0
- - - 1 1 1 1 1
- - - 1 1 1 1 1
- - - 0 0 0 0 0
- - - 0 0 0 0 0
0 0 0 0 0 1 0 1
(05h)
1 1 1 0 0 0 0
1 1 1 0 0 0 1
1 1 1 0 0 1 0
1 1 1 0 0 1 1
1 1 1 0 1 0 0
1 1 1 0 1 0 1
1 1 1 0 1 1 0
1 1 1 0 1 1 1
- - - 0 0 1 1 0
- - - 0 0 1 1 0
- - - 0 0 1 1 0
- - - 0 0 1 1 0
- - - 0 0 1 1 0
- - - 0 0 1 1 0
- - - 0 0 1 1 0
- - - 0 0 1 1 0
0 0 0 0 0 1 1 0
(06h)
1 1 1 1 0 0 0
1 1 1 1 0 0 1
1 1 1 1 0 1 0
1 1 1 1 0 1 1
1 1 1 1 1 0 0
1 1 1 1 1 0 1
1 1 1 1 1 1 0
1 1 1 1 1 1 1
- - - 0 0 0 0 0
- - - 1 0 0 0 1
- - - 1 1 0 1 1
- - - 1 0 0 0 1
- - - 0 0 0 0 0
- - - 1 0 0 0 1
- - - 1 1 0 1 1
- - - 1 1 1 1 1
0 0 0 0 0 1 1 1
(07h)
NOTE: "-" - Don’ t care
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
SEGMENT ICON RAM (ICONRAM)
ICONRAM has segment control data and segment pattern data. COMI1 and COMI2 are the same signal but the
name is different. So the icons on the same SEG are displayed at the same time. The number of icons is 80.
COMI 1
COMI 2
Figure 9. Relationship between ICONRAM and Icon Display
Table 7. Relationship between ICONRAM Address and Display Pattern
ICONRAM bits
ICONRAM address
D7
D6
D5
D4
S1
D3
S2
D2
S3
D1
S4
D0
S5
00h
01h
02h
-
-
-
-
-
-
-
-
-
S6
S7
S8
S9
S10
S15
S11
S12
S13
S14
.
.
.
.
-
.
.
-
.
.
-
.
.
.
.
.
.
.
.
.
.
0Dh
S66
S67
S68
S69
S70
0Eh
0Fh
-
-
-
-
-
-
S71
S76
S72
S77
S73
S78
S74
S79
S75
S80
NOTE: "-" - Don’ t care
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
LOW POWER CONSUMPTION MODE
S6A0093 provides with sleep mode for saving power consumption during standby period.
Sleep Mode (Power Save Bit ON, Oscillation Bit OFF)
To enter the sleep mode, the power circuit and oscillation circuit should be turned off by using the power save
command and the power control command. This mode helps to save power consumption by reducing current to
reset level.
1. Liquid Crystal Display Output
COM1 ~ COM24, COMI1, COMI2: VSS level
SEG1 ~ SEG80: VSS level
2. Data written in DDRAM, CGRAM, ICONRAM and registers are remained as previous value.
3. Operation mode is retained the same as it was prior to execution of the sleep mode.
All internal circuits are stopped.
4. Power Circuit and Oscillation Circuit
The built-in power supply circuit and oscillation circuit are turned off by power save command and
power control command.
LCD DRIVER CIRCUIT
LCD Driver circuit has 26 common and 80 segment signals for driving LCD. Data from ICONRAM/ CGRAM/
CGROM are transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. In case of
2-line display mode, COM1 ~ COM16, COMI1 and COMI2 have 1/17 duty, and in 3-line mode, COM1 ~ COM24,
COMI1 and COMI2 have 1/25 duty ratio. SEG bi-directional function is selected by DIRS input pin, and COM shift
direction is selected by function set instruction "S" bit.
Table 8. SEG Data Shift Direction
DIRS pin
Low
SEG data shift direction
SEG1
®
SEG2 ® SEG3
.... …………………….............. SEG78 ®
SEG79 ®
SEG2 ®
SEG80
SEG1
High
SEG80
®
SEG79 SEG78
®
....... …………………........... SEG3
®
Table 9. COM Data Shift Direction
COM data shift direction
Line
mode
S
0 (left)
1 (right)
0 (left)
COM1 ® COM2 ...... ………….... COM15 ® COM16 ® COMI1 (COMI2)
COMI1 (COMI2) ® COM16 ® COM15 .... ………….. ...... COM2 ® COM1
COM1 ® COM2 ... …………....... COM23 ® COM24 ® COMI1 (COMI2)
COMI1 (COMI2) ® COM24 ® COM23 ..... ……………. .. COM2 ® COM1
2-line
mode
3-line
mode
1 (right)
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
INSTRUCTION DESCRIPTION
Table 10. Instruction Table
Instruction
RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
DDRAM address is set to 00h from AC and the cursor returns
to 00h position
Return
home
0
0
0
0
0
0
0
1
-
The contents of DDRAM are not changed.
Double height mode
DH2, DH1 = 00: normal display (default)
01: COM1 ~ COM16 is a double height,
COM17~COM24 is normal
10: 1) 2-line mode : normal display
2) 3-line mode : COM1~COM8 is normal,
COM9 ~ COM24 is a double
height
Double
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
DH2 DH1
height mode
11: normal display
Power save / oscillation circuit ON / OFF
Power
save
OS
PS OS = 0: oscillator OFF (default) 1: oscillator ON
PS = 0: power save OFF (default) 1: power save ON
Display line mode
N = 0: 2-line display mode (default) 1: 3-line display mode
shifting direction of COM.
S = 0: 1) 2-line mode: COM1 -> COM16 (default)
Function
set
N
S
CG
2) 3-line mode: COM1 -> COM24 (default)
1: 1) 2-line mode: COM16 -> COM1
2) 3-line mode: COM24 -> COM1
Select CGRAM or CGROM
CG = 0: CGROM (default) 1: CGRAM
Determination of the DDRAM line which is displayed at the first
line at LCD
LS2, LS1 = 00: DDRAM line 1 shows at the first line of
LS2 LS1 LCD (default).
Line shift
mode
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
01: DDRAM line 2 shows at the first line of LCD.
10: DDRAM line 3 shows at the first line of LCD.
11: DDRAM line 4 shows at the first line of LCD
Determination of bias
BS = 0: 1/5 bias (default)
1: 1/4 bias
Bias control
-
BS
LCD power control
VC = 0: voltage converter OFF (default)
1: voltage converter ON
Power
control
VC
VR
VF VR = 0: voltage regulator OFF (default)
1: voltage regulator ON
VF = 0: voltage follower OFF (default)
1: voltage follower ON
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Table 10. Instruction Table (Continued)
Instruction
RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description
Cursor / blink / display ON / OFF
Display
control
C = 0: cursor OFF (default), 1: cursor ON
B = 0: blink OFF (default), 1: blink ON
D = 0: display OFF (default), 1: display ON
0
0
0
1
0
1
C
B
D
DD/CGRAM
address
set
DDRAM / CGRAM address
0
0
1
0
AC6 AC5 AC4 AC3 AC2 AC1 AC0 range: DDRAM 00h ~ 3Fh
CGRAM 40h ~ 7Fh
ICONRAM
address
set
ICONRAM address, electronic volume and test byte address
IA0 range: ICONRAM 00h ~ 0Fh
EV 10h (electronic volume byte), TE 11h (test byte)
1
0
IA4
IA3
IA2
IA1
Write
Data
1
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0 Write DDRAM / CGRAM / ICONRAM
Read
Data
D0 Read DDRAM / CGRAM / ICONRAM or registers data
(NOTE1)
NOP
Test
0
0
0
0
0
0
0
1
0
1
0
*
0
*
0
*
0
*
Non-operation Instruction
Don’ t use this Instruction.
NOTES:
1. "-": Don’ t care
2. "*": Don’ t use
3: Instruction execution time depends on the internal process time of S6A0093, therefore it is necessary to provide a time larger
than one MPU interface cycle time (tc) between execution of two successive instructions.
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Return Home
S6A0093
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
-
Return Home instruction field makes cursor return home.
DDRAM address is set to 00h from AC and the cursor returns to 00h position. The contents of DDRAM are not
changed.
Double Height Mode
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
0
DH2
DH1
Double Height mode instruction field selects double height line type.
DH2, DH1 = 00: normal display line mode (default)
01: COM1 ~ COM16 is a double height,
COM17 ~ COM24 is normal
10: 1) 2-line mode: normal display
2) 3-line mode: COM1 ~ COM8 is normal
COM9 ~ COM24 is a double height
11: normal display
Figure 10. 3 Line Normal Mode Display (DH2, DH1 = 00)
Figure 11. COM1 ~ 16 is a Double Height Line, COM17 ~ 24 is Normal (DH2, DH1 = 01)
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Figure 12. COM1 ~ 8 is Normal, COM9 ~ COM24 is a Double Height Line (DH2, DH1 = 10)
Figure 13. 2-line Normal Mode Display (DH2, DH1 = 00)
Figure 14. COM1 ~ 16 is a Double Height Line (DH2, DH1 = 01)
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Power Save Set
S6A0093
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
1
OS
PS
Power Save instruction field is used to control the oscillator and to set or to reset the power save mode.
OS: oscillator ON / OFF control Bit
When OS = "High", oscillator is turned ON
When OS = "Low", oscillator is turned OFF (default)
PS: power save ON / OFF control bit
When PS = "High", power save mode is turned ON
When PS = "Low", power save mode is turned OFF (default)
Function Set
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
0
N
S
CG
N: display line mode Instruction field selects 2 line or 3 line display mode
When N = "High", 3 line display mode
When N = "Low", 2 line display mode (default)
S: data shift direction of common
S sets the shift direction of common display data
When S = "High", COM right shift
When S = "Low", COM left shift (default)
(refer to table 9)
CG: CGRAM enable bit
When CG = "High", CGRAM can be accessed and you can use this RAM for eight
special character area. (00h - 07h = CGRAM font display)
When CG = "Low", CGRAM is disabled. CGROM (00h~07h) can be accessed and
the additional current consumption is saved by using this mode (default).
(00h - 07h = CGROM font display)
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Line Shift Mode
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
0
LS2
LS1
Line Shift mode instruction field selects the DD RAM to be displayed in first line.
LS2, LS1 = 00: DDRAM line 1 shows at the first line of LCD (default).
01: DDRAM line 2 shows at the first line of LCD.
10: DDRAM line 3 shows at the first line of LCD.
11: DDRAM line 4 shows at the first line of LCD.
LCD
LCD
LCD
LCD
DD RAM Line1 (00h~0Fh)
DD RAM Line2 (10h~1Fh)
DD RAM Line3 (20h~2Fh)
DD RAM Line4 (30h~3Fh)
DD RAM Line1 (00h~0Fh)
DD RAM Line2 (10h~1Fh)
DD RAM Line2 (10h~1Fh)
DD RAM Line3 (20h~2Fh)
DD RAM Line3 (20h~2Fh)
DD RAM Line4 (30h~3Fh)
DD RAM Line4 (30h~3Fh)
DD RAM Line1 (00h~0Fh)
DD RAM Line4 (30h~3Fh)
LS2, LS1 = 00
DD RAM Line1 (00h~0Fh)
LS2, LS1 = 01
DD RAM Line2 (10h~1Fh)
LS2, LS1 = 10
DD RAM Line3 (20h~2Fh)
LS2, LS1 = 11
Figure 15. Line Shift Mode Display at 3 Line LCD
LCD
LCD
LCD
LCD
DD RAM Line1 (00h~0Fh)
DD RAM Line2 (10h~1Fh)
DD RAM Line3 (20h~2Fh)
DD RAM Line4 (30h~3Fh)
DD RAM Line2 (10h~1Fh)
DD RAM Line3 (20h~2Fh)
DD RAM Line4 (30h~3Fh)
DD RAM Line1 (00h~0Fh)
DD RAM Line3 (20h~2Fh)
DD RAM Line4 (30h~3Fh)
DD RAM Line4 (30h~3Fh)
DD RAM Line1 (00h~0Fh)
DD RAM Line1 (00h~0Fh)
DD RAM Line2 (10h~1Fh)
DD RAM Line2 (10h~1Fh)
DD RAM Line3 (20h~2Fh)
LS2, LS1 = 00
LS2, LS1 = 01
LS2, LS1 = 10
LS2, LS1 = 11
Figure 16. Line Shift Mode Display at 2 Line LCD
Bias Control
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
1
-
BS
Bias Control instruction field sets LCD bias voltages generated internally.
This bit is used when the internal voltage follower is ON.
BS = 0: 1/5 bias (default)
1: 1/4 bias (V2 = V3)
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Power Control Set
S6A0093
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
0
VC
VR
VF
Power Control instruction field sets voltage regulator/ converter/ follower on / off.
VC: voltage converter circuit control bit
When VC= "High", voltage converter is turned ON.
When VC = "Low", voltage converter is turned OFF (default).
VR: voltage regulator circuit control bit
When VR = "High", voltage regulator is turned ON.
When VR = "Low", voltage regulator is turned OFF (default).
VF: voltage follower circuit control bit
When VF = "High", voltage follower is turned ON.
When VF = "Low", voltage follower is turned OFF (default).
*NOTE: The oscillation circuit must be turned on for the voltage converter circuit to be active.
Display Control
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
0
1
C
B
D
Display Control instruction field controls cursor / blink / display ON / OFF.
C: cursor ON / OFF control bit
When C = "High", cursor is turned ON.
When C = "Low", cursor is disappeared in current display (default).
B: cursor blink ON / OFF control bit
When C = "High" and B = "High", S6A0093 make LCD alternate between inverting display character and normal
display character at the cursor position with about a half second.
On the contrary, if C = "Low", only a normal character is displayed regardless of "B" flag.
When B = "Low", blink is OFF (default).
D: display ON / OFF control bit
When D = "High", entire display is turned ON.
When D = "Low", display is turned OFF, but display data are remained in DDRAM (default).
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Table 11. Cursor Attributes
C, B
Display state
1, 0
1, 1
(Blinking mode)
0, 0
0, 1
DD/CG RAM Address Set
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
DD/CG RAM Address Set instruction field sets DDRAM / CGRAM address.
Before writing / reading data into / from the RAM, set the address by RAM Address Set instruction. Next, when data
are written / read in succession, the address is automatically increased by 1. After accessing 7Fh, the address of AC
is 00h.
The address ranges are 00h ~ 7Fh.
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
Table 12. DD/CG RAM Address Mapping
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
00h
10h
20h
30h
40h
50h
60h
70h
DDRAM line 1 (00h ~ 0Fh)
DDRAM line 2 (10h ~ 1Fh)
DDRAM line 3 (20h ~ 2Fh)
DDRAM line 4 (30h ~ 3Fh)
CGRAM (pattern 0)
CGRAM (pattern 2)
CGRAM (pattern 4)
CGRAM (pattern 6)
CGRAM (pattern 1)
CGRAM (pattern 3)
CGRAM (pattern 5)
CGRAM (pattern 7)
ICONRAM Address Set
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
0
IA4
IA3
IA2
IA1
IA0
ICONRAM Address Set instruction field sets ICONRAM / Registers address.
Before writing/reading data into/from the ICON RAM, set the address by ICONRAM Address Set instruction. Next,
when data are written/read in succession, the address is automatically increased by 1. The 5 icons at a time can
blink, if C and B bits of the display instructions are enabled. The blink attributes of ICON are same as the cursor blink.
For accessing DD/CGRAM, the DD/CGRAM Address Set instruction should be set before. After accessing 0Fh, the
address of ICONRAM address is 00h. The ICONRAM address ranges are 00h ~ 1Fh.
Table 13. ICONRAM Address Mapping
Address
00h
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ICON RAM (00h ~ 0Fh)
10h
EV TE
Reserved
EV: electronic volume register (10h) - default (00000)
TE: test register (Do not use) (11h)
When the EV and TE registers are written, the address counter (AC) is not increased.
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Write Data
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
D7
D6
D5
D4
D3
D2
D1
D0
This instruction field make S6A0093 write binary 8-bit data to DDRAM / CGRAM / ICONRAM or register. The RAM
address to be written into is determined by previous DD/CGRAM Address Set or ICONRAM Address Set instruction.
After writing operation, the address is automatically increased by 1.
Read Data
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
D7
D6
D5
D4
D3
D2
D1
D0
DDRAM / CGRAM / ICONRAM data read instruction.
Each RAM is selected by address set instruction. And then you can read the RAM data. You can get correct RAM
data from second read transaction. The first read data after setting RAM address is dummy data, so the correct RAM
data come from the second read transaction. After reading operation, the address is increased by 1 automatically.
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
INITIALIZING & POWER SAVE MODE SETUP
HARDWARE RESET
When RESETB pin = "Low", S6A0093 can be initialized as the following state.
(1) Control display ON / OFF instruction
C = 0: cursor OFF
B = 0: blink OFF
D = 0: display OFF
(2) Power save set instruction
OS = 0: oscillator OFF
PS = 0: power save OFF
(3) Power control set instruction
VR = 0: voltage regulator OFF
VC = 0: voltage converter OFF
VF = 0: voltage follower OFF
(4) Function set instruction
N
S
= 0: 2 line display mode
= 0: COM left shift
CG = 0: CGRAM is not used.
(5) Return Home
Address counter = 00h
(6) Electronic contrast control register: 10h = (0, 0, 0, 0, 0)
(7) In case of 4-bit interface mode selection
S6A0093 considers the first 4-bit data from MPU as the high order bits.
*NOTE: If initialization is not done by the RESETB pin at application, unknown condition might result. Then
you can initialize by instruction.
VDD
tRESETB
RESETB
tRW
RESET pulse width
RESET start time
tRW
10ms
tRESETB
50ns
Figure 17. RESET Timing
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
INITIALIZING AND POWER SAVE SETUP
Initializing by Instruction
VDD-VSS Power ON
Keep RESETB Pin = "L"
When the power is stable,
release the reset state (RESETB = "H").
NOTE:
At command 5 and 6, the internal RAM
should be cleared.
Waiting for 10us or more
To clear DDRAM, Set address at 00h (first
DDRAM) and then write 20h (space
character code) 64 times
Command Input
1. Function Set (N, S, CG)
2. Electronic Volume Register Setup (ICONRAM 10h)
3. Power Save (PS: Power Save OFF, OS: OSC ON)
4. Power Control (VC, VR, VF are all ON)
To clear CGRAM, set address at 40h (first
CGRAM) and then write 00h (null data) 64 times
To clear ICONRAM, set ICONRAM address at
00h (first ICONRAM) and then write 00h (null
data) 16 times.
Waiting for 20ms or more
Command Input
5. RAM Address Set
Command Input
6. Data Writing (RAM Clear)
(DDRAM = 20h, CG/ICONRAM = 00h)
Command Input
7. Display Control (D: ON)
End of Initialization
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80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
Sleep Mode Set or Release by Instruction
a) Sleep Mode Set
End of Initialization
Normal Operation Status
(Power save is OFF and Oscillator is ON.)
Command Input
1. Display Control (D: OFF)
2. Power Save (PS: Power Save ON, OS: OSC OFF)
3. Power Control (VC, VR, VF are all OFF)
Enter the Sleep Mode
b) Sleep Mode Release
Sleep Mode
Command Input
1. Power Save (PS: Power Save OFF, OS: OSC ON)
2. Power Control (VC, VR, VF are all ON)
Waiting for 20ms or more
Command Input
3. Display Control (D: ON)
Return to Normal Operation
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Recommendation of Power ON / OFF Sequence
a) Power ON Sequence
Power ON
Voltage Converter ON
[VC, VR, VF = 1, 0, 0]
Waiting for ³ 1ms
Voltage Regulator ON
[VC, VR, VF = 1, 1, 0]
Waiting for ³ 1ms
Voltage Follower ON
[VC, VR, VF = 1, 1, 1]
Operation Command Input
b) Power OFF Sequence
Operation Command Input
Display OFF
Voltage Regulator OFF
[VC, VR, VF = 1, 0, 1]
Waiting for ³ 50ms
Voltage Follower OFF
[VC, VR, VF = 1, 0, 0]
Waiting for ³ 1ms
Voltage Converter OFF
[VC, VR, VF = 0, 0, 0]
Waiting for ³ 1ms
Operation Command Input
32
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
LCD DRIVING POWER SUPPLY CIRCUIT
The Power Supply Circuit produces LCD panel driving voltage at low power consumption. The LCD Driving Power
Supply circuit consists of Voltage converter, Voltage regulator, and Voltage follower. It is controlled by power control
instruction. Table 14 shows how the LCD Driving Power Supply circuit works by power control instruction sets.
Table 14. Power Supply Control Mode Set
Voltage
converter
Voltage
regulator
Voltage
follower
V0, V1, V2,
V3, V4 pin
VC VR VF
VOUT pin
VR pin
Internal
voltage
output
Used for
voltage
adjustment
Internal voltage output
1 1 1
Enable
Disable
Enable
Enable
Enable
Enable
External
voltage
input
Used for
voltage
adjustment
Internal voltage output
0 1 1
V1~V4: internal voltage
output
V0: external voltage input
0 0 1
0 0 0
Disable
Disable
Disable
Disable
Enable
Disable
Open
Open
Open
V0~V4: external voltage
Open
input
NOTE: SEC recommendation is to use only the case listed above table.
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
VOLTAGE CONVERTER
The Voltage Converter circuit generates positive 4-time voltage of 1.8V that is generated internally. VOUT is
generated from the voltage converter. And this conversion voltage is used in the built-in Voltage regulator circuit.
This application circuit is same as 3-times DC/DC converter.
DD
V
S6A0093
VOUT
VDD
-
+
-
CAP1+
CAP1-
CAP2+
CAP2-
VOUT
+
4 x 1.8V = 7.2V
+
-
1.8V
(Internal)
SS
V
Figure 18. DC/DC Converter Output and Circuit
34
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
VOLTAGE REGULATOR
The Voltage Regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained by
adjusting resistors Ra and Rb as shown in equation (1) or (2), and by setting electronic contrast control data bits, see
equation (3) or (4).
The potential of V0 Pin can be adjusted within VOUT - VREF. VREF is the internal constant voltage source of the chip
and this value is 2.0V in the condition VDD ³ 2.4V
The REF selects which voltage is used for voltage regulator between the external VEXT and the internal VREF.
n
Voltage regulation by adjusting resistors Ra, Rb
When REF is "Low"
When REF is "High"
Rb
Rb
V0 = ( 1 +
Ra
V0 = ( 1 +
) x VREF --- (1)
) x VEXT --- (2)
Ra
The internal VREF of voltage regulator has the temperature compensation function, and the temperature coefficient
is about 0.0%/°C.
Rb
VOUT
VR
V0
_
VEXT
REF
Ra
VREF
Inside Chip
VSS
GND
Figure 19. Voltage Regulator Circuit
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
ELECTRONIC CONTRAST CONTROL (32 STEPS)
Electronic Contrast Control data bits is 10h = (C4, C3, C2, C1, C0). Voltage regulation is adjusted as 32-contrast
step according to the value of Electronic Contrast Control data bits. LCD drive voltage V0 has one of 32 voltage
values if 5-bit data is set to the electronic contrast control register (ICONRAM address 10h). When using the
Electronic Contrast Control function, you need to turn the voltage regulators on using power control instruction.
When REF = "Low"
V0 = ( 1 +
When REF = "High"
Rb
Ra
Rb
V0 = ( 1 +
Ra
) x VEV --- (3)
) x VEV --- (4)
VEV = VREF - na (n = 0, 1, 2, ..., 30, 31)
a = VREF / 150
VEV = VEXT - na (n = 0, 1, 2, ..., 30, 31)
a = VEXT / 150
Table 15. Electronic Contrast Control Register
C7 C6 C5 C4 C3 C2 C1 C0
No.
V0
Contrast
na
1
2
-
-
-
-
.
-
-
-
-
.
-
-
-
-
.
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
1
1
.
0
1
0
1
.
0a (default)
Maximum
High
1a
2a
3a
.
.
.
3
.
.
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
31
32
-
-
-
-
-
-
1
1
1
1
1
1
1
1
0
1
30 a
31a
Minimum
Low
("-": Don’ t care)
36
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
Rb
VOUT
VR
V0
_
+
VEXT
Ra
REF
VREF
+
VEV
-
Inside Chip
VSS
GND
Figure 20. Electronic Contrast Control Circuit
37
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
VOLTAGE GENERATOR CIRCUIT
VDD
-
VDD
CAP1+
CAP1-
CAP2+
CAP2-
C1
C1
C1
+
VOUT
VR
Rb
Ra
GND
-
+
C2
V0
V1
V2
V3
C2
C2
C2
C2
V4
VSS
GND
C1: 0.1 ~ 4.7uF
C2: 0.1 ~ 4.7uF
Figure 21. When Built-in Power Supply is used (VC, VR, VF = 1, 1, 1)
VDD
VDD
VDD
VDD
VDD
VDD
CAP1+
CAP1-
CAP2+
CAP2-
CAP1+
CAP1-
CAP2+
CAP2-
CAP1+
CAP1-
CAP2+
CAP2-
External
Power
Supply
VOUT
VOUT
VOUT
GND
VR
VR
VR
Rb
Ra
GND
- +
C2
- +
External
Power
Supply
V0
V1
V2
V0
V1
V2
V3
V0
V1
V2
External
Power
C2
C2
C2
C2
V3
V4
Supply
V3
V4
V4
VSS
VSS
VSS
GND
GND
GND
(VC, VR, VF = 0, 1, 1)
(VC, VR, VF = 0, 0, 1)
(VC, VR, VF = 0, 0, 0)
All capacitor is C2.
C2: 0.1 ~ 4.7uF
Figure 22. When External Power Supply is used
38
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
MPU INTERFACE
VCC
A0
RS
VDD
PS
MI
A1-A7
IORQ
CSB
Decoder
S6A0093
RD
WR
E_RD
MPU
RW_WR
DB[0:7]
RESETB
D0-D7
RES
IF
GND
VSS
RESETB
Figure 23. Parallel Interfacing with 8080-series Microprocessors
VCC
A0
RS
VDD
PS
MI
A1-A7
VMA
CSB
Decoder
S6A0093
R/W
E
RW_WR
E_RD
MPU
D0-D7
RES
DB[0:7]
RESETB
IF
GND
VSS
RESETB
Figure 24. Parallel Interfacing with 6800-series Microprocessors
39
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
VCC
PORT4
PORT3
RS
VDD
VDD
CSB
or VSS
S6A0093
MI
IF
E_RD
RW_WR
MPU
PORT1
PORT2
RES
SCL(DB6)
SI(DB7)
PS
RESETB
GND
VSS
RESETB
Figure 25. Clock Synchronized Serial Interfacing with any Microprocessors
40
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
APPLICATION INFORMATION FOR LCD PANEL
Chip Bottom & Lower View (S bit = "0", DIRS = "0")
................................................
C
C
C
C
C
C
C
C
C
C
C
C
C
O
O
O
O
O
O
O
O
O
O
O
O
O
M
M
M
M
M
M
M
M
M
M
M
M
M
2
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
C
O
M
M
I2
4
3
2
1
6
5
4
3
2
1
0
9
C
O
2
2
2
2
1
1
1
1
1
1
1
M
C
C
C
C
C
C
C
C
C
C
O
O
O
O
O
O
O
O
O
O
M
M
M
M
M
M
M
M
M
M
B O T T O M V IE W
I1
C
O
Chip Bottom & Upper View (S bit = "1", DIRS = "1")
C
C
C
C
C
C
C
C
C
C
C
C
C
O
O
O
O
O
O
O
O
O
O
O
O
O
M
M
M
M
M
M
M
M
M
M
M
M
M
9
1
1
1
1
1
1
1
2
2
2
2
C
C
O M I 1
0
1
2
3
4
5
6
1
2
3
4
O
M
1
2
3
4
5
6
7
8
7
8
9
0
C
C
C
C
C
C
C
O
O
O
O
O
O
O
M
M
M
M
M
M
M
1
B O T T O M V IE W
C
C
C
C
O M
O
O
O
M
M
M
1
1
2
................................................
I
2
41
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Chip Top & Lower View (S bit = "0", DIRS = "1")
................................................
C
C
C
C
O
O
O
O
M
M
M
M
2
1
1
0
9
8
7
8
7
6
5
4
3
2
1
I1
C
C
C
C
C
C
C
C
C
C
C
C
C
O
O
O
O
O
O
O
O
O
O
O
O
O
M
M
M
M
M
M
M
M
M
M
M
M
M
I2
2
2
2
2
1
1
1
1
1
1
1
9
4
3
2
1
6
5
4
3
2
1
0
1
C
O
M
M
M
M
M
M
M
M
C
C
C
C
C
C
C
O
O
O
O
O
O
O
T O P
V IE W
C
O M
Chip Top & Upper View (S bit = "1", DIRS = "0")
C
C
O
M
I
1
1
2
3
4
5
6
7
8
7
8
9
0
C
C
C
C
C
C
C
C
C
C
C
C
C
O
O
O
O
O
O
O
O
O
O
O
O
O
M
M
M
M
M
M
M
M
M
M
M
M
M
I 2
O
O
O
O
O
O
O
O
M
M
M
M
M
M
M
M
1
2
4
3
2
1
6
5
4
3
2
1
0
C
C
C
C
C
C
C
O
O
O
O
2
2
2
1
1
1
1
1
1
1
9
T O P
V IE W
C
C
C
C
M
M
M
M
1
1
2
................................................
42
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
FRAME FREQUENCY
1/17 Duty (2-line mode)
1-line selection period
1
2
. . . . . . 16 17 1
2
. . . . . . 16 17 1
2
. . . . . . 16 17 1
2
. . . . . . 16 17
V0
V1
COM1
V4
VSS
1 Frame
1 Frame
1-line Selection Period = 16 Clocks
One Frame
= 16 x 17 x 36.8 ms = 10.0 ms (1 Clock = 36.8 ms at fOSC =27.2 kHz)
Frame Frequency
= 1 / 10.0 ms = 100 Hz
1/25 Duty (3-line mode)
1-line selection period
2 . . . . . . . . . . . . .
24 25 1
2
. . . . . . . . . . . . .
24 25 1 2 . . . . . . . . . .
1
V0
V1
COM1
V4
VSS
1 Frame
1 Frame
1-line Selection Period = 16 Clocks
One Frame
= 16 x 25 x 25 ms = 10.0 ms (1 Clock = 25 ms at fOSC =40 kHz)
Frame Frequency
= 1 / 10.0 ms = 100 Hz
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
MAXIMUM ABSOLUTE RATINGS
Table 16. Maximum Absolute Ratings
Symbol Value
-0.3 to + 7.0
Characteristic
Power supply voltage (1)
Power supply voltage (2)
Power supply voltage (3)
Input voltage
Unit
V
VDD
VOUT, V0
V1, V2, V3, V4
VIN
-0.3 to + 8.0
-0.3 to V0
V
V
-0.3 to VDD+0.3
-30 to +85
V
Operating temperature
TOPR
oC
oC
Storage temperature
TSTG
-55 to +125
NOTES:
1. All the voltage levels are based on VSS = 0V.
2. Voltage greater than above may damage the circuit.
Voltage level: VOUT ³ V0 ³ VDD ³ VSS
3. Voltage level: V0 ³ V1 ³ V2 ³ V3 ³ V4 ³ VSS
44
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Table 17. DC Characteristics
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
V
Operating voltage
VDD
-
2.4
-
3.6
Display operation
VLCD = 6V without load
No access from MPU
IDD1
-
-
80
Supply current
(VDD = 3V,
Ta = 25 oC)
mA
Access operation from MPU
(fcyc = 200kHz)
IDD2
-
-
-
-
500
5
Sleep operation without load
oscillator OFF, power save ON
IDDS1
VIH
VIL
-
-
0.7VDD
VSS
VDD
Input voltage (1)
Output voltage
V
V
0.3VDD
VDD-
0.4
VOH
IOH = -1mA, VDD = 2.4V
VOL
IIZ
IOL = 1mA, VDD = 2.4V
VIN = 0V to VDD
VIN = 0V to VDD
Io = ±50mA
0.4
1
mA
mA
Input leakage current
Output leakage current
-1
-3
-
-
IOZ
3
RCOM
RSEG
-
-
5
RON resistance
kW
Io = ±50mA
-
10
Frame frequency
(internal OSC)
fFR
VEF
VDD = 3V, Ta = 25 oC
70
95
100
99
130
-
Hz
%
V
Conversion
RL = ¥
efficiency
Voltage
converter
Output
voltage
VOUT
Ta = 25 oC, C = 1mF
6.9
7.2
7.5
Voltage regulator
reference voltage
VREF
VLCD
Ta = 25 oC
1.94
4.0
2.0
-
2.06
6.0
V
LCD driving voltage
VLCD = V0 - VSS
NOTE:
1. RESETB pin is schmitt input (0.8VDD £ VIH £ VDD, VSS £ VIL £ 0.2VDD).
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S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Table 18. DC Characteristics
(VDD = 3.6V to 5.5V, Ta = -30 to +85 oC)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
V
Operating voltage
VDD
-
3.6
-
5.5
Display operation
VLCD = 6V without load
No access from MPU
IDD1
-
-
100
Supply current
(VDD = 5V,
Ta = 25 oC)
mA
Access operation from MPU
(fcyc = 200kHz)
IDD2
-
-
-
-
1000
10
Sleep operation without load
oscillator OFF, power save ON
IDDS1
VIH
VIL
-
-
0.7VDD
VSS
VDD
Input voltage (1)
Output voltage
V
V
0.3VDD
VDD-
0.4
VOH
IOH = -1mA, VDD = 4.0V
VOL
IIZ
IOL = 1mA, VDD = 4.0V
VIN = 0V to VDD
VIN = 0V to VDD
Io = ±50mA
0.4
1
mA
mA
Input leakage current
Output leakage current
-1
-3
-
-
IOZ
3
RCOM
RSEG
-
-
5
RON resistance
kW
Io = ±50mA
-
10
Frame frequency
(internal OSC)
fFR
VEF
VDD = 5V, Ta = 25 oC
70
95
100
99
130
-
Hz
%
V
Conversion
RL = ¥
efficiency
Voltage
converter
Output
voltage
VOUT
Ta = 25 oC, C = 1mF
6.9
7.2
7.5
Voltage regulator
reference voltage
VREF
VLCD
Ta = 25 oC
1.94
4.0
2.0
-
2.06
6.0
V
LCD driving voltage
VLCD = V0 - VSS
NOTE:
1. RESETB pin is schmitt input (0.8VDD £ VIH £ VDD, VSS £ VIL £ 0.2VDD).
46
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
S6A0093
AC CHARACTERISTICS
Parallel Write Interface (68 Mode)
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC)
Characteristic
E_RD cycle time
Symbol
TC
Min.
650
-
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
-
25
-
Pulse rise / fall time
E_RD pulse width high
E_RD pulse width low
RS and CSB setup time
RS and CSB hold time
DB setup time
tR,tF
TWH
TWL
tSU1
tH1
450
150
60
-
ns
-
30
-
tSU2
tH2
100
50
-
DB hold time
-
(VDD = 3.6V to 5.5V, Ta = -30 to +85 oC)
Characteristic
E_RD cycle time
Symbol
TC
Min.
350
-
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
-
25
-
Pulse rise / fall time
E_RD pulse width high
E_RD pulse width low
RS and CSB setup time
RS and CSB hold time
DB setup time
tR,tF
TWH
TWL
tSU1
tH1
250
150
40
-
ns
-
10
-
tSU2
tH2
40
-
DB hold time
10
-
R S ,CSB
R W _ W R
SU1
H1
t
t
W H
W L
t
t
tF
E_RD
SU2
H 2
t
t
R
t
Valid Data
DB0~DB7
C
t
Figure 26. Write Timing Diagram (68-series)
47
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Parallel Read Interface (68 Mode)
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC)
Characteristic
E_RD cycle time
Symbol
tC
Min.
650
-
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
-
25
-
Pulse rise / fall time
E_RD pulse width high
E_RD pulse width low
RS and CSB setup time
RS and CSB hold time
DB output delay time
DB output hold time
tR,tF
tWH
tWL
tSU
450
150
60
-
ns
-
tH
30
-
tD
100
50
-
tDH
-
(VDD = 3.6V to 5.5V, Ta = -30 to +85 oC)
Characteristic
E_RD cycle time
Symbol
tC
Min.
650
-
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
-
25
-
Pulse rise / fall time
E_RD pulse width high
E_RD pulse width low
RS and CSB setup time
RS and CSB hold time
DB output delay time
DB output hold time
tR,tF
tWH
tWL
tSU
450
150
60
-
ns
-
tH
30
-
tD
100
50
-
tDH
-
RS,CSB
RW_WR
SU
t
H
t
WH
WL
t
t
F
t
E_RD
D
t
DH
t
R
t
Valid Data
DB0~DB7
C
t
Figure 27. Read Timing Diagram (68-seres)
48
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Parallel Write Interface (80 Mode)
S6A0093
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC)
Characteristic
RW_WR cycle time
Pulse rise / fall time
RW_WR pulse width high
RW_WR pulse width low
RS and CSB setup time
RS and CSB hold time
DB setup time
Symbol
tC
Min.
650
-
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
-
25
-
tR,tF
tWH
tWL
150
450
60
-
ns
tSU1
tH1
-
30
-
tSU2
tH2
100
50
-
DB hold time
-
(VDD = 3.6V to 5.5V, Ta = -30 to +85 oC)
Characteristic
RW_WR cycle time
Pulse rise / fall time
RW_WR pulse width high
RW_WR pulse width low
RS and CSB setup time
RS and CSB hold time
DB setup time
Symbol
tC
Min.
350
-
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
-
25
-
tR,tF
tWH
tWL
100
250
40
-
ns
tSU1
tH1
-
10
-
tSU2
tH2
40
-
DB hold time
10
-
RS,CSB
E_RD
SU1
H1
t
t
W L
W H
t
t
R
t
RW_WR
SU2
H2
t
t
F
t
Valid Data
DB0~DB7
C
t
Figure 28. Write Timing Diagram (80-series)
49
S6A0093
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Parallel Read Interface (80 Mode)
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC)
Characteristic
E_RD cycle time
Symbol
tC
Min.
650
-
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
-
25
-
Pulse rise / fall time
E_RD pulse width high
E_RD pulse width low
RS and CSB setup time
RS and CSB hold time
DB output delay time
DB output hold time
tR,tF
tWH
tWL
tSU
150
450
60
-
ns
-
tH
30
-
tD
100
50
-
tDH
-
(VDD = 3.6V to 5.5V, Ta = -30 to +85 oC)
Characteristic
E_RD cycle time
Symbol
tC
Min.
650
-
Typ.
Max.
Unit
-
-
-
-
-
-
-
-
-
25
-
Pulse rise / fall time
E_RD pulse width high
E_RD pulse width low
RS and CSB setup time
RS and CSB hold time
DB output delay time
DB output hold time
tR,tF
tWH
tWL
tSU
150
450
60
-
ns
-
tH
30
-
tD
100
50
-
tDH
-
RS,CSB
RW_WR
SU
H
t
t
W L
W H
t
t
R
t
E_RD
D
DH
t
t
F
t
Valid Data
DB0~DB7
C
t
Figure 29. Read Timing Diagram (80-series)
50
80 SEG / 26 COM DRIVER & CONTROLLER FOR STN LCD
Clock Synchronized Serial Mode
S6A0093
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC)
Characteristic
SCL clock cycle time
Pulse rise / fall time
SCL clock width (high, low)
CSB setup time
Symbol
tC
Min
1000
-
Typ
Max
Unit
-
-
-
-
-
-
-
-
-
25
-
tR,tF
tW
300
150
700
50
tSU1
tH1
-
CSB hold time
-
ns
RS data setup time
RS data hold time
SI data setup time
SI data hold time
tSU2
tH2
-
300
50
-
tSU3
tH3
-
50
(VDD = 2.4V to 3.6V, Ta = -30 to +85 oC)
Characteristic
SCL clock cycle time
Pulse rise / fall time
SCL clock width (high, low)
CSB setup time
Symbol
tC
Min
600
-
Typ
Max
Unit
-
-
-
-
-
-
-
-
-
25
-
tR,tF
tW
200
100
400
50
tSU1
tH1
-
CSB hold time
-
ns
RS data setup time
RS data hold time
SI data setup time
SI data hold time
tSU2
tH2
-
200
40
-
tSU3
tH3
-
40
C
H1
t
t
tSU1
CSB
SCL
W
W
t
t
R
t
F
t
SU2
H2
t
t
RS
SI
tSU3
tH3
Figure 30. Clock Synchronized Serial Interface Mode Timing Diagram
51
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