S6A0094_技术文档

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

S6A0094 Specification Revision History

Content

Version

Date

0.0

Original

Apr.1999

CGROM font table added at table 5

COM data shift direction changed at table 9

Read data instruction separation according to RE bit at table 10

Symbol register is changed to ICONRAM at table 12

IDD1 is changed at table 18, 19

0.1

May.1999

0.2

0.3

0.4

IDD1 is changed at table 18, 19

Jun.1999

July.1999

Nov.1999

Jun.2000

Sep.2000

Pad location added at table 1 and 2

VDD change (2.4V~5.5V -> 2.4V~3.6V)

Inspection

0.5

ICON function addition (p21)

1

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

CONTENTS

INTRODUCTION.......................................................................................................................................... 1

FEATURES ................................................................................................................................................. 1

BLOCK DIAGRAM ...................................................................................................................................... 3

PAD CONFIGURATION .............................................................................................................................. 4

PAD CENTER COORDINATES .................................................................................................................. 5

PIN DESCRIPTION...................................................................................................................................... 5

POWER SUPPLY................................................................................................................................. 6

LCD DRIVER SUPPLY......................................................................................................................... 6

SYSTEM CONTROL............................................................................................................................. 7

MPU INTERFACE ................................................................................................................................ 8

LCD DRIVER OUTPUTS ...................................................................................................................... 8

TEST.................................................................................................................................................... 8

FUNCTION DESCRIPTION.......................................................................................................................... 9

SYSTEM INTERFACE.......................................................................................................................... 9

ADDRESS COUNTER (AC)................................................................................................................ 13

DISPLAY DATA RAM (DDRAM) ......................................................................................................... 13

CHARACTER GENERATOR ROM (CGROM)..................................................................................... 13

CHARACTER GENERATOR RAM (CGRAM) ..................................................................................... 19

SEGMENT ICON RAM (ICONRAM).................................................................................................... 20

HIGH POWER MODE......................................................................................................................... 22

LOW POWER CONSUMPTION MODE .............................................................................................. 22

LCD DRIVER CIRCUIT....................................................................................................................... 23

INSTRUCTION DESCRIPTION.................................................................................................................. 24

INITIALIZING & POWER SAVE MODE SETUP......................................................................................... 35

HARDWARE RESET.......................................................................................................................... 35

INITIALIZING AND POWER SAVE SETUP......................................................................................... 37

LCD DRIVING POWER SUPPLY CIRCUIT................................................................................................ 40

VOLTAGE CONVERTER.................................................................................................................... 40

VOLTAGE REGULATOR.................................................................................................................... 41

ELECTRONIC CONTRAST CONTROL (32 STEPS)........................................................................... 42

VOLTAGE GENERATOR CIRCUIT .................................................................................................... 44

MPU INTERFACE...................................................................................................................................... 45

APPLICATION INFORMATION FOR LCD PANEL .................................................................................... 47

FRAME FREQUENCY............................................................................................................................... 51

MAXIMUM ABSOLUTE RATINGS............................................................................................................. 52

ELECTRICAL CHARACTERISTICS.......................................................................................................... 53

DC CHARACTERISTICS.................................................................................................................... 53

AC CHARACTERISTICS .................................................................................................................... 54

2

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

INTRODUCTION

The S6A0094 is an LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can

display 2, 3 or 4 lines of 16 characters with 5 x 8 dots format. It is capable of interfacing various microprocessors,

supporting the 4-bit, 8-bit parallel modes and the clock synchronized serial mode. Voltage converter, oscillator,

voltage regulator, voltage follower and bias circuit are built in the IC. The double height character mode and line

vertical scroll functions are supported.

FEATURES

Driver Outputs

-

Common outputs: 34 common

Segment outputs: 80 segment

Applicable Panel Size

Font

Display

Duty

1 / 18

1 / 26

1 / 34

Contents of outputs

2-line x 16 characters

3-line x 16 characters

4-line x 16 characters

2 x 16 characters + 160 icons

3 x 16 characters + 160 icons

4 x 16 characters + 160 icons

5 x 8

Internal Memory

-

Character Generator ROM (CGROM): 21,760 bits (544 characters x 5 x 8 dots)

Character Generator RAM (CGRAM): 240 bits (6 characters x 5 x 8 dots)

Display Data RAM (DDRAM): 640 bits (16 characters x 5 lines )

Segment Icon RAM (ICONRAM): 160 bits (160 icons)

MPU Interface

-

No busy MPU interface (no busy check or no execution waiting time)

8-bit parallel interface mode: 68-series and 80-series are available

4-bit parallel interface mode: 68-series and 80-series are available

Serial interface mode: 4-pin clock synchronized serial interface

Function Set

-

Various instructions set: display control, power save, power control, etc.

COM / SEG bi-directional ( 4-type LCD application available)

H/W reset (RESETB)

Built-in Analog Circuit

-

Internal RC oscillator circuit or external clock

Electronic volume for contrast control (32 steps)

Voltage converter / voltage regulator / voltage follower & bias circuit

Low Power Operation

-

Sleep mode operation (5uA Max.)

Normal mode operation (TBD)

1

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Operating Voltage Range

-

Power supply voltage (VDD): 2.2V – 3.6V

LCD driving voltage (VLCD = V0 - VSS): 7.0V Max.

Package Type

Gold bumped chip

-

2

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

BLOCK DIAGRAM

RESETB

CK

PS

Oscillator

Timing Generator

IF

M I

CSB

RS

RW_WR

E_RD

Instruction

Register

(IR)

8

Instruction

Decoder

Parallel

Interface

4 bit/8 bit

COM1-

COM32

34 bits

Shift

Common

Driver

Address

Counter

Display

Data RAM

(DDRAM)

640 bits

Register

COM I1

COM I2

DB7

(SI)

Serial

Interface

Input Buffer

Data

Register

(DR)

8

DB6

(SCL)

7

DB5-

DB4

8

SEG1-

SEG80

Data Output

Register

(OR)

8

80 bits

Shift

Register

80 bits

Latch

Circuit

Segment

Driver

DB3-

DB0

8

DUTY1

DUTY0

Character

Generator

RAM

Character

Generator

ROM

Cursor

and

LCD

Driver

Icon

RAM

Blink

Controller

Voltage

Selector

160 bits

(CGRAM)

240 bits

(CGROM)

21760 bits

5

V_DD

GND

Segment Data Conversion

LCD Driving Power Circuit

Voltage Converter

Voltage Regulator

Voltage Follower & Bias Resistor

VR V1 V2 V3 V4

CAP1+ CAP1- CAP2+ CAP2- VOUT V0

Figure 1. Block Diagram

DIRS

3

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

PAD CONFIGURATION (NOT FIXED)

............................

164

183

Y

81

X

(0,0)

62

...........................

DUMMY PAD

PAD

Figure 2. Pad Configuration

Table 1. S6A0094 Pad Dimensions

Size

Item

Pad No.

Unit

X

Y

Chip size

-

1 – 66

6320

1860

90

70

90

mm

Pad pitch

63~80,83~162,165~182

62,81,82,163,164,183

1~61

60

100

50

100

50

63~80

83~162

100

50

Bumped pad size

165~182

100

60

62,81

60

82,163

100

60

164,183

100

Bumped pad height

All pad

17 (Typ.)

COG Align Key Coordinate

ILB Align Key Coordinate

42mm

108mm

42mm

108mm

30mm 30mm 30mm

(+3110, +880)

(-3110, +880)

(-2830, -835)

(+2830, -830)

4

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: mm]

P a d

N o

P a d

N o

P a d

N o

P a d

X

Y

X

Y

X

Y

N a m e

1

R S

- 2 7 0 0

- 8 2 0

6 2

D U M M Y 1

3 0 5 0

- 7 0 0

1 2 3

S E G 4 1

- 3 5

8 2 0

2

V S S

R W _ W R

V D D

E _ R D

V S S

C S B

D B 7

D B 6

D B 5

D B 4

D B 3

D B 2

D B 1

D B 0

V D D

V S S

V 4

- 2 6 1 0

- 2 5 2 0

- 2 4 3 0

- 2 3 4 0

- 2 2 5 0

- 2 1 6 0

- 2 0 7 0

- 1 9 8 0

- 1 8 9 0

- 1 8 0 0

- 1 7 1 0

- 1 6 2 0

- 1 5 3 0

- 1 4 4 0

- 1 3 5 0

- 1 2 6 0

- 1 1 7 0

- 1 0 8 0

- 9 9 0

- 9 0 0

- 8 1 0

- 7 2 0

- 6 3 0

- 5 4 0

- 4 5 0

- 3 6 0

- 2 7 0

- 1 8 0

- 9 0

- 8 2 0

6 3

6 4

C O M I 1

C O M 1

3 0 5 0

2 8 4 5

2 7 6 5

2 6 9 5

2 6 2 5

2 5 5 5

2 4 8 5

2 4 1 5

2 3 4 5

2 2 7 5

2 2 0 5

2 1 3 5

2 0 6 5

1 9 9 5

1 9 2 5

1 8 5 5

1 7 8 5

1 7 1 5

1 6 4 5

1 5 7 5

1 5 0 5

1 4 3 5

1 3 6 5

1 2 9 5

1 2 2 5

1 1 5 5

1 0 8 5

1 0 1 5

9 4 5

- 6 2 0

- 5 5 0

- 4 8 0

- 4 1 0

- 3 4 0

- 2 7 0

- 2 0 0

- 1 3 0

- 6 0

1 2 4

1 2 5

1 2 6

1 2 7

1 2 8

1 2 9

1 3 0

1 3 1

1 3 2

1 3 3

1 3 4

1 3 5

1 3 6

1 3 7

1 3 8

1 3 9

1 4 0

1 4 1

1 4 2

1 4 3

1 4 4

1 4 5

1 4 6

1 4 7

1 4 8

1 4 9

1 5 0

1 5 1

1 5 2

1 5 3

1 5 4

1 5 5

1 5 6

1 5 7

1 5 8

1 5 9

1 6 0

1 6 1

1 6 2

1 6 3

1 6 4

1 6 5

1 6 6

1 6 7

1 6 8

1 6 9

1 7 0

1 7 1

1 7 2

1 7 3

1 7 4

1 7 5

1 7 6

1 7 7

1 7 8

1 7 9

1 8 0

1 8 1

1 8 2

1 8 3

S E G 4 2

S E G 4 3

S E G 4 4

S E G 4 5

S E G 4 6

S E G 4 7

S E G 4 8

S E G 4 9

S E G 5 0

S E G 5 1

S E G 5 2

S E G 5 3

S E G 5 4

S E G 5 5

S E G 5 6

S E G 5 7

S E G 5 8

S E G 5 9

S E G 6 0

S E G 6 1

S E G 6 2

S E G 6 3

S E G 6 4

S E G 6 5

S E G 6 6

S E G 6 7

S E G 6 8

S E G 6 9

S E G 7 0

S E G 7 1

S E G 7 2

S E G 7 3

S E G 7 4

S E G 7 5

S E G 7 6

S E G 7 7

S E G 7 8

S E G 7 9

S E G 8 0

D U M M Y 4

D U M M Y 5

C O M I 2

C O M 3 2

C O M 3 1

C O M 3 0

C O M 2 9

C O M 2 8

C O M 2 7

C O M 2 6

C O M 2 5

C O M 2 4

C O M 2 3

C O M 2 2

C O M 2 1

C O M 2 0

C O M 1 9

C O M 1 8

C O M 1 7

C O M I 2

D U M M Y 6

- 1 0 5

- 1 7 5

- 2 4 5

- 3 1 5

- 3 8 5

- 4 5 5

- 5 2 5

- 5 9 5

- 6 6 5

- 7 3 5

- 8 0 5

- 8 7 5

- 9 4 5

8 2 0

6 5 0

5 7 0

5 0 0

4 3 0

3 6 0

2 9 0

2 2 0

1 5 0

8 0

3

4

6 5

C O M 2

5

6 6

C O M 3

6

6 7

C O M 4

7

6 8

C O M 5

8

6 9

C O M 6

9

7 0

C O M 7

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

2 5

2 6

2 7

2 8

2 9

3 0

3 1

3 2

3 3

3 4

3 5

3 6

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

4 9

5 0

5 1

5 2

5 3

5 4

5 5

5 6

5 7

5 8

5 9

6 0

6 1

7 1

C O M 8

7 2

C O M 9

1 0

7 3

C O M 1 0

C O M 1 1

C O M 1 2

C O M 1 3

C O M 1 4

C O M 1 5

C O M 1 6

C O M I 1

D U M M Y 2

D U M M Y 3

S E G 1

8 0

7 4

1 5 0

2 2 0

2 9 0

3 6 0

4 3 0

5 0 0

5 7 0

6 5 0

8 2 0

7 5

7 6

- 1 0 1 5

- 1 0 8 5

- 1 1 5 5

- 1 2 2 5

- 1 2 9 5

- 1 3 6 5

- 1 4 3 5

- 1 5 0 5

- 1 5 7 5

- 1 6 4 5

- 1 7 1 5

- 1 7 8 5

- 1 8 5 5

- 1 9 2 5

- 1 9 9 5

- 2 0 6 5

- 2 1 3 5

- 2 2 0 5

- 2 2 7 5

- 2 3 4 5

- 2 4 1 5

- 2 4 8 5

- 2 5 5 5

- 2 6 2 5

- 2 6 9 5

- 2 7 6 5

- 2 8 4 5

- 3 0 5 0

7 7

7 8

7 9

8 0

8 1

V 4

8 2

V 3

8 3

V 3

8 4

S E G 2

V 2

8 5

S E G 3

V 2

8 6

S E G 4

V 1

8 7

S E G 5

V 1

8 8

S E G 6

V 0

8 9

S E G 7

V 0

9 0

S E G 8

V 0

9 1

S E G 9

V 0

0

9 2

S E G 1 0

S E G 1 1

S E G 1 2

S E G 1 3

S E G 1 4

S E G 1 5

S E G 1 6

S E G 1 7

S E G 1 8

S E G 1 9

S E G 2 0

S E G 2 1

S E G 2 2

S E G 2 3

S E G 2 4

S E G 2 5

S E G 2 6

S E G 2 7

S E G 2 8

S E G 2 9

S E G 3 0

S E G 3 1

S E G 3 2

S E G 3 3

S E G 3 4

S E G 3 5

S E G 3 6

S E G 3 7

S E G 3 8

S E G 3 9

S E G 4 0

V R

9 0

9 3

V R

1 8 0

9 4

V S S

D U T Y 1

V D D

D U T Y 0

V S S

V O U T

C A P 2 -

C A P 2 +

C A P 1 -

C A P 1 +

V S S

D IR S

V D D

C K

2 7 0

9 5

3 6 0

9 6

4 5 0

9 7

5 4 0

9 8

6 3 0

9 9

7 2 0

1 0 0

1 0 1

1 0 2

1 0 3

1 0 4

1 0 5

1 0 6

1 0 7

1 0 8

1 0 9

1 1 0

1 1 1

1 1 2

1 1 3

1 1 4

1 1 5

1 1 6

1 1 7

1 1 8

1 1 9

1 2 0

1 2 1

1 2 2

8 1 0

9 0 0

9 9 0

1 0 8 0

1 1 7 0

1 2 6 0

1 3 5 0

1 4 4 0

1 5 3 0

1 6 2 0

1 7 1 0

1 8 0 0

1 8 9 0

1 9 8 0

2 0 7 0

2 1 6 0

2 2 5 0

2 3 4 0

2 4 3 0

2 5 2 0

2 6 1 0

2 7 0 0

8 7 5

8 0 5

7 3 5

1 0

6 6 5

- 6 0

V S S

P S

5 9 5

- 1 3 0

- 2 0 0

- 2 7 0

- 3 4 0

- 4 1 0

- 4 8 0

- 5 5 0

- 6 2 0

- 7 0 0

5 2 5

V D D

IF

4 5 5

3 8 5

V S S

M I

3 1 5

2 4 5

V D D

R E S E T B

T E S T

1 7 5

1 0 5

3 5

5

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

PIN DESCRIPTION

POWER SUPPLY

Table 3. Pin Description

Name

VDD

VSS

I/O

Description

Power supply

Power

Connect to MPU power supply pin

0V (GND)

Bias voltage level for LCD driving

Voltages should have the following relationship;

V0 ³ V1 ³ V2 ³ V3 ³ V4 ³ VSS

When the built-in power circuit is active and internal 1/5 bias resistors

are used.

V0

V1

V2

V3

V4

LCD bias

1/5 bias

V1

V2

V3

V4

(2/5) x

V0

(1/5) x

V0

I/O

(4/5) x V0 (3/5) x V0

When the built-in power circuit is active and internal 1/4 bias resistors

are used.

LCD bias

V1

V2

V3

V4

(1/4) x

V0

1/4 bias (3/4) x V0

(2/4) x V0

LCD DRIVER SUPPLY

Table 3. Pin Description (Continued)

Name

CAP1+

CAP1-

CAP2+

CAP2-

VOUT

I/O

O

Description

Capacitor + connecting pin for the internal voltage converter

Capacitor - connecting pin for the internal voltage converter

Capacitor + connecting pin for the internal voltage converter

Capacitor - connecting pin for the internal voltage converter

DC/DC voltage converter output

O

I/O

Voltage adjust pin

VR

I

This pin gives a voltage between V0 and VSS by resistance-division of

voltage.

6

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

SYSTEM CONTROL

Table 3. Pin Description (Continued)

Description

Name

I/O

External clock input

It must be fixed to "High" or "Low" when the internal oscillation circuit is used.

In case of the external clock mode, CK is used as the clock and OS bit

should be OFF.

CK

I

MPU interface selection input

MI = "Low": 80 series MPU

MI = "High": 68 series MPU

MI

I

Parallel / Serial selection input

When PS = "Low": Serial mode

When PS = "High": 4-bit/8-bit bus mode

PS

Interface data length selection pin for parallel data input

When PS = "Low"

IF = "Low" or "High": serial interface mode

When PS = “High”

IF = "Low": 4-bit bus mode

IF

I

IF = "High": 8-bit bus mode

SEG direction selection input

When DIRS = "Low”

SEG1 ® SEG2 ® SEG79 ® SEG80

When DIRS = "High”

DIRS

SEG80 ® SEG79 ® SEG2 ® SEG1

Display line mode selection input

DUTY1

DUTY0

Mode

Duty

0

1

0

1

2-line

3-line

4-line

1/18

1/26

1/34

DUTY1

DUTY0

I

0/1

7

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

MPU INTERFACE

Table 3. Pin Description (Continued)

Description

Name

I/O

Reset input

S6A0094 is initialized while RESETB is low.

RESETB

I

Chip selection input

S6A0094 is selected while CSB is low.

CSB

RS

I

Register selection input

When RS = "Low", instruction register

When RS = "High", data register

In 80-series MPU interface mode

This pin is connected to WR pin of MPU and is an active low write signal.

In 68-series MPU interface mode

This pin is connected to R/W pin of MPU.

When RW_WR = "Low", write mode

RW_WR

I

When RW_WR = "High", read mode

In 80-series MPU interface mode

This pin is connected to RD pin of MPU and is a active low read signal.

In 68-series MPU interface mode

E_RD

I

This pin is connected to E pin of MPU and enable read or write command

according to RW_WR signal.

When 8-bit bus mode, used as bi-directional data bus DB0 - DB7.

During 4-bit bus mode, only DB4 - DB7 are used. In this case DB0 - DB3 pins

are not used.

When serial mode, DB6 (SCL) is used as serial clock input pin and DB7 (SI)

is used as serial data input pin.

DB0 - DB3

DB4 - DB5

DB6 (SCL),

DB7 (SI)

I/O

LCD DRIVER OUTPUTS

Name

I/O

O

Description

Common signal output for driving LCD

Common signal output for icon display

Segment signal output for driving LCD

COM1 – COM32

COMI1, COMI2

SEG1 – SEG80

O

TEST

Name

I/O

Description

Test pin

TEST

I

This pin is not used for normal operation. Open at normal operation mode

NOTE: DUMMY – These pins should be opened (floated).

8

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

FUNCTION DESCRIPTION

SYSTEM INTERFACE

S6A0094 has two kinds of interface type with MPU: bus mode, serial mode. Serial or bus mode is selected by PS

pin. In bus mode, 4-bit bus or 8-bit bus is selected by IF pin, and 68 series MPU or 80 series MPU is selected by

MI pin.

Table 4. Various Kinds of MPU Interface according to PS, MI and IF

PS

MI

68 series

(H)

IF

8 bit (H) CSB

4 bit (L) CSB

8 bit (H) CSB

CSB

RS

RW_WR

R/W

E_RD

E

DB0~DB3

DB4~DB5

DB6

DB7

(1)

R/W

E

*

Bus

mode (H)

WR

RD

DB0~DB3

80 series

(L)

4 bit (L)

(H)/(L)

CSB

WR

*

Serial

mode (L)

(H)/(L)⁽²⁾

RS

(H)/(L)

SCL

SI

*

NOTES:

1. ‘ * ‘: Don’t care (High, Low or Open)

2. ‘ (H)/(L) ‘: Fixed High (VDD) or Low (VSS)

PS: "High" = bus mode, "Low" = serial mode

MI: "High" = 68-series MPU, "Low" = 80-series MPU

IF: "High" = 8-bit mode, "Low" = 4-bit mode (PS: "High")

CSB: "High" = chip is not selected, "Low" = chip is selected

RS: "High" = data register, "Low" = instruction register

RW_WR: read / write indicating signal in 68 mode or active low signal for enabling write in 80 mode.

E_RD: active high signal for enabling command is 68 mode or active low signal for enabling read in 80 mode.

SCL (DB6): serial clock input

SI (DB7): serial data input

9

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Interface with MPU in Parallel Mode (PS = "High")

During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data

register (DR) is used as temporary data storage place for being written into DDRAM / CGRAM / ICONRAM and

one of these RAM is selected by RAM address setting instruction. The Instruction register (IR) is used only to

store instruction code transferred from MPU. To select DR or IR register, RS input pin is used.

During reading operation, 8-bit register, output data register (OR) is used. The output data register (OR) is used

as temporary data storage place for being read from DDRAM / CGRAM / ICONRAM and one of these RAM is

selected by RAM address setting instruction. After RAM address setting, first reading is a dummy cycle in 8-bit

bus mode (figure 3, 4). The valid data comes from second reading. In 4-bit bus mode, after RAM address setting,

first and second reading are dummy cycles (figure 5, 6). The valid data comes from third reading. The dummy

read make the address counter (AC) increased by 1. So it is recommended to set address again before writing.

The instruction read cycle is not supported and it is regarded as a no operation cycle.

In 4-bit bus mode, it is needed to transfer 4-bit data (through DB7-DB4) by two times. The high order bits (for 8-bit

mode DB7-DB4) are written before the low order bits (for 8-bit mode DB3-DB0) in write and low order bits (for 8-bit

mode DB3-DB0) are read before the high order bits (for 8-bit mode DB7-DB4) in read transaction. The DB0-DB3

pins are floated in this 4-bit bus mode. After RESETB resets, S6A0094 considers first 4-bit data from MPU as the

high order bits.

IF

MI

CSB

RS

RW_WR

E_RD

Valid

DB7-DB0

Data

Instruction

Write

NOP

Dummy

Read

RAM

Read

Data

Write

Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)

10

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

IF

MI

CSB

RS

RW_WR

E_RD

DB7-DB0

Valid

Data

Instruction

W rite

NOP

Dummy

Read

RAM

Read

Data

W rite

Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)

IF

MI

CSB

RS

RW_WR

E_RD

upper

4-bit

lower

4-bit

upper

4-bit

lower

4-bit

upper

4-bit

lower

4-bit

DB7-DB4

Instruction Write

NOP

Dummy Read

RAM Read

Data Write

Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (68-series MPU Mode)

IF

MI

CSB

RS

RW_WR

E_RD

upper

4-bit

lower

4-bit

upper

4-bit

lower

4-bit

upper

4-bit

lower

4-bit

DB7-DB4

Instruction Write

NOP

Dummy Read

RAM

Data Write

Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (80-series MPU Mode)

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S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Interface with MPU in Serial Mode (PS = "Low")

When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, four ports, SCL

(DB6, synchronizing transfer clock), SI (DB7, serial input data), RS (register selection input) and CSB (chip

selection input) are used.

By setting CSB to "Low", S6A0094 can receive SCL input. If CSB is set to "High", S6A0094 resets the internal 8-

bit shift register and 3-bit counter. Serial data is input in the order of "D7, D6, D5, D4, D3, D2, D1, D0" from the

serial data input pin (SI = DB7) at the rising edge of serial clock (SCL = DB6).

At the rising edge of the 8th serial clock, the serial data (D7-D0) is converted into 8 bit bus mode data. The RS

input of the DR/IR selection is latched at the rising edge of the 8th serial clock (SCL).

In serial mode, the read is not possible.

CSB

SI (DB7)

SCL (DB6)

RS

D7

D6

D5

D4

D3

D2

D1

D0

D7

1

2

3

4

5

6

7

8

9

Figure 7. Timing Diagram of Serial Data Transfer

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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

ADDRESS COUNTER (AC)

Address Counter (AC) in S6A0094 stores DDRAM / CGRAM / ICONRAM address. After writing into or reading

from DDRAM / CGRAM / ICONRAM, AC is automatically increased by 1. The address counter is only one and

stores the address among DDRAM / CGRAM / ICONRAM.

DISPLAY DATA RAM (DDRAM)

DDRAM stores display data of maximum 80 x 8 bits (Max. 80 characters). DDRAM address is set in the address

counter (AC) as a hexadecimal number.

1st Ch.

16th Ch.

~

COM1

COM9

COM8

30

40

50

60

70

31

41

51

61

71

32

42

52

62

72

33

43

53

63

73

34

44

54

64

74

35

45

55

65

75

36

46

56

66

76

37

47

57

67

77

38

48

58

68

78

39

49

59

69

79

3A 3B 3C 3D 3E

4A 4B 4C 4D 4E

5A 5B 5C 5D 5E

6A 6B 6C 6D 6E

7A 7B 7C 7D 7E

3F

4F

5F

6F

7F

COM16

~

COM17 COM24

~

COM25 COM32

Hidden Line

SEG1

SEG80

DDRAM Address in 4 line Display

Figure 8. DDRAM Address

CHARACTER GENERATOR ROM (CGROM)

CGROM has one main ROM and four option ROM. The main CGROM has 160 characters and the option

CGROMs have 96 characters each. The total CGROM has 5 x 8-dot 544 characters. The R1, R0 bits select an

option CGROM between 4 option CGROM. If one of 4 CGROM is selected, the other CGROM font can not be

used. The CG bit of the instruction table selects the 6 characters (00h ~ 05h) of CGROM or CGRAM.

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S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Table 5. CGROM Character Code (Main ROM)

14

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

Table 5. CGROM Character Code (Option ROM1) (Continued)

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S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Table 5. CGROM Character Code (Option ROM2) (Continued)

16

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

Table 5. CGROM Character Code (Option ROM3) (Continued)

17

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Table 5. CGROM Character Code (Option ROM4) (Continued)

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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

CHARACTER GENERATOR RAM (CGRAM)

CGRAM has up to 5 x 8-dot 6 characters. By writing font data to CGRAM, user defined character can be used.

CGRAM can be written regardless of CG bit.

Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)

Character code

CGRAM address

CGRAM data

Pattern

(DDRAM data)

number

D7 D6 D5 D4 D3 D2 D1 D0

RE

A6 A5 A4 A3 A2 A1 A0

P7 P6 P5 P4 P3 P2 P1 P0

0 0 0 0 0 0 0

0 0 0 0 0 0 1

0 0 0 0 0 1 0

0 0 0 0 0 1 1

0 0 0 0 1 0 0

0 0 0 0 1 0 1

0 0 0 0 1 1 0

0 0 0 0 1 1 1

- - - 0 1 0 1 0

- - - 1 0 1 0 1

- - - 0 1 0 1 0

- - - 1 0 1 0 1

- - - 0 1 0 1 0

- - - 1 0 1 0 1

- - - 0 1 0 1 0

- - - 1 0 1 0 1

0 0 0 0 0 0 0 0

(00h)

1

Pattern 1

Pattern 2

Pattern 3

Pattern 4

0 0 0 1 0 0 0

0 0 0 1 0 0 1

0 0 0 1 0 1 0

0 0 0 1 0 1 1

0 0 0 1 1 0 0

0 0 0 1 1 0 1

0 0 0 1 1 1 0

0 0 0 1 1 1 1

- - - 0 0 0 0 0

- - - 1 1 1 1 1

- - - 0 0 0 0 0

- - - 1 1 1 1 1

- - - 0 0 0 0 0

- - - 1 1 1 1 1

- - - 0 0 0 0 0

- - - 1 1 1 1 1

0 0 0 0 0 0 0 1

(01h)

1

0 0 1 0 0 0 0

0 0 1 0 0 0 1

0 0 1 0 0 1 0

0 0 1 0 0 1 1

0 0 1 0 1 0 0

0 0 1 0 1 0 1

0 0 1 0 1 1 0

0 0 1 0 1 1 1

- - - 0 1 0 1 0

0 0 0 0 0 0 1 0

(02h)

0 0 1 1 0 0 0

0 0 1 1 0 0 1

0 0 1 1 0 1 0

0 0 1 1 0 1 1

0 0 1 1 1 0 0

0 0 1 1 1 0 1

0 0 1 1 1 1 0

0 0 1 1 1 1 1

- - - 0 1 1 1 0

- - - 1 0 1 0 1

- - - 1 1 0 1 1

- - - 1 0 1 0 1

- - - 0 1 1 1 0

- - - 1 1 1 1 1

0 0 0 0 0 0 1 1

(03h)

NOTE: ”-” - Don’t care

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S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) (continued)

Character code

CGRAM address

CGRAM data

Pattern

(DDRAM data)

number

D7 D6 D5 D4 D3 D2 D1 D0 RE

A6 A5 A4 A3 A2 A1 A0

P7 P6 P5 P4 P3 P2 P1 P0

0 1 0 0 0 0 0

0 1 0 0 0 0 1

0 1 0 0 0 1 0

0 1 0 0 0 1 1

0 1 0 0 1 0 0

0 1 0 0 1 0 1

0 1 0 0 1 1 0

0 1 0 0 1 1 1

- - - 1 1 0 1 1

- - - 1 0 0 0 1

- - - 0 0 0 0 0

- - - 1 0 0 0 1

- - - 1 1 0 1 1

- - - 1 1 1 1 1

0 0 0 0 0 1 0 0

1

Pattern 5

(04h)

0 1 0 1 0 0 0

0 1 0 1 0 0 1

0 1 0 1 0 1 0

0 1 0 1 0 1 1

0 1 0 1 1 0 0

0 1 0 1 1 0 1

0 1 0 1 1 1 0

0 1 0 1 1 1 1

- - - 1 1 1 1 1

- - - 0 0 0 0 0

- - - 1 1 1 1 1

- - - 0 0 0 0 0

0 0 0 0 0 1 0 1

1

Pattern 6

(05h)

NOTE: ”-” - Don’t care

SEGMENT ICON RAM (ICONRAM)

ICONRAM has segment control data and segment pattern data. The number of icons is 160.

Figure 9. Relationship between ICONRAM and Icon Display

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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

Table 7. Relationship between ICONRAM Address and Display Pattern

ICONRAM bits

RE

ICONRAM address

D7

D6

D5

D4

S1

S6

D3

S2

S7

D2

S3

S8

D1

S4

S9

D0

S5

1

60h

61h

BONF IORH-

BONF IORH

-

S10

.

1

6Eh

6Fh

70h

71h

BONF IORH

-

S71

S76

S81

S86

S72

S77

S82

S87

S73

S78

S83

S88

S74

S79

S84

S89

S75

S80

S85

S90

.

1

7Eh

7Fh

BONF IORH

-

S151

S156

S152

S157

S153

S158

S154

S159

S155

S160

NOTE1:

D7(BONF)

D6(IORH)

Function

0

1

-

No blink.

0

1

D4 to D0 blink in black-and-white reverse form.

The bits of “1” out of D4 to D0 blink.

NOTE2: ”-” - Don’t care

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S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

HIGH POWER MODE

The power circuit built-in the S6A0094 is a low power consumption type (when the High Power mode is OFF).

Accordingly, in the case of a large load liquid crystal or panel, the display quality may be degraded. In the case,

the display quality can be improved by entering HPM = “1” by command. Before determining whether or not to use

this mode. It is recommended to make a display check with real machine. In the case, the display quality cannot

be improved satisfactorily though the power mode is set, a liquid crystal driver power must be supplied from the

outside.

LOW POWER CONSUMPTION MODE

S6A0094 provides with sleep mode for saving power consumption during standby period.

Sleep Mode (Power Save Bit ON, Oscillation Bit OFF)

To enter the Sleep mode, the power circuit and oscillation circuit should be turned off by using the power save

command and the power control command. This mode helps to save power consumption by reducing current to

reset level.

1. Liquid Crystal Display Output

COM1 - COM32, COMI1, COMI2 : VSS level

SEG1 - SEG80 : VSS level

2. Data written in DDRAM, CGRAM, ICONRAM and registers are remained as previous value.

3. Operation mode is retained the same as it was prior to execution of the sleep mode.

All internal circuits are stopped.

4. Power Circuit and Oscillation Circuit

The built-in power supply circuit and oscillation circuit are turned off by power save command and power

control command.

22

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

LCD DRIVER CIRCUIT

LCD Driver circuit has 34 commons and 80 segments signals for driving LCD. Data from ICONRAM / CGRAM /

CGROM are transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. In case of

2-line display mode COM1 - COM16, COMI1 and COMI2 have 1/18 duty, in 3-line mode COM1 - COM24, COMI1

and COMI2 have 1/26 duty, and in 4-line mode COM1 - COM32, COMI1 and COMI2 have 1/34 duty ratio. SEG bi-

directional function is selected by DIRS input pin, and COM shift direction is selected by function set instruction

"SS" bit.

Table 8. SEG Data Shift Direction

DIRS pin

Low

SEG data shift direction

SEG1 ® SEG2 ® SEG3

SEG80 ® SEG79 ® SEG78

................... SEG78 ® SEG79 ® SEG80

High

................... SEG3 ® SEG2 ® SEG1

Table 9. COM Data Shift Direction

COM data shift direction

Line

CS

mode

0 (left)

1 (right)

0 (left)

COM1 ® COM2 ..…….. COM15 ® COM16 ® COMI1 ® COMI2

COM16 ® COM15 ……..... COM2 ® COM1 ® COMI1 ® COMI2

COM1 ® COM2 ............ COM23 ® COM24 ® COMI1 ® COMI2

COM24 ® COM23 .....…...... COM2 ® COM1 ® COMI1 ® COMI2

COM1 ® COM2 .......…. COM31 ® COM32 ® COMI1 ® COMI2

COM32 ® COM31 ..…….... COM2 ® COM1 ® COMI1 ® COMI2

2-line

mode

3-line

mode

1 (right)

0 (left)

4-line

mode

1 (right)

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S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

INSTRUCTION DESCRIPTION

Table 10. Instruction Table

Instruction RE RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description

DDRAM address is set to 30h from AC and the cursor returns

to home position The contents of DDRAM are not changed.

0

1

0

1

*

Determination of the DDRAM line which is displayed at the

first line at LCD

Return home

line shift

LS1, LS0 = 00: DDRAM line 1 shows at the first line of LCD

*

LS1 LS0

(default)

01: DDRAM line 2 shows at the first line of LCD

10: DDRAM line 3 shows at the first line of LCD

11: DDRAM line 4 shows at the first line of LCD

Line blink mode

LB4 = 0: DDRAM4 is normal display (default)

1: DDRAM4 is blink mode

LB3 = 0: DDRAM3 is normal display (default)

LB4 LB3 LB2 LB1 1: DDRAM3 is blink mode

0

1

0

LB2 = 0: DDRAM2 is normal display (default)

1: DDRAM2 is blink mode

LB1 = 0: DDRAM1 is normal display (default)

1: DDRAM1 is blink mode

Line blink

double height

Doubled height mode

DH4 = 0: DDRAM4 is normal display (default)

1: DDRAM4 is double height

DH3 = 0: DDRAM3 is normal display (default)

DH4 DH3 DH2 DH1 1: DDRAM3 is double height

1

0

1

0

DH2 = 0: DDRAM2 is normal display (default)

1: DDRAM2 is double height

DH1 = 0: DDRAM1 is normal display (default)

1: DDRAM1 is double height

Cursor / blink / display ON / OFF

C = 0: cursor OFF (default)

1: cursor ON

B = 0: blink OFF (default)

1: blink ON

Display control 0/1

0

1

C

B

RE

D

RE=0: extension register OFF (default)

1: extension register ON

D = 0: display OFF (default)

1: display ON

Power save / oscillation circuit ON / OFF

OS = 0: oscillator OFF (default)

1: oscillator ON

OS PS

Power save

0/1

0

1

0

*

PS = 0: power save OFF (default)

1: power save ON

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80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

Table 10. Instruction Table (Continued)

Instruction RE RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Description

LCD power control

HPM = 0: high power mode OFF (default)

1: High power mode ON

VR = 0 : Voltage regulator OFF (default)

1 : Voltage regulator ON

VC

0

1

0

1

HPM VR VF

VF = 0 : Voltage follower OFF (default)

1 : Voltage follower ON

VC = 0 : Voltage converter OFF (default)

1 : Voltage converter ON

Power

control

Internal resistor select

IRS = 0: external resistors are used for regulator (default)

1: internal resistors are used for regulator

LCD bias select

BS = 0: 1/5 bias (default)

IRS BS IR1 IR0 1: 1/4 bias

1

0

1

0

1

Internal resistor ratio select

IR1, IR0 = 00: (1+Rb/Ra) = 2.81

01: (1+Rb/Ra) = 3.27

10: (1+Rb/Ra) = 3.50

11: (1+Rb/Ra) = 3.00

Option CGROM select

R1,R0 = 00: main ROM + option ROM1 (default)

01: main ROM + option ROM2

10: main ROM + option ROM3

11: main ROM + option ROM4

R0 CS CG

Shifting direction of COM

0

1

0

1

0

R1

CS = 0: COM1 ® COM32 (default)

1: COM32 ® COM1

Select CGRAM or CGROM

System

set

CG = 0: CGROM (default), 1: CGRAM

Segment symmetry of each segment character

SS = 0: normal character display (default)

1: symmetrical character display

*

SS

*

DDRAM or Electronic volume Address

Range: 30h - 7Fh

0

1

0

1

AC6 AC5 AC4 AC3 AC2 AC1 AC0

DDRAM /

CGRAM

CGRAM or segment ICON RAM Address

Range: 00h - 2Fh

address set

Write DDRAM / CGRAM / ICONRAM/electronic volume RAM

Write data

Read data

0/1

1

D7

D6

D5

D4

D3

D2

D1

D0 This is determined by the address set instruction executed

immediately before writing data.

Read DDRAM / CGRAM / ICONRAM

D0

This is determined by the address set instruction executed

immediately before reading data.

NOP

Test

0/1

0

*

0

*

0

*

0

*

Non-operation Instruction

Don’t use this Instruction

NOTES:

1. "-": Don’t care

2. "*": Don’t use

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S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Return Home

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

*

*: Don’t care

Return Home instruction field makes cursor return home. DDRAM address is set to 30h from address counter and

the cursor returns to home position. The contents of DDRAM are not changed.

Line Shift Mode

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

1

*

LS2

LS1

*: Don’t care

Line Shift mode instruction field selects the DDRAM to be displayed in first line.

LS1, LS0 = 00: scroll amount 0 line (default)

01: scroll 1 line upward (display line 1 from DDRAM line 2)

10: scroll 2 line upward (display line 2 from DDRAM line 3)

11: scroll 2 line upward (display line 3 from DDRAM line 4)

Figure 10. Line Shift Mode Display at 3-line LCD

Figure 11. Line Shift Mode Display at 4-line LCD

26

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Line Blink Display Control

S6A0094

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

LB4

LB3

LB2

LB1

Displays the specified line in black-and-white form. The specified line corresponds to the address line of DDRAM.

Display the specified line of the DDRAM in black-and-white form by setting LB4 to LB1. Blinking is performed at

the same frequency as cursor blink. If blinking is caused to occur at the same time, the cursor position will be hard

to know.

LB4 = 0: displays the data for line 4 of the DDRAM in standard form (no blink)

(DDRAM 60H to 6FH)

= 1: displays the data for line 4 of the DDRAM in black-and-white reverse blink form

(DDRAM 60H to 6FH)

LB3 = 0: displays the data for line 3 of the DDRAM in standard form (no blink)

(DDRAM 50H to 5FH)

= 1: displays the data for line 3 of the DDRAM in black-and-white reverse blink form

(DDRAM 50H to 5FH)

LB2 = 0: displays the data for line 2 of the DDRAM in standard form (no blink)

(DDRAM 40H to 4FH)

= 1: displays the data for line 2 of the DDRAM in black-and-white reverse blink form

(DDRAM 40H to 4FH)

LB1 = 0: displays the data for line 1 of the DDRAM in standard form (no blink)

(DDRAM 30H to 3FH)

= 1: displays the data for line 1 of the DDRAM in black-and-white reverse blink form

(DDRAM 30H to 3FH)

Double Height Mode

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

1

0

DH4

DH3

DH2

DH1

Double Height mode instruction field selects double height line type.

DH4 = 0: displays the data for line 4 of the DDRAM in standard form

(DDRAM 60H to 6FH)

= 1: displays the data for line 4 of the DDRAM in vertical double size form

(DDRAM 60H to 6FH)

DH3 = 0: displays the data for line 3 of the DDRAM in standard form

(DDRAM 50H to 5FH)

= 1: displays the data for line 3 of the DDRAM in vertical double size form

(DDRAM 50H to 5FH)

DH2 = 0: displays the data for line 2 of the DDRAM in standard form

(DDRAM 40H to 4FH)

= 1: displays the data for line 2 of the DDRAM in vertical double size form

(DDRAM 40H to 4FH)

DH1 = 0: displays the data for line 1 of the DDRAM in standard form

(DDRAM 30H to 3FH)

= 1: displays the data for line 1 of the DDRAM in vertical double size form

(DDRAM 30H to 3FH)

27

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Figure 12. Line Double Height Mode Display

28

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Display Control

S6A0094

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0/1

0

1

0

C

B

RE

D

Display Control instruction field controls cursor / blink / display ON / OFF.

C: Cursor ON / OFF control bit

When C = "High", cursor is turned ON

When C = "Low", cursor is disappeared in current display (default).

B: Cursor blink ON / OFF control bit

When C = "High" and B = "High", S6A0094 make LCD alternate between inverting display character and

normal

display character at the cursor position with about a half second. On the contrary, if C = "Low", only a normal

character is displayed regardless of "B" flag.

When B = "Low", blink is OFF (default).

RE: Extended register access is specified by setting RE

When RE = “High”, extended register ON

When RE = “Low”, extended register OFF

D: Display ON / OFF control bit

When D = "High", entire display is turned ON.

When D = "Low", display is turned OFF, but display data are remained in DDRAM (default).

Table 11. Cursor Attributes

C, B

Display state

1, 0

1, 1

(Blinking mode)

0, 0

0, 1

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S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Power Save

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0/1

0

1

0

*

OS

PS

*: Don’t care

Power Save instruction field is used to control the oscillator and to set or to reset the power save mode.

OS: oscillator ON / OFF control bit

When OS = "High", internal oscillator is turned ON

When OS = "Low", internal oscillator is turned OFF (default)

PS: power save ON / OFF control bit

When PS = "High", power save mode is turned ON

When PS = "Low", power save mode is turned OFF (default)

Power Control (1)

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

1

HPM

VR

VF

VC

Power Control instruction field sets high power mode and voltage regulator / converter / follower ON / OFF.

HPM: high power mode control bit

When HPM = “High”, high power mode is turned ON

When HPM = “Low”, high power mode is turned OFF (default)

VR: voltage regulator circuit control bit

When VR = "High", voltage regulator is turned ON

When VR = "Low", voltage regulator is turned OFF (default)

VF: voltage follower circuit control bit

When VF = "High", voltage follower is turned ON

When VF = "Low", voltage follower is turned OFF (default)

VC: voltage converter circuit control bit

When VC = "High", voltage converter is turned ON

When VC = "Low", voltage converter is turned OFF (default)

NOTE: The oscillation circuit must be turned on for the voltage converter circuit to be active.

Power Control (2)

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

1

0

1

IRS

BS

IR1

IR0

IRS: initial resistors select

When IRS = “High”, internal resistors are used for regulator

When IRS = “Low”, external resistors are used for regulator (default)

BS: bias select

When BS = “High”, it’s 1/4 bias

When BS = “Low”, it’s 1/5 bias (default)

IR1, IR0: internal resistor ratio select

When IR1,IR0 = 00, (1 + Rb/Ra) = 2.81, V0 = 5.60V

When IR1,IR0 = 01, (1 + Rb/Ra) = 3.27, V0 = 6.54V

When IR1,IR0 = 10, (1 + Rb/Ra) = 3.50, V0 = 7.00V

When IR1,IR0 = 11, (1 + Rb/Ra) = 3.00, V0 = 6.00V

30

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

System Set (1)

S6A0094

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

R1

R0

CS

CG

R1, R0: selects an option ROM

When R1, R0 = 00, standard ROM (160 characters) + option ROM1 (96 characters)

When R1, R0 = 01, standard ROM (160 characters) + option ROM2 (96 characters)

When R1, R0 = 10, standard ROM (160 characters) + option ROM3 (96 characters)

When R1, R0 = 11, standard ROM (160 characters) + option ROM4 (96 characters)

CS: data shift direction of common

CS sets the shift direction of common display data

When CS = "High", COM right shift

When CS = "Low", COM left shift (default)

(refer to table 9 and figure 13)

CG: CGRAM enable bit

When CG = "High", CGRAM can be used and you can use this RAM for eight special character area.

(00h - 05h=CGRAM font display)

When CG = "Low", CGRAM is disabled. CGROM (00h - 05h) can be used and the additional current

consumption is saved by using this mode (default)

(00h - 05h=CGROM font display)

System Set (2)

RE RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

1

0

*

SS

*

*: Don’t care

SS: the normal / reverse character display of SEG is specified by setting SS.

When SS = “LOW”, normal display of SEG

When SS = ‘HIGH”, reverse display of SEG

Figure 13. Example of Display according to SS and CS-bit

31

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

DDRAM Address Set

RE

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

RS

0

1

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Above RAM Address Set instruction field sets DDRAM and electronic volume register in the address counter.

Before writing / reading data into / from the DDRAM, set the address by DDRAM Address set instruction. Next,

when data are written / read in succession, the address is automatically increased by 1. After accessing 7Fh, the

address of AC is 00h. The read data from the unused address are unknown.

The address ranges are 00h - 7Fh.

Table 12. RAM Address Mapping (RE = 0)

Address

00h

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

Unused

EV Test

Unused

10h

Unused

20h

Unused

30h

DDRAM line-1

DDRAM line-2

DDRAM line-3

DDRAM line-4

DDRAM line-5

40h

50h

60h

70h

EV: Electric volume RAM

TEST: Testing register, don’ use it.

32

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

CGRAM Address Set

S6A0094

RE

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

RS

1

0

1

AC6

AC5

AC4

AC3

AC2

AC1

AC0

Above RAM Address set instruction field sets CGRAM, segment icon RAM in the address counter.

Before writing / reading data into / from the CGRAM / ICONRAM, set the address by CGRAM Address Set

instruction. Next, when data are written/read in succession, the address is automatically increased by 1. After

accessing 7Fh, the address of AC is 00h. The read data from the unused address are unknown.

The address ranges are 00h - 7Fh.

Table 13. RAM Address Mapping (RE = 1)

Address

00h

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

CGRAM (00H)

CGRAM (02H)

CGRAM (04H)

CGRAM (01H)

CGRAM (03H)

CGRAM (05H)

10h

20h

30h

Unused

40h

50h

60h

ICONRAM (S1 - S80)

70h

ICONRAM (S81 - S160)

33

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Write Data

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0/1

1

D7

D6

D5

D4

D3

D2

D1

D0

This instruction field make S6A0094 write binary 8-bit data to DDRAM / CGRAM / ICONRAM or register. The RAM

address to be written into is determined by previous DD/CGRAM Address Set instruction. After writing operation,

the address counter (AC) automatically increased by 1.

Read Data

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0/1

1

D7

D6

D5

D4

D3

D2

D1

D0

DDRAM / CGRAM / ICONRAM data read instruction.

Each RAM is selected by address set instruction. And then you can read the RAM data. You can get correct RAM

data from second read transaction. The first read data after setting RAM address is dummy data, so the correct

RAM data come from the second read transaction. After reading operation, the address counter (AC) is increased

by 1 automatically.

NOP

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0/1

0

No operation command

It is recommended to add this command at each breakpoint of the program.

Test Mode

RE

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0/1

0

*

*: Don’t care

An IC test mode set command. Don’t use it any case.

34

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

INITIALIZING & POWER SAVE MODE SETUP

HARDWARE RESET

When RESETB pin = "Low", S6A0094 can be initialized as the following state.

(1) Control Display ON / OFF Instruction

C = 0: cursor OFF

B = 0: blink OFF

RE = 0: extension register OFF

D = 0: display OFF

(2) Power Save Set Instruction

OS = 0: oscillator OFF

PS = 0: power save OFF

(3) Power Control Set Instruction

HPM = 0: high power mode OFF

VR = 0: voltage regulator OFF

VF = 0: voltage follower OFF

VC = 0: voltage converter OFF

IRS = 1: for built-in resistor

BS = 0: 1/5 bias

IR1, 0 = 00: Rb / Ra = 2.81

(4) System Set Instruction

R1, R0 = 00: main ROM + option ROM

CS = 0: COM left shift

SS = 0 : normal display character

CG = 0: CGRAM is not used

(5) Return Home

Address counter = 30h

(6) Electronic Contrast Control Register: address 10h = data (0, 0, 0, 0, 0)

(7) In Case of 4-bit Interface Mode Selection

S6A0094 considers the first 4-bit data from MPU as the high order bits.

NOTE: If initialization is not done by the RESETB pin at application, unknown condition might result. Then you can

initialize by instruction.

35

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Figure 14. RESET Timing

36

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

INITIALIZING AND POWER SAVE SETUP

Initializing by Instruction

NOTE:

At command 5 and 6, the internal RAM

should be cleared.

To clear DDRAM,

RE bit should be set 0,

set address at 30h (first DDRAM)

and then write 20h (space character code)

80 times

To clear CGRAM (RE=1),

RE bit should be set 1,

Set address at 00h (first CGRAM)

and then write 00h (null data) 48 times

To clear ICONRAM (RE=1),

RE bit should be set 1,

set ICONRAM address at 60h (first

ICONRAM) and then write 00h (null data)

32 times

37

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Sleep Mode Set or Release by Instruction

a) Sleep Mode Set

End of Initialization

Normal Operation status

(Power save is OFF and oscillator is ON.)

Command Input

1. Display Control (D: OFF)

2. Power Save (PS: Power Save ON, OS: OSC OFF)

3. Power Control (VR, VF, VC are all OFF)

Enter the Sleep Mode

b) Sleep Mode Release

Sleep Mode

Command input

1. Power Save (PS: Power Save OFF, OS: OSC ON)

2. Power Control (VR, VF, VC are all ON)

Waiting for 500 us or more

Command Input

3. Display Control (D: ON)

Return to Normal Operation

38

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

Recommendation of Power ON / OFF Sequence

a) Power ON Sequence

Power ON

Voltage Converter ON

[VR, VF, VC = 0, 0, 1]

Waiting for ³ 1ms

Voltage Regulator ON

[VR, VF, VC = 1, 0, 1]

Waiting for ³ 1ms

Voltage Follower ON

[VR, VF, VC = 1, 1, 1]

Operation Command Input

b) Power OFF Sequence

Operation Command Input

Display OFF

Voltage Regulator OFF

[VR, VF, VC = 0, 1, 1]

Waiting for ³ 50ms

Voltage Follower OFF

[VR, VF, VC = 0, 0, 1]

Waiting for ³ 1ms

Voltage Converter OFF

[VR, VF, VC = 0, 0, 0]

Waiting for ³ 1ms

Operation Command Input

39

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

LCD DRIVING POWER SUPPLY CIRCUIT

The Power Supply circuit produces LCD panel driving voltage at low power consumption. The LCD driving Power

Supply circuit consists of voltage converter, voltage regulator, and voltage follower. It is controlled by power

control instruction. Table 14 shows how the LCD Driving Power Supply circuit works by power control instruction

sets.

Table 14. Power Supply Control Mode Set

Voltage

regulator

Voltage

follower

Voltage

converter

V0, V1, V2,

V3, V4 pin

VR VF VC

VOUT pin

VR pin

Internal

voltage

output

Used for

voltage

adjustment

Internal voltage output

1 1 1

Enable

Disable

External

voltage

input

Used for

voltage

adjustment

Internal voltage output

1 1 0

V1~V4: Internal voltage output

0 1 0

0 0 0

Disable

Enable

Disable

Open

V0: External voltage input

V0~V4: External voltage input

NOTE: SEC recommendation is to use only the case listed above table.

VOLTAGE CONVERTER

The Voltage Converter circuit generates positive 4 times voltage of 2.0V that is generated internally. VOUT is

generated from the Voltage Converter. And this conversion voltage is used in the built-in voltage regulator circuit.

This application circuit is same as 3 times DC/DC converter.

Figure 15. DC/DC Converter Output and Circuit

40

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

VOLTAGE REGULATOR

The Voltage Regulator circuit is used to obtain an appropriate LCD panel driving voltage. This voltage is obtained

by adjusting resistors Ra and Rb as shown in equation (1), and by setting electronic contrast control data bits, see

equation (2).

The potential of V0 Pin can be adjusted within VOUT - VREF. VREF is the internal constant voltage source of the

chip and this value is 2.0V in the condition VDD ³ 2.2V

n

Voltage regulation by adjusting resistors Ra, Rb

When REF is "Low"

Rb

V0 = ( 1 +

) x VREF --- (1)

Ra

The internal VREF of voltage regulator has the temperature compensation function, and the temperature coefficient

is approximately 0%

Figure 16. Voltage Regulator Circuit

41

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

ELECTRONIC CONTRAST CONTROL (32 STEPS)

Electronic Contrast Control data bits is 10h = (d4, d3, d2, d1, d0). Voltage regulation is adjusted as 32-contrast

step according to the value of Electronic Contrast Control data bits. LCD drive voltage V0 has one of 32 voltage

values if 5-bit data is set to the Electronic Contrast Control register (RE = 0 address 08h). When using the

Electronic Contrast Control function, you need to turn the voltage regulators on using power control instruction.

When REF = "Low"

Rb

V0 = ( 1 +

) x VEV --- (2)

Ra

VEV = VREF - na (n = 0, 1, 2, ... 30, 31)

a = VREF / 150

Table 15. Electronic Contrast Control Register

No.

d7 d6 d5 d4 d3 d2 d1 d0

V0

Contrast

na

1

2

3

4

.

-

.

-

.

-

.

0

.

0

.

0

.

0

1

.

0

1

0

1

.

0a (default)

Maximum

High

1a

2a

3a

.

31

-

1

0

1

30 a

31a

Minimum

Low

32

NOTE:

1. "-": Don’t care

42

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

Figure 17. Electronic Contrast Control Circuit

The voltage rage of the V5 output can be adjusted by changing the built-in resister ratio (1 + Rb / Ra) by

command. Reference values are shown in table 16.

Table 16. V0 Voltage Regulating Built-in Resister Ratio Set Values (Reference Values)

Command

(1+Rb / Ra)

V0

IR1

IR0

0

1

0

1

0

1

2.81

3.27

3.50

3.00

5.60V

6.54V

7.00V

6.00V

43

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

VOLTAGE GENERATOR CIRCUIT

Figure 18. When Built-in Power Supply is used (VR, VF, VC = 1, 1, 1)

Figure 19. When External Power Supply is used

44

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

MPU INTERFACE

Figure 20. Parallel Interfacing with 8080-series Microprocessors

Figure 21. Parallel Interfacing with 6800-series Microprocessors

45

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Figure 22. Clock Synchronized Serial Interfacing with any Microprocessors

46

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

APPLICATION INFORMATION FOR LCD PANEL

Chip Bottom & Lower View (CS bit = "0", DIRS = "0")

Figure 23. Chip Bottom & Lower View (CS bit = "0", DIRS = "0")

47

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Chip Bottom & Upper View (CS bit = "1", DIRS = "1")

Figure 24. Chip Bottom & Upper View (CS bit = "1", DIRS = "1")

48

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Chip Top & Lower View (CS bit = "0", DIRS = "1")

S6A0094

Figure 25. Chip Top & Lower View (CS bit = "0", DIRS = "1")

49

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Chip Top & Upper View (CS bit = "1", DIRS = "0")

Figure 26. Chip Top & Upper View (CS bit = "0", DIRS = "1")

50

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

FRAME FREQUENCY

1/18 Duty (2-line Mode)

1-line Selection Period = 16 Clocks

One Frame

Frame Frequency

= 16 x 18 x 44.44 us = 12.8 ms (1 Clock = 44.44 us at fOSC = 45 kHz)

= 1 / 12.8 ms = 78.1 Hz

1/26 Duty (3-line Mode)

1-line Selection Period = 16 Clocks

One Frame

Frame Frequency

= 16 x 26 x 29.63 us = 12.33 ms (1 Clock = 29.63 us at fOSC = 45 kHz)

= 1 / 12.33 ms = 81.1 Hz

1/34 Duty (4-line Mode)

1-line Selection Period = 16 Clocks

One Frame

Frame Frequency

= 16 x 34 x 22.2 us = 11.97 ms (1 Clock = 22.2 us at fOSC = 45 kHz)

= 1 / 11.97 ms = 83 Hz

51

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

MAXIMUM ABSOLUTE RATINGS

Table 17. Maximum Absolute Ratings

Symbol Value

-0.3 to + 7.0

Characteristic

Power supply voltage (1)

Power supply voltage (2)

Power supply voltage (3)

Input voltage

Unit

V

VDD

VOUT, V0

V1, V2, V3, V4

VIN

-0.3 to + 9.0

-0.3 to V0

V

-0.3 to VDD+0.3

-30 to +85

V

Operating temperature

Storage temperature

TOPR

^oC

TSTG

-55 to +125

NOTE1: All the voltage levels are based on VSS = 0V.

NOTE2: Voltage greater than above may damage the circuit

Voltage level : VOUT ³ V0 ³ VDD ³ VSS

Voltage level : V0 ³ V1 ³ V2 ³ V3 ³ V4 ³ VSS

52

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

S6A0094

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS

Table 18. DC Characteristics

(VDD = 2.2V to 3.6V, Ta = -30 to +85 ^oC)

Min.

Typ.

Max.

Unit

Item

Symbol

Condition

V

Operating voltage

VDD

-

2.2

-

3.6

Display operation

VLCD=6V without load

No access from MPU

IDD1

-

95

Supply current

(VDD = 3V,

Ta = 25 ^oC)

Access operation from MPU

(Fcyc = 200kHZ)

uA

IDD2

-

500

5

Sleep operation without load

oscillator OFF, power save ON

IDDS1

VIH

VIL

-

0.8VDD

Vss

VDD

Input voltage

V

0.2VDD

VDD-

0.4

VOH

IOH = -1mA, VDD =2.4V

Output voltage

VOL

IIZ

IOL = 1mA, VDD =2.4V

VIN = 0V to VDD

Io = ±50uA

0.4

1

uA

Input leakage current

Output leakage current

-1

-3

-

IOZ

3

RCOM

RSEG

-

5

RON resistance

kW

Io = ±50uA

-

10

VDD = 3V, Ta = 25 ^oC

(4-line mode)

Hz

Frame frequency

(Internal OSC)

Conversion

70

85

100

fFR

VEF

RL = ¥

95

99

-

%

V

efficiency

Voltage

converter

Output

voltage

VOUT

Ta = 25 ^oC, C = 1uF

7.5

8.0

8.5

Voltage regulator

reference voltage

VREF

VLCD

Ta = 25 ^oC

1.94

3.0

2.0

-

2.06

7.0

V

LCD driving voltage

VLCD = V0 - Vss

53

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

AC CHARACTERISTICS

Parallel Write Interface (68 Mode)

(VDD = 2.2V to 3.6V, Ta = -30 to +85 ^oC)

Characteristic

E_RD cycle time

Symbol

tC

Min.

650

-

Typ.

Max.

Unit

-

25

-

Pulse rise / fall time

E_RD pulse width high

E_RD pulse width low

RS and CSB setup time

RS and CSB hold time

DB setup time

tR,tF

tWH

tWL

450

150

60

-

ns

tSU1

tH1

-

30

-

tSU2

tH2

100

50

-

DB hold time

-

Figure 27. Write Timing Diagram (68-series)

54

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Parallel Read Interface (68 Mode)

S6A0094

(VDD = 2.2V to 3.6V, Ta = -30 to +85 ^oC)

Characteristic

E_RD cycle time

Symbol

tC

Min.

650

-

Typ.

Max.

Unit

-

25

-

Pulse rise / fall time

E_RD pulse width high

E_RD pulse width low

RS and CSB setup time

RS and CSB hold time

DB output delay time

DB output hold time

tR,tF

tWH

tWL

tSU

450

150

60

-

ns

-

tH

30

-

tD

100

50

-

tDH

-

Figure 28. Read Timing Diagram (68-series)

55

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Parallel Write Interface (80 Mode)

(VDD = 2.2V to 3.6V, Ta = -30 to +85 ^oC)

Characteristic

RW_WR cycle time

Pulse rise / fall time

RW_WR pulse width high

RW_WR pulse width low

RS and CSB setup time

RS and CSB hold time

DB setup time

Symbol

tC

Min.

650

-

Typ.

Max.

Unit

-

25

-

tR,tF

tWH

tWL

150

450

60

-

ns

tSU1

tH1

-

30

-

tSU2

tH2

100

50

-

DB hold time

-

Figure 29. Write Timing Diagram (80-series)

56

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Parallel Read Interface (80 Mode)

S6A0094

(VDD = 2.2V to 3.6V, Ta = -30 to +85 ^oC)

Characteristic

E_RD cycle time

Symbol

tC

Min.

650

-

Typ.

Max.

Unit

-

25

-

Pulse rise / fall time

E_RD pulse width high

E_RD pulse width low

RS and CSB setup time

RS and CSB hold time

DB output delay time

DB output hold time

tR,tF

tWH

tWL

tSU

150

450

60

-

ns

-

tH

30

-

tD

100

50

-

tDH

-

Figure 30. Read Timing Diagram (80-series)

57

S6A0094

80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD

Clock Synchronized Serial Mode

(VDD = 2.2V to 3.6V, Ta = -30 to +85 ^oC)

Characteristic

SCL clock cycle time

Pulse rise / fall time

SCL clock width (high, low)

CSB setup time

Symbol

tC

Min.

1000

-

Typ.

Max.

Unit

-

25

-

tR,tF

tW

300

150

700

50

tSU1

tH1

-

CSB hold time

-

ns

RS data setup time

RS data hold time

SI data setup time

SI data hold time

tSU2

tH2

-

300

50

-

tSU3

tH3

-

50

Figure 31. Clock Synchronized Serial Interface Mode Timing Diagram

58


型号：	S6A0094
厂家：	SAMSUNG
描述：	80 SEG / 34 COM DRIVER & CONTROLLER FOR STN LCD 80 SEG / 34 COM驱动程序和控制器的STN LCD 驱动控制器 CD
文件：	总62页 (文件大小：731K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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