S3C830A [SAMSUNG]
8-Bit CMOS Microcontroller; 8位CMOS微控制器
| 型号： | S3C830A |
| 厂家： | 
SAMSUNG |
| 描述： | 8-Bit CMOS Microcontroller |
| 文件： | 总342页 (文件大小：1658K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
21-S3-C830A/P830A-032002
USER'S MANUAL
S3C830A/P830A
8-Bit CMOS
Microcontroller
Revision 1
NOTIFICATION OF REVISIONS
ORIGINATOR:
Samsung Electronics, SOC Development Group, Ki-Heung, South Korea
S3C830A/P830A Microcontroller
PRODUCT NAME:
DOCUMENT NAME:
S3C830A/P830A User's Manual, Revision 1
DOCUMENT NUMBER: 21-S3-C830A-03-2002
EFFECTIVE DATE:
SUMMARY:
March, 2002
As a result of additional product testing and evaluation, some specifications
published in the S3C830A/P830A User's Manual, Revision 0, have been
changed.
These changes for S3C830A/P830A microcontroller, which are described in
detail in the Revision Descriptions section below, are related to the followings:
—
—
—
—
Chapter 4./10. Basic Timer Control Register
Chapter 20. Operating temperature of Absolute Maximum Ratings
Chapter 20. Main Oscillator Clock Stabilization Time
Chapter 20./22. Operating Voltage Range
DIRECTIONS:
Please note the changes in your copy (copies) of the S3C830A/P830A User's
Manual, Revision 0. Or, simply attach the Revision Descriptions of the next page
to S3C830A/P830A User's Manual, Revision 0.
REVISION HISTORY
Revision
Date
Remark
0
November, 2001
Preliminary Spec for internal release only.
Reviewed by Min-Su Lee.
1
March, 2002
Reviewed by Min-Su Lee.
REVISION DESCRIPTIONS
1. BASIC TIMER CONTROL REGISTER
The contents of BTCON.0 should be changed “Clock Frequency Divider Clear Bit for Basic Timer and Timer0”
into 'Clock Frequency Divider Clear Bit for all Timers' in the Page 4-6, 10-2.
2. OPERATING TEMPERATURE
Operating temperature of absolute maximum ratings (TA) must be changed -40°C into -25°C in the Table 20-1.
3. ELECTRICAL DATA (Page 20-10)
Table 20-11. Main Oscillator Clock Stabilization Time (tST1
)
°
°
(TA = – 25 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter Conditions
VDD = 4.5V to 5.5V
Min
Typ
Max
Unit
Crystal
–
–
10
mS
Stabilization occurs when VDD is equal to the
minimum oscillator voltage range.
Ceramic
–
–
4
mS
External clock
XIN input high and low level width(tXH, tXL)
111
–
1250
nS
4. INSTRUCTION CLOCK(Page 20-11, 22-4)
The minimum frequency of instruction clock must be changed 100kHz into 25kHz in the Figure 20-7 and 22-2.
S3C830A/P830A
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1
Important Notice
The information in this publication has been
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
carefully checked and is believed to be entirely
accurate at the time of publication. Samsung
assumes no responsibility, however, for possible
errors or omissions, or for any consequences
resulting from the use of the information contained
herein.
Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
Samsung product could create a situation where
personal injury or death may occur.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
Should the Buyer purchase or use a Samsung
product for any such unintended or unauthorized
application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all
claims, costs, damages, expenses, and reasonable
attorney fees arising out of, either directly or
indirectly, any claim of personal injury or death that
may be associated with such unintended or
unauthorized use, even if such claim alleges that
Samsung was negligent regarding the design or
manufacture of said product.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.
S3C830A/P830A 8-Bit CMOS Microcontrollers
User's Manual, Revision 1
Publication Number: 21-S3-C830A/P830A-032002
© 2002 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are designed
and manufactured in accordance with the highest quality standards and objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung-Eup
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 440-900
TEL: (82)-(31)-209-1934
FAX: (82)-(31)-209-1899
Home Page: http://www.samsungsemi.com
Printed in the Republic of Korea
Preface
The S3C830A/P830A Microcontroller User's Manual is designed for application designers and programmers who
are using the S3C830A/P830A microcontroller for application development. It is organized in two main parts:
Part I Programming Model
Part II Hardware Descriptions
Part I contains software-related information to familiarize you with the microcontroller's architecture,
programming model, instruction set, and interrupt structure. It has six chapters:
Chapter 1
Chapter 2
Chapter 3
Product Overview
Address Spaces
Addressing Modes
Chapter 4
Chapter 5
Chapter 6
Control Registers
Interrupt Structure
Instruction Set
Chapter 1, "Product Overview," is a high-level introduction to S3C830A/P830A with general product descriptions,
as well as detailed information about individual pin characteristics and pin circuit types.
Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register
addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack
operations.
Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the
S3C8-series CPU.
Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register
values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read,
alphabetically organized, register descriptions as a quick-reference source when writing programs.
Chapter 5, "Interrupt Structure," describes the S3C830A/P830A interrupt structure in detail and further prepares
you for additional information presented in the individual hardware module descriptions in Part II.
Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series
microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of
each instruction are presented in a standard format. Each instruction description includes one or more practical
examples of how to use the instruction when writing an application program.
A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the
first time, we recommend that you first read Chapters 1–3 carefully. Then, briefly look over the detailed
information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.
Part II "hardware Descriptions," has detailed information about specific hardware components of the
S3C830A/P830A microcontroller. Also included in Part II are electrical, mechanical, OTP, and development tools
data. It has 17 chapters:
Chapter 7
Clock Circuit
Chapter 16
Chapter 17
Chapter 18
Chapter 19
Chapter 20
Chapter 21
Chapter 22
Chapter 23
Serial I/O Interface
Low Voltage Reset
PLL Frequency Synthesizer
Intermediate Frequency Counter
Electrical Data
Mechanical Data
S3P830A OTP
Development Tools
Chapter 8
Chapter 9
Chapter 10
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Chapter 15
RESET and Power-Down
I/O Ports
Basic Timer and Timer 0
8-bit Timer 1
16-bit Timer 2
Watch Timer
LCD Controller/Driver
8-bit Analog-to-Digital Converter
Two order forms are included at the back of this manual to facilitate customer order for S3C830A/P830A
microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these
forms, fill them out, and then forward them to your local Samsung Sales Representative.
S3C830A/P830A MICROCONTROLLER
iii
Table of Contents
Part I — Programming Model
Chapter 1
Product Overview
S3C8-Series Microcontrollers...................................................................................................................1-1
S3C830A Microcontroller.........................................................................................................................1-1
OTP.........................................................................................................................................................1-1
Features ..................................................................................................................................................1-2
Block Diagram.........................................................................................................................................1-3
Pin Assignment........................................................................................................................................1-4
Pin Descriptions.......................................................................................................................................1-5
Pin Circuits..............................................................................................................................................1-8
Chapter 2
Address Spaces
Overview.................................................................................................................................................2-1
Program Memory (ROM) .........................................................................................................................2-2
Register Architecture ...............................................................................................................................2-3
Register Page Pointer (PP) .............................................................................................................2-5
Register Set 1 .................................................................................................................................2-6
Register Set 2 .................................................................................................................................2-6
Prime Register Space......................................................................................................................2-7
Working Registers...........................................................................................................................2-8
Using the Register Points ................................................................................................................2-9
Register Addressing.................................................................................................................................2-11
Common Working Register Area (C0H–CFH)..................................................................................2-13
4-bit Working Register Addressing...................................................................................................2-14
8-bit Working Register Addressing...................................................................................................2-16
System and User Stacks..........................................................................................................................2-18
Chapter 3
Addressing Modes
Overview.................................................................................................................................................3-1
Register Addressing Mode (R) .................................................................................................................3-2
Indirect Register Addressing Mode (IR)....................................................................................................3-3
Indexed Addressing Mode (X)..................................................................................................................3-7
Direct Address Mode (DA) .......................................................................................................................3-10
Indirect Address Mode (IA) ......................................................................................................................3-12
Relative Address Mode (RA)....................................................................................................................3-13
Immediate Mode (IM) ..............................................................................................................................3-14
S3C830A/P830A MICROCONTROLLER
v
Table of Contents (Continued)
Chapter 4
Control Registers
Overview ................................................................................................................................................ 4-1
Chapter 5
Interrupt Structure
Overview ................................................................................................................................................ 5-1
Interrupt Types ............................................................................................................................... 5-2
S3C830A Interrupt Structure........................................................................................................... 5-3
Interrupt Vector Addresses ............................................................................................................. 5-4
Enable/Disable Interrupt Instructions (EI, DI) .................................................................................. 5-6
System-Level Interrupt Control Registers........................................................................................ 5-6
Interrupt Processing Control Points................................................................................................. 5-7
Peripheral Interrupt Control Registers............................................................................................. 5-8
System Mode Register (SYM)......................................................................................................... 5-9
Interrupt Mask Register (IMR)......................................................................................................... 5-10
Interrupt Priority Register (IPR)....................................................................................................... 5-11
Interrupt Request Register (IRQ) .................................................................................................... 5-13
Interrupt Pending Function Types................................................................................................... 5-14
Interrupt Source Polling Sequence.................................................................................................. 5-15
Interrupt Service Routines .............................................................................................................. 5-15
Generating Interrupt Vector Addresses ........................................................................................... 5-16
Nesting of Vectored Interrupts ........................................................................................................ 5-16
Instruction Pointer (IP).................................................................................................................... 5-16
Fast Interrupt Processing................................................................................................................ 5-16
Chapter 6
Instruction Set
Overview ................................................................................................................................................ 6-1
Data Types..................................................................................................................................... 6-1
Register Addressing........................................................................................................................ 6-1
Addressing Modes.......................................................................................................................... 6-1
Flags Register (Flags) .................................................................................................................... 6-6
Flag Descriptions............................................................................................................................ 6-7
Instruction Set Notation .................................................................................................................. 6-8
Condition Codes............................................................................................................................. 6-12
Instruction Descriptions................................................................................................................... 6-13
vi
S3C830A/P830A MICROCONTROLLER
Table of Contents (Continued)
Part II Hardware Descriptions
Chapter 7
Clock Circuit
Overview.................................................................................................................................................7-1
System Clock Circuit .......................................................................................................................7-1
Clock Status During Power-Down Modes.........................................................................................7-2
System Clock Control Register (CLKCON)......................................................................................7-3
Chapter 8
RESET and Power-Down
System Reset ..........................................................................................................................................8-1
Overview.........................................................................................................................................8-1
Normal Mode Reset Operation ........................................................................................................8-1
Hardware Reset Values...................................................................................................................8-2
Power-Down Modes.................................................................................................................................8-5
Stop Mode.......................................................................................................................................8-5
Idle Mode ........................................................................................................................................8-6
Chapter 9
I/O Ports
Overview.................................................................................................................................................9-1
Port Data Registers .........................................................................................................................9-3
Port 0 ..............................................................................................................................................9-4
Port 1 ..............................................................................................................................................9-6
Port 2 ..............................................................................................................................................9-9
Port 3 ..............................................................................................................................................9-11
Port 4, 5 ..........................................................................................................................................9-13
Port 6, 7 ..........................................................................................................................................9-14
Port 8 ..............................................................................................................................................9-15
Chapter 10
Basic Timer and Timer 0
Overview.................................................................................................................................................10-1
Basic Timer (BT) .....................................................................................................................................10-1
Basic Timer Control Register (BTCON) ...........................................................................................10-2
Basic Timer Function Description....................................................................................................10-3
8-Bit Timer/Counter 0 ..............................................................................................................................10-5
Timer/Counter 0 Control Register (T0CON).....................................................................................10-5
Timer 0 Function Description...........................................................................................................10-8
S3C830A/P830A MICROCONTROLLER
vii
Table of Contents (Continued)
Chapter 11
8-bit Timer 1
Overview ................................................................................................................................................ 11-1
Function Description....................................................................................................................... 11-1
Timer 1 Control Register (T1CON) ................................................................................................. 11-2
Block Diagram................................................................................................................................ 11-3
Chapter 12
16-bit Timer 2
Overview ................................................................................................................................................ 12-1
Function Description....................................................................................................................... 12-1
Timer 2 Control Register (T2CON) ................................................................................................. 12-2
Block Diagram................................................................................................................................ 12-3
Chapter 13
Watch Timer
Overview ................................................................................................................................................ 13-1
Watch Timer Control Register (WTCON)........................................................................................ 13-2
Watch Timer Circuit Diagram ......................................................................................................... 13-3
Chapter 14
LCD Controller/Driver
Overview ................................................................................................................................................ 14-1
LCD Circuit Diagram....................................................................................................................... 14-2
LCD RAM Address Area................................................................................................................. 14-3
LCD Control Register (LCON), F1H at Bank 0 of Set 1................................................................... 14-4
LCD Mode Register (LMOD)........................................................................................................... 14-5
LCD Drive Voltage.......................................................................................................................... 14-7
LCD COM/SEG Signals.................................................................................................................. 14-7
viii
S3C830A/P830A MICROCONTROLLER
Table of Contents (Continued)
Chapter 15
8-bit Analog-to-Digital Converter
Overview.................................................................................................................................................15-1
Function Description................................................................................................................................15-1
Conversion Timing ..........................................................................................................................15-2
A/D Converter Control Register (ADCON) .......................................................................................15-2
Internal Reference Voltage Levels...................................................................................................15-3
Block Diagram.........................................................................................................................................15-3
Chapter 16
Serial I/O Interface
Overview.................................................................................................................................................16-1
Programming Procedure .................................................................................................................16-1
SIO0 and SIO1 Control Registers (SIO0CON, SIO1CON)...............................................................16-2
SIO0 and SIO1 Pre-Scaler Register (SIO0PS, SIO1PS)..................................................................16-4
SIO0 Block Diagram................................................................................................................................16-5
Serial I/O Timing Diagram (SIO0, SIO1)..........................................................................................16-6
Chapter 17
Low Voltage Reset
Overview.................................................................................................................................................17-1
LVREN Pin......................................................................................................................................17-1
Block Diagram.................................................................................................................................17-1
Chapter 18
PLL Frequency Synthesizer
Overview.................................................................................................................................................18-1
PLL Frequency Synthesizer Function.......................................................................................................18-2
PLL Data Register (PLLD) .......................................................................................................................18-3
Reference Frequency Generator..............................................................................................................18-4
PLL Mode Register (PLLMOD) ................................................................................................................18-5
PLL Reference Frequency Selection Register (PLLREF) .........................................................................18-7
Phase Detector, Charge PUMP, and Unlock Detector..............................................................................18-8
Using The PLL Frequency Synthesizer ....................................................................................................18-9
S3C830A/P830A MICROCONTROLLER
ix
Table of Contents (Concluded)
Chapter 19
Intermediate Frequency Counter
Overview ................................................................................................................................................ 19-1
IFC Mode Register (IFMOD)................................................................................................................... 19-2
IFC Gate Flag Register (PLLREF.5)........................................................................................................ 19-2
Gate Times............................................................................................................................................. 19-3
IF Counter (IFC) Operation ..................................................................................................................... 19-6
Input Pin Configuration ........................................................................................................................... 19-7
IFC Data Calculation............................................................................................................................... 19-8
Chapter 20
Electrical Data
Overview ................................................................................................................................................ 20-1
Chapter 21
Mechanical Data
Overview ................................................................................................................................................ 21-1
Chapter 22
S3P830A OTP
Overview ................................................................................................................................................ 22-1
Operating Mode Characteristics...................................................................................................... 22-3
Chapter 23
Development Tools
Overview ................................................................................................................................................ 23-1
SHINE............................................................................................................................................ 23-1
SAMA Assembler ........................................................................................................................... 23-1
SASM88......................................................................................................................................... 23-1
HEX2ROM...................................................................................................................................... 23-1
Target Boards................................................................................................................................. 23-1
TB830A Target Board..................................................................................................................... 23-3
SMDS2+ Selection (SAM8) ............................................................................................................ 23-5
Idle LED ......................................................................................................................................... 23-5
Stop LED........................................................................................................................................ 23-5
x
S3C830A/P830A MICROCONTROLLER
List of Figures
Figure
Title
Page
Number
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
Block Diagram........................................................................................................1-3
S3C830A Pin Assignments (100-QFP) ...................................................................1-4
Pin Circuit Type A ..................................................................................................1-8
Pin Circuit Type A-2 (EO).......................................................................................1-8
Pin Circuit Type B (RESET) ...................................................................................1-8
Pin Circuit Type B-4 ...............................................................................................1-8
Pin Circuit Type B-5 (CE).......................................................................................1-8
Pin Circuit Type C ..................................................................................................1-8
Pin Circuit Type E-4 (P0, P3) .................................................................................1-9
Pin Circuit Type D-7 (P1)........................................................................................1-9
Pin Circuit Type F-16 (P2.0-P2.3)...........................................................................1-9
Pin Circuit Type H (COM0-COM3)..........................................................................1-9
Pin Circuit Type H-39 .............................................................................................1-10
Pin Circuit Type H-41 (P4-P8) ................................................................................1-10
Pin Circuit Type D-4 (P2.4-P2.7) ............................................................................1-10
1-9
1-10
1-11
1-12
1-13
1-14
1-15
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
Program Memory Address Space...........................................................................2-2
Internal Register File Organization .........................................................................2-4
Register Page Pointer (PP) ....................................................................................2-5
Set 1, Set 2, Prime Area Register, and LCD Data Register Map.............................2-7
8-Byte Working Register Areas (Slices)..................................................................2-8
Contiguous 16-Byte Working Register Block...........................................................2-9
Non-Contiguous 16-Byte Working Register Block...................................................2-10
16-Bit Register Pair ................................................................................................2-11
Register File Addressing.........................................................................................2-12
Common Working Register Area............................................................................2-13
4-Bit Working Register Addressing.........................................................................2-15
4-Bit Working Register Addressing Example ..........................................................2-15
8-Bit Working Register Addressing.........................................................................2-16
8-Bit Working Register Addressing Example ..........................................................2-17
Stack Operations....................................................................................................2-18
2-9
2-10
2-11
2-12
2-13
2-14
2-15
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Register Addressing ...............................................................................................3-2
Working Register Addressing .................................................................................3-2
Indirect Register Addressing to Register File ..........................................................3-3
Indirect Register Addressing to Program Memory...................................................3-4
Indirect Working Register Addressing to Register File ............................................3-5
Indirect Working Register Addressing to Program or Data Memory ........................3-6
Indexed Addressing to Register File .......................................................................3-7
Indexed Addressing to Program or Data Memory with Short Offset ........................3-8
Indexed Addressing to Program or Data Memory ...................................................3-9
Direct Addressing for Load Instructions...................................................................3-10
Direct Addressing for Call and Jump Instructions....................................................3-11
Indirect Addressing.................................................................................................3-12
Relative Addressing ...............................................................................................3-13
Immediate Addressing............................................................................................3-14
3-9
3-10
3-11
3-12
3-13
3-14
S3C830A/P830A MICROCONTROLLER
xi
List of Figures (Continued)
Figure
Title
Page
Number
Number
4-1
Register Description Format .................................................................................. 4-4
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
S3C8-Series Interrupt Types.................................................................................. 5-2
S3C830A Interrupt Structure.................................................................................. 5-3
ROM Vector Address Area..................................................................................... 5-4
Interrupt Function Diagram.................................................................................... 5-7
System Mode Register (SYM)................................................................................ 5-9
Interrupt Mask Register (IMR)................................................................................ 5-10
Interrupt Request Priority Groups........................................................................... 5-11
Interrupt Priority Register (IPR).............................................................................. 5-12
Interrupt Request Register (IRQ) ........................................................................... 5-13
6-1
System Flags Register (FLAGS)............................................................................ 6-6
7-1
7-2
7-3
7-4
7-5
Main Oscillator Circuit (Crystal or Ceramic Oscillator) ........................................... 7-1
Main Oscillator Circuit (External Oscillator)........................................................... 7-1
System Clock Circuit Diagram............................................................................... 7-2
System Clock Control Register (CLKCON) ............................................................ 7-3
STOP Control Register (STPCON)........................................................................ 7-4
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
Port 0 High-Byte Control Register (P0CONH)........................................................ 9-4
Port 0 Low-Byte Control Register (P0CONL).......................................................... 9-5
Port 0 Pull-up Control Register (P0PUR) ............................................................... 9-5
Port 1 High-Byte Control Register (P1CONH)........................................................ 9-7
Port 1 Low-Byte Control Register (P1CONL).......................................................... 9-7
Port 1 Interrupt Control Register (P1INT)............................................................... 9-8
Port 1 Interrupt Pending Register (P1PND)............................................................ 9-8
Port 2 High-Byte Control Register (P2CONH)........................................................ 9-9
Port 2 Low-Byte Control Register (P2CONL).......................................................... 9-10
Port 3 High-Byte Control Register (P3CONH)........................................................ 9-11
Port 3 Low-Byte Control Register (P3CONL).......................................................... 9-12
Port 3 Pull-up Control Register (P3PUR) ............................................................... 9-12
Port Group 0 Control Register (PG0CON) ............................................................. 9-13
Port Group 1 Control Register (PG1CON) ............................................................. 9-14
Port Group 2 Control Register (PG2CON) ............................................................. 9-15
9-9
9-10
9-11
9-12
9-13
9-14
9-15
xii
S3C830A/P830A MICROCONTROLLER
List of Figures (Continued)
Page
Title
Page
Number
Number
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
Basic Timer Control Register (BTCON) ..................................................................10-2
Basic Timer Block Diagram ....................................................................................10-4
Timer 0 Control Register (T0CON) .........................................................................10-6
Timer 0 Interrupt Pending Register (INTPND).........................................................10-7
Simplified Timer 0 Function Diagram: Interval Timer Mode....................................10-8
Simplified Timer 0 Function Diagram: PWM Mode.................................................10-9
Simplified Timer 0 Function Diagram: Capture Mode .............................................10-10
Timer 0 Block Diagram...........................................................................................10-11
11-1
11-2
Timer 1 Control Register (T1CON) .........................................................................11-2
Timer 1 Functional Block Diagram..........................................................................11-3
12-1
12-2
Timer 2 Control Register (T2CON) .........................................................................12-2
Timer 2 Functional Block Diagram..........................................................................12-3
13-1
13-2
Watch Timer Control Register (WTCON) ...............................................................13-2
Watch Timer Circuit Diagram .................................................................................13-3
14-1
14-2
14-3
14-4
14-5
14-6
14-7
LCD Function Diagram...........................................................................................14-1
LCD Circuit Diagram ..............................................................................................14-2
LCD Display Data RAM Organization .....................................................................14-3
Select/No-Select Bias Signals in Static Display Mode.............................................14-7
Select/No-Select Bias Signals in 1/2 Duty, 1/2 Bias Display Mode..........................14-8
Select/No-Select Bias Signals in 1/3 Duty, 1/3 Bias Display Mode..........................14-8
Voltage Dividing Resistor Circuit Diagram..............................................................14-9
15-1
15-2
15-3
15-4
A/D Converter Control Register (ADCON) ..............................................................15-2
A/D Converter Data Register (ADDATA).................................................................15-3
A/D Converter Functional Block Diagram ...............................................................15-3
Recommended A/D Converter Circuit for Highest Absolute Accuracy.....................15-4
16-1
16-2
16-3
16-4
16-5
16-6
16-7
Serial I/O Module Control Register (SIO0CON)......................................................16-2
Serial I/O Module Control Register (SIO1CON)......................................................16-3
SIO0 Pre-scaler Register (SIO0PS)........................................................................16-4
SIO1 Pre-scaler Register (SIO1PS)........................................................................16-4
SIO0 Functional Block Diagram..............................................................................16-5
SIO1 Functional Block Diagram..............................................................................16-5
Serial I/O Timing in Transmit/Receive Mode
(Tx at falling, SIO0CON.4 or SIO1CON.4 = 0)........................................................16-6
Serial I/O Timing in Transmit/Receive Mode
16-8
(Tx at rising, SIO0CON.4 or SIO1CON.4 = 0)........................................................16-6
S3C830A/P830A MICROCONTROLLER
xiii
List of Figures (Concluded)
Page
Title
Page
Number
Number
17-1
Low Voltage Reset Block Diagram......................................................................... 17-1
18-1
18-2
18-3
Block Diagram of the PLL Frequency Synthesizer ................................................. 18-1
PLL Register Configuration.................................................................................... 18-3
Reference Frequency Generator............................................................................ 18-4
19-1
19-2
19-3
19-4
19-5
IF Counter Block Diagram ..................................................................................... 19-1
Gate Timing (1,4, or 8 ms)..................................................................................... 19-3
Gate Timing (When Open) .................................................................................... 19-4
Gate Timing (1-ms Error)....................................................................................... 19-5
AMIF and FMIF Pin Configuration ......................................................................... 19-7
20-1
20-2
20-3
20-4
20-5
20-6
20-7
Input Timing for External Interrupts (Ports 1) ......................................................... 20-5
Input Timing for RESET ........................................................................................ 20-5
Stop Mode Release Timing Initiated by RESET..................................................... 20-6
Stop Mode Release Timing Initiated by Interrupts.................................................. 20-7
Serial Data Transfer Timing................................................................................... 20-9
Clock Timing Measurement at XIN ........................................................................ 20-11
Operating Voltage Range ...................................................................................... 20-11
21-1
Package Dimensions (100-QFP-1420C) ................................................................ 21-1
22-1
22-2
S3P830A Pin Assignments (100-Pin QFP Package).............................................. 22-2
Operating Voltage Range ...................................................................................... 22-4
23-1
23-2
23-3
23-4
SMDS Product Configuration (SMDS2+) ............................................................... 23-2
TB830A Target Board Configuration..................................................................... 23-3
50-Pin Connectors (J101, J102) for TB830A.......................................................... 23-6
S3C830/F830 Probe Adapter Cables for 100-QFP Package .................................. 23-6
xiv
S3C830A/P830A MICROCONTROLLER
List of Tables
Table
Title
Page
Number
Number
1-1
2-1
S3C830A Pin Descriptions......................................................................................1-5
S3C830A Register Type Summary.........................................................................2-3
4-1
4-2
4-3
Set 1 Registers.......................................................................................................4-1
Set 1, Bank 0 Registers..........................................................................................4-2
Set 1, Bank 1 Registers..........................................................................................4-3
5-1
5-2
5-3
Interrupt Vectors.....................................................................................................5-5
Interrupt Control Register Overview........................................................................5-6
Interrupt Source Control and Data Registers...........................................................5-8
6-1
6-2
6-3
6-4
6-5
6-6
Instruction Group Summary....................................................................................6-2
Flag Notation Conventions .....................................................................................6-8
Instruction Set Symbols..........................................................................................6-8
Instruction Notation Conventions............................................................................6-9
Opcode Quick Reference .......................................................................................6-10
Condition Codes.....................................................................................................6-12
8-1
8-2
8-3
S3C830A Set 1 Register and Values after RESET..................................................8-2
S3C830A Set 1, Bank 0 Register Values after RESET ...........................................8-3
S3C830A Set 1, Bank 1 Register Values after RESET ...........................................8-4
9-1
9-2
S3C830A Port Configuration Overview...................................................................9-2
Port Data Register Summary..................................................................................9-3
14-1
14-2
14-3
14-4
14-5
LCD Control Register (LCON) Organization............................................................14-4
LCD Clock Signal (LCDCK) Frame Frequency .......................................................14-5
LCD Mode Control Register (LMOD) Organization, F2H at Bank 0 of Set 1............14-6
Maximum Number of Display Digits per Duty Cycle................................................14-6
LCD Drive Voltage Values......................................................................................14-7
18-1
18-2
PLLMOD Organization ...........................................................................................18-6
PLLREF Register Organization...............................................................................18-7
S3C830A/P830A MICROCONTROLLER
xv
List of Tables (Continued)
Table
Title
Page
Number
Number
19-1
19-2
IFMOD Organization.............................................................................................. 19-2
IF Counter Frequency Characteristics.................................................................... 19-6
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
Absolute Maximum Ratings................................................................................... 20-2
D.C. Electrical Characteristics ............................................................................... 20-2
A.C. Electrical Characteristics................................................................................ 20-5
Input/Output Capacitance...................................................................................... 20-6
Data Retention Supply Voltage in Stop Mode ........................................................ 20-6
A/D Converter Electrical Characteristics................................................................ 20-7
PLL Electrical Characteristics ................................................................................ 20-8
Low Voltage Reset Electrical Characteristics ......................................................... 20-8
Synchronous SIO Electrical Characteristics........................................................... 20-9
Main Oscillator Frequency (fx)............................................................................... 20-10
Main Oscillator Clock Stabilization Time (tST1) ...................................................... 20-10
22-1
22-2
22-3
Descriptions of Pins Used to Read/Write the EPROM............................................ 22-3
Comparison of S3P830A and S3C830A Features.................................................. 22-3
Operating Mode Selection Criteria......................................................................... 22-3
23-1
23-2
Power Selection Settings for TB830A .................................................................... 23-4
The SMDS2+ Tool Selection Setting ..................................................................... 23-5
xvi
S3C830A/P830A MICROCONTROLLER
List of Programming Tips
Description
Chapter 2:
Page
Number
Address Spaces
Using the Page Pointer for RAM clear (Page 0, Page1).......................................................................2-5
Setting the Register Pointers ...............................................................................................................2-9
Using the RPs to Calculate the Sum of a Series of Registers...............................................................2-10
Addressing the Common Working Register Area.................................................................................2-14
Standard Stack Operations Using PUSH and POP ..............................................................................2-19
S3C830A/P830A MICROCONTROLLER
xvii
List of Register Descriptions
Register
Identifier
Full Register Name
Page
Number
ADCON
BTCON
CLKCON
FLAGS
IFMOD
IMR
A/D Converter Control Register..............................................................................4-5
Basic Timer Control Register..................................................................................4-6
System Clock Control Register...............................................................................4-7
System Flags Register ...........................................................................................4-8
IF Counter Mode Register ......................................................................................4-9
Interrupt Mask Register ..........................................................................................4-10
Interrupt Pending Register......................................................................................4-11
Instruction Pointer (High Byte) ...............................................................................4-12
Instruction Pointer (Low Byte) ................................................................................4-12
Interrupt Priority Register........................................................................................4-13
Interrupt Request Register......................................................................................4-14
LCD Control Register .............................................................................................4-15
LCD Mode Control Register....................................................................................4-16
Port 0 Control Register (High Byte) ........................................................................4-17
Port 0 Control Register (Low Byte) .........................................................................4-18
Port 0 Pull-up Control Register...............................................................................4-19
Port 1 Control Register (High Byte) ........................................................................4-20
Port 1 Control Register (Low Byte) .........................................................................4-21
Port 1 Interrupt Control Register.............................................................................4-22
Port 1 Interrupt Pending Register ...........................................................................4-23
Port 2 Control Register (High Byte) ........................................................................4-24
Port 2 Control Register (Low Byte) .........................................................................4-25
Port 3 Control Register (High Byte) ........................................................................4-26
Port 3 Control Register (Low Byte) .........................................................................4-27
Port 3 Pull-up Control Register...............................................................................4-28
INTPND
IPH
IPL
IPR
IRQ
LCON
LMOD
P0CONH
P0CONL
P0PUR
P1CONH
P1CONL
P1INT
P1PND
P2CONH
P2CONL
P3CONH
P3CONL
P3PUR
S3C830A/P830A MICROCONTROLLER
xix
List of Register Descriptions (Continued)
Register
Identifier
Full Register Name
Page
Number
PG0CON
PG1CON
PG2CON
PLLMOD
PLLREF
PP
Port Group 0 Control Register ................................................................................4-29
Port Group 1 Control Register ................................................................................4-30
Port Group 2 Control Register ................................................................................4-31
PLL Mode Register.................................................................................................4-32
PLL Reference Frequency Selection Register.........................................................4-33
Register Page Pointer.............................................................................................4-34
Register Pointer 0...................................................................................................4-35
Register Pointer 1...................................................................................................4-35
SIO0 Control Register ............................................................................................4-36
SIO1 Control Register ............................................................................................4-37
Stack Pointer (High Byte) .......................................................................................4-38
Stack Pointer (Low Byte) ........................................................................................4-38
Stop Control Register .............................................................................................4-39
System Mode Register ...........................................................................................4-40
Timer 0 Control Register ........................................................................................4-41
Timer 1 Control Register ........................................................................................4-42
Timer 2 Control Register ........................................................................................4-43
Watch Timer Control Register ................................................................................4-44
RP0
RP1
SIO0CON
SIO1CON
SPH
SPL
STPCON
SYM
T0CON
T1CON
T2CON
WTCON
xx
S3C830A/P830A MICROCONTROLLER
List of Instruction Descriptions
Instruction
Mnemonic
Full Register Name
Page
Number
ADC
ADD
AND
BAND
BCP
BITC
BITR
BITS
BOR
BTJRF
BTJRT
BXOR
CALL
CCF
CLR
Add with Carry........................................................................................................6-14
Add ........................................................................................................................6-15
Logical AND...........................................................................................................6-16
Bit AND..................................................................................................................6-17
Bit Compare...........................................................................................................6-18
Bit Complement .....................................................................................................6-19
Bit Reset ................................................................................................................6-20
Bit Set....................................................................................................................6-21
Bit OR....................................................................................................................6-22
Bit Test, Jump Relative on False............................................................................6-23
Bit Test, Jump Relative on True .............................................................................6-24
Bit XOR..................................................................................................................6-25
Call Procedure .......................................................................................................6-26
Complement Carry Flag .........................................................................................6-27
Clear......................................................................................................................6-28
Complement...........................................................................................................6-29
Compare................................................................................................................6-30
Compare, Increment, and Jump on Equal ..............................................................6-31
Compare, Increment, and Jump on Non-Equal.......................................................6-32
Decimal Adjust.......................................................................................................6-33
Decrement .............................................................................................................6-35
Decrement Word....................................................................................................6-36
Disable Interrupts ...................................................................................................6-37
Divide (Unsigned)...................................................................................................6-38
Decrement and Jump if Non-Zero ..........................................................................6-39
Enable Interrupts....................................................................................................6-40
Enter......................................................................................................................6-41
Exit ........................................................................................................................6-42
Idle Operation ........................................................................................................6-43
Increment...............................................................................................................6-44
Increment Word .....................................................................................................6-45
Interrupt Return......................................................................................................6-46
Jump......................................................................................................................6-47
Jump Relative........................................................................................................6-48
Load.......................................................................................................................6-49
Load Bit..................................................................................................................6-51
COM
CP
CPIJE
CPIJNE
DA
DEC
DECW
DI
DIV
DJNZ
EI
ENTER
EXIT
IDLE
INC
INCW
IRET
JP
JR
LD
LDB
S3C830A/P830A MICROCONTROLLER
xxi
List of Instruction Descriptions (Continued)
Instruction
Mnemonic
Full Register Name
Page
Number
LDC/LDE
LDCD/LDED
LDCI/LDEI
LDCPD/LDEPD
LDCPI/LDEPI
LDW
Load Memory .........................................................................................................6-52
Load Memory and Decrement ................................................................................6-54
Load Memory and Increment..................................................................................6-55
Load Memory with Pre-Decrement .........................................................................6-56
Load Memory with Pre-Increment...........................................................................6-57
Load Word .............................................................................................................6-58
Multiply (Unsigned).................................................................................................6-59
Next .......................................................................................................................6-60
No Operation..........................................................................................................6-61
Logical OR .............................................................................................................6-62
Pop from Stack.......................................................................................................6-63
Pop User Stack (Decrementing) .............................................................................6-64
Pop User Stack (Incrementing)...............................................................................6-65
Push to Stack .........................................................................................................6-66
Push User Stack (Decrementing)............................................................................6-67
Push User Stack (Incrementing) .............................................................................6-68
Reset Carry Flag ....................................................................................................6-69
Return ....................................................................................................................6-70
Rotate Left .............................................................................................................6-71
Rotate Left through Carry .......................................................................................6-72
Rotate Right ...........................................................................................................6-73
Rotate Right through Carry.....................................................................................6-74
Select Bank 0.........................................................................................................6-75
Select Bank 1.........................................................................................................6-76
Subtract with Carry.................................................................................................6-77
Set Carry Flag........................................................................................................6-78
Shift Right Arithmetic..............................................................................................6-79
Set Register Pointer ...............................................................................................6-80
Stop Operation.......................................................................................................6-81
Subtract..................................................................................................................6-82
Swap Nibbles .........................................................................................................6-83
Test Complement under Mask................................................................................6-84
Test under Mask.....................................................................................................6-85
Wait for Interrupt ....................................................................................................6-86
Logical Exclusive OR .............................................................................................6-87
MULT
NEXT
NOP
OR
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
RCF
RET
RL
RLC
RR
RRC
SB0
SB1
SBC
SCF
SRA
SRP/SRP0/SRP1
STOP
SUB
SWAP
TCM
TM
WFI
XOR
xxii
S3C830A/P830A MICROCONTROLLER
S3C830A/P830A
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
S3C8-SERIES MICROCONTROLLERS
Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned
to specific interrupt levels.
S3C830A MICROCONTROLLER
The S3C830A single-chip microcontroller are fabricated using the highly advanced CMOS process. Its design is
based on the powerful SAM88RC CPU core. Stop and idle (power-down) modes were implemented to reduce
power consumption.
The S3C830A is a microcontroller with a 48K-byte mask-programmable ROM embedded.
The S3P830A is a microcontroller with a 48K-byte one-time-programmable ROM embedded.
Using the SAM88RC modular design approach, the following peripherals were integrated with the SAM88RC
CPU core:
— Large number of programable I/O ports (Total 72 pins)
— PLL frequency synthesizer
— 16-bits intermediate frequency counter
— Two synchronous SIO modules
— Two 8-bit timer/counters
— One 16-bit timer/counter
— Low voltage reset
— A/D converter with 4 selectable input pins
OTP
The S3C830A microcontroller is also available in OTP (One Time Programmable) version, S3P830A.
The S3P830A microcontroller has an on-chip 48K-byte one-time-programmable EPROM instead of masked
ROM. The S3P830A is comparable to S3C830A, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C830A/P830A
FEATURES
CPU
Two 8-bit Serial I/O Interface
•
SAM88RC CPU core
•
•
•
8-bit transmit/receive mode
8-bit receive mode
Selectable baud rate or external clock source
Memory
•
•
2064-byte internal register file (including LCD
display RAM)
48K-byte internal program memory area
PLL Frequency Synthesizer
•
VIN level: 300mVpp (minimum)
•
•
AMVCO range: 0.5 MHz–30 MHz
FMVCO range: 30 MHz–150 MHz
Instruction Set
•
•
78 instructions
Idle and Stop instructions
16-Bit Intermediate Frequency (IF) Counter
•
VIN level: 300mVpp (minimum)
72 I/O Pins
•
•
AMIF range: 100 kHz–1 MHz
FMIF range: 5 MHz–15 MHz
•
•
32 normal I/O pins
40 pins sharing with LCD segment signals
LCD Controller/Driver
Interrupts
•
•
•
40 segments and 4 common terminals
4/3/2 common and static selectable
Internal or external resistor circuit for LCD bias
•
•
8 interrupt levels and 17 internal sources
Fast interrupt processing feature
8-Bit Basic Timer
Low Voltage Reset (LVR)
•
•
Watchdog timer function
4 kinds of clock source
•
•
Low voltage check to make system reset
VLVR: 3.5 V (typical)
Timer/Counter 0
Two Power-Down Modes
•
•
•
Programmable 8-bit internal timer
External event counter function
PWM and capture function
•
•
Idle mode: only CPU clock stops
Stop mode: system clock and CPU clock stop
Oscillation Source
Crystal or ceramic for system clock (fx)
Timer/Counter 1
•
•
•
Programmable 8-bit interval timer
External event counter function
Instruction Execution Time
890 ns at 4.5 MHz (minimum)
•
Timer/Counter 2
•
•
Programmable 16-bit interval timer
External event counter function
Operating Temperature Range
–25 °C to +85 °C
•
Watch Timer
Operating Voltage Range
•
•
Interval Time: 50ms, 0.5s, 1.0s at 4.5 MHz
1/1.5/3/6 kHz buzzer output selectable
•
•
3.0 V to 5.5 V at 0.4 MHz–4.5 MHz
4.5 V to 5.5 V in PLL/IFC block
Analog to Digital Converter
Package Type
100-pin QFP package
•
•
4-channel analog input
8-bit conversion resolution
•
1-2
S3C830A/P830A
PRODUCT OVERVIEW
BLOCK DIAGRAM
P1.0-P1.7/
INT0-INT7
RESET
CE
XIN
XOUT
P0.0
OSC
P0.1/T0CLK
P0.2/T0CAP
P0.3/T0OUT/T0PWM
P0.4/T1CLK
P0.5/T1OUT
P0.6/T2CLK
P0.7/T2OUT
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
P0.2/T0CAP
P0.1/T0CLK
P0.3/T0OUT/T0PWM
8-Bit Timer/
Counter0
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/INT4
P1.5/INT5
P1.6/INT6
P1.7/INT7
8-Bit Timer/
Counter1
P0.4/T1CLK
P0.5/T1OUT
P0.6/T2CLK
P0.7/T2OUT
16-Bit Timer/
Counter2
I/O Port and Interrupt Control
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4
P3.1/SCK0
P3.2/SO0
P3.3/SI0
P3.4/SCK1
P3.5/SO1
P3.6/SI1
SIO 0
SIO 1
P2.5
P2.6
P2.7
P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
P3.4/SCK1
P3.5/SO1
P3.6/SI1
P3.7
Watchdog
Timer
Basic Timer
Watch Timer
P3.0/BUZ
SAM88RC Core
COM0-3
P8.7-P4.0/SEG0-39
BIAS
P4.0/SEG39
P4.1/SEG38
P4.2/SEG37
P4.3/SEG36
P4.4/SEG35
P4.5/SEG34
P4.6/SEG33
P4.7/SEG32
LCD Driver/
Controller
VLC0-VLC2
VCOAM
VCOFM
EO0/EO1
PLL
Synthesizer
P5.0/SEG31
P5.1/SEG30
P5.2/SEG29
P5.3/SEG28
P5.4/SEG27
P5.5/SEG26
P5.6/SEG25
P5.7/SEG24
AMIF
FMIF
IF Counter
8-Bit ADC
P2.0-P2.3/AD0-AD3
P6.0/SEG23
P6.1/SEG22
P6.2/SEG21
P6.3/SEG20
P6.4/SEG19
P6.5/SEG18
P6.6/SEG17
P6.7/SEG16
AVDD
Port 8
48K-byte
ROM
2064-byte
Register File
P8.0/SEG7
P8.1/SEG6
P8.2/SEG5
P8.3/SEG4
P8.4/SEG3
P8.5/SEG2
P8.6/SEG1
P8.7/SEG0
P7.0/SEG15
P7.1/SEG14
P7.2/SEG13
P7.3/SEG12
P7.4/SEG11
P7.5/SEG10
P7.6/SEG9
P7.7/SEG8
Low Voltage
Reset
LVREN
TEST1 TEST3 VDD
VSS
TEST2
VDDPLL0 VSSPLL
VDDPLL1
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C830A/P830A
PIN ASSIGNMENT
P1.7/INT7
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AMIF
VSSPLL
VCOAM
VCOFM
VDDPLL1
LVREN
TEST3
BIAS
VLC0
VLC1
VLC2
COM0
COM1
COM2
COM3
SEG0/P8.7
SEG1/P8.6
SEG2/P8.5
SEG3/P8.4
SEG4/P8.3
SEG5/P8.2
SEG6/P8.1
SEG7/P8.0
SEG8/P7.7
SEG9/P7.6
SEG10/P7.5
SEG11/P7.4
SEG12/P7.3
SEG13/P7.2
SEG14/P7.1
P2.5
P2.6
P2.7
AVDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
VDD
S3C830A
VSS
XOUT
XIN
TEST1
100-QFP-1420C
TEST2
P3.4/SCK1
RESET
P3.5/SO1
P3.6/SI1
P3.7
P4.0/SEG39
P4.1/SEG38
P4.2/SEG37
P4.3/SEG36
P4.4/SEG35
Figure 1-2. S3C830A Pin Assignments (100-QFP)
1-4
S3C830A/P830A
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C830A Pin Descriptions
Pin
Pin
Names
Pin
Type
Circuit Pin No.
Type
Share
Pins
Description
P0.0
I/O I/O port with bit programmable pins; Schmitt
trigger input or push-pull, open-drain output
and software assignable pull-ups.
E-4
86
87
88
89
90
91
92
93
–
T0CLK
T0CAP
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
T0OUT/T0PWM
T1CLK
TOUT
T2CLK
T2OUT
P1.0-P1.7
I/O I/O port with bit programmable pins; Schmitt
trigger Input or push-pull output and software
assignable pull-ups;
D-7
94-1
INT0-INT7
Alternately used for external interrupt input
(noise filters, interrupt enable and pending
control).
P2.0-P2.3
P2.4-P2.7
I/O I/O port with bit programmable pins; Schmitt
trigger input or push-pull output and software
assignable pull-ups.
F-16
D-4
2-5
6-9
AD0-AD3
–
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
I/O I/O port with bit programmable pins; Schmitt
trigger input or push-pull, open-drain output
and software assignable pull-ups.
E-4
11
12
13
14
21
23
24
25
BUZ
SCLK0
SO0
SI0
SCK1
SO1
SI1
–
P4.0-P4.7
P5.0-P5.7
P6.0-P6.7
P7.0-P7.7
P8.0-P8.7
I/O I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
H-41
H-41
H-41
H-41
H-41
26-33
34-41
42-49
50-57
58-65
SEG39-SEG32
SEG31-SEG24
SEG23-SEG16
SEG15-SEG8
SEG7-SEG0
I/O I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
I/O I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
I/O I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
I/O I/O port with nibble programmable pins;
Schmitt trigger input or push-pull, open-drain
output and software assignable pull-ups.
1-5
PRODUCT OVERVIEW
S3C830A/P830A
Table 1-1. S3C830A Pin Descriptions (Continued)
Pin
Names
Pin
Type
Pin
Description
Circuit Pin No.
Type
Share
Pins
COM0-COM3
SEG0-SEG39
BIAS
O
Common signal output for LCD display
H
69-66
65-26
73
–
I/O LCD segment signal output
H-41
–
P8-P4
I
I
LCD power control
–
–
VLC0
VLC1
VLC2
LCD power supply
Voltage dividing resistors are assignable by
software
–
72-70
VDD
VSS
–
–
Main power supply
Main ground
–
–
15
16
–
–
VDDPLL0-1
VSSPLL
AVDD
–
–
–
PLL/IFC power supply
PLL/IFC ground
–
–
–
82, 76
79
–
–
–
A/D converter power supply
10
XOUT, XIN
–
I
Main oscillator pins for CPU oscillation
Test signal input pin
–
–
17, 18
19, 20
–
–
TEST1,
TEST2
(Must be connected to VSS
)
TEST3
O
I
Test signal output pin
(Must be remained to open)
–
74
75
–
–
LVREN
LVR enable pin
A
(Must be connected to VDD or VSS
)
I
I
System reset pin
B
22
85
–
–
RESET
CE
Input pin for checking device power
Normal operation is high level and PLL/IFC
Operation is stopped at low power
B-5
EO0
EO1
O
O
I
PLL's phase error output0
A-2
A-2
B-4
83
84
–
–
–
PLL's phase error output1
VCOAM
VCOFM
External VCOAM/VCOFM signal inputs
78, 77
1-6
S3C830A/P830A
PRODUCT OVERVIEW
Table 1-1. S3C830A Pin Descriptions (Continued)
Pin
Pin
Names
Pin
Type
Circuit Pin No.
Share
Pins
Description
Type
FMIF, AMIF
AD0-AD3
BUZ
I
FM/AM intermediate frequency signal inputs
B-4
81, 80
2-5
–
I/O ADC input pins
F-16
E-4
P2.0-P2.3
P3.0
I/O 1, 1.5, 3 or 6 kHz frequency output for buzzer
sound at 4.5 MHz clock
11
SCK0
SO0
I/O SIO0 interface signal
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
E-4
D-7
12
13
14
21
23
24
87
88
89
89
90
91
92
93
94-1
P3.1
P3.2
I/O SIO0 interface data output signal
I/O SIO0 interface data input signal
I/O SIO1 interface signal
SI0
P3.3
SCK1
SO1
P3.4
I/O SIO1 interface data output signal
I/O SIO1 interface data input signal
I/O Timer 0 clock input
P3.5
SI1
P3.6
T0CLK
T0CAP
T0OUT
T0PWM
T1CLK
T1OUT
T2CLK
T2OUT
INT0-INT7
P0.1
I/O Timer 0 capture input
I/O Timer 0 clock output
P0.2
P0.3
I/O Timer 0 PWM output
P0.3
I/O Timer 1 clock input
P0.4
I/O Timer 1 clock output
P0.5
I/O Timer 2 clock input
P0.6
I/O Timer 2 clock output
P0.7
I/O External interrupt input pins
P1.0-P1.7
1-7
PRODUCT OVERVIEW
S3C830A/P830A
PIN CIRCUITS
VDD
In
Type A
P-Channel
N-Channel
Feedback
Enable
In
Pull-down
Enable
N-CH
Figure 1-3. Pin Circuit Type A
Figure 1-6. Pin Circuit Type B-4
VDD
Up
P-Channel
Out
In
Down
N-Channel
Figure 1-4. Pin Circuit Type A-2 (EO)
Figure 1-7. Pin Circuit Type B-5 (CE)
VDD
VDD
Pull-up
Resistor
P-Channel
Data
Out
In
N-Channel
Output
Disable
Schmitt Trigger
Figure 1-8. Pin Circuit Type C
Figure 1-5. Pin Circuit Type B (RESET)
1-8
S3C830A/P830A
PRODUCT OVERVIEW
VDD
DD
V
Open-Drain
Enable
Pull-up
Enable
Pull-up
Resistor
DD
V
Pull-up
Enable
Data
Output
Disable
Circuit
Type C
I/O
P-CH
N-CH
Data
I/O
ADCEN
Output
Disable
ADC Select
Data
SS
V
Schmitt Trigger
To ADC
Figure 1-9. Pin Circuit Type E-4 (P0, P3)
Figure 1-11. Pin Circuit Type F-16 (P2.0-P2.3)
VLC0
VLC1
VDD
Pull-up
P-Channel
Enable
COM
Data
Out
Circuit
Type C
I/O
Output
Disable
Port
Enable
VLC2
(PG2CON.4-5)
Schmitt Trigger
Figure 1-12. Pin Circuit Type H (COM0-COM3)
Figure 1-10. Pin Circuit Type D-7 (P1)
1-9
PRODUCT OVERVIEW
S3C830A/P830A
VLC0
VDD
VLC1
Pull-up
Enable
Out
SEG
Data
Circuit
Type C
I/O
Output
Disable
Output
Disable
VLC2
Figure 1-15. Pin Circuit Type D-4 (P2.4-P2.7)
Figure 1-13. Pin Circuit Type H-39
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Open
Drain
P-CH
N-CH
Data
I/O
Output
Disable1
SEG
Circuit
Type H-39
Output
Disable2
Figure 1-14. Pin Circuit Type H-41 (P4-P8)
1-10
S3C830A/P830A
ADDRESS SPACES
2
ADDRESS SPACES
OVERVIEW
The S3C830A microcontroller has two types of address space:
— Internal program memory (ROM)
— Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.
The S3C830A has an internal 48-Kbyte mask-programmable ROM.
The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes.
A 20-byte LCD display register file is implemented.
There are 2,134 mapped registers in the internal register file. Of these, 2,064 are for general-purpose.
(This number includes a 16-byte working register common area used as a "scratch area" for data operations,
eight 192-byte prime register areas, and eight 64-byte areas (Set 2)). Thirteen 8-bit registers are used for the
CPU and the system control, and 57 registers are mapped for peripheral controls and data registers. Ten register
locations are not mapped.
2-1
ADDRESS SPACES
S3C830A/P830A
PROGRAM MEMORY (ROM)
Program memory (ROM) stores program codes or table data. The S3C830A has 48K bytes internal mask-
programmable program memory.
The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this
address range can be used as normal program memory. If you use the vector address area to store a program
code, be careful not to overwrite the vector addresses stored in these locations.
The ROM address at which a program execution starts after a reset is 0100H.
(Decimal)
49,151
(HEX)
BFFFH
48K-bytes
Internal
Program
Memory Area
255
0
FFH
0H
Interrupt
Vector Area
Figure 2-1. Program Memory Address Space
2-2
S3C830A/P830A
ADDRESS SPACES
REGISTER ARCHITECTURE
In the S3C830A implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called
set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank
1), and the lower 32-byte area is a single 32-byte common area.
In case of S3C830A the total number of addressable 8-bit registers is 2134. Of these 2134 registers, 13 bytes are
for CPU and system control registers, 57 bytes are for peripheral control and data registers, 16 bytes are used as
a shared working registers, and 2048 registers are for general-purpose use, page 0-page 7 (including 20 bytes for
LCD display registers).
You can always address set 1 register locations, regardless of which of the eight register pages is currently
selected. Set 1 locations, however, can only be addressed using register addressing modes.
The extension of register space into separately addressable areas (sets, banks, and pages) is supported by
various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer
(PP).
Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2–1.
Table 2-1. S3C830A Register Type Summary
Register Type
Number of Bytes
General-purpose registers (including the 16-byte
common working register area, eight 192-byte prime
register area (including LCD data registers), and eight
64-byte set 2 area).
2,064
CPU and system control registers
Mapped clock, peripheral, I/O control, and data registers
13
57
2,134
Total Addressable Bytes
2-3
ADDRESS SPACES
S3C830A/P830A
FFH
FFH
FFH
FFH
Page 7
Set 1
FFH
FFH
Bank 1
Page 1
Page 0
Bank 0
32
Bytes
System and
Peripheral Control
Set 2
Registers
(Register Addressing Mode)
Registers
(Indirect Register,
Indexed Mode,
E0H
DFH
64
Bytes
System Registers
(Register Addressing Mode)
and Stack Operations)
256
Bytes
D0H
CFH
Working Registers
(Working Register
Addressing Only)
C0H
BFH
Page 0
C0H
13H
~
~
~
Prime
Data Registers
(All Addressing Modes)
192
Page 7
~
~
Bytes
Prime
Data Registers
(All Addressing Modes)
LCD Display Register
20
Bytes
~
~
00H
00H
Figure 2-2. Internal Register File Organization
2-4
S3C830A/P830A
ADDRESS SPACES
REGISTER PAGE POINTER (PP)
The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using
an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the
register page pointer (PP, DFH). In the S3C830A microcontroller, a paged register file expansion is implemented
for LCD data registers, and the register page pointer must be changed to address other pages.
After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always
"0000", automatically selecting page 0 as the source and destination page for register addressing.
Register Page Pointer (PP)
DFH ,Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Destination register page selection bits:
Source register page selection bits:
0000 Source: Page 0
0000
Destination: Page 0
NOTE:
A hardware reset operation writes the 4-bit destination and
source values shown above to the register page pointer. These values should
be modified to address other pages.
Figure 2-3. Register Page Pointer (PP)
+
PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1)
LD
SRP
LD
CLR
DJNZ
CLR
PP,#00H
#0C0H
R0,#0FFH
@R0
R0,RAMCL0
@R0
; Destination ¬ 0, Source ¬
0
; Page 0 RAM clear starts
RAMCL0
; R0 = 00H
LD
LD
CLR
DJNZ
CLR
PP,#10H
R0,#0FFH
@R0
R0,RAMCL1
@R0
; Destination ¬ 1, Source ¬
; Page 1 RAM clear starts
0
RAMCL1
; R0 = 00H
NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.
2-5
ADDRESS SPACES
S3C830A/P830A
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.
The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and
bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware
reset operation always selects bank 0 addressing.
The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 57 mapped system and
peripheral control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte
common working register area (C0H–CFH). You can use the common working register area as a “scratch” area
for data operations being performed in other areas of the register file.
Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing (For more information about
working register addressing, please refer to Chapter 3, "Addressing Modes.")
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. For the S3C830A,
the set 2 address range (C0H–FFH) is accessible on pages 0-7.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only
Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register
Indirect addressing mode or Indexed addressing mode.
The set 2 register area of page 0 is commonly used for stack operations.
2-6
S3C830A/P830A
ADDRESS SPACES
PRIME REGISTER SPACE
The lower 192 bytes (00H–BFH) of the S3C830A's eight 256-byte register pages is called prime register area.
Prime registers can be accessed using any of the seven addressing modes
(see Chapter 3, "Addressing Modes.")
The prime register area on page 0 is immediately addressable following a reset. In order to address prime
registers on pages 0, 1, 2, 3, 4, 5, 6, or 7 you must set the register page pointer (PP) to the appropriate source
and destination values.
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
Page 4
FFH
Page 3
FFH
Page 2
FFH
FFH
Set 1
Page 1
Bank 0
Bank 1
Page 0
FFH
FCH
E0H
D0H
C0H
Set 2
Page 7
C0H
BFH
Page 0
13H
00H
LCD Data
Register Area
Prime
Space
CPU and system control
General-purpose
Peripheral and I/O
LCD data register
00H
Figure 2-4. Set 1, Set 2, Prime Area Register, and LCD Data Register Map
2-7
ADDRESS SPACES
S3C830A/P830A
WORKING REGISTERS
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one
that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:
— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)
— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)
All the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.
The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).
FFH
Slice 32
F8H
F7H
F0H
Slice 31
1 1 1 1 1 X X X
Set 1
Only
RP1 (Registers R8-R15)
Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.
CFH
C0H
~
~
0 0 0 0 0 X X X
10H
FH
8H
7H
0H
RP0 (Registers R0-R7)
Slice 2
Slice 1
Figure 2-5. 8-Byte Working Register Areas (Slices)
2-8
S3C830A/P830A
ADDRESS SPACES
USING THE REGISTER POINTS
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction.
(see Figures 2-6 and 2-7).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed
addressing modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice
(see Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-
contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to either of the two 8-byte slices in the working register block, you can
flexibly define the working register area to support program requirements.
+
PROGRAMMING TIP — Setting the Register Pointers
SRP
SRP1
SRP0
CLR
LD
#70H
#48H
#0A0H
RP0
RP1,#0F8H
; RP0 ¬ 70H, RP1 ¬ 78H
; RP0 ¬ no change, RP1 ¬ 48H,
; RP0 ¬ A0H, RP1 ¬ no change
; RP0 ¬ 00H, RP1 ¬ no change
; RP0 ¬ no change, RP1 ¬ 0F8H
Register File
Contains 32
8-Byte Slices
0 0 0 0 1 X X X
RP1
FH (R15)
16-Byte
Contiguous
Working
8-Byte Slice
8-Byte Slice
8H
7H
0 0 0 0 0 X X X
RP0
Register block
0H (R0)
Figure 2-6. Contiguous 16-Byte Working Register Block
2-9
ADDRESS SPACES
S3C830A/P830A
F7H (R7)
F0H (R0)
8-Byte Slice
16-Byte
Contiguous
working
Register File
Contains 32
8-Byte Slices
1 1 1 1 0 X X X
Register block
RP0
0 0 0 0 0 X X X
RP1
7H (R15)
0H (R0)
8-Byte Slice
Figure 2-7. Non-Contiguous 16-Byte Working Register Block
+
PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H
contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:
SRP0
ADD
ADC
ADC
ADC
ADC
#80H
; RP0 ¬ 80H
; R0 ¬ R0 + R1
; R0 ¬ R0 + R2 + C
; R0 ¬ R0 + R3 + C
; R0 ¬ R0 + R4 + C
; R0 ¬ R0 + R5 + C
R0,R1
R0,R2
R0,R3
R0,R4
R0,R5
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used
to calculate the sum of these registers, the following instruction sequence would have to be used:
ADD
ADC
ADC
ADC
ADC
80H,81H
80H,82H
80H,83H
80H,84H
80H,85H
; 80H ¬ (80H) + (81H)
; 80H ¬ (80H) + (82H) + C
; 80H ¬ (80H) + (83H) + C
; 80H ¬ (80H) + (84H) + C
; 80H ¬ (80H) + (85H) + C
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
2-10
S3C830A/P830A
ADDRESS SPACES
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or register
pair, you can access any location in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that
space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and
the least significant byte is always stored in the next (+1) odd-numbered register.
Working register addressing differs from Register addressing as it uses a register pointer to identify a specific
8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB
Rn
LSB
n = Even address
Rn+1
Figure 2-8. 16-Bit Register Pair
2-11
ADDRESS SPACES
S3C830A/P830A
Special-Purpose Registers
Bank 1 Bank 0
General-Purpose Register
FFH
FFH
Control
Registers
E0H
D0H
Set 2
System
Registers
CFH
C0H
C0H
BFH
RP1
RP0
Register
Pointers
Each register pointer (RP) can independently point
to one of the 24 8-byte "slices" of the register file
(other than set 2). After a reset, RP0 points to
locations C0H-C7H and RP1 to locations C8H-CFH
(that is, to the common working register area).
Prime
Registers
LCD Data
Registers
NOTE:
In the S3C830A microcontroller,
pages 0-7 are implemented.
Pages 0-7 contain all of the addressable
registers in the internal register file.
00H
Page 0
Page 0
Register Addressing Only
All
Indirect Register,
Indexed
All
Addressing
Modes
Addressing
Modes
Addressing
Modes
Can be Pointed
Can be Pointed by Register Pointer
by register Pointer
Figure 2-9. Register File Addressing
2-12
S3C830A/P830A
ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H–CFH)
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations
C0H–CFH, as the active 16-byte working register block:
RP0 ® C0H–C7H
RP1 ® C8H–CFH
This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages.
FFH
Page 7
FFH
Page 6
FFH
Page 5
FFH
Page 4
FFH
Page 3
FFH
Page 2
FFH
Page 1
Set 1
FFH
Page 0
FFH
FCH
0
Set 2
E0H
~
~
D0H
C0H
Page 7
C0H
BFH
~
Page 0
13H
00H
~
LCD Data
Registers
~
~
~
Following a hardware reset, register
pointers RP0 and RP1 point to the
common working register area,
locations C0H-CFH.
Prime
Space
~
~
RP0 = 1 1 0 0
RP1 = 1 1 0 0
0 0 0 0
1 0 0 0
00H
Figure 2-10. Common Working Register Area
2-13
ADDRESS SPACES
S3C830A/P830A
+
PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Examples 1. LD
0C2H,40H
; Invalid addressing mode!
Use working register addressing instead:
SRP
LD
#0C0H
R2,40H
; R2 (C2H) ¬ the value in location 40H
2. ADD
0C3H,#45H
; Invalid addressing mode!
Use working register addressing instead:
SRP
ADD
#0C0H
R3,#45H
; R3 (C3H) ¬ R3 + 45H
4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:
— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).
— The five high-order bits in the register pointer select an 8-byte slice of the register space.
— The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.
Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
2-14
S3C830A/P830A
ADDRESS SPACES
RP0
RP1
Selects
RP0 or RP1
Address
OPCODE
4-bit address
provides three
low-order bits
Register pointer
provides five
high-order bits
Together they create an
8-bit register address
Figure 2-11. 4-Bit Working Register Addressing
RP0
RP1
0 1 1 1 0 0 0 0
0 1 1 1 1 0 0 0
Selects RP0
R6
OPCODE
Register
Instruction
'INC R6'
address
(76H)
0 1 1 1 0 1 1 0
0 1 1 0 1 1 1 0
Figure 2-12. 4-Bit Working Register Addressing Example
2-15
ADDRESS SPACES
S3C830A/P830A
8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
"1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.
As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.
Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).
RP0
RP1
Selects
RP0 or RP1
Address
These address
bits indicate 8-bit
working register
addressing
8-bit logical
address
1
1
0
0
Register pointer
provides five
Three low-order bits
high-order bits
8-bit physical address
Figure 2-13. 8-Bit Working Register Addressing
2-16
S3C830A/P830A
ADDRESS SPACES
RP0
0 1 1 0 0
RP1
1 0 1 0 1
0 0 0
0 0 0
Selects RP1
R11
8-bit address
form instruction
'LD R11, R2'
Register
address
(0ABH)
1 1 0 0
1
0 1 1
1 0 1 0 1
0 1 1
Specifies working
register addressing
Figure 2-14. 8-Bit Working Register Addressing Example
2-17
ADDRESS SPACES
S3C830A/P830A
SYSTEM AND USER STACK
The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH
and POP instructions are used to control system stack operations. The S3C830A architecture supports stack
operations in the internal register file.
Stack Operations
Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-15.
High Address
PCL
PCL
PCH
Top of
PCH
Top of
stack
stack
Flags
Stack contents
after a call
Stack contents
after an
instruction
interrupt
Low Address
Figure 2-15. Stack Operations
User-Defined Stacks
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
Stack Pointers (SPL, SPH)
Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations.
The most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least
significant byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined.
Because only internal memory space is implemented in the S3C830A, the SPL must be initialized to an 8-bit
value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if
necessary.
When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the
register file), you can use the SPH register as a general-purpose data register. However, if an overflow or
underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register
during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register,
overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can
initialize the SPL value to "FFH" instead of "00H".
2-18
S3C830A/P830A
ADDRESS SPACES
+
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD
SPL,#0FFH
; SPL ¬ FFH
; (Normally, the SPL is set to 0FFH by the initialization
; routine)
•
•
•
PUSH
PUSH
PUSH
PUSH
•
PP
; Stack address 0FEH ¬ PP
; Stack address 0FDH ¬ RP0
; Stack address 0FCH ¬ RP1
; Stack address 0FBH ¬ R3
RP0
RP1
R3
•
•
POP
POP
POP
POP
R3
; R3 ¬ Stack address 0FBH
; RP1 ¬ Stack address 0FCH
; RP0 ¬ Stack address 0FDH
; PP ¬ Stack address 0FEH
RP1
RP0
PP
2-19
ADDRESS SPACES
S3C830A/P830A
NOTES
2-20
S3C830A/P830A
ADDRESSING MODES
3
ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM88RC instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are
available for each instruction. The seven addressing modes and their symbols are:
— Register (R)
— Indirect Register (IR)
— Indexed (X)
— Direct Address (DA)
— Indirect Address (IA)
— Relative Address (RA)
— Immediate (IM)
3-1
ADDRESSING MODES
S3C830A/P830A
REGISTER ADDRESSING MODE (R)
In Register addressing mode (R), the operand value is the content of a specified register or register pair
(see Figure 3-1).
Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte
working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Program Memory
Register File
OPERAND
8-bit Register
File Address
dst
Point to One
Register in Register
File
OPCODE
One-Operand
Instruction
(Example)
Value used in
Instruction Execution
Sample Instruction:
DEC
CNTR
;
Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File
RP0 or RP1
MSB Point to
RP0 or RP1
Selected
RP points
to start
Program Memory
of working
register
block
4-bit
Working Register
3 LSBs
dst
src
Point to the
Working Register
(1 of 8)
OPCODE
OPERAND
Two-Operand
Instruction
(Example)
Sample Instruction:
ADD R1, R2
;
Where R1 and R2 are registers in the curruntly
selected working register area.
Figure 3-2. Working Register Addressing
3-2
S3C830A/P830A
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of
the operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Please note, however, that you cannot access locations C0H–FFH in
set 1 using the Indirect Register addressing mode.
Program Memory
Register File
ADDRESS
8-bit Register
File Address
dst
Point to One
Register in Register
File
OPCODE
One-Operand
Instruction
(Example)
Address of Operand
used by Instruction
OPERAND
Value used in
Instruction Execution
Sample Instruction:
RL
@SHIFT
;
Where SHIFT is the label of an 8-bit register address
Figure 3-3. Indirect Register Addressing to Register File
3-3
ADDRESSING MODES
S3C830A/P830A
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory
Example
REGISTER
PAIR
dst
Instruction
References
Program
Points to
Register Pair
OPCODE
16-Bit
Memory
Address
Points to
Program
Memory
Program Memory
OPERAND
Sample Instructions:
Value used in
Instruction
CALL
JP
@RR2
@RR2
Figure 3-4. Indirect Register Addressing to Program Memory
3-4
S3C830A/P830A
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
MSB Points to
RP0 or RP1
RP0 or RP1
Selected
RP points
to start fo
working register
block
Program Memory
~
~
~
~
4-bit
Working
Register
Address
3 LSBs
dst
src
Point to the
Working Register
(1 of 8)
ADDRESS
OPERAND
OPCODE
Sample Instruction:
OR R3, @R6
Value used in
Instruction
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
ADDRESSING MODES
S3C830A/P830A
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
Program Memory
4-bit Working
Register Address
dst
src
Register
Pair
Next 2-bit Point
to Working
Register Pair
(1 of 4)
OPCODE
Example Instruction
References either
Program Memory or
Data Memory
16-Bit
address
points to
program
memory
or data
Program Memory
or
Data Memory
LSB Selects
memory
Value used in
Instruction
OPERAND
Sample Instructions:
LDC
LDE
LDE
R5,@RR6
R3,@RR14
@RR4, R8
;
;
;
Program memory access
External data memory access
External data memory access
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
S3C830A/P830A
ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory. Please note, however, that you cannot access
locations C0H–FFH in set 1 using Indexed addressing mode.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128
to +127. This applies to external memory accesses only (see Figure 3-8.)
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address
(see Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for
external data memory, when implemented.
Register File
RP0 or RP1
~
~
~
~
Selected RP
points to
start of
working
register
block
Value used in
Instruction
OPERAND
+
Program Memory
Base Address
3 LSBs
Two-Operand
Instruction
Example
dst/src
x
INDEX
Point to One of the
Woking Register
(1 of 8)
OPCODE
Sample Instruction:
LD R0, #BASE[R1]
;
Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
3-7
ADDRESSING MODES
S3C830A/P830A
INDEXED ADDRESSING MODE (Continued)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
~
~
Program Memory
OFFSET
NEXT 2 Bits
4-bit Working
Register Address
dst/src
OPCODE
Register
Pair
x
Point to Working
Register Pair
(1 of 4)
16-Bit
address
added to
offset
Program Memory
or
LSB Selects
Data Memory
+
16-Bits
8-Bits
Value used in
Instruction
OPERAND
16-Bits
Sample Instructions:
LDC
LDE
R4, #04H[RR2]
R4,#04H[RR2]
;
;
The values in the program address (RR2 + 04H)
are loaded into register R4.
Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
S3C830A/P830A
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
Program Memory
~
~
OFFSET
OFFSET
NEXT 2 Bits
4-bit Working
Register Address
Register
Pair
dst/src
src
Point to Working
Register Pair
OPCODE
16-Bit
address
added to
offset
Program Memory
or
LSB Selects
Data Memory
+
16-Bits
8-Bits
Value used in
Instruction
OPERAND
16-Bits
Sample Instructions:
LDC
LDE
R4, #1000H[RR2]
R4,#1000H[RR2]
;
;
The values in the program address (RR2 + 1000H)
are loaded into register R4.
Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory
3-9
ADDRESSING MODES
S3C830A/P830A
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Memory
Address
Used
Program Memory
Upper Address Byte
Lower Address Byte
dst/src "0" or "1"
OPCODE
LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
Sample Instructions:
LDC
LDE
R5,1234H
R5,1234H
;
;
The values in the program address (1234H)
are loaded into register R5.
Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
3-10
S3C830A/P830A
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Memory
Address
Used
Upper Address Byte
Lower Address Byte
OPCODE
Sample Instructions:
JP
C,JOB1
;
;
Where JOB1 is a 16-bit immediate address
Where DISPLAY is a 16-bit immediate address
CALL DISPLAY
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
ADDRESSING MODES
S3C830A/P830A
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be
executed. Only the CALL instruction can use the Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are
assumed to be all zeros.
Program Memory
Next Instruction
LSB Must be Zero
dst
Current
OPCODE
Instruction
Lower Address Byte
Upper Address Byte
Program Memory
Locations 0-255
Sample Instruction:
CALL #40H
;
The 16-bit value in program memory addresses 40H
and 41H is the subroutine start address.
Figure 3-12. Indirect Addressing
3-12
S3C830A/P830A
ADDRESSING MODES
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified
in the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.
Several program control instructions use the Relative Address mode to perform conditional jumps. The
instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
Program Memory
Next OPCODE
Program Memory
Address Used
Current
PC Value
+
Displacement
OPCODE
Current Instruction
Signed
Displacement Value
Sample Instructions:
JR
ULT,$+OFFSET
;
Where OFFSET is a value in the range +127 to -128
Figure 3-13. Relative Addressing
3-13
ADDRESSING MODES
S3C830A/P830A
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the
operand field itself. The operand may be one byte or one word in length, depending on the instruction used.
Immediate addressing mode is useful for loading constant values into registers.
Program Memory
OPERAND
OPCODE
(The Operand value is in the instruction)
Sample Instruction:
LD
R0,#0AAH
Figure 3-14. Immediate Addressing
3-14
S3C830A/P830A
CONTROL REGISTER
4
CONTROL REGISTERS
OVERVIEW
In this chapter, detailed descriptions of the S3C830A control registers are presented in an easy-to-read format.
You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates
the important features of the standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.
Data and counter registers are not described in detail in this reference chapter. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.
The locations and read/write characteristics of all mapped registers in the S3C830A register file are listed in
Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, “RESET and Power-
Down."
Table 4-1. Set 1 Registers
Register Name
Mnemonic
Address
Decimal Hex
Locations D0H-D2H are not mapped.
R/W
RESET Values (bit)
7
6
5
4
3
2
1
0
Basic timer control register
System clock control register
System flags register
BTCON
CLKCON
FLAGS
RP0
211
212
213
214
215
216
217
218
219
220
221
222
223
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
x
1
1
x
x
x
x
0
x
0
0
0
0
x
1
1
x
x
x
x
0
x
–
0
0
0
x
0
0
x
x
x
x
0
x
–
0
0
0
x
0
0
x
x
x
x
0
x
x
0
0
0
x
0
1
x
x
x
x
0
x
x
0
0
0
x
–
–
x
x
x
x
0
x
x
0
0
0
0
–
–
x
x
x
x
0
x
0
0
0
0
0
–
–
x
x
x
x
0
x
0
0
Register pointer 0
Register pointer 1
RP1
Stack pointer (high byte)
Stack pointer (low byte)
Instruction pointer (high byte)
Instruction pointer (low byte)
Interrupt request register
Interrupt mask register
System mode register
Register page pointer
SPH
SPL
IPH
IPL
IRQ
IMR
R/W
R/W
R/W
SYM
PP
4-1
CONTROL REGISTERS
Register Name
S3C830A/P830A
Table 4-2. Set 1, Bank 0 Registers
Mnemonic
Address
Decimal
R/W
RESET Values (bit)
Hex
E0H
E1H
E2H
E3H
E4H
E5H
E6H
7
0
1
0
0
1
0
–
6
0
1
0
0
1
0
–
5
0
1
0
0
1
0
–
4
0
1
0
0
1
0
–
3
0
1
0
0
1
0
–
2
0
1
0
0
1
0
–
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
Timer 0 counter register
Timer 0 data register
T0CNT
T0DATA
T0CON
T1CNT
224
225
226
227
228
229
230
R
R/W
R/W
R
Timer 0 control register
Timer 1 counter register
Timer 1 data register
T1DATA
T1CON
INTPND
R/W
R/W
R/W
Timer 1 control register
Interrupt pending register
Location E7H is not mapped.
Watch timer control register
SIO 0 control register
SIO 0 data register
WTCON
SIO0CON
SIO0DATA
SIO0PS
SIO1CON
SIO1DATA
SIO1PS
ADCON
ADDATA
LCON
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
x
0
0
–
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
–
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
–
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
–
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
0
0
0
x
x
SIO 0 prescaler register
SIO 1 control register
SIO 1 data register
SIO 1 prescaler register
A/D converter control register
A/D converter data register
LCD control register
LCD mode register
R/W
R/W
R/W
R
LMOD
IF counter mode register
IF counter 1
IFMOD
IFCNT1
IFCNT0
PLLD1
IF counter 0
R
PLL data register 1
R/W
R/W
(note)
(note)
PLL data register 0
PLLD0
(note)
PLL mode register
PLLMOD
PLLREF
(note)
PLL reference frequency register
Location FAH is not mapped.
STPCON 251 FBH
Location FCH is not mapped.
BTCNT 253 FDH
Location FEH is not mapped.
IPR 255 FFH
STOP control register
Basic timer counter
R/W
R/W
R/W
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
Interrupt priority register
NOTE: Refer to the corresponding register in this chapter.
4-2
S3C830A/P830A
CONTROL REGISTER
Table 4-3. Set 1, Bank 1 Registers
Register Name
Mnemonic
Address
Decimal
R/W
RESET Values (bit)
Hex
E0H
E1H
E2H
7
0
0
0
6
0
0
0
5
0
0
0
4
0
0
0
3
0
0
0
2
0
0
0
1
0
0
0
0
0
0
0
Port 0 control register (high byte)
Port 0 control register (low byte)
P0CONH
P0CONL
P0PUR
224
225
226
R/W
R/W
R/W
Port 0 pull-up resistors enable
register
Location E3H is not mapped.
Port 1 control register (high byte)
Port 1 control register (low byte)
Port 1 interrupt control register
Port 1 interrupt pending register
Port 2 control register (high byte)
Port 2 control register (low byte)
Port 3 control register (high byte)
Port 3 control register (low byte)
P1CONH
P1CONL
P1INT
228
229
230
231
232
233
234
235
236
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P1PND
P2CONH
P2CONL
P3CONH
P3CONL
P3PUR
Port 3 pull-up resistors enable
register
Port group 0 control register
Port group 1 control register
Port group 2 control register
Port 0 data register
PG0CON
237
238
239
240
241
242
243
244
245
246
247
248
EDH
EEH
EFH
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PG1CON
PG2CON
P0
Port 1 data register
P1
Port 2 data register
P2
Port 3 data register
P3
Port 4 data register
P4
Port 5 data register
P5
Port 6 data register
P6
Port 7 data register
P7
Port 8 data register
P8
Location F9H is not mapped.
Timer 2 counter (high byte)
Timer 2 counter (low byte)
Timer 2 data register (high byte)
Timer 2 data register (low byte)
Timer 2 control register
T2CNTH
T2CNTL
T2DATAH
T2DATAL
T2CON
250
251
252
253
254
FAH
FBH
FCH
FDH
FEH
R
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
R
R/W
R/W
R/W
Location FFH is not mapped.
4-3
CONTROL REGISTERS
S3C830A/P830A
Bit number(s) that is/are appended to
the register name for bit addressing
Name of individual
bit or related bits
Register location
in the internal
register file
Register address
(hexadecimal)
Register ID
Register name
FLAGS
-
System Flags Register
D5H
Set 1
Bit Identifier
RESET Value
Read/Write
Bit Addressing
Mode
.7
x
.6
x
.5
x
.4
x
.3
x
.2
.1
.0
0
x
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register addressing mode only
.7
Carry Flag (C)
Operation does not generate a carry or borrow condition
Operation generates carry-out or borrow into high-order bit 7
0
0
.6
.5
Zero Flag (Z)
Operation result is a non-zero value
Operation result is zero
0
0
Sign Flag (S)
Operation generates positive number (MSB = "0")
0
0
Operation generates negative number (MSB = "1")
R = Read-only
W = Write-only
R/W = Read/write
'-' = Not used
Description of the
effect of specific
bit settings
Bit number:
MSB = Bit 7
LSB = Bit 0
Type of addressing
that must be used to
address the bit
RESET value notation:
'-' = Not used
'x' = Undetermined value
'0' = Logic zero
(1-bit, 4-bit, or 8-bit)
'1' = Logic one
Figure 4-1. Register Description Format
4-4
S3C830A/P830A
CONTROL REGISTER
ADCON — A/D Converter Control Register
EFH
Set 1, Bank 0
Bit Identifier
.7
–
.6
–
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
–
–
R/W
R/W
R
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
Not used for the S3C830A
A/D Input Pin Selection Bits
0
0
1
1
0
1
0
1
AD0 (P2.0)
AD1 (P2.1)
AD2 (P2.2)
AD3 (P2.3)
.3
End-of-Conversion Bit (read-only)
0
1
Conversion not complete
Conversion complete
.2–.1
Clock Source Selection Bits
0
0
1
1
0
1
0
1
fxx/16
fxx/8
fxx/4
fxx
.0
Start or Enable Bit
0
1
Disable operation
Start operation (automatically disable operation after conversion complete).
4-5
CONTROL REGISTERS
S3C830A/P830A
BTCON — Basic Timer Control Register
D3H
Set 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.4
.3–.2
Watchdog Timer Function Disable Code (for System Reset)
1
0
1
0
Disable watchdog timer function
Enable watchdog timer function
Others
Basic Timer Input Clock Selection Bits
fxx/4096 (3)
fxx/1024
fxx/128
0
0
1
1
0
1
0
1
fxx/16
Basic Timer Counter Clear Bit (1)
.1
0
1
No effect
Clear the basic timer counter value
Clock Frequency Divider Clear Bit for all timers (2)
.0
0
1
No effect
Clear both clock frequency dividers
NOTES:
1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to “00H”. Immediately following the write
operation, the BTCON.1 value is automatically cleared to “0”.
2. When you write a “1” to BTCON.0, the corresponding frequency divider is cleared to “00H”. Immediately following the
write operation, the BTCON.0 value is automatically cleared to “0”.
3. The fxx is selected clock for system (main OSC. only for S3C830A).
4-6
S3C830A/P830A
CONTROL REGISTER
CLKCON— System Clock Control Register
D4H
Set 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
–
–
R/W
R/W
–
–
–
Addressing Mode
Register addressing mode only
.7
Oscillator IRQ Wake-up Function Bit
0
1
Enable IRQ for main wake-up in power down mode
Disable IRQ for main wake-up in power down mode
.6–.5
.4–.3
Not used for the S3C830A
CPU Clock (System Clock) Selection Bits (note)
0
0
1
1
0
1
0
1
fxx/16
fxx/8
fxx/2
fxx
.2–.0
Not used for the S3C830A
NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load
the appropriate values to CLKCON.3 and CLKCON.4.
4-7
CONTROL REGISTERS
S3C830A/P830A
FLAGS— System Flags Register
D5H
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
Carry Flag (C)
0
1
Operation does not generate a carry or borrow condition
Operation generates a carry-out or borrow into high-order bit 7
Zero Flag (Z)
0
1
Operation result is a non-zero value
Operation result is zero
Sign Flag (S)
0
1
Operation generates a positive number (MSB = "0")
Operation generates a negative number (MSB = "1")
Overflow Flag (V)
0
1
Operation result is £ +127 or ³ –128
Operation result is > +127 or < –128
Decimal Adjust Flag (D)
0
1
Add operation completed
Subtraction operation completed
Half-Carry Flag (H)
0
1
No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3
Fast Interrupt Status Flag (FIS)
0
1
Interrupt return (IRET) in progress (when read)
Fast interrupt service routine in progress (when read)
Bank Address Selection Flag (BA)
0
1
Bank 0 is selected
Bank 1 is selected
4-8
S3C830A/P830A
CONTROL REGISTER
IFMOD— IF Counter Mode Register
F3H
Set 1, Bank 0
Bit Identifier
.7
–
.6
–
.5
–
.4
–
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
–
–
–
–
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.4
.3–.2
Not used for the S3C830A
Interrupt Sampling Clock Selection Bits
0
0
1
1
0
1
0
1
IFC is disabled; FMIF/AMIF are pulled down and FMIF/AMIF's feed-back
resistor are off.
Enable IFC operation; AMIF pin is selected; FMIF is pulled down and
FMIF's feed-back resistor is off.
Enable IFC operation; FMIF pin is selected; AMIF is pulled down and
AMIF's feed-back resistor is off.
Enable IFC operation; Both AMIF and FMIF are selected.
.1–.0
Gate Time Selection Bits
0
0
1
1
0
1
0
1
Gate opens in 1-millisecond intervals
Gate opens in 4-millisecond intervals
Gate opens in 8-millisecond intervals
Gate remains open continuously
4-9
CONTROL REGISTERS
S3C830A/P830A
IMR— Interrupt Mask Register
DDH
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
.0
x
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
Interrupt Level 7 (IRQ7) Enable Bit; IF Interrupt
Disable (mask)
0
1
Enable (unmask)
Interrupt Level 6 (IRQ6) Enable Bit; CE Interrupt
Disable (mask)
0
1
Enable (unmask)
Interrupt Level 5 (IRQ5) Enable Bit; P1.4-P1.7
0
1
Disable (mask)
Enable (unmask)
Interrupt Level 4 (IRQ4) Enable Bit; P1.0-P1.3
0
1
Disable (mask)
Enable (unmask)
Interrupt Level 3 (IRQ3) Enable Bit; Watch Timer
0
1
Disable (mask)
Enable (unmask)
.2
.1
.0
Interrupt Level 2 (IRQ2) Enable Bit; SIO 0, SIO 1 Interrupt
0
1
Disable (mask)
Enable (unmask)
Interrupt Level 1 (IRQ1) Enable Bit; Timer 1, Timer 2 Interrupt
0
1
Disable (mask)
Enable (unmask)
Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match/Capture or Overflow
0
1
Disable (mask)
Enable (unmask)
NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.
4-10
S3C830A/P830A
CONTROL REGISTER
INTPND— Interrupt Pending Register
E6H
Set 1, Bank 0
Bit Identifier
.7
–
.6
–
.5
–
.4
–
.3
–
.2
–
.1
0
.0
0
RESET Value
Read/Write
–
–
–
–
–
–
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.2
.1
Not used for the S3C830A
Timer 0 Match/Capture Interrupt Pending Bit
0
1
Interrupt request is not pending (when read), pending bit clear (when write 0)
Interrupt request is pending
.0
Timer 0 Overflow Interrupt Pending Bit
0
1
Interrupt request is not pending (when read), pending bit clear (when write 0)
Interrupt request is pending
4-11
CONTROL REGISTERS
S3C830A/P830A
IPH— Instruction Pointer (High Byte)
DAH
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
.0
x
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
Instruction Pointer Address (High Byte)
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL
register (DBH).
IPL— Instruction Pointer (Low Byte)
DBH
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
Instruction Pointer Address (Low Byte)
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction
pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH
register (DAH).
4-12
S3C830A/P830A
CONTROL REGISTER
IPR— Interrupt Priority Register
FFH
Set 1, Bank 0
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Priority Control Bits for Interrupt Groups A, B, and C (note)
.7, .4, and .1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Group priority undefined
B > C > A
A > B > C
B > A > C
C > A > B
C > B > A
A > C > B
Group priority undefined
.6
.5
.3
.2
.0
Interrupt Subgroup C Priority Control Bit
0
1
IRQ6 > IRQ7
IRQ7 > IRQ6
Interrupt Group C Priority Control Bit
0
1
IRQ5 > (IRQ6, IRQ7)
(IRQ6, IRQ7) > IRQ5
Interrupt Subgroup B Priority Control Bit
0
1
IRQ3 > IRQ4
IRQ4 > IRQ3
Interrupt Group B Priority Control Bit
0
1
IRQ2 > (IRQ3, IRQ4)
(IRQ3, IRQ4) > IRQ2
Interrupt Group A Priority Control Bit
0
1
IRQ0 > IRQ1
IRQ1 > IRQ0
NOTE: Interrupt Group A - IRQ0, IRQ1
Interrupt Group B - IRQ2, IRQ3, IRQ4
Interrupt Group C - IRQ5, IRQ6, IRQ7
4-13
CONTROL REGISTERS
S3C830A/P830A
IRQ— Interrupt Request Register
DCH
Set 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R
R
R
R
R
R
R
R
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
Level 7 (IRQ7) Request Pending Bit; IF Interrupt
0
1
Not pending
Pending
Level 6 (IRQ6) Request Pending Bit; CE Interrupt
0
1
Not pending
Pending
Level 5 (IRQ5) Request Pending Bit; P1.4-P1.7
0
1
Not pending
Pending
Level 4 (IRQ4) Request Pending Bit; P1.0-P1.3
0
1
Not pending
Pending
Level 3 (IRQ3) Request Pending Bit; Watch Timer
0
1
Not pending
Pending
Level 2 (IRQ2) Request Pending Bit; SIO 0, SIO 1 Interrupt
0
1
Not pending
Pending
Level 1 (IRQ1) Request Pending Bit; Timer 1, Timer 2 Interrupt
0
1
Not pending
Pending
Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow
0
1
Not pending
Pending
4-14
S3C830A/P830A
CONTROL REGISTER
LCON — LCD Control Register
F1H
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
–
–
–
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
LCD Output Control Bit
0
1
LCD output is low and current to dividing resistors is cut off
IF LMOD.3 = "0", LCD display is turned off
IF LMOD.3 = "1", output COM and SEG signals in display mode
.6–.4
.3–.0
Not used for the S3C830A
LCD Port Selection Bit
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Select LCD SEG0-39
Select LCD SEG0-35/P4.0-4.3 as I/O port
Select LCD SEG0-31/P4 as I/O port
Select LCD SEG0-27/P4, P5.0-5.3 as I/O port
Select LCD SEG0-23/P4, P5 as I/O port
Select LCD SEG0-19/P4, P5, P6.0-6.3 as I/O port
Select LCD SEG0-15/P4, P5, P6 as I/O port
Select LCD SEG0-11/P4, P5, P6, P7.0-7.3 as I/O port
Select LCD SEG0-7/P4, P5, P6, P7 as I/O port
Select LCD SEG0-3/P4, P5, P6, P7, P8.0-8.3 as I/O port
All I/O port (P4-P8)
4-15
CONTROL REGISTERS
S3C830A/P830A
LMOD — LCD Mode Control Register
F2H
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
COM Signal Enable/Disable Bit
0
1
Enable COM signal
Disable COM signal
.6
LCD Voltage Dividing Resistor Control Bit
0
1
Internal voltage dividing resistors
External voltage dividing resistors; internal voltage dividing resistors are off
.5–.4
LCD Clock (LCDCK) Frequency Selection Bits
0
0
1
1
0
1
0
1
62.5 Hz at fxx = 4.5 MHz
125 Hz at fxx = 4.5 MHz
250 Hz at fxx = 4.5 MHz
500 Hz at fxx = 4.5 MHz
.3–.0
Duty and Bias Selection for LCD Display
0
1
1
1
1
1
x
0
0
0
0
1
x
0
0
1
1
0
x
0
1
1
0
0
LCD display off (COM and SEG output low)
1/4 duty, 1/3 bias
1/3 duty, 1/3 bias
1/3 duty, 1/2 bias
1/2 duty, 1/2 bias
Static
4-16
S3C830A/P830A
CONTROL REGISTER
P0CONH— Port 0 Control Register (High Byte)
E0H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P0.7/T2OUT
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (T2OUT)
Output mode, push-pull
P0.6/T2CLK
0
0
1
1
0
1
0
1
Input mode (T2CLK)
Output mode, open-drain
Not available
Output mode, push-pull
P0.5/T1OUT
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (T1OUT)
Output mode, push-pull
P0.4/T1CLK
0
0
1
1
0
1
0
1
Input mode (T1CLK)
Output mode, open-drain
Not available
Output mode, push-pull
4-17
CONTROL REGISTERS
S3C830A/P830A
P0CONL— Port 0 Control Register (Low Byte)
E1H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P0.3/T0OUT/T0PWM
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (T0OUT, T0PWM)
Output mode, push-pull
P0.2/T0CAP
0
0
1
1
0
1
0
1
Input mode (T0CAP)
Output mode, open-drain
Not available
Output mode, push-pull
P0.1/T0CLK
0
0
1
1
0
1
0
1
Input mode (T0CLK)
Output mode, open-drain
Not available
Output mode, push-pull
P0.0
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Not available
Output mode, push-pull
4-18
S3C830A/P830A
CONTROL REGISTER
P0PUR— Port 0 Pull-up Control Register
E2H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P0.7 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P0.6 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P0.5 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P0.4 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P0.3 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P0.2 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P0.1 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P0.0 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
4-19
CONTROL REGISTERS
S3C830A/P830A
P1CONH — Port 1 Control Register (High Byte)
E4H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P1.7/INT7
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Schmitt trigger input mode; interrupt on rising or falling edge
Output mode, push-pull
P1.6/INT6
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Schmitt trigger input mode; interrupt on rising or falling edge
Output mode, push-pull
P1.5/INT5
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Schmitt trigger input mode; interrupt on rising or falling edge
Output mode, push-pull
P1.4/INT4
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Schmitt trigger input mode; interrupt on rising or falling edge
Output mode, push-pull
4-20
S3C830A/P830A
CONTROL REGISTER
P1CONL — Port 1 Control Register (Low Byte)
E5H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P1.3/INT3
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Schmitt trigger input mode; interrupt on rising or falling edge
Output mode, push-pull
P1.2/INT2
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Schmitt trigger input mode; interrupt on rising or falling edge
Output mode, push-pull
P1.1/INT1
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Schmitt trigger input mode; interrupt on rising or falling edge
Output mode, push-pull
P1.0/INT0
0
0
1
1
0
1
0
1
Schmitt trigger input mode; pull-up; interrupt on falling edge
Schmitt trigger input mode; interrupt on rising edge
Schmitt trigger input mode; interrupt on rising or falling edge
Output mode, push-pull
4-21
CONTROL REGISTERS
S3C830A/P830A
P1INT — Port 1 Interrupt Control Register
F6H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P1.7 External Interrupt (INT7) Enable Bit
0
1
Disable interrupt
Enable interrupt
P1.6 External Interrupt (INT6) Enable Bit
0
1
Disable interrupt
Enable interrupt
P1.5 External Interrupt (INT5) Enable Bit
0
1
Disable interrupt
Enable interrupt
P1.4 External Interrupt (INT4) Enable Bit
0
1
Disable interrupt
Enable interrupt
P1.3 External Interrupt (INT3) Enable Bit
0
1
Disable interrupt
Enable interrupt
P1.2 External Interrupt (INT2) Enable Bit
0
1
Disable interrupt
Enable interrupt
P1.1 External Interrupt (INT1) Enable Bit
0
1
Disable interrupt
Enable interrupt
P1.0 External Interrupt (INT0) Enable Bit
0
1
Disable interrupt
Enable interrupt
4-22
S3C830A/P830A
CONTROL REGISTER
P1PND — Port 1 Interrupt Pending Register
F7H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P1.7/INT7 Interrupt Pending Bit
0
1
Interrupt request is not pending, pending bit clear when write 0
Interrupt request is pending
P1.6/INT6 Interrupt Pending Bit
0
1
Interrupt request is not pending, pending bit clear when write 0
Interrupt request is pending
P1.5/INT5 Interrupt Pending Bit
0
1
Interrupt request is not pending, pending bit clear when write 0
Interrupt request is pending
P1.4/INT4 Interrupt Pending Bit
0
1
Interrupt request is not pending, pending bit clear when write 0
Interrupt request is pending
P1.3/INT3 Interrupt Pending Bit
0
1
Interrupt request is not pending, pending bit clear when write 0
Interrupt request is pending
P1.2/INT2 Interrupt Pending Bit
0
1
Interrupt request is not pending, pending bit clear when write 0
Interrupt request is pending
P1.1/INT1 Interrupt Pending Bit
0
1
Interrupt request is not pending, pending bit clear when write 0
Interrupt request is pending
P1.0/INT0 Interrupt Pending Bit
0
1
Interrupt request is not pending, pending bit clear when write 0
Interrupt request is pending
4-23
CONTROL REGISTERS
S3C830A/P830A
P2CONH— Port 2 Control Register (High Byte)
E8H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5-.4
.3–.2
.1–.0
P2.7
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Not available
Output mode, push-pull
P2.6
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Not available
Output mode, push-pull
P2.5
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Not available
Output mode, push-pull
P2.4
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Not available
Output mode, push-pull
4-24
S3C830A/P830A
CONTROL REGISTER
P2CONL— Port 2 Control Register (Low Byte)
E9H
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P2.3/AD3
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Alternative function (ADC mode)
Output mode, push-pull
P2.2/AD2
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Alternative function (ADC mode)
Output mode, push-pull
P2.1/AD1
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Alternative function (ADC mode)
Output mode, push-pull
P2.0/AD0
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Alternative function (ADC mode)
Output mode, push-pull
4-25
CONTROL REGISTERS
S3C830A/P830A
P3CONH— Port 3 Control Register (High Byte)
EAH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P3.7
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Not available
Output mode, push-pull
P3.6/SI1
0
0
1
1
0
1
0
1
Input mode (SI1)
Output mode, open-drain
Not available
Output mode, push-pull
P3.5/SO1
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (SO1)
Output mode, push-pull
P3.4/SCK1
0
0
1
1
0
1
0
1
Input mode (SCK1)
Output mode, pull-up
Alternative function (SCK1 out)
Output mode, push-pull
4-26
S3C830A/P830A
CONTROL REGISTER
P3CONL— Port 3 Control Register (Low Byte)
EBH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P3.3/SI0
0
0
1
1
0
1
0
1
Input mode (SI0)
Output mode, open-drain
Not available
Output mode, push-pull
P3.2/SO0
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (SO0)
Output mode, push-pull
P3.1/SCK0
0
0
1
1
0
1
0
1
Input mode (SCK0)
Output mode, open-drain
Alternative function (SCK0 out)
Output mode, push-pull
P3.0/BUZ
0
0
1
1
0
1
0
1
Input mode
Output mode, open-drain
Alternative function (BUZ)
Output mode, push-pull
4-27
CONTROL REGISTERS
S3C830A/P830A
P3PUR— Port 3 Pull-up Control Register
ECH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P3.7 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.6 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.5 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.4 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.3 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.2 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.1 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
P3.0 Pull-up Resistor Enable Bit
0
1
Pull-up disable
Pull-up enable
4-28
S3C830A/P830A
CONTROL REGISTER
PG0CON— Port Group 0 Control Register
EDH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P4.0-P4.3/SEG39-36 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P4.4-P4.7/SEG35-32 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P5.0-P5.3/SEG31-28 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P5.4-P5.7/SEG27-24 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
4-29
CONTROL REGISTERS
S3C830A/P830A
PG1CON— Port Group 1 Control Register
EEH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.6
.5–.4
.3–.2
.1–.0
P6.0-P6.3/SEG23-20 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P6.4-P6.7/SEG19-16 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P7.0-P7.3/SEG15-12 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
P7.4-P7.7/SEG11-8 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
4-30
S3C830A/P830A
CONTROL REGISTER
PG2CON— Port Group 2 Control Register
EFH
Set 1, Bank 1
Bit Identifier
.7
–
.6
–
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
–
–
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Not used for the S3C830A
P1.4-P1.7 Input Enable Bits
.7–.6
.5
0
1
Port 1.4-1.7 input enable
Port 1.4-1.7 input disable
.4
P1.0-P1.3 Input Enable Bits
0
1
Port 1.0-1.3 input enable
Port 1.0-1.3 input disable
.3–.2
P8.0-P8.3/SEG7-4 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
.1–.0
P8.4-P8.7/SEG3-0 Mode Selection Bits
0
0
1
1
0
1
0
1
Input mode
Input mode, pull-up
Open-drain output mode
Push-pull output mode
4-31
CONTROL REGISTERS
S3C830A/P830A
PLLMOD— PLL Mode Register
F8H
Set 1, Bank 0
Bit Identifier
.7
.6
.5
.4
–
.3
0
.2
0
.1
.0
0
(note)
(note)
(note)
0
RESET Value
Read/Write
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
PLL Frequency Division Method Selection Flag
0
1
Direct method for AM
Pulse swallow method for FM
PLL Enable/Disable Bit
0
1
Disable PLL
Enable PLL
Bit Value to be Loaded into Swallow Counter
NF bit is loaded into the LSB of swallow counter
.4
.3
Not used for the S3C830A
INTIF Interrupt Enable Bit
0
1
Disable INTIF interrupt
Enable INTIF interrupt
.2
INTIF Interrupt Pending Bit
0
0
1
Interrupt is not pending (when read)
Clear pending bit (when write)
Interrupt is pending (when read)
.1
.0
INTCE Interrupt Enable Bit
0
1
Disable INTCE interrupt requests at the CE pin
Enable INTCE interrupt requests at the CE pin
INTCE Interrupt Pending Bit
0
0
1
Interrupt is not pending (when read)
Clear pending bit (when write)
Interrupt is pending (when read)
NOTE: If a system reset occurs during operation mode, the current value contained is retained. If a system reset occurs
after power-on, the value is undefined.
4-32
S3C830A/P830A
CONTROL REGISTER
PLLREF— PLL Reference Frequency Selection Register
F9H
Set 1, Bank 0
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
RESET Value
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
PLL Frequency Synthesizer Locked/Unlocked Status Flag
0
1
PLL is currently in locked state
PLL is currently in unlocked state
.6
CE Pin level Status Flag
0
1
CE pin is currently low level
CE pin is currently high level
.5
IF Counter Gate Open/Close Status Flag
0
1
Gate is currently open
Gate is currently close
Power on Flag (3)
.4
0
1
Clear power-on flag bit (when write)
Power-on occurred (when read)
.3 – .0
Reference Frequency Selection Bits
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1-kHz signal
3-kHz signal
5-kHz signal
6.25-kHz signal
9-kHz signal
10-kHz signal
12.5-kHz signal
25-kHz signal
50-kHz signal
100-kHz signal
NOTES:
1. If a system reset occurs during operation mode, the current value contained is retained. If a system reset occurs after
power-on, the value is undefined.
2. If a system reset occurs during operation mode, the current value contained is retained. If a system reset occurs after
power-on, the value is "1".
3. The POF bit is read initially to check whether or not power has been turned on.
4-33
CONTROL REGISTERS
S3C830A/P830A
PP— Register Page Pointer
DFH
Set 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.4
Destination Register Page Selection Bits
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Destination: page 0
Destination: page 1
Destination: page 2
Destination: page 3
Destination: page 4
Destination: page 5
Destination: page 6
Destination: page 7
.3 – .0
Source Register Page Selection Bits
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Source: page 0
Source: page 1
Source: page 2
Source: page 3
Source: page 4
Source: page 5
Source: page 6
Source: page 7
NOTE: In the S3C830A microcontroller, the internal register file is configured as eight pages (Pages 0-7).
The pages 0-6 are used for general purpose register file, and page 4 is used for LCD data register or general
purpose registers.
4-34
S3C830A/P830A
CONTROL REGISTER
RP0— Register Pointer 0
D6H
Set 1
Bit Identifier
.7
1
.6
1
.5
0
.4
0
.3
0
.2
–
.1
–
.0
–
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
–
–
–
Addressing Mode
Register addressing only
.7–.3
.2–.0
Register Pointer 0 Address Value
Register pointer 0 can independently point to one of the 256-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP0 points to address C0H in register set 1, selecting the 8-byte working register
slice C0H–C7H.
Not used for the S3C830A
RP1— Register Pointer 1
D7H
Set 1
Bit Identifier
.7
1
.6
1
.5
0
.4
0
.3
1
.2
–
.1
–
.0
–
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
–
–
–
Addressing Mode
Register addressing only
.7 – .3
Register Pointer 1 Address Value
Register pointer 1 can independently point to one of the 256-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP1 points to address C8H in register set 1, selecting the 8-byte working register
slice C8H–CFH.
.2 – .0
Not used for the S3C830A
4-35
CONTROL REGISTERS
S3C830A/P830A
SIO0CON— SIO 0 Control Register
E9H
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
SIO 0 Shift Clock Selection Bit
.7
.6
.5
.4
0
1
Internal clock (P.S clock)
External clock (SCK0)
Data Direction Control Bit
0
1
MSB-first mode
LSB-first mode
SIO 0 Mode Selection Bit
0
1
Receive-only mode
Transmit/receive mode
Shift Clock Edge Selection Bit
0
1
Tx at falling edges, Rx at rising edges
Tx at rising edges, Rx at falling edges
SIO 0 Counter Clear and Shift Start Bit
.3
.2
.1
.0
0
1
No action
Clear 3-bit counter and start shifting
SIO 0 Shift Operation Enable Bit
0
1
Disable shifter and clock counter
Enable shifter and clock counter
SIO 0 Interrupt Enable Bit
0
1
Disable SIO 0 Interrupt
Enable SIO 0 Interrupt
SIO 0 Interrupt Pending Bit
0
0
1
No interrupt pending
Clear pending condition (when write)
Interrupt is pending
4-36
S3C830A/P830A
CONTROL REGISTER
SIO1CON— SIO 1 Control Register
ECH
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
SIO 1 Shift Clock Selection Bit
.7
.6
.5
.4
0
1
Internal clock (P.S clock)
External clock (SCK1)
Data Direction Control Bit
0
1
MSB-first mode
LSB-first mode
SIO 1 Mode Selection Bit
0
1
Receive-only mode
Transmit/receive mode
Shift Clock Edge Selection Bit
0
1
Tx at falling edges, Rx at rising edges
Tx at rising edges, Rx at falling edges
SIO 1 Counter Clear and Shift Start Bit
.3
.2
.1
.0
0
1
No action
Clear 3-bit counter and start shifting
SIO 1 Shift Operation Enable Bit
0
1
Disable shifter and clock counter
Enable shifter and clock counter
SIO 1 Interrupt Enable Bit
0
1
Disable SIO 1 Interrupt
Enable SIO 1 Interrupt
SIO 1 Interrupt Pending Bit
0
0
1
No interrupt pending
Clear pending condition (when write)
Interrupt is pending
4-37
CONTROL REGISTERS
S3C830A/P830A
SPH— Stack Pointer (High Byte)
D8H
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
.0
x
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
Stack Pointer Address (High Byte)
The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer
address (SP15–SP8). The lower byte of the stack pointer value is located in register
SPL (D9H). The SP value is undefined following a reset.
SPL— Stack Pointer (Low Byte)
D9H
Set 1
Bit Identifier
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
Stack Pointer Address (Low Byte)
The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer
address (SP7–SP0). The upper byte of the stack pointer value is located in register
SPH (D8H). The SP value is undefined following a reset.
4-38
S3C830A/P830A
CONTROL REGISTER
STPCON— Stop Control Register
FBH
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.0
STOP Control Bits
1 0 1 0 0 1 0 1 Enable stop instruction
Other values Disable stop instruction
NOTE: Before execute the STOP instruction, set this STPCON register as “10100101b”. Otherwise the STOP
instruction will not execute as well as reset will be generated.
4-39
CONTROL REGISTERS
S3C830A/P830A
SYM— System Mode Register
DEH
Set 1
Bit Identifier
.7
0
.6
–
.5
–
.4
x
.3
x
.2
x
.1
.0
0
0
RESET Value
Read/Write
R/W
–
–
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Not used, But you must keep "0"
Not used for the S3C830A
.7
.6–.5
.4–.2
Fast Interrupt Level Selection Bits (1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Fast Interrupt Enable Bit (2)
.1
0
1
Disable fast interrupt processing
Enable fast interrupt processing
Global Interrupt Enable Bit (3)
.0
0
1
Disable all interrupt processing
Enable all interrupt processing
NOTES:
1. You can select only one interrupt level at a time for fast interrupt processing.
2. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2-SYM.4.
3. Following a reset, you must enable global interrupt processing by executing an EI instruction
(not by writing a "1" to SYM.0).
4-40
S3C830A/P830A
CONTROL REGISTER
T0CON— Timer 0 Control Register
E2H
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.5
Timer 0 Input Clock Selection Bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fxx/1024
fxx/256
fxx/64
fxx/8
fxx
External clock (T0CLK) falling edge
External clock (T0CLK) rising edge
Counter stop
.4–.3
Timer 0 Operating Mode Selection Bits
0
0
1
1
0
1
0
1
Interval mode
Capture mode (capture on rising edge, counter running, OVF can occur)
Capture mode (capture on falling edge, counter running, OVF can occur)
PWM mode (OVF & match interrupt can occur)
Timer 0 Counter Clear Bit (note)
.2
.1
.0
0
1
No effect
Clear the timer 0 counter (when write)
Timer 0 Match/Capture Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
Timer 0 Overflow Interrupt Enable
0
1
Disable overflow interrupt
Enable overflow interrupt
NOTE: When you write a "1" to T0CON.2, the timer 0 counter value is cleared to "00H". Immediately following the write
operation, the T0CON.2 value is automatically cleared to "0".
4-41
CONTROL REGISTERS
S3C830A/P830A
T1CON— Timer 1 Control Register
E5H
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.5
Timer 1 Input Clock Selection Bits
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
fxx/256
fxx/64
fxx/8
fxx
External clock (T1CLK) input
.4
.3
Not used for the S3C830A
Timer 1 Counter Clear Bit (Note)
0
1
No effect
Clear the timer 1 counter (when write)
.2
.1
.0
Timer 1 Counter Enable Bit
0
1
Disable counting operation
Enable counting operation
Timer 1 Interrupt Enable Bit
0
1
Disable timer 1 interrupt
Enable timer 1 interrupt
Timer 1 Interrupt Pending Bit
0
0
1
No timer 1 interrupt pending (when read)
Clear timer 1 interrupt pending condition (when write)
T1 interrupt is pending
NOTE: When you write a "1" to T1CON.3, the timer 1 counter value is cleared to "00H”. Immediately following the write
operation, the T1CON.3 value is automatically cleared to "0".
4-42
S3C830A/P830A
CONTROL REGISTER
T2CON— Timer 2 Control Register
FEH
Set 1, Bank 1
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
RESET Value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7–.5
Timer 2 Input Clock Selection Bits
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
fxx/256
fxx/64
fxx/8
fxx
External clock (T2CLK) input
.4
.3
Not used for the S3C830A
Timer 2 Counter Clear Bit (Note)
0
1
No effect
Clear the timer 2 counter (when write)
.2
.1
.0
Timer 2 Counter Enable Bit
0
1
Disable counting operation
Enable counting operation
Timer 2 Interrupt Enable Bit
0
1
Disable timer 2 interrupt
Enable timer 2 interrupt
Timer 2 Interrupt Pending Bit
0
0
1
No timer 2 interrupt pending (when read)
Clear timer 2 interrupt pending bit (when write)
T2 interrupt is pending
NOTE: When you write a "1" to T2CON.3, the timer 2 counter value is cleared to "00H". Immediately following the write
operation, the T2CON.3 value is automatically cleared to "0".
4-43
CONTROL REGISTERS
S3C830A/P830A
WTCON— Watch Timer Control Register
E8H
Set 1, Bank 0
Bit Identifier
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
.0
0
0
RESET Value
Read/Write
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Not used for the S3C830A
Watch Timer Enable Bit
.7
.6
0
1
Disable watch timer; clear frequency dividing circuits
Enable watch timer
.5–.4
.3–.2
Buzzer Signal Selection Bits (at 4.5 MHz)
0
0
1
1
0
1
0
1
1 kHz buzzer (BUZ) signal output
1.5 kHz buzzer (BUZ) signal output
3 kHz buzzer (BUZ) signal output
6 kHz buzzer (BUZ) signal output
Watch Timer Speed Selection Bits (at 4.5 MHz)
0
0
1
0
1
1
1.0 s Interval
0.5 s Interval
50 ms Interval
.1
.0
Watch Timer Interrupt Enable Bit
0
1
Disable watch timer interrupt
Enable watch timer interrupt
Watch Timer Interrupt Pending Bit
0
1
1
Interrupt is not pending (when read)
Clear pending bit (when write)
Interrupt is pending (when read)
4-44
S3C830A/P830A
INTERRUPT STRUCTURE
5
INTERRUPT STRUCTURE
OVERVIEW
The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM88RC
CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt
level has more than one vector address, the vector priorities are established in hardware. A vector address can
be assigned to one or more sources.
Levels
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks
can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight
possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an
interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from
device to device. The S3C830A interrupt structure recognizes eight interrupt levels.
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just
identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels
is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by
IPR settings lets you define more complex priority relationships between different levels.
Vectors
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all.
The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors
used for S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the
vector priorities are set in hardware. S3C830A uses seventeen vectors.
Sources
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.
Each vector can have several interrupt sources. In the S3C830A interrupt structure, there are seventeen possible
interrupt sources.
When a service routine starts, the respective pending bit should be either cleared automatically by hardware or
cleared "manually" by program software. The characteristics of the source's pending mechanism determine which
method would be used to clear its respective pending bit.
5-1
INTERRUPT STRUCTURE
INTERRUPT TYPES
S3C830A/P830A
The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are
combined to determine the interrupt structure of an individual device and to make full use of its available
interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1,
2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):
Type 1:
Type 2:
Type 3:
One level (IRQn) + one vector (V1) + one source (S1)
One level (IRQn) + one vector (V1) + multiple sources (S1 – Sn)
One level (IRQn) + multiple vectors (V1 – Vn) + multiple sources (S1 – Sn , Sn+1 – Sn+m
)
In the S3C830A microcontroller, two interrupt types are implemented.
Levels
Vectors
Sources
Type 1:
Type 2:
IRQn
V1
S1
S1
IRQn
IRQn
V1
S2
S3
Sn
V1
V2
V3
Vn
S1
Type 3:
NOTES:
S2
S3
Sn
Sn + 1
Sn + 2
Sn + m
1. The number of Sn and Vn value is expandable.
2. In the S3C830A implementation,
interrupt types 1 and 3 are used.
Figure 5-1. S3C8-Series Interrupt Types
5-2
S3C830A/P830A
INTERRUPT STRUCTURE
S3C830A INTERRUPT STRUCTURE
The S3C830A microcontroller supports seventeen interrupt sources. All seventeen of the interrupt sources have a
corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific
interrupt structure, as shown in Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a
single level are fixed in hardware).
When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the
program counter value and status flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the
service routine is executed.
Levels
Vectors
Sources
Reset/Clear
100H
H/W
RESET
Basic timer overflow
Timer 0 match/capture
Timer 0 overflow
Timer 2 match
S/W
E0H
E2H
E4H
E6H
E8H
EAH
F2H
IRQ0
IRQ1
H/W,S/W
S/W
S/W
Timer 1 match
S/W
SIO1 interrupt
IRQ2
IRQ3
S/W
SIO0 interrupt
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
S/W
Watch timer
D0H
D2H
D4H
D6H
D8H
DAH
DCH
DEH
C0H
C2H
P1.0 external interrupt
P1.1 external interrupt
P1.2 external interrupt
P1.3 external interrupt
P1.4 external interrupt
P1.5 external interrupt
P1.6 external interrupt
P1.7 external interrupt
CE interrupt
IRQ4
IRQ5
IRQ6
IRQ7
IF interrupt
NOTES:
1. Within a given interrupt level, the low vector address has high priority.
For example, E0H has higher priority than E2H within the level IRQ0.
The priorities within each level are set at the factory.
2. External interrupts are triggered by a rising or falling edge, depending on the
corresponding control register setting.
Figure 5-2. S3C830A Interrupt Structure
5-3
INTERRUPT STRUCTURE
S3C830A/P830A
INTERRUPT VECTOR ADDRESSES
All interrupt vector addresses for the S3C830A interrupt structure are stored in the vector address area of the first
256 bytes of the program memory (ROM).
You can allocate unused locations in the vector address area as normal program memory. If you do so, please be
careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
The program reset address in the ROM is 0100H.
(Decimal)
49,151
(HEX)
BFFFH
48K-byte
Program Memory
Area
100H
FFH
RESET
Address
255
0
Interrupt
Vector Address
Area
00H
Figure 5-3. ROM Vector Address Area
5-4
S3C830A/P830A
INTERRUPT STRUCTURE
Request Reset/Clear
Table 5-1. Interrupt Vectors
Interrupt Source
Vector Address
Decimal
Value
Hex
Value
Interrupt
Level
Priority in H/W
Level
S/W
256
100H
Basic timer overflow
–
Ö
Ö
RESET
226
224
230
228
234
232
242
214
212
210
208
222
220
218
216
192
194
E2H
E0H
E6H
E4H
EAH
E8H
F2H
D6H
D4H
D2H
D0H
DEH
DCH
DAH
D8H
C0H
C2H
Timer 0 overflow
Timer 0 match/capture
Timer 1 match
IRQ0
1
0
1
0
1
0
–
3
2
1
0
3
2
1
0
–
–
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
IRQ1
IRQ2
Timer 2 match
SIO0 interrupt
SIO1 interrupt
Watch timer
IRQ3
IRQ4
P1.3 external interrupt
P1.2 external interrupt
P1.1 external interrupt
P1.0 external interrupt
P1.7 external interrupt
P1.6 external interrupt
P1.5 external interrupt
P1.4 external interrupt
CE interrupt
IRQ5
IRQ6
IRQ7
IF interrupt
NOTES:
1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.
5-5
INTERRUPT STRUCTURE
S3C830A/P830A
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)
Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then
serviced as they occur according to the established priorities.
NOTE
The system initialization routine executed after a reset must always contain an EI instruction to globally
enable the interrupt structure.
During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable
interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register.
SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS
In addition to the control registers for specific interrupt sources, four system-level registers control interrupt
processing:
— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.
— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.
— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to
each interrupt source).
— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable
fast interrupts and control the activity of external interface, if implemented).
Table 5-2. Interrupt Control Register Overview
Control Register
ID
R/W
Function Description
Interrupt mask register
IMR
R/W
Bit settings in the IMR register enable or disable interrupt
processing for each of the eight interrupt levels: IRQ0–IRQ7.
Interrupt priority register
IPR
R/W
Controls the relative processing priorities of the interrupt
levels. The eight levels of S3C830A are organized into three
groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is
IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.
Interrupt request register
System mode register
IRQ
R
This register contains a request pending bit for each interrupt
level.
SYM
R/W
This register enables/disables fast interrupt processing, and
dynamic global interrupt processing.
NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.
5-6
S3C830A/P830A
INTERRUPT STRUCTURE
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.
The system-level control points in the interrupt structure are:
— Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )
— Interrupt level enable/disable settings (IMR register)
— Interrupt level priority settings (IPR register)
— Interrupt source enable/disable settings in the corresponding peripheral control registers
NOTE
When writing an application program that handles interrupt processing, be sure to include the necessary
register file address (register pointer) information.
EI
S
R
Q
Interrupt Request Register
(Read-only)
Polling
Cycle
RESET
IRQ0-IRQ7,
Interrupts
Interrupt Priority
Register
Vector
Interrupt
Cycle
Interrupt Mask
Register
Global Interrupt Control
(EI, DI or SYM.0
manipulation)
Figure 5-4. Interrupt Function Diagram
5-7
INTERRUPT STRUCTURE
S3C830A/P830A
PERIPHERAL INTERRUPT CONTROL REGISTERS
For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by the related peripheral (see Table 5-3).
Table 5-3. Interrupt Source Control and Data Registers
Interrupt Source
Timer 0 overflow
Timer 0 match/capture
Interrupt Level
Register(s)
Location(s) in Set 1
IRQ0
T0CON
T0CNT
T0DATA
INTPND
E2H, bank 0
E0H, bank 0
E1H, bank 0
E6H, bank 0
Timer 1 match
IRQ1
IRQ2
T1CON
T1CNT
T1DATA
E5H, bank 0
E3H, bank 0
E4H, bank0
Timer 2 match
T2CON
T2CNTH, T2CNTL
T2DATAH, T2DATAL
FEH, bank 1
FAH, FBH, bank 1
FCH, FDH, bank 1
SIO0 interrupt
SIO1 interrupt
SIO0CON
SIO0DATA
SIO0PS
SIO1CON
SIO1DATA
SIO1PS
E9H, bank 0
EAH, bank 0
EBH, bank 0
ECH, bank 0
EDH, bank 0
EEH, bank 0
Watch timer
IRQ3
IRQ4
WTCON
E8H, bank 0
P1.3 external interrupt
P1.2 external interrupt
P1.1 external interrupt
P1.0 external interrupt
P1CONL
P1INT
P1PND
E5H, bank 1
E6H, bank 1
E7H, bank 1
P1.7 external interrupt
P1.6 external interrupt
P1.5 external interrupt
P1.4 external interrupt
IRQ5
P1CONH
P1INT
P1PND
E4H, bank 1
E6H, bank 1
E7H, bank 1
CE interrupt
IRQ6
IRQ7
PLLMOD
PLLREF
PLLD1, PLLD0
F8H, bank 0
F9H, bank 0
F6H, F7H, bank 0
IF interrupt
IFMOD
F3H, bank 0
IFCNT1, IFCNT0
PLLMOD
F4H, F5H, bank 0
F8H, bank 0
PLLREF
F9H, bank 0
5-8
S3C830A/P830A
INTERRUPT STRUCTURE
SYSTEM MODE REGISTER (SYM)
The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to
control fast interrupt processing (see Figure 5-5).
A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2, is
undetermined.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be
included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly
to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions
for this purpose.
System Mode Register (SYM)
DEH, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Global interrupt enable bit:
0 = Disable all interrupts processing
1 = Enable all interrupts processing
Always logic "0"
Not used for the Fast interrupt level
S3C830A selection bits:
Fast interrupt enable bit:
0 = Disable fast interrupts processing
1 = Enable fast interrupts processing
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Figure 5-5. System Mode Register (SYM)
5-9
INTERRUPT STRUCTURE
S3C830A/P830A
INTERRUPT MASK REGISTER (IMR)
The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual
interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required
settings by the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit
of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a
level's IMR bit to "1", interrupt processing for the level is enabled (not masked).
The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions
using the Register addressing mode.
Interrupt Mask Register (IMR)
DDH, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt level enable bits
0 = Disable (mask) interrupt level
1 = Enable (un-mask) interrupt level
NOTE:
Before IMR register is changed to any value, all interrupts must be disable.
Using DI instruction is recommended.
Figure 5-6. Interrupt Mask Register (IMR)
5-10
S3C830A/P830A
INTERRUPT STRUCTURE
INTERRUPT PRIORITY REGISTER (IPR)
The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels
in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore
be written to their required settings by the initialization routine.
When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two
sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This
priority is fixed in hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by
the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register
priority definitions (see Figure 5-7):
Group A
Group B
Group C
IRQ0, IRQ1
IRQ2, IRQ3, IRQ3
IRQ5, IRQ6, IRQ7
IPR
IPR
IPR
Group A
Group B
Group C
A1
A2
B1
B2
C1
C2
B21
B22
C21
C22
IRQ0
IRQ1
IRQ2 IRQ3
IRQ4
IRQ5 IRQ6
IRQ7
Figure 5-7. Interrupt Request Priority Groups
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.
For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B"
would select the relationship C > B > A.
The functions of the other IPR bit settings are as follows:
— IPR.5 controls the relative priorities of group C interrupts.
— Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5,
6, and 7. IPR.6 defines the subgroup C relationship. IPR.5 controls the interrupt group C.
— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.
5-11
INTERRUPT STRUCTURE
S3C830A/P830A
Interrupt Priority Register (IPR)
FFH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Group priority:
D7 D4 D1
Group A
0 = IRQ0 > IRQ1
1 = IRQ1 > IRQ0
Group B
0 = IRQ2 > (IRQ3, IRQ4)
1 = (IRQ3, IRQ4) > IRQ2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 = Undefined
1 = B > C > A
0 = A > B > C
1 = B > A > C
0 = C > A > B
1 = C > B > A
0 = A > C > B
1 = Undefined
Subgroup B
0 = IRQ3 > IRQ4
1 = IRQ4 > IRQ3
Group C
0 = IRQ5 > (IRQ6, IRQ7)
1 = (IRQ6, IRQ7) > IRQ5
Subgroup C
0 = IRQ6 > IRQ7
1 = IRQ7 > IRQ6
Figure 5-8. Interrupt Priority Register (IPR)
5-12
S3C830A/P830A
INTERRUPT STRUCTURE
INTERRUPT REQUEST REGISTER (IRQ)
You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for
all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same
number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued
for that level. A "1" indicates that an interrupt request has been generated for that level.
IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of
the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of
specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”.
You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing
is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,
however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events
occurred while the interrupt structure was globally disabled.
Interrupt Request Register (IRQ)
DCH, Set 1, Read-only
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt level request pending bits:
0 = Interrupt level is not pending
1 = Interrupt level is pending
Figure 5-9. Interrupt Request Register (IRQ)
5-13
INTERRUPT STRUCTURE
S3C830A/P830A
INTERRUPT PENDING FUNCTION TYPES
Overview
There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the
interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service
routine.
Pending Bits Cleared Automatically by Hardware
For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding
pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is
waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service
routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or
written by application software.
In the S3C830A interrupt structure, the timer 0 overflow interrupt (IRQ0) belongs to this category of interrupts in
which pending condition is cleared automatically by hardware.
Pending Bits Cleared by the Service Routine
The second type of pending bit is the one that should be cleared by program software. The service routine must
clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must
be written to the corresponding pending bit location in the source’s mode or control register.
5-14
S3C830A/P830A
INTERRUPT STRUCTURE
INTERRUPT SOURCE POLLING SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request bit to "1".
2. The CPU polling procedure identifies a pending condition for that source.
3. The CPU checks the source's interrupt level.
4. The CPU generates an interrupt acknowledge signal.
5. Interrupt logic determines the interrupt's vector address.
6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).
7. The CPU continues polling for interrupt requests.
INTERRUPT SERVICE ROUTINES
Before an interrupt request is serviced, the following conditions must be met:
— Interrupt processing must be globally enabled (EI, SYM.0 = "1")
— The interrupt level must be enabled (IMR register)
— The interrupt level must have the highest priority if more than one levels are currently requesting service
— The interrupt must be enabled at the interrupt's source (peripheral control register)
When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.
The CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.
2. Save the program counter (PC) and status flags to the system stack.
3. Branch to the interrupt vector to fetch the address of the service routine.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores
the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.
5-15
INTERRUPT STRUCTURE
S3C830A/P830A
GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that
correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:
1. Push the program counter's low-byte value to the stack.
2. Push the program counter's high-byte value to the stack.
3. Push the FLAG register values to the stack.
4. Fetch the service routine's high-byte address from the vector location.
5. Fetch the service routine's low-byte address from the vector location.
6. Branch to the service routine specified by the concatenated 16-bit vector address.
NOTE
A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH.
NESTING OF VECTORED INTERRUPTS
It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,
you must follow these steps:
1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).
2. Load the IMR register with a new mask value that enables only the higher priority interrupt.
3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it
occurs).
4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the
previous mask value from the stack (POP IMR).
5. Execute an IRET.
Depending on the application, you may be able to simplify the procedure above to some extent.
INSTRUCTION POINTER (IP)
The instruction pointer (IP) is adopted by all the S3C8-series microcontrollers to control the optional high-speed
interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP
registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).
FAST INTERRUPT PROCESSING
The feature called fast interrupt processing allows an interrupt within a given level to be completed in
approximately 6 clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast
interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt
processing for the selected level, you set SYM.1 to “1”.
5-16
S3C830A/P830A
INTERRUPT STRUCTURE
FAST INTERRUPT PROCESSING (Continued)
Two other system registers support fast interrupt processing:
— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the
program counter values), and
— When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated
register called FLAGS' ("FLAGS prime").
NOTE
For the S3C830A microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–
IRQ7, can be selected for fast interrupt processing.
Procedure for Initiating Fast Interrupts
To initiate fast interrupt processing, follow these steps:
1. Load the start address of the service routine into the instruction pointer (IP).
2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)
3. Write a "1" to the fast interrupt enable bit in the SYM register.
Fast Interrupt Service Routine
When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:
1. The contents of the instruction pointer and the PC are swapped.
2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.
3. The fast interrupt status bit in the FLAGS register is set.
4. The interrupt is serviced.
5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction
pointer and PC values are swapped back.
6. The content of FLAGS' ("FLAGS prime") is copied automatically back to the FLAGS register.
7. The fast interrupt status bit in FLAGS is cleared automatically.
Relationship to Interrupt Pending Bit Types
As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by
hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the
application program's interrupt service routine. You can select fast interrupt processing for interrupts with either
type of pending condition clear function — by hardware or by software.
Programming Guidelines
Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the
SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,
including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast
interrupt service routine ends.
5-17
INTERRUPT STRUCTURE
S3C830A/P830A
NOTES
5-18
S3C830A/P830A
INSTRUCTION SET
6
INSTRUCTION SET
OVERVIEW
The SAM88RC instruction set is specifically designed to support the large register files that are typical of most
SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of
the instruction set include:
— A full complement of 8-bit arithmetic and logic operations, including multiply and divide
— No special I/O instructions (I/O control/data registers are mapped directly into the register file)
— Decimal adjustment included in binary-coded decimal (BCD) operations
— 16-bit (word) data can be incremented and decremented
— Flexible instructions for bit addressing, rotate, and shift operations
DATA TYPES
The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can
be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least
significant (right-most) bit.
REGISTER ADDRESSING
To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is
specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory
addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."
ADDRESSING MODES
There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA),
Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please
refer to Section 3, "Addressing Modes."
6-1
INSTRUCTION SET
S3C830A/P830A
Table 6-1. Instruction Group Summary
Operands Instruction
Mnemonic
Load Instructions
CLR
dst
Clear
LD
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst,src
dst
Load
LDB
Load bit
LDE
Load external data memory
Load program memory
LDC
LDED
LDCD
LDEI
Load external data memory and decrement
Load program memory and decrement
Load external data memory and increment
Load program memory and increment
Load external data memory with pre-decrement
Load program memory with pre-decrement
Load external data memory with pre-increment
Load program memory with pre-increment
Load word
LDCI
LDEPD
LDCPD
LDEPI
LDCPI
LDW
POP
Pop from stack
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
dst,src
dst,src
src
Pop user stack (decrementing)
Pop user stack (incrementing)
Push to stack
dst,src
dst,src
Push user stack (decrementing)
Push user stack (incrementing)
6-2
S3C830A/P830A
INSTRUCTION SET
Table 6-1. Instruction Group Summary (Continued)
Operands Instruction
Mnemonic
Arithmetic Instructions
ADC
ADD
CP
dst,src
dst,src
Add with carry
Add
dst,src
dst
Compare
DA
Decimal adjust
Decrement
Decrement word
Divide
DEC
DECW
DIV
dst
dst
dst,src
dst
INC
Increment
INCW
MULT
SBC
SUB
dst
Increment word
Multiply
dst,src
dst,src
dst,src
Subtract with carry
Subtract
Logic Instructions
AND
COM
OR
dst,src
dst
Logical AND
Complement
dst,src
dst,src
Logical OR
XOR
Logical exclusive OR
6-3
INSTRUCTION SET
Mnemonic
S3C830A/P830A
Table 6-1. Instruction Group Summary (Continued)
Operands Instruction
Program Control Instructions
BTJRF
BTJRT
CALL
CPIJE
CPIJNE
DJNZ
ENTER
EXIT
IRET
JP
dst,src
dst,src
dst
Bit test and jump relative on false
Bit test and jump relative on true
Call procedure
dst,src
dst,src
r,dst
Compare, increment and jump on equal
Compare, increment and jump on non-equal
Decrement register and jump on non-zero
Enter
Exit
Interrupt return
cc,dst
dst
Jump on condition code
Jump unconditional
JP
JR
cc,dst
Jump relative on condition code
Next
NEXT
RET
Return
WFI
Wait for interrupt
Bit Manipulation Instructions
BAND
BCP
BITC
BITR
BITS
BOR
BXOR
TCM
TM
dst,src
dst,src
dst
Bit AND
Bit compare
Bit complement
Bit reset
dst
dst
Bit set
dst,src
dst,src
dst,src
dst,src
Bit OR
Bit XOR
Test complement under mask
Test under mask
6-4
S3C830A/P830A
Mnemonic
INSTRUCTION SET
Table 6-1. Instruction Group Summary (Concluded)
Operands Instruction
Rotate and Shift Instructions
RL
dst
dst
dst
dst
dst
dst
Rotate left
RLC
RR
Rotate left through carry
Rotate right
RRC
SRA
SWAP
Rotate right through carry
Shift right arithmetic
Swap nibbles
CPU Control Instructions
CCF
DI
Complement carry flag
Disable interrupts
Enable interrupts
Enter Idle mode
No operation
EI
IDLE
NOP
RCF
SB0
SB1
SCF
Reset carry flag
Set bank 0
Set bank 1
Set carry flag
SRP
src
src
src
Set register pointers
Set register pointer 0
Set register pointer 1
Enter Stop mode
SRP0
SRP1
STOP
6-5
INSTRUCTION SET
S3C830A/P830A
FLAGS REGISTER (FLAGS)
The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these
bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and
FLAGS.2 are used for BCD arithmetic.
The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank
address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register
can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.
Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For
example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND
instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will
occur to the Flags register producing an unpredictable result.
System Flags Register (FLAGS)
D5H, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Bank address
status flag (BA)
Carry flag (C)
Fast interrupt
status flag (FS)
Zero flag (Z)
Sign flag (S)
Half-carry flag (H)
Decimal adjust flag (D)
Overflow flag (V)
Figure 6-1. System Flags Register (FLAGS)
6-6
S3C830A/P830A
INSTRUCTION SET
FLAG DESCRIPTIONS
C
Carry Flag (FLAGS.7)
The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to
the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the
specified register. Program instructions can set, clear, or complement the carry flag.
Z
Zero Flag (FLAGS.6)
For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For
operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is
logic zero.
S
V
D
Sign Flag (FLAGS.5)
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the
result. A logic zero indicates a positive number and a logic one indicates a negative number.
Overflow Flag (FLAGS.4)
The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than
– 128. It is also cleared to "0" following logic operations.
Decimal Adjust Flag (FLAGS.3)
The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a
subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by
programmers, and cannot be used as a test condition.
H
Half-Carry Flag (FLAGS.2)
The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows
out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous
addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a
program.
FIS Fast Interrupt Status Flag (FLAGS.1)
The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.
When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET
instruction is executed.
BA Bank Address Flag (FLAGS.0)
The BA flag indicates which register bank in the set 1 area of the internal register file is currently
selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0
instruction and is set to "1" (select bank 1) when you execute the SB1 instruction.
6-7
INSTRUCTION SET
S3C830A/P830A
INSTRUCTION SET NOTATION
Table 6-2. Flag Notation Conventions
Flag
C
Z
Description
Carry flag
Zero flag
S
V
D
H
0
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Cleared to logic zero
Set to logic one
1
*
Set or cleared according to operation
Value is unaffected
Value is undefined
–
x
Table 6-3. Instruction Set Symbols
Symbol
dst
src
@
Description
Destination operand
Source operand
Indirect register address prefix
Program counter
PC
IP
Instruction pointer
FLAGS
RP
#
Flags register (D5H)
Register pointer
Immediate operand or register address prefix
Hexadecimal number suffix
Decimal number suffix
Binary number suffix
Opcode
H
D
B
opc
6-8
S3C830A/P830A
Notation
INSTRUCTION SET
Table 6-4. Instruction Notation Conventions
Description Actual Operand Range
cc
r
Condition code
Working register only
See list of condition codes in Table 6-6.
Rn (n = 0–15)
rb
r0
rr
Bit (b) of working register
Rn.b (n = 0–15, b = 0–7)
Rn (n = 0–15)
Bit 0 (LSB) of working register
Working register pair
RRp (p = 0, 2, 4, ..., 14)
reg or Rn (reg = 0–255, n = 0–15)
reg.b (reg = 0–255, b = 0–7)
R
Register or working register
Bit 'b' of register or working register
Register pair or working register pair
Rb
RR
reg or RRp (reg = 0–254, even number only, where
p = 0, 2, ..., 14)
IA
Ir
Indirect addressing mode
addr (addr = 0–254, even number only)
@Rn (n = 0–15)
Indirect working register only
IR
Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)
Irr
Indirect working register pair only
@RRp (p = 0, 2, ..., 14)
IRR
Indirect register pair or indirect working
register pair
@RRp or @reg (reg = 0–254, even only, where
p = 0, 2, ..., 14)
X
Indexed addressing mode
#reg [Rn] (reg = 0–255, n = 0–15)
XS
Indexed (short offset) addressing mode
#addr [RRp] (addr = range –128 to +127, where
p = 0, 2, ..., 14)
xl
Indexed (long offset) addressing mode
#addr [RRp] (addr = range 0–65535, where
p = 0, 2, ..., 14)
da
ra
Direct addressing mode
Relative addressing mode
addr (addr = range 0–65535)
addr (addr = number in the range +127 to –128 that is
an offset relative to the address of the next instruction)
im
Immediate addressing mode
#data (data = 0–255)
iml
Immediate (long) addressing mode
#data (data = range 0–65535)
6-9
INSTRUCTION SET
S3C830A/P830A
Table 6-5. Opcode Quick Reference
OPCODE MAP
LOWER NIBBLE (HEX)
–
0
1
2
3
4
5
6
7
DEC
R1
DEC
IR1
ADD
r1,r2
ADD
r1,Ir2
ADD
R2,R1
ADD
IR2,R1
ADD
R1,IM
BOR
r0–Rb
U
P
P
E
R
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC
R1
RLC
IR1
ADC
r1,r2
ADC
r1,Ir2
ADC
R2,R1
ADC
IR2,R1
ADC
R1,IM
BCP
r1.b, R2
INC
R1
INC
IR1
SUB
r1,r2
SUB
r1,Ir2
SUB
R2,R1
SUB
IR2,R1
SUB
R1,IM
BXOR
r0–Rb
JP
IRR1
SRP/0/1
IM
SBC
r1,r2
SBC
r1,Ir2
SBC
R2,R1
SBC
IR2,R1
SBC
R1,IM
BTJR
r2.b, RA
DA
R1
DA
IR1
OR
r1,r2
OR
r1,Ir2
OR
R2,R1
OR
IR2,R1
OR
R1,IM
LDB
r0–Rb
POP
R1
POP
IR1
AND
r1,r2
AND
r1,Ir2
AND
R2,R1
AND
IR2,R1
AND
R1,IM
BITC
r1.b
COM
R1
COM
IR1
TCM
r1,r2
TCM
r1,Ir2
TCM
R2,R1
TCM
IR2,R1
TCM
R1,IM
BAND
r0–Rb
N
I
PUSH
R2
PUSH
IR2
TM
r1,r2
TM
r1,Ir2
TM
R2,R1
TM
IR2,R1
TM
R1,IM
BIT
r1.b
DECW
RR1
DECW
IR1
PUSHUD PUSHUI
IR1,R2
MULT
R2,RR1
MULT
IR2,RR1
MULT
IM,RR1
LD
r1, x, r2
B
B
L
E
IR1,R2
RL
R1
RL
IR1
POPUD
IR2,R1
POPUI
IR2,R1
DIV
R2,RR1
DIV
IR2,RR1
DIV
IM,RR1
LD
r2, x, r1
INCW
RR1
INCW
IR1
CP
r1,r2
CP
r1,Ir2
CP
R2,R1
CP
IR2,R1
CP
R1,IM
LDC
r1, Irr2, xL
CLR
R1
CLR
IR1
XOR
r1,r2
XOR
r1,Ir2
XOR
R2,R1
XOR
IR2,R1
XOR
R1,IM
LDC
r2, Irr2, xL
RRC
R1
RRC
IR1
CPIJE
Ir,r2,RA
LDC
r1,Irr2
LDW
LDW
LDW
LD
r1, Ir2
RR2,RR1 IR2,RR1 RR1,IML
SRA
R1
SRA
IR1
CPIJNE
Irr,r2,RA
LDC
r2,Irr1
CALL
IA1
LD
IR1,IM
LD
Ir1, r2
H
E
X
RR
R1
RR
IR1
LDCD
r1,Irr2
LDCI
r1,Irr2
LD
R2,R1
LD
R2,IR1
LD
R1,IM
LDC
r1, Irr2, xs
SWAP
R1
SWAP
IR1
LDCPD
r2,Irr1
LDCPI
r2,Irr1
CALL
IRR1
LD
IR2,R1
CALL
DA1
LDC
r2, Irr1, xs
6-10
S3C830A/P830A
INSTRUCTION SET
Table 6-5. Opcode Quick Reference (Continued)
OPCODE MAP
LOWER NIBBLE (HEX)
–
8
9
A
B
C
D
E
F
U
P
P
E
R
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
LD
r1,R2
LD
r2,R1
DJNZ
r1,RA
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
NEXT
ENTER
EXIT
WFI
SB0
SB1
IDLE
STOP
DI
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
¯
N
I
B
B
L
E
EI
RET
IRET
RCF
SCF
CCF
NOP
H
E
X
LD
r1,R2
LD
r2,R1
DJNZ
r1,RA
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
6-11
INSTRUCTION SET
S3C830A/P830A
CONDITION CODES
The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"
after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.
Table 6-6. Condition Codes
Binary
Mnemonic
Description
Always false
Flags Set
0000
1000
F
–
T
Always true
–
0111 (note)
1111 (note)
0110 (note)
1110 (note)
1101
C
Carry
C = 1
C = 0
Z = 1
Z = 0
S = 0
S = 1
V = 1
V = 0
Z = 1
Z = 0
NC
Z
No carry
Zero
NZ
PL
MI
OV
Not zero
Plus
0101
Minus
0100
Overflow
1100
NOV
EQ
No overflow
Equal
0110 (note)
1110 (note)
1001
NE
Not equal
GE
Greater than or equal
Less than
(S XOR V) = 0
(S XOR V) = 1
(Z OR (S XOR V)) = 0
(Z OR (S XOR V)) = 1
C = 0
0001
LT
1010
GT
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
0010
LE
1111 (note)
0111 (note)
1011
UGE
ULT
UGT
ULE
C = 1
(C = 0 AND Z = 0) = 1
(C OR Z) = 1
0011
NOTES:
1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For
example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;
after a CP instruction, however, EQ would probably be used.
2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
6-12
S3C830A/P830A
INSTRUCTION SET
INSTRUCTION DESCRIPTIONS
This section contains detailed information and programming examples for each instruction in the SAM8
instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.
The following information is included in each instruction description:
— Instruction name (mnemonic)
— Full instruction name
— Source/destination format of the instruction operand
— Shorthand notation of the instruction's operation
— Textual description of the instruction's effect
— Specific flag settings affected by the instruction
— Detailed description of the instruction's format, execution time, and addressing mode(s)
— Programming example(s) explaining how to use the instruction
6-13
INSTRUCTION SET
S3C830A/P830A
ADC — Add with carry
ADC
dst,src
Operation:
dst ¬ dst + src + c
The source operand, along with the setting of the carry flag, is added to the destination operand
and the sum is stored in the destination. The contents of the source are unaffected. Two's-
complement addition is performed. In multiple precision arithmetic, this instruction permits the
carry from the addition of low-order operands to be carried into the addition of high-order
operands.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result
is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if there is a carry from the most significant bit of the low-order four bits of the result;
cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
12
13
r
r
r
lr
dst
src
3
3
6
6
14
15
R
R
R
IR
dst
6
16
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and
register 03H = 0AH:
ADC R1,R2
®
®
®
®
®
R1 = 14H, R2 = 03H
ADC R1,@R2
ADC 01H,02H
ADC 01H,@02H
ADC 01H,#11H
R1 = 1BH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1",
and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds
03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
6-14
S3C830A/P830A
INSTRUCTION SET
ADD — Add
ADD
dst,src
Operation:
dst ¬ dst + src
The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if a carry from the low-order nibble occurred.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
02
03
r
r
r
lr
dst
src
3
3
6
6
04
05
R
R
R
IR
dst
6
06
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD R1,R2
®
®
®
®
®
R1 = 15H, R2 = 03H
ADD R1,@R2
ADD 01H,02H
ADD 01H,@02H
ADD 01H,#25H
R1 = 1CH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working
register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H
in register R1.
6-15
INSTRUCTION SET
S3C830A/P830A
AND — Logical AND
AND
dst,src
Operation:
dst ¬ dst AND src
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits
in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the
source are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
52
53
r
r
r
lr
dst
src
3
3
6
6
54
55
R
R
R
IR
dst
6
56
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND R1,R2
®
®
®
®
®
R1 = 02H, R2 = 03H
AND R1,@R2
AND 01H,02H
AND 01H,@02H
AND 01H,#25H
R1 = 02H, R2 = 03H
Register 01H = 01H, register 02H = 03H
Register 01H = 00H, register 02H = 03H
Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source
working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source
operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
6-16
S3C830A/P830A
INSTRUCTION SET
BAND — Bit AND
BAND
dst,src.b
BAND
dst.b,src
Operation:
dst(0) ¬ dst(0) AND src(b)
or
dst(b) ¬ dst(b) AND src(0)
The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of
the destination (or source). The resultant bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
dst | b | 0
src | b | 1
src
dst
3
6
67
r0
Rb
3
6
67
Rb
r0
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four
bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H and register 01H = 05H:
BAND R1,01H.1
BAND 01H.1,R1
®
®
R1 = 06H, register 01H = 05H
Register 01H = 05H, R1 = 07H
In the first example, source register 01H contains the value 05H (00000101B) and destination
working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1
value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the
value 06H (00000110B) in register R1.
6-17
INSTRUCTION SET
S3C830A/P830A
BCP — Bit Compare
BCP
dst,src.b
Operation:
dst(0) – src(b)
The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.
The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both
operands are unaffected by the comparison.
Flags:
C: Unaffected.
Z: Set if the two bits are the same; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | b | 0
src
3
6
17
r0
Rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H and register 01H = 01H:
BCP
R1,01H.1
®
R1 = 07H, register 01H = 01H
If destination working register R1 contains the value 07H (00000111B) and the source register
01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of
the source register (01H) and bit zero of the destination register (R1). Because the bit values are
not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).
6-18
S3C830A/P830A
INSTRUCTION SET
BITC — Bit Complement
BITC
dst.b
Operation:
dst(b) ¬ NOT dst(b)
This instruction complements the specified bit within the destination without affecting any other
bits in the destination.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst | b | 0
2
4
57
rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H
BITC R1.1
®
R1 = 05H
If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"
complements bit one of the destination and leaves the value 05H (00000101B) in register R1.
Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H)
is cleared.
6-19
INSTRUCTION SET
S3C830A/P830A
BITR— Bit Reset
BITR
dst.b
Operation:
dst(b) ¬ 0
The BITR instruction clears the specified bit within the destination without affecting any other bits
in the destination.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst | b | 0
2
4
77
rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BITR R1.1
®
R1 = 05H
If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one
of the destination register R1, leaving the value 05H (00000101B).
6-20
S3C830A/P830A
INSTRUCTION SET
BITS— Bit Set
BITS
dst.b
Operation:
dst(b) ¬ 1
The BITS instruction sets the specified bit within the destination without affecting any other bits
in the destination.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst | b | 1
2
4
77
rb
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BITS R1.3
®
R1 = 0FH
If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit
three of the destination register R1 to "1", leaving the value 0FH (00001111B).
6-21
INSTRUCTION SET
S3C830A/P830A
BOR— Bit OR
BOR
BOR
dst,src.b
dst.b,src
Operation:
dst(0) ¬ dst(0) OR src(b)
or
dst(b) ¬ dst(b) OR src(0)
The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the
destination (or the source). The resulting bit value is stored in the specified bit of the destination.
No other bits of the destination are affected. The source is unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
dst | b | 0
src | b | 1
src
dst
3
6
07
r0
Rb
3
6
07
Rb
r0
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four
bits, the bit address 'b' is three bits, and the LSB address value is one bit.
Examples:
Given: R1 = 07H and register 01H = 03H:
BOR R1, 01H.1
BOR 01H.2, R1
®
®
R1 = 07H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 contains the value 07H (00000111B) and
source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs
bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value
(07H) in working register R1.
In the second example, destination register 01H contains the value 03H (00000011B) and the
source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically
ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H
in register 01H.
6-22
S3C830A/P830A
INSTRUCTION SET
BTJRF — Bit Test, Jump Relative on False
BTJRF
dst,src.b
Operation:
If src(b) is a "0", then PC ¬ PC + dst
The specified bit within the source operand is tested. If it is a "0", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRF instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
(Note 1)
dst
src
opc
src | b | 0
dst
3
10
37
RA
rb
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BTJRF SKIP,R1.3
®
PC jumps to SKIP location
If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3"
tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the
memory location pointed to by the SKIP. (Remember that the memory location must be within
the allowed range of + 127 to – 128.)
6-23
INSTRUCTION SET
S3C830A/P830A
BTJRT— Bit Test, Jump Relative on True
BTJRT
dst,src.b
Operation:
If src(b) is a "1", then PC ¬ PC + dst
The specified bit within the source operand is tested. If it is a "1", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRT instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
(Note 1)
dst
src
opc
src | b | 1
dst
3
10
37
RA
rb
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BTJRT
SKIP,R1.1
If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1"
tests bit one in the source register (R1). Because it is a "1", the relative address is added to the
PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the
memory location must be within the allowed range of + 127 to – 128.)
6-24
S3C830A/P830A
INSTRUCTION SET
BXOR— Bit XOR
BXOR
BXOR
dst,src.b
dst.b,src
Operation:
dst(0) ¬ dst(0) XOR src(b)
or
dst(b) ¬ dst(b) XOR src(0)
The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB)
of the destination (or source). The result bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
dst | b | 0
src | b | 1
src
dst
3
6
27
r0
Rb
3
6
27
Rb
r0
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four
bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):
BXOR R1,01H.1
BXOR 01H.2,R1
®
®
R1 = 06H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 has the value 07H (00000111B) and source
register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs
bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in
bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is
unaffected.
6-25
INSTRUCTION SET
S3C830A/P830A
CALL— Call Procedure
CALL
dst
Operation:
SP
@SP
SP
@SP
PC
¬
¬
¬
¬
¬
SP – 1
PCL
SP –1
PCH
dst
The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The
specified destination address is then loaded into the program counter and points to the first
instruction of a procedure. At the end of the procedure the return instruction (RET) can be used
to return to the original program flow. RET pops the top of the stack back into the program
counter.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
opc
opc
dst
3
14
F6
F4
D4
DA
IRR
IA
dst
dst
2
2
12
14
Examples:
Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:
CALL 3521H ®
SP = 0000H
(Memory locations 0000H = 1AH, 0001H = 4AH, where
4AH is the address that follows the instruction.)
SP = 0000H (0000H = 1AH, 0001H = 49H)
SP = 0000H (0000H = 1AH, 0001H = 49H)
CALL @RR0 ®
CALL #40H
®
In the first example, if the program counter value is 1A47H and the stack pointer contains the
value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the
stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the
value 3521H, the address of the first instruction in the program sequence to be executed.
If the contents of the program counter and stack pointer are the same as in the first example, the
statement "CALL @RR0" produces the same result except that the 49H is stored in stack
location 0001H (because the two-byte instruction format was used). The PC is then loaded with
the value 3521H, the address of the first instruction in the program sequence to be executed.
Assuming that the contents of the program counter and stack pointer are the same as in the first
example, if program address 0040H contains 35H and program address 0041H contains 21H, the
statement "CALL #40H" produces the same result as in the second example.
6-26
S3C830A/P830A
INSTRUCTION SET
CCF— Complement Carry Flag
CCF
Operation:
C ¬ NOT C
The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic
zero; if C = "0", the value of the carry flag is changed to logic one.
Flags:
C: Complemented.
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
EF
Example:
Given: The carry flag = "0":
CCF
If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H),
changing its value from logic zero to logic one.
6-27
INSTRUCTION SET
S3C830A/P830A
CLR— Clear
CLR
dst
Operation:
dst ¬ "0"
The destination location is cleared to "0".
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
B0
B1
R
IR
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR
CLR
00H
®
Register 00H = 00H
@01H ®
Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H
value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)
addressing mode to clear the 02H register value to 00H.
6-28
S3C830A/P830A
INSTRUCTION SET
COM— Complement
COM
dst
Operation:
dst ¬ NOT dst
The contents of the destination location are complemented (one's complement); all "1s" are
changed to "0s", and vice-versa.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
60
61
R
IR
Examples:
Given: R1 = 07H and register 07H = 0F1H:
COM R1
®
®
R1 = 0F8H
R1 = 07H, register 07H = 0EH
COM @R1
In the first example, destination working register R1 contains the value 07H (00000111B). The
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros,
and vice-versa, leaving the value 0F8H (11111000B).
In the second example, Indirect Register (IR) addressing mode is used to complement the value
of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
6-29
INSTRUCTION SET
S3C830A/P830A
CP— Compare
CP
dst,src
Operation:
dst – src
The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags are set accordingly. The contents of both operands are unaffected by the
comparison.
Flags:
C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst |
src
2
4
6
A2
r
r
A3
r
lr
opc
opc
src
dst
dst
src
3
3
6
6
A4
A5
R
R
R
IR
6
A6
R
IM
Examples:
1. Given: R1 = 02H and R2 = 03H:
CP R1,R2 ® Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the
value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1
value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S
are "1".
2. Given: R1 = 05H and R2 = 0AH:
CP
JP
INC
R1,R2
UGE,SKIP
R1
SKIP LD
R3,R1
In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"
and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"
executes, the value 06H remains in working register R3.
6-30
S3C830A/P830A
INSTRUCTION SET
CPIJE— Compare, Increment, and Jump on Equal
CPIJE
dst,src,RA
Operation:
If dst – src = "0", PC ¬ PC + RA
Ir ¬ Ir + 1
The source operand is compared to (subtracted from) the destination operand. If the result is "0",
the relative address is added to the program counter and control passes to the statement whose
address is now in the program counter. Otherwise, the instruction immediately following the
CPIJE instruction is executed. In either case, the source pointer is incremented by one before
the next instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src dst
RA
3
12
C2
r
Ir
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 02H:
CPIJE R1,@R2,SKIP ®
R2 = 04H, PC jumps to SKIP location
In this example, working register R1 contains the value 02H, working register R2 the value 03H,
and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value
02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the
relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that
the memory location must be within the allowed range of + 127 to – 128.)
6-31
INSTRUCTION SET
S3C830A/P830A
CPIJNE— Compare, Increment, and Jump on Non-Equal
CPIJNE
dst,src,RA
Operation:
If dst – src "0", PC ¬ PC + RA
Ir ¬ Ir + 1
The source operand is compared to (subtracted from) the destination operand. If the result is not
"0", the relative address is added to the program counter and control passes to the statement
whose address is now in the program counter; otherwise the instruction following the CPIJNE
instruction is executed. In either case the source pointer is incremented by one before the next
instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src dst
RA
3
12
D2
r
Ir
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 04H:
CPIJNE
R1,@R2,SKIP ®
R2 = 04H, PC jumps to SKIP location
Working register R1 contains the value 02H, working register R2 (the source pointer) the value
03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts
04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal,
the relative address is added to the PC and the PC then jumps to the memory location pointed to
by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.
(Remember that the memory location must be within the allowed range of + 127 to – 128.)
6-32
S3C830A/P830A
INSTRUCTION SET
DA— Decimal Adjust
DA
dst
Operation:
dst ¬ DA dst
The destination operand is adjusted to form two 4-bit BCD digits following an addition or
subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table
indicates the operation performed. (The operation is undefined if the destination operand was not
the result of a valid addition or subtraction of BCD digits):
Instruction
Carry
Before DA
Bits 4–7
Value (Hex)
H Flag
Before DA
Bits 0–3
Value (Hex)
Number Added
to Byte
Carry
After DA
0
0
0
0
0
0
1
1
1
0
0
1
1
0–9
0–8
0–9
A–F
9–F
A–F
0–2
0–2
0–3
0–9
0–8
7–F
6–F
0
0
1
0
0
1
0
0
1
0
1
0
1
0–9
A–F
0–3
0–9
A–F
0–3
0–9
A–F
0–3
0–9
6–F
0–9
6–F
00
0
0
0
1
1
1
1
1
1
0
0
1
1
06
06
ADD
ADC
60
66
66
60
66
66
00 = – 00
FA = – 06
A0 = – 60
9A = – 66
SUB
SBC
Flags:
C: Set if there was a carry from the most significant bit; cleared otherwise (see table).
Z: Set if result is "0"; cleared otherwise.
S: Set if result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
40
41
R
IR
6-33
INSTRUCTION SET
S3C830A/P830A
DA— Decimal Adjust
DA
(Continued)
Example:
Given: Working register R0 contains the value 15 (BCD), working register R1 contains
27 (BCD), and address 27H contains 46 (BCD):
ADD
DA
R1,R0
R1
;
;
C ¬ "0", H ¬ "0", Bits 4–7 = 3, bits 0–3 = C, R1 ¬ 3CH
R1 ¬ 3CH + 06
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is
incorrect, however, when the binary representations are added in the destination location using
standard binary arithmetic:
0 0 0 1 0 1 0 1
+ 0 0 1 0 0 1 1 1
15
27
0 0 1 1 1 1 0 0
=
3CH
The DA instruction adjusts this result so that the correct BCD representation is obtained:
0 0 1 1 1 1 0 0
+ 0 0 0 0 0 1 1 0
0 1 0 0 0 0 1 0
=
42
Assuming the same values given above, the statements
SUB
DA
27H,R0 ;
@R1
C ¬ "0", H ¬ "0", Bits 4–7 = 3, bits 0–3 = 1
@R1 ¬ 31–0
;
leave the value 31 (BCD) in address 27H (@R1).
6-34
S3C830A/P830A
INSTRUCTION SET
DEC— Decrement
DEC
dst
Operation:
dst ¬ dst – 1
The contents of the destination operand are decremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
00
01
R
IR
Examples:
Given: R1 = 03H and register 03H = 10H:
DEC R1
®
®
R1 = 02H
DEC @R1
Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1"
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the
statement "DEC @R1" decrements the value 10H contained in the destination register 03H by
one, leaving the value 0FH.
6-35
INSTRUCTION SET
S3C830A/P830A
DECW— Decrement Word
DECW
dst
Operation:
dst ¬ dst – 1
The contents of the destination location (which must be an even address) and the operand
following that location are treated as a single 16-bit value that is decremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
80
81
RR
IR
Examples:
Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:
DECW RR0
DECW @R2
®
®
R0 = 12H, R1 = 33H
Register 30H = 0FH, register 31H = 20H
In the first example, destination register R0 contains the value 12H and register R1 the value
34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word
and decrements the value of R1 by one, leaving the value 33H.
NOTE:
A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW
instruction. To avoid this problem, we recommend that you use DECW as shown in the following
example:
LOOP: DECW RR0
LD
OR
JR
R2,R1
R2,R0
NZ,LOOP
6-36
S3C830A/P830A
INSTRUCTION SET
DI— Disable Interrupts
DI
Operation:
SYM (0) ¬ 0
Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all
interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,
but the CPU will not service them while interrupt processing is disabled.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
8F
Example:
Given: SYM = 01H:
DI
If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the
register and clears SYM.0 to "0", disabling interrupt processing.
Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.
6-37
INSTRUCTION SET
S3C830A/P830A
DIV— Divide (Unsigned)
DIV
dst,src
Operation:
dst ÷ src
dst (UPPER) ¬ REMAINDER
dst (LOWER) ¬ QUOTIENT
The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits)
is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of
8
the destination. When the quotient is ³ 2 , the numbers stored in the upper and lower halves of
the destination for quotient and remainder are incorrect. Both operands are treated as unsigned
integers.
Flags:
C: Set if the V flag is set and quotient is between 28 and 29 –1; cleared otherwise.
Z: Set if divisor or quotient = "0"; cleared otherwise.
S: Set if MSB of quotient = "1"; cleared otherwise.
V: Set if quotient is ³ 28 or if divisor = "0"; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
RR
RR
RR
src
opc
src
dst
3
26/10
26/10
26/10
94
95
96
R
IR
IM
NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.
Examples:
Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:
DIV
DIV
DIV
RR0,R2
®
®
®
R0 = 03H, R1 = 40H
R0 = 03H, R1 = 20H
R0 = 03H, R1 = 80H
RR0,@R2
RR0,#20H
In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H
(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit
RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains
the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the
destination register RR0 (R0) and the quotient in the lower half (R1).
6-38
S3C830A/P830A
INSTRUCTION SET
DJNZ— Decrement and Jump if Non-Zero
DJNZ
r,dst
Operation:
r ¬ r – 1
If r ¹ 0, PC ¬ PC + dst
The working register being used as a counter is decremented. If the contents of the register are
not logic zero after decrementing, the relative address is added to the program counter and
control passes to the statement whose address is now in the PC. The range of the relative
address is +127 to –128, and the original value of the PC is taken to be the address of the
instruction byte following the DJNZ statement.
NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at
the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
r | opc
dst
2
8 (jump taken)
8 (no jump)
rA
RA
r = 0 to F
Example:
Given: R1 = 02H and LOOP is the label of a relative address:
SRP
#0C0H
DJNZ R1,LOOP
DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the
destination operand instead of a numeric relative address value. In the example, working register
R1 contains the value 02H, and LOOP is the label for a relative address.
The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.
Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative
address specified by the LOOP label.
6-39
INSTRUCTION SET
S3C830A/P830A
EI— Enable Interrupts
EI
Operation:
SYM (0) ¬ 1
An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to
be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was
set while interrupt processing was disabled (by executing a DI instruction), it will be serviced
when you execute the EI instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
9F
Example:
Given: SYM = 00H:
EI
If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the
statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for
global interrupt processing.)
6-40
S3C830A/P830A
INSTRUCTION SET
ENTER— Enter
ENTER
Operation:
SP
@SP
IP
¬
¬
¬
¬
¬
SP – 2
IP
PC
PC
IP
@IP
IP + 2
This instruction is useful when implementing threaded-code languages. The contents of the
instruction pointer are pushed to the stack. The program counter (PC) value is then written to the
instruction pointer. The program memory word that is pointed to by the instruction pointer is
loaded into the PC, and the instruction pointer is incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
14
1F
Example:
The diagram below shows one example of how to use an ENTER statement.
Before
After
Data
Address
IP
Data
Address
IP
0050
0040
0022
0043
0110
0020
Address
Data
1F
Address
40 Enter
Data
1F
PC
SP
40 Enter
PC
SP
41 Address H 01
42 Address L 10
43 Address H
41 Address H 01
42 Address L 10
43 Address H
20
21
22
00
50
IPH
IPL
Data
110 Routine
Memory
Memory
22
Data
Stack
Stack
6-41
INSTRUCTION SET
S3C830A/P830A
EXIT— Exit
EXIT
Operation:
IP
¬
¬
¬
¬
@SP
SP
PC
IP
SP + 2
@IP
IP + 2
This instruction is useful when implementing threaded-code languages. The stack value is
popped and loaded into the instruction pointer. The program memory word that is pointed to by
the instruction pointer is then loaded into the program counter, and the instruction pointer is
incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode (Hex)
opc
1
14 (internal stack)
16 (internal stack)
2F
Example:
The diagram below shows one example of how to use an EXIT statement.
Before
After
Data
Address
IP
Data
Address
IP
0050
0040
0022
0052
0060
0022
Address
Data
Address
Data
PC
SP
PC
SP
50 PCL old
51 PCH
60
00
60
Main
140 Exit
2F
20
21
22
00
50
IPH
IPL
Data
Memory
Memory
Data
22
Stack
Stack
6-42
S3C830A/P830A
INSTRUCTION SET
IDLE— Idle Operation
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle
mode can be released by an interrupt request (IRQ) or an external reset operation.
In application programs, a IDLE instruction must be immediately followed by at least three NOP
instructions. This ensures an adeguate time interval for the clock to stabilize before the next
instruction is executed. If three or more NOP instructons are not used after IDLE instruction,
leakage current could be flown because of the floating state in the internal bus.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
6F
–
–
Example:
The instruction
IDLE
NOP
NOP
NOP
; stops the CPU clock but not the system clock
6-43
INSTRUCTION SET
S3C830A/P830A
INC— Increment
INC
dst
Operation:
dst ¬ dst + 1
The contents of the destination operand are incremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
dst | opc
opc
1
4
rE
r
r = 0 to F
dst
2
4
4
20
21
R
IR
Examples:
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:
INC
INC
INC
R0
®
®
®
R0 = 1CH
00H
@R0
Register 00H = 0DH
R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement
"INC R0" leaves the value 1CH in that same register.
The next example shows the effect an INC instruction has on register 00H, assuming that it
contains the value 0CH.
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the
value of register 1BH from 0FH to 10H.
6-44
S3C830A/P830A
INSTRUCTION SET
INCW— Increment Word
INCW
dst
Operation:
dst ¬ dst + 1
The contents of the destination (which must be an even address) and the byte following that
location are treated as a single 16-bit value that is incremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
A0
A1
RR
IR
Examples:
Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:
INCW RR0
INCW @R1
®
®
R0 = 1AH, R1 = 03H
Register 02H = 10H, register 03H = 00H
In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H
in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the
value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect
Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to
00H and register 02H from 0FH to 10H.
NOTE:
A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an
INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the
following example:
LOOP:
INCW
LD
OR
RR0
R2,R1
R2,R0
NZ,LOOP
JR
6-45
INSTRUCTION SET
S3C830A/P830A
IRET— Interrupt Return
IRET
IRET (Normal)
IRET (Fast)
Operation:
FLAGS ¬ @SP
SP ¬ SP + 1
PC ¬ @SP
PC « IP
FLAGS ¬ FLAGS'
FIS ¬
0
SP ¬ SP + 2
SYM(0) ¬
1
This instruction is used at the end of an interrupt service routine. It restores the flag register and
the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the
fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast
interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.
Flags:
All flags are restored to their original settings (that is, the settings before the interrupt occurred).
Format:
Bytes
Cycles
Opcode (Hex)
IRET
(Normal)
opc
1
10 (internal stack)
12 (internal stack)
BF
Bytes
Cycles
Opcode (Hex)
IRET
(Fast)
opc
1
6
BF
Example:
In the figure below, the instruction pointer is initially loaded with 100H in the main program
before interrupts are enabled. When an interrupt occurs, the program counter and instruction
pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return
address. The last instruction in the service routine normally is a jump to IRET at address FFH.
This causes the instruction pointer to be loaded with 100H "again" and the program counter to
jump back to the main program. Now, the next interrupt can occur and the IP is still correct at
100H.
0H
FFH
IRET
100H
Interrupt
Service
Routine
JP to FFH
FFFFH
NOTE:
In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay
attention to the order of the last two instructions. The IRET cannot be immediately proceeded by
a clearing of the interrupt status (as with a reset of the IPR register).
6-46
S3C830A/P830A
INSTRUCTION SET
JP— Jump
JP
cc,dst
(Conditional)
JP
dst
(Unconditional)
Operation:
If cc is true, PC ¬ dst
The conditional JUMP instruction transfers program control to the destination address if the
condition specified by the condition code (cc) is true; otherwise, the instruction following the JP
instruction is executed. The unconditional JP simply replaces the contents of the PC with the
contents of the specified register pair. Control then passes to the statement addressed by the
PC.
Flags:
No flags are affected.
Format: (1)
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(2)
cc | opc
dst
3
8
ccD
DA
cc = 0 to F
opc
dst
2
8
30
IRR
NOTES:
1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.
2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the
opcode are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:
JP
JP
C,LABEL_W
@00H
®
®
LABEL_W = 1000H, PC = 1000H
PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the
statement
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to
that location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.
The second example shows an unconditional JP. The statement "JP @00" replaces the contents
of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
6-47
INSTRUCTION SET
S3C830A/P830A
JR— Jump Relative
JR
cc,dst
Operation:
If cc is true, PC ¬ PC + dst
If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program
counter; otherwise, the instruction following the JR instruction is executed. (See list of condition
codes).
The range of the relative address is +127, –128, and the original value of the program counter is
taken to be the address of the first instruction byte following the JR statement.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(1)
cc | opc
dst
2
6
ccB
RA
cc = 0 to F
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each
four bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H:
JR
C,LABEL_X
®
PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will
pass control to the statement whose address is now in the PC. Otherwise, the program
instruction following the JR would be executed.
6-48
S3C830A/P830A
INSTRUCTION SET
LD— Load
LD
dst,src
Operation:
dst ¬ src
The contents of the source are loaded into the destination. The source's contents are unaffected.
No flags are affected.
Flags:
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
IM
R
dst | opc
src | opc
opc
src
dst
2
4
4
rC
r8
r
r
2
2
3
3
4
r9
R
r
r = 0 to F
dst | src
4
4
C7
D7
r
lr
r
Ir
opc
src
dst
src
6
6
E4
E5
R
R
R
IR
opc
dst
6
6
E6
D6
R
IM
IM
IR
opc
opc
opc
src
dst
x
3
3
3
6
6
6
F5
87
97
IR
r
R
x [r]
r
dst | src
src | dst
x
x [r]
6-49
INSTRUCTION SET
S3C830A/P830A
LD— Load
LD
(Continued)
Examples:
Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,
register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
R0,#10H
R0,01H
®
®
®
®
®
®
®
®
®
®
R0 = 10H
R0 = 20H, register 01H = 20H
Register 01H = 01H, R0 = 01H
R1 = 20H, R0 = 01H
01H,R0
R1,@R0
@R0,R1
00H,01H
02H,@00H
00H,#0AH
@00H,#10H
@00H,02H
R0 = 01H, R1 = 0AH, register 01H = 0AH
Register 00H = 20H, register 01H = 20H
Register 02H = 20H, register 00H = 01H
Register 00H = 0AH
Register 00H = 01H, register 01H = 10H
Register 00H = 01H, register 01H = 02, register 02H = 02H
R0 = 0FFH, R1 = 0AH
R0,#LOOP[R1] ®
#LOOP[R0],R1 ®
Register 31H = 0AH, R0 = 01H, R1 = 0AH
6-50
S3C830A/P830A
INSTRUCTION SET
LDB— Load Bit
LDB
dst,src.b
LDB
dst.b,src
Operation:
dst(0) ¬ src(b)
or
dst(b) ¬ src(0)
The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the
source is loaded into the specified bit of the destination. No other bits of the destination are
affected. The source is unaffected.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
dst | b | 0
src | b | 1
src
dst
3
6
47
r0
Rb
3
6
47
Rb
r0
NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the
bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples:
Given: R0 = 06H and general register 00H = 05H:
LDB
LDB
R0,00H.2
00H.0,R0
®
®
R0 = 07H, register 00H = 05H
R0 = 06H, register 00H = 04H
In the first example, destination working register R0 contains the value 06H and the source
general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the
00H register into bit zero of the R0 register, leaving the value 07H in register R0.
In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit
zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in
general register 00H.
6-51
INSTRUCTION SET
S3C830A/P830A
LDC/LDE— Load Memory
LDC/LDE
dst,src
Operation:
dst ¬ src
This instruction loads a byte from program or data memory into a working register or vice-versa.
The source values are unaffected. LDC refers to program memory and LDE to data memory.
The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd
number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
1.
2.
3.
4.
5.
opc
opc
opc
opc
opc
dst | src
src | dst
dst | src
src | dst
dst | src
2
10
C3
D3
E7
F7
A7
r
Irr
2
3
3
4
10
12
12
14
Irr
r
XS
XS
r
XS [rr]
r
XS [rr]
r
XLL
XLH
XLH
DAH
DAH
DAH
DAH
XL [rr]
XLL
DAL
DAL
DAL
DAL
6.
7.
8.
9.
opc
opc
opc
opc
src | dst
dst | 0000
src | 0000
dst | 0001
src | 0001
4
4
4
4
4
14
14
14
14
14
B7
A7
B7
A7
B7
XL [rr]
r
DA
r
r
DA
r
DA
r
10.
opc
DA
NOTES:
1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.
2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one
byte.
3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two
bytes.
4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set
of values, used in formats 9 and 10, are used to address data memory.
6-52
S3C830A/P830A
INSTRUCTION SET
LDC/LDE— Load Memory
LDC/LDE
(Continued)
Examples:
Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations
0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory
locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:
LDC
R0,@RR2
; R0 ¬ contents of program memory location 0104H
; R0 = 1AH, R2 = 01H, R3 = 04H
LDE
R0,@RR2
; R0 ¬ contents of external data memory location 0104H
; R0 = 2AH, R2 = 01H, R3 = 04H
LDC (note) @RR2,R0
; 11H (contents of R0) is loaded into program memory
; location 0104H (RR2),
; working registers R0, R2, R3 ® no change
LDE
LDC
LDE
@RR2,R0
; 11H (contents of R0) is loaded into external data memory
; location 0104H (RR2),
; working registers R0, R2, R3 ® no change
R0,#01H[RR2]
R0,#01H[RR2]
; R0 ¬ contents of program memory location 0105H
; (01H + RR2),
; R0 = 6DH, R2 = 01H, R3 = 04H
; R0 ¬ contents of external data memory location 0105H
; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H
LDC (note) #01H[RR2],R0
; 11H (contents of R0) is loaded into program memory location
; 0105H (01H + 0104H)
LDE
LDC
LDE
#01H[RR2],R0
; 11H (contents of R0) is loaded into external data memory
; location 0105H (01H + 0104H)
R0,#1000H[RR2] ; R0 ¬ contents of program memory location 1104H
; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H
R0,#1000H[RR2] ; R0 ¬ contents of external data memory location 1104H
; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H
LDC
LDE
R0,1104H
R0,1104H
; R0 ¬ contents of program memory location 1104H, R0 = 88H
; R0 ¬ contents of external data memory location 1104H,
; R0 = 98H
LDC (note) 1105H,R0
; 11H (contents of R0) is loaded into program memory location
; 1105H, (1105H) ¬ 11H
LDE
1105H,R0
; 11H (contents of R0) is loaded into external data memory
; location 1105H, (1105H) ¬ 11H
NOTE: These instructions are not supported by masked ROM type devices.
6-53
INSTRUCTION SET
S3C830A/P830A
LDCD/LDED— Load Memory and Decrement
LDCD/LDED dst,src
Operation:
dst ¬ src
rr ¬ rr – 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then decremented. The contents of the source are unaffected.
LDCD references program memory and LDED references external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E2
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and
external data memory location 1033H = 0DDH:
LDCD
R8,@RR6
; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is decremented by one
; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ¬ RR6 – 1)
LDED
R8,@RR6
; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is decremented by one (RR6 ¬ RR6 – 1)
; R8 = 0DDH, R6 = 10H, R7 = 32H
6-54
S3C830A/P830A
INSTRUCTION SET
LDCI/LDEI— Load Memory and Increment
LDCI/LDEI
dst,src
Operation:
dst ¬ src
rr ¬ rr + 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then incremented automatically. The contents of the source are unaffected.
LDCI refers to program memory and LDEI refers to external data memory. The assembler
makes 'Irr' even for program memory and odd for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E3
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and
1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:
LDCI
R8,@RR6
; 0CDH (contents of program memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)
; R8 = 0CDH, R6 = 10H, R7 = 34H
LDEI
R8,@RR6
; 0DDH (contents of data memory location 1033H) is loaded
; into R8 and RR6 is incremented by one (RR6 ¬ RR6 + 1)
; R8 = 0DDH, R6 = 10H, R7 = 34H
6-55
INSTRUCTION SET
S3C830A/P830A
LDCPD/LDEPD— Load Memory with Pre-Decrement
LDCPD/
LDEPD
dst,src
Operation:
rr ¬ rr – 1
dst ¬ src
These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is
first decremented. The contents of the source location are then loaded into the destination
location. The contents of the source are unaffected.
LDCPD refers to program memory and LDEPD refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for external data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src | dst
2
14
F2
Irr
r
Examples:
Given: R0 = 77H, R6 = 30H, and R7 = 00H:
LDCPD @RR6,R0
; (RR6 ¬ RR6 – 1)
; 77H (contents of R0) is loaded into program memory location
; 2FFFH (3000H – 1H)
; R0 = 77H, R6 = 2FH, R7 = 0FFH
LDEPD @RR6,R0
; (RR6 ¬ RR6 – 1)
; 77H (contents of R0) is loaded into external data memory
; location 2FFFH (3000H – 1H)
; R0 = 77H, R6 = 2FH, R7 = 0FFH
6-56
S3C830A/P830A
INSTRUCTION SET
LDCPI/LDEPI— Load Memory with Pre-Increment
LDCPI/
LDEPI
dst,src
Operation:
rr ¬ rr + 1
dst ¬ src
These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is
first incremented. The contents of the source location are loaded into the destination location.
The contents of the source are unaffected.
LDCPI refers to program memory and LDEPI refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src | dst
2
14
F3
Irr
r
Examples:
Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:
LDCPI
@RR6,R0
; (RR6 ¬ RR6 + 1)
; 7FH (contents of R0) is loaded into program memory
; location 2200H (21FFH + 1H)
; R0 = 7FH, R6 = 22H, R7 = 00H
LDEPI
@RR6,R0
; (RR6 ¬ RR6 + 1)
; 7FH (contents of R0) is loaded into external data memory
; location 2200H (21FFH + 1H)
; R0 = 7FH, R6 = 22H, R7 = 00H
6-57
INSTRUCTION SET
S3C830A/P830A
LDW— Load Word
LDW
dst,src
Operation:
dst ¬ src
The contents of the source (a word) are loaded into the destination. The contents of the source
are unaffected.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
RR
RR
src
RR
IR
opc
opc
src
dst
dst
3
8
8
C4
C5
src
4
8
C6
RR
IML
Examples:
Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH,
register 01H = 02H, register 02H = 03H, and register 03H = 0FH:
LDW
LDW
RR6,RR4
00H,02H
®
®
R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH
Register 00H = 03H, register 01H = 0FH,
register 02H = 03H, register 03H = 0FH
LDW
LDW
LDW
LDW
RR2,@R7
®
®
®
®
R2 = 03H, R3 = 0FH,
04H,@01H
RR6,#1234H
02H,#0FEDH
Register 04H = 03H, register 05H = 0FH
R6 = 12H, R7 = 34H
Register 02H = 0FH, register 03H = 0EDH
In the second example, please note that the statement "LDW 00H,02H" loads the contents of
the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in
general register 00H and the value 0FH in register 01H.
The other examples show how to use the LDW instruction with various addressing modes and
formats.
6-58
S3C830A/P830A
INSTRUCTION SET
MULT— Multiply (Unsigned)
MULT
dst,src
Operation:
dst ¬ dst ´ src
The 8-bit destination operand (even register of the register pair) is multiplied by the source
operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination
address. Both operands are treated as unsigned integers.
Flags:
C: Set if result is > 255; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if MSB of the result is a "1"; cleared otherwise.
V: Cleared.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
RR
RR
RR
src
opc
src
dst
3
22
22
22
84
85
86
R
IR
IM
Examples:
Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:
MULT
MULT
MULT
00H, 02H
®
®
®
Register 00H = 01H, register 01H = 20H, register 02H = 09H
Register 00H = 00H, register 01H = 0C0H
00H, @01H
00H, #30H
Register 00H = 06H, register 01H = 00H
In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in
the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The
16-bit product, 0120H, is stored in the register pair 00H, 01H.
6-59
INSTRUCTION SET
S3C830A/P830A
NEXT— Next
NEXT
Operation:
PC ¬ @ IP
IP ¬ IP + 2
The NEXT instruction is useful when implementing threaded-code languages. The program
memory word that is pointed to by the instruction pointer is loaded into the program counter. The
instruction pointer is then incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
10
0F
Example:
The following diagram shows one example of how to use the NEXT instruction.
Before
After
Data
Address
IP
Data
Address
IP
0043
0120
0045
0130
Address
Data
Address
43 Address H
Data
PC
43 Address H 01
PC
44 Address L 10
45 Address H
44 Address L
45 Address H
120 Next
Memory
130 Routine
Memory
6-60
S3C830A/P830A
INSTRUCTION SET
NOP— No Operation
NOP
Operation:
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are
executed in sequence in order to effect a timing delay of variable duration.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
FF
Example:
When the instruction
NOP
is encountered in a program, no operation occurs. Instead, there is a delay in instruction
execution time.
6-61
INSTRUCTION SET
S3C830A/P830A
OR— Logical OR
OR
dst,src
Operation:
dst ¬ dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a "1" being
stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is
stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
42
43
r
r
r
lr
dst
src
3
3
6
6
44
45
R
R
R
IR
dst
6
46
R
IM
Examples:
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and
register 08H = 8AH:
OR
OR
OR
OR
OR
R0,R1
®
®
®
®
®
R0 = 3FH, R1 = 2AH
R0,@R2
00H,01H
01H,@00H
00H,#02H
R0 = 37H, R2 = 01H, register 01H = 37H
Register 00H = 3FH, register 01H = 37H
Register 00H = 08H, register 01H = 0BFH
Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value
2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the
result (3FH) in destination register R0.
The other examples show the use of the logical OR instruction with the various addressing
modes and formats.
6-62
S3C830A/P830A
INSTRUCTION SET
POP— Pop From Stack
POP
dst
Operation:
dst ¬ @SP
SP ¬ SP + 1
The contents of the location addressed by the stack pointer are loaded into the destination. The
stack pointer is then incremented by one.
Flags:
No flags affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
50
51
R
IR
Examples:
Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH,
and stack register 0FBH = 55H:
POP
POP
00H
®
®
Register 00H = 55H, SP = 00FCH
@00H
Register 00H = 01H, register 01H = 55H, SP = 00FCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H"
loads the contents of location 00FBH (55H) into destination register 00H and then increments the
stack pointer by one. Register 00H then contains the value 55H and the SP points to location
00FCH.
6-63
INSTRUCTION SET
S3C830A/P830A
POPUD— Pop User Stack (Decrementing)
POPUD
dst,src
Operation:
dst ¬ src
IR ¬ IR – 1
This instruction is used for user-defined stacks in the register file. The contents of the register file
location addressed by the user stack pointer are loaded into the destination. The user stack
pointer is then decremented.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src
dst
3
8
92
R
IR
Example:
Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and
register 02H = 70H:
POPUD 02H,@00H
®
Register 00H = 41H, register 02H = 6FH, register 42H = 6FH
If general register 00H contains the value 42H and register 42H the value 6FH, the statement
"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The
user stack pointer is then decremented by one, leaving the value 41H.
6-64
S3C830A/P830A
INSTRUCTION SET
POPUI— Pop User Stack (Incrementing)
POPUI
dst,src
Operation:
dst ¬ src
IR ¬ IR + 1
The POPUI instruction is used for user-defined stacks in the register file. The contents of the
register file location addressed by the user stack pointer are loaded into the destination. The user
stack pointer is then incremented.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src
dst
3
8
93
R
IR
Example:
Given: Register 00H = 01H and register 01H = 70H:
POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H
®
If general register 00H contains the value 01H and register 01H the value 70H, the statement
"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user
stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.
6-65
INSTRUCTION SET
S3C830A/P830A
PUSH— Push To Stack
PUSH
src
Operation:
SP ¬ SP – 1
@SP ¬ src
A PUSH instruction decrements the stack pointer value and loads the contents of the source
(src) into the location addressed by the decremented stack pointer. The operation then adds the
new value to the top of the stack.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
src
2
8 (internal clock)
8 (external clock)
70
R
8 (internal clock)
8 (external clock)
71
IR
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:
PUSH
PUSH
40H
®
Register 40H = 4FH, stack register 0FFH = 4FH,
SPH = 0FFH, SPL = 0FFH
@40H
®
Register 40H = 4FH, register 4FH = 0AAH, stack register
0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH
In the first example, if the stack pointer contains the value 0000H, and general register 40H the
value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It
then loads the contents of register 40H into location 0FFFFH and adds this new value to the top
of the stack.
6-66
S3C830A/P830A
INSTRUCTION SET
PUSHUD— Push User Stack (Decrementing)
PUSHUD
dst,src
Operation:
IR ¬ IR – 1
dst ¬ src
This instruction is used to address user-defined stacks in the register file. PUSHUD decrements
the user stack pointer and loads the contents of the source into the register addressed by the
decremented stack pointer.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst
src
3
8
82
IR
R
Example:
Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:
PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H
®
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The
01H register value, 05H, is then loaded into the register addressed by the decremented user
stack pointer.
6-67
INSTRUCTION SET
S3C830A/P830A
PUSHUI— Push User Stack (Incrementing)
PUSHUI
dst,src
Operation:
IR ¬ IR + 1
dst ¬ src
This instruction is used for user-defined stacks in the register file. PUSHUI increments the user
stack pointer and then loads the contents of the source into the register location addressed by
the incremented user stack pointer.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst
src
3
8
83
IR
R
Example:
Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:
PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H
®
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H
register value, 05H, is then loaded into the location addressed by the incremented user stack
pointer.
6-68
S3C830A/P830A
INSTRUCTION SET
RCF— Reset Carry Flag
RCF
RCF
Operation:
C ¬ 0
The carry flag is cleared to logic zero, regardless of its previous value.
C: Cleared to "0".
Flags:
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
CF
Example:
Given: C = "1" or "0":
The instruction RCF clears the carry flag (C) to logic zero.
6-69
INSTRUCTION SET
S3C830A/P830A
RET— Return
RET
Operation:
PC ¬ @SP
SP ¬ SP + 2
The RET instruction is normally used to return to the previously executing procedure at the end
of a procedure entered by a CALL instruction. The contents of the location addressed by the
stack pointer are popped into the program counter. The next statement that is executed is the
one that is addressed by the new program counter value.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode (Hex)
opc
1
8 (internal stack)
10 (internal stack)
AF
Example:
Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:
RET PC = 101AH, SP = 00FEH
®
The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte
of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the
PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to
memory location 00FEH.
6-70
S3C830A/P830A
INSTRUCTION SET
RL— Rotate Left
RL
dst
Operation:
C ¬ dst (7)
dst (0) ¬ dst (7)
dst (n + 1) ¬ dst (n), n = 0–6
The contents of the destination operand are rotated left one bit position. The initial value of bit 7
is moved to the bit zero (LSB) position and also replaces the carry flag.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
90
91
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:
RL
RL
00H
®
®
Register 00H = 55H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
@01H
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement
"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)
and setting the carry and overflow flags.
6-71
INSTRUCTION SET
S3C830A/P830A
RLC— Rotate Left Through Carry
RLC
dst
Operation:
dst (0) ¬ C
C ¬ dst (7)
dst (n + 1) ¬ dst (n), n = 0–6
The contents of the destination operand with the carry flag are rotated left one bit position. The
initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
10
11
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":
RLC
RLC
00H
®
®
Register 00H = 54H, C = "1"
@01H
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement
"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag
and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H
(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
6-72
S3C830A/P830A
INSTRUCTION SET
RR— Rotate Right
RR
dst
Operation:
C ¬ dst (0)
dst (7) ¬ dst (0)
dst (n) ¬ dst (n + 1), n = 0–6
The contents of the destination operand are rotated right one bit position. The initial value of bit
zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
E0
E1
R
IR
Examples:
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:
RR
RR
00H
®
®
Register 00H = 98H, C = "1"
Register 01H = 02H, register 02H = 8BH, C = "1"
@01H
In the first example, if general register 00H contains the value 31H (00110001B), the statement
"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to
bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also
resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
6-73
INSTRUCTION SET
S3C830A/P830A
RRC— Rotate Right Through Carry
RRC
dst
Operation:
dst (7) ¬ C
C ¬ dst (0)
dst (n) ¬ dst (n + 1), n = 0–6
The contents of the destination operand and the carry flag are rotated right one bit position. The
initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit
7 (MSB).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0" cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
C0
C1
R
IR
Examples:
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":
RRC
RRC
00H
®
®
Register 00H = 2AH, C = "1"
@01H
Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement
"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1")
replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new
value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both
cleared to "0".
6-74
S3C830A/P830A
INSTRUCTION SET
SB0— Select Bank 0
SB0
Operation:
BANK ¬ 0
The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,
selecting bank 0 register addressing in the set 1 area of the register file.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
4F
Example:
The statement
SB0
clears FLAGS.0 to "0", selecting bank 0 register addressing.
6-75
INSTRUCTION SET
S3C830A/P830A
SB1— Select Bank 1
SB1
Operation:
BANK ¬ 1
The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,
selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not
implemented in some S3C8-series microcontrollers.)
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
5F
Example:
The statement
SB1
sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.
6-76
S3C830A/P830A
INSTRUCTION SET
SBC— Subtract with Carry
SBC
dst,src
Operation:
dst ¬ dst – src – c
The source operand, along with the current value of the carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the source are
unaffected. Subtraction is performed by adding the two's-complement of the source operand to
the destination operand. In multiple precision arithmetic, this instruction permits the carry
("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of
high-order operands.
Flags:
C: Set if a borrow occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign
of the result is the same as the sign of the source; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise, indicating a "borrow".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
32
33
r
r
r
lr
dst
src
3
3
6
6
34
35
R
R
R
IR
dst
6
36
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and
register 03H = 0AH:
SBC
SBC
SBC
SBC
SBC
R1,R2
®
®
®
®
®
R1 = 0CH, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#8AH
R1 = 05H, R2 = 03H, register 03H = 0AH
Register 01H = 1CH, register 02H = 03H
Register 01H = 15H,register 02H = 03H, register 03H = 0AH
Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H,
the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the
destination (10H) and then stores the result (0CH) in register R1.
6-77
INSTRUCTION SET
S3C830A/P830A
SCF— Set Carry Flag
SCF
Operation:
Flags:
C ¬ 1
The carry flag (C) is set to logic one, regardless of its previous value.
C: Set to "1".
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
DF
Example:
The statement
SCF
sets the carry flag to logic one.
6-78
S3C830A/P830A
INSTRUCTION SET
SRA— Shift Right Arithmetic
SRA
dst
Operation:
dst (7) ¬ dst (7)
C ¬ dst (0)
dst (n) ¬ dst (n + 1), n = 0–6
An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.
7
6
0
C
Flags:
C: Set if the bit shifted from the LSB position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
D0
D1
R
IR
Examples:
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":
SRA
SRA
00H
®
®
Register 00H = 0CD, C = "0"
@02H
Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement
"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C
flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves
the value 0CDH (11001101B) in destination register 00H.
6-79
INSTRUCTION SET
S3C830A/P830A
SRP/SRP0/SRP1— Set Register Pointer
SRP
src
src
src
SRP0
SRP1
Operation:
If src (1) = 1 and src (0) = 0 then: RP0 (3–7)
¬
¬
¬
¬
¬
¬
src (3–7)
src (3–7)
src (4–7),
0
If src (1) = 0 and src (0) = 1 then: RP1 (3–7)
If src (1) = 0 and src (0) = 0 then: RP0 (4–7)
RP0 (3)
RP1 (4–7)
RP1 (3)
src (4–7),
1
The source data bits one and zero (LSB) determine whether to write one or both of the register
pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register
pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
src
opc
src
2
4
31
IM
Examples:
The statement
SRP #40H
sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location
0D7H to 48H.
The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to
68H.
6-80
S3C830A/P830A
INSTRUCTION SET
STOP— Stop Operation
STOP
Operation:
The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,
peripheral registers, and I/O port control and data registers are retained. Stop mode can be
released by an external reset operation or by external interrupts. For the reset operation, the
RESET pin must be held to Low level until the required oscillation stabilization interval has
elapsed.
In application programs, a STOP instruction must be immediately followed by at least three NOP
instructions. This ensures an adeguate time interval for the clock to stabilize before the next
instruction is executed. If three or more NOP instructons are not used after STOP instruction,
leakage current could be flown because of the floating state in the internal bus.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
7F
–
–
Example:
The statement
STOP
NOP
NOP
NOP
; halts all microcontroller operations
6-81
INSTRUCTION SET
S3C830A/P830A
SUB— Subtract
SUB
dst,src
Operation:
dst ¬ dst – src
The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the
two's complement of the source operand to the destination operand.
Flags:
C: Set if a "borrow" occurred; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the
sign of the result is of the same as the sign of the source operand; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise indicating a "borrow".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst |
src
2
4
6
22
r
r
23
r
lr
opc
opc
src
dst
dst
src
3
3
6
6
24
25
R
R
R
IR
6
26
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB
SUB
SUB
SUB
SUB
SUB
R1,R2
®
®
®
®
®
®
R1 = 0FH, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#90H
01H,#65H
R1 = 08H, R2 = 03H
Register 01H = 1EH, register 02H = 03H
Register 01H = 17H, register 02H = 03H
Register 01H = 91H; C, S, and V = "1"
Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination
value (12H) and stores the result (0FH) in destination register R1.
6-82
S3C830A/P830A
INSTRUCTION SET
SWAP— Swap Nibbles
SWAP
dst
Operation:
dst (0 – 3) « dst (4 – 7)
The contents of the lower four bits and upper four bits of the destination operand are swapped.
7
4 3
0
Flags:
C: Undefined.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
F0
F1
R
IR
Examples:
Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:
SWAP
SWAP
00H
®
®
Register 00H = 0E3H
@02H
Register 02H = 03H, register 03H = 4AH
In the first example, if general register 00H contains the value 3EH (00111110B), the statement
"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value
0E3H (11100011B).
6-83
INSTRUCTION SET
S3C830A/P830A
TCM— Test Complement Under Mask
TCM
dst,src
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask). The TCM statement complements the destination operand, which is then ANDed with the
source mask. The zero (Z) flag can then be checked to determine the result. The destination and
source operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
62
63
r
r
r
lr
dst
src
3
3
6
6
64
65
R
R
R
IR
dst
6
66
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TCM
TCM
TCM
TCM
R0,R1
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "1"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "1"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "1"
TCM
00H,#34
®
Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register
for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one
and can be tested to determine the result of the TCM operation.
6-84
S3C830A/P830A
INSTRUCTION SET
TM— Test Under Mask
TM
dst,src
Operation:
dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to
determine the result. The destination and source operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
72
73
r
r
r
lr
dst
src
3
3
6
6
74
75
R
R
R
IR
dst
6
76
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TM
TM
TM
TM
R0,R1
®
®
®
®
R0 = 0C7H, R1 = 02H, Z = "0"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "0"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
TM
00H,#54H
®
Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register
for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic
zero and can be tested to determine the result of the TM operation.
6-85
INSTRUCTION SET
S3C830A/P830A
WFI— Wait for Interrupt
WFI
Operation:
The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take
place during this wait state. The WFI status can be released by an internal interrupt, including a
fast interrupt .
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4n
3F
( n = 1, 2, 3, … )
Example:
The following sample program structure shows the sequence of operations that follow a "WFI"
statement:
Main program
.
.
.
EI
WFI
(Enable global interrupt)
(Wait for interrupt)
(Next instruction)
.
.
.
Interrupt occurs
Interrupt service routine
.
.
.
Clear interrupt flag
IRET
Service routine completed
6-86
S3C830A/P830A
INSTRUCTION SET
XOR— Logical Exclusive OR
XOR
dst,src
Operation:
dst ¬ dst XOR src
The source operand is logically exclusive-ORed with the destination operand and the result is
stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever
the corresponding bits in the operands are different; otherwise, a "0" bit is stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
B2
B3
r
r
r
lr
dst
src
3
3
6
6
B4
B5
R
R
R
IR
dst
6
B6
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
XOR
XOR
XOR
XOR
XOR
R0,R1
®
®
®
®
®
R0 = 0C5H, R1 = 02H
R0,@R1
00H,01H
00H,@01H
00H,#54H
R0 = 0E4H, R1 = 02H, register 02H = 23H
Register 00H = 29H, register 01H = 02H
Register 00H = 08H, register 01H = 02H, register 02H = 23H
Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains
the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0
value and stores the result (0C5H) in the destination register R0.
6-87
INSTRUCTION SET
S3C830A/P830A
NOTES
6-88
S3C830A/P830A
CLOCK CIRCUIT
7
CLOCK CIRCUIT
OVERVIEW
The clock frequency generated for the S3C830A by an external crystal can range from 0.4 MHz to 4.5 MHz. The
maximum CPU clock frequency is 4.5 MHz. The XIN and XOUT pins connect the external oscillator or clock
source to the on-chip clock circuit.
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components:
— External crystal or ceramic resonator oscillation source (or an external clock source)
— Oscillator stop and wake-up functions
— Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)
— System clock control register, CLKCON
— STOP control register, STPCON
CPU Clock Notation
In this document, the following notation is used for descriptions of the CPU clock;
fx: main clock
fxt: sub clock (the fxt is not implemented in the S3C830A)
fxx: selected system clock
C1
C2
XIN
XIN
S3C830A
S3C830A
XOUT
XOUT
Figure 7-1. Main Oscillator Circuit
(Crystal or Ceramic Oscillator)
Figure 7-2. Main Oscillator Circuit
(External Oscillator)
7-1
CLOCK CIRCUIT
S3C830A/P830A
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
— In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset
operation or an external interrupt (with RC delay noise filter).
— In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers, timer/
counters, and watch timer. Idle mode is released by a reset or by an external or internal interrupt.
Stop Release
INT
Main-System
Oscillator
Circuit
Sub-system
Oscillator
Circuit
fX
fXt
Selector 1
fXX
Stop
Logic "0"
Logic "0"
Stop
Logic "1"
Basic Timer
Timer/Counters
Watch Timer
LCD Controller
SIO0, SIO1
1/8-1/4096
STOP OSC
inst.
STPCON
Frequency
Dividing
Circuit
A/D Converter
PLL Frequency Synthesizer
IF Counter
1/1 1/2 1/8 1/16
Selector 2
System Clock
CLKCON.4-.3
CPU Clock
NOTE:
The fxt is not implemented in the S3C830A.
IDLE Instruction
Figure 7-3. System Clock Circuit Diagram
7-2
S3C830A/P830A
CLOCK CIRCUIT
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in the set 1, address D4H. It is read/write addressable and
has the following functions:
— Oscillator frequency divide-by value
After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If
necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1.
System Clock Control Register (CLKCON)
D4H, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
(must keep always 0)
Not used
(must keep always 0)
Oscillator IRQ wake-up
function bit:
0 = Enable IRQ for main
wake-up in power down mode
1 = Disable IRQ for main
wake-up in power down mode
Divide-by selection bits for
CPU clock frequency:
00 = fXX/16
01 = fXX/8
10 = fXX/2
11 = fXX/1 (non-divided)
Figure 7-4. System Clock Control Register (CLKCON)
7-3
CLOCK CIRCUIT
S3C830A/P830A
STOP Control Register (STPCON)
FBH, Set 1,bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
STOP Control bits:
Other values = Disable STOP instruction
10100101 = Enable STOP instruction
NOTE:
Before execute the STOP instruction, set this STPCON register as "10100101B".
Otherwise the STOP instruction will not execute as well as reset will be generated.
Figure 7-5. STOP Control Register (STPCON)
7-4
S3C830A/P830A
RESET and POWER-DOWN
8
RESET and POWER-DOWN
SYSTEM RESET
OVERVIEW
During a power-on reset, the voltage at VDD goes to High level and the RESET pin is forced to Low level. The
RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This
procedure brings the S3C830A into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a
minimum time interval after the power supply comes within tolerance. The minimum required time of a reset
operation for oscillation stabilization is 1 millisecond.
Whenever a reset occurs during normal operation (that is, when both VDD and RESET are High level), the
RESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are then
reset to their default hardware values
In summary, the following sequence of events occurs during a reset operation:
— All interrupt is disabled.
— The watchdog function (basic timer) is enabled.
— Ports 0-3 are set to input mode, and all pull-up resistors are disabled for the I/O port.
— Peripheral control and data register settings are disabled and reset to their default hardware values.
— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM
location 0100H (and 0101H) is fetched and executed.
NORMAL MODE RESET OPERATION
In normal (masked ROM) mode, the Test pin is tied to VSS. A reset enables access to the 48-Kbyte on-chip
ROM.
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing "1010B" to the upper nibble of BTCON.
8-1
RESET and POWER-DOWN
S3C830A/P830A
HARDWARE RESET VALUES
Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral
data registers following a reset operation. The following notation is used to represent reset values:
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
— An "x" means that the bit value is undefined after a reset.
— A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value.
Table 8-1. S3C830A Set 1 Register and Values after RESET
Register Name
Mnemonic
Address
Dec Hex
Locations D0H-D2H are not mapped.
Bit Values after RESET
7
6
5
4
3
2
1
0
Basic Timer Control Register
Clock Control Register
BTCON
CLKCON
FLAGS
RP0
211
212
213
214
215
216
217
218
219
220
221
222
223
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
0
0
x
1
1
x
x
x
x
0
x
0
0
0
0
x
1
1
x
x
x
x
0
x
–
0
0
0
x
0
0
x
x
x
x
0
x
–
0
0
0
x
0
0
x
x
x
x
0
x
x
0
0
0
x
0
1
x
x
x
x
0
x
x
0
0
0
x
–
–
x
x
x
x
0
x
x
0
0
0
0
–
–
x
x
x
x
0
x
0
0
0
0
0
–
–
x
x
x
x
0
x
0
0
System Flags Register
Register Pointer (High Byte)
Register Pointer (Low Byte)
Stack Pointer (High Byte)
Stack Pointer (Low Byte)
Instruction Pointer (High Byte)
Instruction Pointer (Low Byte)
Interrupt Request Register
Interrupt Mask Register
RP1
SPH
SPL
IPH
IPL
IRQ
IMR
System Mode Register
SYM
PP
Register Page Pointer
8-2
S3C830A/P830A
RESET and POWER-DOWN
Table 8-2. S3C830A Set 1, Bank 0 Register Values after RESET
Register Name
Mnemonic
Address
Bit Values after RESET
Dec
Hex
E0H
E1H
E2H
E3H
E4H
E5H
E6H
7
0
1
0
0
1
0
–
6
0
1
0
0
1
0
–
5
0
1
0
0
1
0
–
4
0
1
0
0
1
0
–
3
0
1
0
0
1
0
–
2
0
1
0
0
1
0
–
1
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
Timer 0 Counter Register
Timer 0 Data Register
T0CNT
T0DATA
T0CON
T1CNT
224
225
226
227
228
229
230
Timer 0 Control Register
Timer 1 Counter Register
Timer 1 Data Register
T1DATA
T1CON
INTPND
Timer 1 Control Register
Interrupt Pending Register
Location E7H is not mapped.
Watch Timer Control Register
SIO 0 Control Register
SIO 0 Data Register
WTCON
232
233
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
0
0
0
0
0
0
0
0
x
0
0
–
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
–
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
–
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
–
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
0
0
0
0
0
x
x
SIO0CON
SIO0DATA 234
SIO 0 Prescaler Register
SIO 1 Control Register
SIO 1 Data Register
SIO0PS
235
236
SIO1CON
SIO1DATA 237
SIO 1 Prescaler Register
A/D Converter Control Register
A/D Converter Data Register
LCD Control Register
LCD Mode Register
SIO1PS
ADCON
ADDATA
LCON
238
239
240
241
242
243
244
245
246
247
248
249
LMOD
IF Counter Mode Register
IF Counter 1
IFMOD
IFCNT1
IFCNT0
PLLD1
IF Counter 0
PLL Data Register 1
PLL Data Register 0
PLLD0
(note)
PLL Mode Register
PLLMOD
PLLREF
(note)
PLL Reference Frequency Register
Location FAH is not mapped.
STPCON 251 FBH
Location FCH is not mapped.
BTCNT 253 FDH
Location FEH is not mapped.
IPR 255 FFH
STOP Control Register
Basic Timer Data Register
Interrupt Priority Register
0
0
x
0
0
x
0
0
x
0
0
0
x
0
0
x
0
0
x
0
0
x
0
x
NOTE: Refer to the corresponding register in the chapter 4.
8-3
RESET and POWER-DOWN
S3C830A/P830A
Table 8-3. S3C830A Set 1, Bank 1 Register Values after RESET
Register Name
Mnemonic
Address
Bit Values after RESET
Dec
Hex
E0H
E1H
E2H
7
0
0
0
6
0
0
0
5
0
0
0
4
0
0
0
3
0
0
0
2
0
0
0
1
0
0
0
0
0
0
0
Port 0 Control Register (High Byte)
Port 0 Control Register (Low Byte)
P0CONH
P0CONL
P0PUR
224
225
226
Port 0 Pull-up Resistors Enable
Register
Locations E3H is not mapped.
Port 1 Control Register (High Byte)
Port 1 Control Register (Low Byte)
Port 1 Interrupt Control Register
Port 1 Interrupt Pending Register
Port 2 Control Register (High Byte)
Port 2 Control Register (Low Byte)
Port 3 Control Register (High Byte)
Port 3 Control Register (Low Byte)
P1CONH
P1CONL
P1INT
228
229
230
231
232
233
234
235
236
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P1PND
P2CONH
P2CONL
P3CONH
P3CONL
P3PUR
Port 3 Pull-up Resistors Enable
Register
Port Group 0 Control Register
Port Group 1 Control Register
Port Group 2 Control Register
Port 0 Data Register
PG0CON
237
238
239
240
241
242
243
244
245
246
247
248
EDH
EEH
EFH
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PG1CON
PG2CON
P0
Port 1 Data Register
P1
Port 2 Data Register
P2
Port 3 Data Register
P3
Port 4 Data Register
P4
Port 5 Data Register
P5
Port 6 Data Register
P6
Port 7 Data Register
P7
Port 8 Data Register
P8
Location F9H is not mapped.
Timer 2 Counter (High Byte)
Timer 2 Counter (Low Byte)
Timer 2 Data Register (High Byte)
Timer 2 Data Register (Low Byte)
Timer 2 Control Register
T2CNTH
T2CNTL
T2DATAH
T2DATAL
T2CON
250
251
252
253
254
F9H
FBH
FCH
FDH
FEH
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
Location FFH is not mapped.
8-4
S3C830A/P830A
RESET and POWER-DOWN
POWER-DOWN MODES
STOP MODE
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all
peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than
3 mA. All system functions stop when the clock “freezes”, but data stored in the internal register file is retained.
Stop mode can be released in one of two ways: by a reset or by external interrupts, for more details see Figure 7-
3.
NOTE
Do not use stop mode if you are using an external clock source because XIN input must be restricted
internally to VSS to reduce current leakage.
Using RESET to Release Stop Mode
Stop mode is released when the RESET signal is released and returns to high level: all system and peripheral
control registers are reset to their default hardware values and the contents of all data registers are retained. A
reset operation automatically selects a slow clock fxx/16 because CLKCON.3 and CLKCON.4 are cleared to
'00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization
routine by fetching the program instruction stored in ROM location 0100H.
Using an External Interrupt to Release Stop Mode
External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you
can use to release Stop mode in a given situation depends on the microcontroller’s current internal operating
mode. The external interrupts in the S3C830A interrupt structure that can be used to release Stop mode are:
— External interrupts P1.0–P1.7 (INT0–INT7)
Please note the following conditions for Stop mode release:
— If you release Stop mode using an external interrupt, the current values in system and peripheral control
registers are unchanged except STPCON register.
— If you use an internal or external interrupt for stop mode release, you can also program the duration of the
oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before
entering stop mode.
— When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting
remains unchanged and the currently selected clock value is used.
— The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service
routine, the instruction immediately following the one that initiated Stop mode is executed.
How to Enter into Stop Mode
Handling STPCON register then writing Stop instruction (keep the order).
LD
STPCON, #10100101B
STOP
NOP
NOP
NOP
8-5
RESET and POWER-DOWN
S3C830A/P830A
IDLE MODE
Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some
peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all
peripherals remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered.
There are two ways to release idle mode:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4
and CLKCON.3 are cleared to ‘00B’. If interrupts are masked, a reset is the only way to release idle mode.
2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle
mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock
value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction
immediately following the one that initiated idle mode is executed.
8-6
S3C830A/P830A
I/O PORTS
9
I/O PORTS
OVERVIEW
The S3C830A microcontroller has four bit-programmable and five nibble-programmable I/O ports,
P0–P8. The port 0–8 are all 8-bit ports. This gives a total of 72 I/O pins. Each port can be flexibly configured to
meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No
special I/O instructions are required. All ports of the S3C830A can be configured to input or output mode and P4–
P8 are shared with LCD segment signals.
Table 9-1 gives you a general overview of the S3C830A I/O port functions.
9-1
I/O PORTS
S3C830A/P830A
Table 9-1. S3C830A Port Configuration Overview
Configuration Options
Port
0
1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software; software
assignable pull-up.
Alternately P0.1–P0.7 can be used as T0CLK, T0CAP, T0OUT/T0PWM, T1CLK, T1OUT,
T2CLK, T2OUT.
1
1-bit programmable I/O port.
Schmitt trigger input or push-pull output mode selected by software; software assignable pull-
up .
P1.0–P1.7 can be used as inputs for external interrupts INT0–INT7 (with noise filter and
interrupt control).
2
3
1-bit programmable I/O port.
Schmitt trigger input or push-pull output mode selected by software; software assignable pull-
up. Alternately P2.0–P2.3 can be used as AD0–AD3.
1-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software; software
assignable pull-up.
Alternately P3.0–P3.6 can be used as BUZ, SCK0, SO0, SI0, SCK1, SO1, SI1.
4
5
6
7
8
4-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software;
software assignable pull-up. P4.0–P4.7 can alternately be used as outputs for LCD segment
signals.
4-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software;
software assignable pull-up. P5.0–P5.7 can alternately be used as outputs for LCD segment
signals.
4-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software;
software assignable pull-up. P6.0–P6.7 can alternately be used as outputs for LCD segment
signals.
4-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software;
software assignable pull-up. P7.0–P7.7 can alternately be used as outputs for LCD segment
signals.
4-bit programmable I/O port.
Schmitt trigger input or push-pull, open-drain output mode selected by software;
software assignable pull-up. P8.0–P8.7 can alternately be used as outputs for LCD segment
signals.
9-2
S3C830A/P830A
I/O PORTS
PORT DATA REGISTERS
Table 9-2 gives you an overview of the register locations of all nine S3C830A I/O port data registers. Data
registers for ports 0, 1, 2, 3, 4, 5, 6, 7 and 8 have the general format shown in Figure 9-1.
Table 9-2. Port Data Register Summary
Register Name
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Port 5 data register
Port 6 data register
Port 7 data register
Port 8 data register
Mnemonic
Decimal
240
Hex
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
Location
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P0
P1
P2
P3
P4
P5
P6
P7
P8
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
Set 1, Bank 1
241
242
243
244
245
246
247
248
9-3
I/O PORTS
PORT 0
S3C830A/P830A
Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or
reading the port 0 data register, P0 at location F0H in set 1, bank 1. P0.0–P0.7 can serve inputs, as outputs
(push pull or open-drain) or you can configure the following alternative functions:
— Low-nibble pins (P0.1-P0.3): T0CLK, T0CAP, T0OUT/T0PWM
— High-nibble pins (P0.4-P0.7): T1CLK, T1OUT, T2CLK, T2OUT
Port 0 Control Register
Port 0 has two 8-bit control registers: P0CONH for P0.4–P0.7 and P0CONL for P0.0–P0.3. A reset clears the
P0CONH and P0CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to
select input or output mode (push-pull or open drain) and enable the alternative functions.
When programming the port, please remember that any alternative peripheral I/O function you configure using
the port 0 control registers must also be enabled in the associated peripheral module.
Port 0 Pull-up Resistor Enable Register (P0PUR)
Using the port 0 pull-up resistor enable register, P0PUR (E2H, set 1, bank 1), you can configure pull-up resistors
to individual port 0 pins.
Port 0 Control Register, High Byte
E0H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P0.4/T1CLK
P0.5/T1OUT
P0.6/T2CLK
P0.7/T2OUT
P0CONH bit-pair pin configuration settings
00
01
10
11
Input mode (T1CLK, T2CLK)
Output mode, open-drain
Alternative function (T1OUT, T2OUT)
Output mode, push-pull
Figure 9-1. Port 0 High-Byte Control Register (P0CONH)
9-4
S3C830A/P830A
I/O PORTS
Port 0 Control Register, Low Byte
E1H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P0.0
P0.1/T0CLK
P0.2/T0CAP
P0.3/T0OUT
/T0PWM
P0CONL bit-pair pin configuration settings
00
01
10
11
Input mode (T0CAP, T0CLK)
Output mode, open-drain
Alternative function (T0OUT, T0PWM)
Output mode, push-pull
Figure 9-2. Port 0 Low-Byte Control Register (P0CONL)
Port 0 Pull-up Control Register
E2H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P0PUR bit configuration settings:
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE:
The corresponding pull-up resistor is disabled
automatically, when a bit of port 0 is selected as
output mode.
Figure 9-3. Port 0 Pull-up Control Register (P0PUR)
9-5
I/O PORTS
S3C830A/P830A
PORT 1
Port 1 is an 8-bit I/O Port that you can use two ways:
— General-purpose I/O
— External interrupt inputs for INT0–INT7
Port 1 is accessed directly by writing or reading the port 1 data register, P1 at location F1H in set 1, bank 1.
NOTE
The port 1 inputs can be disabled by PG2CON.5–.4 when the port is selected as input mode. Refer to the
PG2CON register.
Port 1 Control Register (P1CONH, P1CONL)
Port 1 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 1:
P1CONL (low byte, E5H) and P1CONH (high byte, E4H).
When you select output mode, a push-pull circuit is automatically configured. In input mode, three different
selections are available:
— Schmitt trigger input with interrupt generation on falling edges.
— Schmitt trigger input with interrupt generation on rising edges.
— Schmitt trigger input with interrupt generation on falling/rising edges.
Port 1 Interrupt Enable and Pending Registers (P1INT, P1PND)
To process external interrupts at the port 1 pins, two additional control registers are provided: the port 1 interrupt
enable register P1INT (E6H, set 1, bank 1) and the port 1 interrupt pending register P1PND (E7H, set 1, bank 1).
The port 1 interrupt pending register P1PND lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests
by polling the P1PND register at regular intervals.
When the interrupt enable bit of any port 1 pin is “1”, a rising or falling edge at that pin will generate an interrupt
request. The corresponding P1PND bit is then automatically set to “1” and the IRQ level goes low to signal the
CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software
must the clear the pending condition by writing a “0” to the corresponding P1PND bit.
9-6
S3C830A/P830A
I/O PORTS
Port 1 Control Register, High Byte (P1CONH)
E4H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P1.7
(INT7)
P1.6
(INT6)
P1.5
(INT5)
P1.4
(INT4)
P1CONH bit-pair pin configuration
00
01
10
11
Schmitt trigger input mode, pull-up, interrupt on falling edge
Schmitt trigger input mode, interrupt on rising edge
Schmitt trigger input mode, interrupt on rising or falling edge
Output mode, push-pull
Figure 9-4. Port 1 High-Byte Control Register (P1CONH)
Port 1 Control Register, Low Byte (P1CONL)
E5H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P1.3
(INT3)
P1.2
(INT2)
P1.1
(INT1)
P1.0
(INT0)
P1CONL bit-pair pin configuration
00
01
10
11
Schmitt trigger input mode, pull-up, interrupt on falling edge
Schmitt trigger input mode, interrupt on rising edge
Schmitt trigger input mode, interrupt on rising or falling edge
Output mode, push-pull
Figure 9-5. Port 1 Low-Byte Control Register (P1CONL)
9-7
I/O PORTS
S3C830A/P830A
Port 1 Interrupt Control Register (P1INT)
E6H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
P1INT bit configuration settings:
0
1
Disable interrupt
Enable interrupt
Figure 9-6. Port 1 Interrupt Control Register (P1INT)
Port 1 Interrupt Pending Register (P1PND)
E7H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0
P1PND bit configuration settings:
0
Interrupt request is not pending,
pending bit clear when write 0
1
Interrupt request is pending
Figure 9-7. Port 1 Interrupt Pending Register (P1PND)
9-8
S3C830A/P830A
PORT 2
I/O PORTS
Port 2 is an 8-bit I/O port that can be used for general-purpose I/O as A/D converter inputs, AD0–AD3. The pins
are accessed directly by writing or reading the port 2 data register, P2 at location F2H in set 1, bank 1.
To individually configure the port 2 pins P2.0–P2.7, you make bit-pair settings in two control registers located in
set 1, bank 1: P2CONL (low byte, E9H) and P2CONH (high byte, E8H). In input mode, ADC voltage input are
also available.
Port 2 Control Registers
Two 8-bit control registers are used to configure port 2 pins: P2CONL (E9H, set 1, Bank 1) for pins P2.0–P2.3
and P2CONH (E8H, set 1, Bank 1) for pins P2.4–P2.7. Each byte contains four bit-pairs and each bit-pair
configures one port 2 pin. The P2CONH and the P2CONL registers also control the alternative functions.
Port 2 Control Register, High Byte (P2CONH)
E8H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.4
P2.5
P2.6
P2.7
P2CONH bit-pair pin configuration
00
01
10
11
Input mode
Input mode, pull-up
Not available
Output mode, push-pull
Figure 9-8. Port 2 High-Byte Control Register (P2CONH)
9-9
I/O PORTS
S3C830A/P830A
Port 2 Control Register,Low Byte (P2CONL)
E9H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.0 (AD0)
P2.1 (AD1)
P2.2 (AD2)
P2.3 (AD3)
P2CONL bit-pair pin configuration
00
01
10
11
Input mode
Input mode, pull-up
Alternative function (ADC mode)
Output mode, push-pull
Figure 9-9. Port 2 Low-Byte Control Register (P2CONL)
9-10
S3C830A/P830A
PORT 3
I/O PORTS
Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or
reading the port 3 data register, P3 at location F3H in set 1, bank 1. P3.0–P3.7 can serve as inputs or as push-
pull, open-drain outputs. You can configure the following alternative functions:
— BUZ, SCK0, SO0, SI0, SCK1, SO1, and SI1
Port 3 Control Registers
Port 3 has two 8-bit control registers: P3CONH for P3.4–P3.7 and P3CONL for P3.0–P3.3. A reset clears the
P3CONH and P3CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to
select input or output mode, enable pull-up resistors, and enable the alternative functions.
When programming this port, please remember that any alternative peripheral I/O function you configure using
the port 3 control registers must also be enabled in the associated peripheral module.
Port 3 Control Register, High Byte (P3CONH)
EAH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.7
P3.6/SI1
P3.5/SO1
P3.4/SCK1
P3CONH bit-pair pin configuration settings
00
01
10
11
Input mode (SCK1, SI1)
Output mode, open-drain
Alternative function (SCK1, SO1)
Output mode, push-pull
Figure 9-10. Port 3 High-Byte Control Register (P3CONH)
9-11
I/O PORTS
S3C830A/P830A
Port 3 Control Register, Low Byte (P3CONL)
EBH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.0/BUZ
P3.1/SCK0
P3.2/SO0
P3.3/SI0
P3CONL bit-pair pin configuration settings
Input mode (SCK0, SI0)
Output mode, open-drain
00
01
10
11
Alternative function (BUZ, SCK0, SO0)
Output mode, push-pull
Figure 9-11. Port 3 Low-Byte Control Register (P3CONL)
Port 3 Pull-up Control Register
ECH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
P3PUR bit configuration settings:
0
1
Disable pull-up resistor
Enable pull-up resistor
NOTE:
The corresponding pull-up resistor is disabled
automatically, when a bit of port 3 is selected as
output mode.
Figure 9-12. Port 3 Pull-up Control Register (P3PUR)
9-12
S3C830A/P830A
PORT 4, 5
I/O PORTS
Port 4 and 5 are 8-bit I/O ports with nibble configurable pins, respectively. Port 4 and 5 pins are accessed directly
by writing or reading the port 4 and 5 data registers, P4 at location F4H and P5 at location F5H in set 1, bank 1.
P4.0–P4.7 and P5.0–P5.7 can serve as inputs (with or without pull-ups), as output (open drain or push-pull). And
they can serve as segment pins for LCD, also.
Port Group 0 Control Register
Port 4 and 5 have a 8-bit control register: PG0CON.4–.7 for P4.0–P4.7 and PG0CON.0–.3 for P5.0–P5.7. A reset
clears the PG0CON register to “00H”, configuring all pins to input mode.
Port Group 0 Control Register
EDH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P5.4-P5.7
/SEG27-SEG24
P5.0-P5.3
/SEG31-SEG28
P4.4-P4.7
/SEG35-SEG32
P4.0-P4.3
/SEG39-SEG36
PG0CON bit-pair pin configuration settings
Input mode
00
01
10
11
Input mode, pull-up
Output mode, open-drain
Output mode, push-pull
NOTE:
The shared I/O ports with LCD segments should
be selected as one of two by LCON.3-.0.
Figure 9-13. Port Group 0 Control Register (PG0CON)
9-13
I/O PORTS
PORT 6, 7
S3C830A/P830A
Port 6 and 7 are 8-bit I/O port with nibble configurable pins, respectively. Port 6 and 7 pins are accessed directly
by writing or reading the port 6 and 7 data registers, P6 at location F6H and P7 at location F7H in set 1, bank 1.
P6.0–P6.7 and P7.0–P7.7 can serve as inputs (with or without pull-ups), as output (open drain or push-pull). And
they can serve as segment pins for LCD also.
Port Group 1 Control Register
Port 6 and 7 have a 8-bit control register: PG1CON.4–.7 for P6.0–P6.7 and PG1CON.0–.3 for P7.0–P7.7. A reset
clears the PG1CON register to “00H”, configuring all pins to input mode.
Port Group 1 Control Register
EEH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P7.4-P7.7
/SEG11-SEG8
P7.0-P7.3
/SEG15-SEG12
P6.4-P6.7
/SEG19-SEG16
P6.0-P6.3
/SEG23-SEG20
PG1CON bit-pair pin configuration settings
Input mode
00
01
10
11
Input mode, pull-up
Output mode, open-drain
Output mode, push-pull
NOTE:
The shared I/O ports with LCD segments should be
slelected as one of two by LCON.3-.0.
Figure 9-14. Port Group 1 Control Register (PG1CON)
9-14
S3C830A/P830A
PORT 8
I/O PORTS
Port 8 is an 8-bit I/O port with nibble configurable pins. Port 8 pins are accessed directly by writing or reading the
port 8 data register, P8 at location F8H in set 1, bank 1. P8.0–P8.7 can serve as inputs (with or without pull-ups),
as output (open drain or push-pull). And they can serve as segment pins for LCD also.
Port Group 2 Control Register
Port 8 has a 8-bit control register: PG2CON for P8.0–P8.7. A reset clears the PG2CON register to “00H”,
configuring all pins to input mode.
Port Group 2 Control Register
EFH, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P8.4-P8.7
/SEG3-SEG0
P8.0-P8.3
/SEG7-SEG4
Not used
P1.0-P1.3 input enable bit:
0: Enable port 1.0-1.3 input
1: Disable port 1.0-1.3 input
P1.4-P1.7 input enable bit:
0: Enable port 1.4-1.7 input
1: Disable port 1.4-1.7 input
PG2CON bit-pair pin configuration settings
Input mode
00
01
10
Input mode, pull-up
Output mode, open-drain
11
Output mode, push-pull
NOTE:
The shared I/O ports with LCD segments should be
slelected as one of two by LCON.3-.0.
Figure 9-15. Port Group 2 Control Register (PG2CON)
9-15
I/O PORTS
S3C830A/P830A
NOTES
9-16
S3C830A/P830A
BASIC TIMER and TIMER 0
10 BASIC TIMER and TIMER 0
OVERVIEW
The S3C830A has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8-bit
timer/counter is called timer 0.
BASIC TIMER (BT)
You can use the basic timer (BT) in two different ways:
— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.
— To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
The functional components of the basic timer block are:
— Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer
— 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH, read-only)
— Basic timer control register, BTCON (set 1, D3H, read/write)
10-1
BASIC TIMER and TIMER 0
S3C830A/P830A
BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer
counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,
address D3H, and is read/write addressable using Register addressing mode.
A reset clears BTCON to “00H”. This enables the watchdog function and selects a basic timer clock frequency of
fxx/4096. To disable the watchdog function, you must write the signature code “1010B” to the basic timer register
control bits BTCON.7–BTCON.4.
The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during normal operation
by writing a "1" to BTCON.1. To clear the frequency dividers for all timers input clock, you write a "1" to
BTCON.0.
Basic TImer Control Register (BTCON)
D3H, Set 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Divider clear bit for all timers:
0 = No effect
1= Clear dvider
Watchdog timer enable bits:
1010B = Disable watchdog function
Other value = Enable watchdog function
Basic timer counter clear bit:
0 = No effect
1= Clear BTCNT
Basic timer input clock selection bits:
00 = fXX/4096
01 = fXX/1024
10 = fXX/128
11 = fXX/16
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
S3C830A/P830A
BASIC TIMER and TIMER 0
BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to
any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to
“00H”, automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by
the current CLKCON register setting), divided by 4096, as the BT clock.
A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must
be cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always
broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when
stop mode has been released by an external interrupt.
In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT
value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an
internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the
stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal
operation.
In summary, the following events occur when stop mode is released:
1. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode
release and oscillation starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an internal and an
external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock
source.
3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.
4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.
10-3
BASIC TIMER and TIMER 0
S3C830A/P830A
RESET or STOP
Bit 1
Bits 3, 2
Basic Timer Control Register
(Write '1010xxxxB' to Disable)
Data Bus
fXX/4096
Clear
fXX/1024
fXX/128
fXX/16
8-Bit Up Counter
(BTCNT, Read-Only)
fXX
DIV
MUX
OVF
RESET
Start the CPU (note)
R
Bit 0
NOTE:
During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).
Figure 10-2. Basic Timer Block Diagram
10-4
S3C830A/P830A
BASIC TIMER and TIMER 0
8-BIT TIMER/COUNTER 0
Timer/counter 0 has three operating modes, one of which you select using the appropriate T0CON setting:
— Interval timer mode
— Capture input mode with a rising or falling edge trigger at the P0.2 pin
— PWM mode
Timer/counter 0 has the following functional components:
— Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer
— External clock input (P0.1, T0CLK)
— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)
— I/O pins for capture input, match output, or PWM output (P0.2/T0CAP, P0.3/T0OUT, P0.3/T0PWM)
— Timer 0 overflow interrupt (IRQ0, vector E2H) and match/capture interrupt (IRQ0, vector E0H) generation
— Timer 0 control register, T0CON (set 1, E2H, bank 0, read/write)
TIMER/COUNTER 0 CONTROL REGISTER (T0CON)
You use the timer 0 control register, T0CON, to
— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)
— Select the timer 0 input clock frequency
— Clear the timer 0 counter, T0CNT
— Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt
— Clear timer 0 match/capture interrupt pending condition
10-5
BASIC TIMER and TIMER 0
S3C830A/P830A
T0CON is located in set 1, bank 0, at address E2H, and is read/write addressable using Register addressing
mode.
A reset clears T0CON to “00H”. This sets timer 0 to normal interval timer mode, selects an input clock frequency
of fxx/1024, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal
operation by writing a "1" to T0CON.2.
The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address E2H. When a timer 0
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware
or must be cleared by software.
To enable the timer 0 match/capture interrupt (IRQ0, vector E0H), you must write T0CON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls INTPND.1. When a "1" is detected, a
timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer 0 match/capture interrupt pending bit,
INTPND.1.
Timer 0 Control Register (T0CON)
E2H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 0 input clock selection bits:
000 = fxx/1024
001 = fxx/256
Timer 0 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
010 = fxx/64
011 = fxx/8
100 = fxx
Timer 0 match/capture interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
101 = External clock
(P0.1/T0CLK) falling edge
110 = External clock
(P0.1/T0CLK) rising edge
111 = Counter stop
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Timer 0 operating mode selection bits:
00 = Interval mode (P0.3/T0OUT)
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (OVF and match
interrupt can occur)
Figure 10-3. Timer 0 Control Register (T0CON)
10-6
S3C830A/P830A
BASIC TIMER and TIMER 0
Timer 0 Interrupt Pending Register (INTPND)
E6H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Timer 0 overflow interrupt pending bit:
0 = Interrupt request is not pending,
pending bit clear when write "0".
1 = Interrupt request is pending
Timer 0 match/capture pending bit:
0 = Interrupt request is not pending,
pending bit clear when write "0".
1 = Interrupt request is pending
Figure 10-4. Timer 0 Interrupt Pending Register (INTPND)
10-7
BASIC TIMER and TIMER 0
S3C830A/P830A
TIMER 0 FUNCTION DESCRIPTION
Timer 0 Interrupts (IRQ0, Vectors E0H and E2H)
The timer 0 can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/ capture
interrupt (T0INT). T0OVF is belongs to interrupt level IRQ0, vector E2H. T0INT also belongs to interrupt level
IRQ0, but is assigned the separate vector address, E0H.
A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or
should be cleared by software in the interrupt service routine by writing a “0” to the INTPND.0 interrupt pending
bit. However, the timer 0 match/capture interrupt pending condition must be cleared by the application’s interrupt
service routine by writing a "0" to the INTPND.1 interrupt pending bit.
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
timer 0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector
E0H) and clears the counter.
If, for example, you write the value "10H" to T0DATA, the counter will increment until it reaches “10H”. At this
point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes. With each
match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-5).
Interrupt Enable/Disable
Capture Signal
T0CON.1
R (Clear)
8-Bit Up Counter
8-Bit Comparator
CLK
T0INT (IRQ0)
(Match INT)
M
U
X
INTPND.1
Pending
Match
T0OUT (P0.3)
Timer 0 Buffer Register
Timer 0 Data Register
T0CON.4-.3
Match Signal
T0CON.2
T0OVF
Figure 10-5. Simplified Timer 0 Function Diagram: Interval Timer Mode
10-8
S3C830A/P830A
BASIC TIMER and TIMER 0
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0PWM (P0.3) pin. As in interval timer mode, a match signal is generated when the counter value is identical to
the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the
counter. Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H".
Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the T0PWM (P0.3) pin is held to Low level as long as the reference
data value is less than or equal to ( £ ) the counter value and then the pulse is held to High level for as long as
the data value is greater than ( > ) the counter value. One pulse width is equal to tCLK ´ 256 (see Figure 10-6).
T0CON.0
Interrupt Enable/Disable
Capture Signal
T0CON.1
T0OVF(IRQ0)
(Overflow INT)
CLK
8-Bit Up Counter
8-Bit Comparator
INTPND.0
T0INT (IRQ0)
(Match INT)
M
U
X
Match
INTPND.1
Pending
T0PWM
Output (P0.3)
High level when
data > counter,
Lower level when
data < counter
Timer 0 Buffer Register
Timer 0 Data Register
T0CON.4-.3
Match Signal
T0CON.2
T0OVF
Figure 10-6. Simplified Timer 0 Function Diagram: PWM Mode
10-9
BASIC TIMER and TIMER 0
Capture Mode
S3C830A/P830A
In capture mode, a signal edge that is detected at the T0CAP (P0.2) pin opens a gate and loads the current
counter value into the timer 0 data register. You can select rising or falling edges to trigger this operation.
Timer 0 also gives you capture input source: the signal edge at the T0CAP (P0.2) pin. You select the capture
input by setting the values of the timer 0 capture input selection bits in the port 0 control register, P0CONL.5–.4,
(set 1, bank 1, E1H). When P0CONL.5–.4 is "00", the T0CAP input is selected.
Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated
whenever a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter
value is loaded into the timer 0 data register.
By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency,
you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 10-7).
T0CON.0
T0OVF(IRQ0)
8-Bit Up Counter
INTPND.0
CLK
(Overflow INT)
Interrupt Enable/Disable
T0CON.1
T0INT (IRQ0)
(Capture INT)
M
U
X
INTPND.1
Pending
T0CAP input
(P0.2)
Match Signal
T0CON.4-.3
T0CON.4-.3
Timer 0 Data Register
Figure 10-7. Simplified Timer 0 Function Diagram: Capture Mode
10-10
S3C830A/P830A
BASIC TIMER and TIMER 0
T0CON.0
T0CON.7-.5
T0OVF
(IRQ0)
OVF
INTPND.0
Data BUS
8
fxx/1024
fxx/256
fxx/64
fxx/8
T0CON.2
Clear
fxx/1
8-Bit Up Counter
(Read-Only)
MUX
R
T0CLK
T0CON.1
T0INT
(IRQ0)
M
U
X
8-Bit Comparator
INTPND.1
Match
M
U
X
T0OUT
T0PWM
Timer 0 Buffer Register
Timer 0 Data Register
T0CAP
T0CON.4-.3
Match signal
T0CON.2
T0OVF
T0CON.4-.3
8
Data BUS
Figure 10-8. Timer 0 Block Diagram
10-11
BASIC TIMER and TIMER 0
S3C830A/P830A
NOTES
10-12
S3C830A/P830A
8-BIT TIMER 1
11 8-BIT TIMER 1
OVERVIEW
The 8-bit timer 1 is an 8-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate
T1CON setting.
Timer 1 has the following functional components:
— Clock frequency divider (fxx divided by 256, 64, 8 or 1) with multiplexer
— External clock input (P0.4/T1CLK)
— 8-bit counter (T1CNT), 8-bit comparator, and 8-bit reference data register (T1DATA)
— Timer 1 interrupt (IRQ1, vector E6H) generation
— Timer 1 control register, T1CON (set 1, Bank 0, E5H, read/write)
FUNCTION DESCRIPTION
Interval Timer Function
The timer 1 can generate an interrupt, the timer 1 match interrupt (T1INT). T1INT belongs to interrupt level
IRQ1, and is assigned the separate vector address, E6H.
The T1INT pending condition should be cleared by software when it has been serviced. Even though T1INT is
disabled, the application’s service routine can detect a pending condition of T1INT by the software and execute
it’s sub-routine. When this case is used, the T1INT pending bit must be cleared by the application subroutine by
writing a “0” to the T1CON.0 pending bit.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to
the Timer 1 reference data registers, T1DATA. The match signal generates a timer 1 match interrupt (T1INT,
vector E6H) and clears the counter.
If, for example, you write the value 10H to T1DATA and 0EH to T1CON, the counter will increment until it
reaches 10H. At this point, the Timer 1 interrupt request is generated, the counter value is reset, and counting
resumes.
11-1
8-BIT TIMER 1
S3C830A/P830A
TIMER 1 CONTROL REGISTER (T1CON)
You use the timer 1 control register, T1CON, to
— Enable the timer 1 operating (interval timer)
— Select the timer 1 input clock frequency
— Clear the timer 1 counter, T1CNT
— Enable the timer 1 interrupt and clear timer 1 interrupt pending condition
T1CON is located in set 1, bank 0, at address E5H, and is read/write addressable using register addressing
mode.
A reset clears T1CON to "00H". This sets timer 1 to disable interval timer mode, and disables timer 1 interrupt.
You can clear the timer 1 counter at any time during normal operation by writing a “1” to T1CON.3
To enable the timer 1 interrupt (IRQ1, vector E6H), you must write T1CON.2, and T1CON.1 to "1". To detect an
interrupt pending condition when T1INT is disabled, the application program polls pending bit, T1CON.0. When a
"1" is detected, a timer 1 interrupt is pending. When the T1INT sub-routine has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, T1CON.0.
Timer 1 Control Register
E5H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 1 input clock selection bits:
000 = fxx/256
Timer 1 interrupt pending bit:
0 = No interrupt pending
001 = fxx/64
010 = fxx/8
0 = Clear pending bit (when write)
1 = Interrupt is pending
011 = fxx
111= External clock (T1CLK) input
Timer 1 interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Not used
Timer 1 count enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer 1 counter clear bit:
0 = No affect
1 = Clear the timer 1 counter
(when write)
Figure 11-1. Timer 1 Control Register (T1CON)
11-2
S3C830A/P830A
8-BIT TIMER 1
BLOCK DIAGRAM
Bits 7, 6, 5
Data Bus
8
Bit 3
T1CLK
(P0.4)
fxx/256
M
U
X
8-bit up-Counter
(Read Only)
R
fxx/64
fxx/8
fxx/1
Clear
Pending
Bit 0
T1INT
IRQ1
8-bit Comparator
Match
Bit 2
Timer 1 Buffer Register
Bit 1
Counter clear signal (T1CON.3) only
Timer 1 Data Register
(Read/Write)
8
Data Bus
NOTE:
To be loaded T1DATA value to buffer register for comparing, T1CON.3 bit must be set 1.
Figure 11-2. Timer 1 Functional Block Diagram
11-3
8-BIT TIMER 1
S3C830A/P830A
NOTES
11-4
S3C830A/P830A
16-BIT TIMER 2
12 16-BIT TIMER 2
OVERVIEW
The 16-bit timer 2 is an 16-bit general-purpose timer. Timer 2 has the interval timer mode by using the
appropriate T2CON setting.
Timer 2 has the following functional components:
— Clock frequency divider (fxx divided by 256, 64, 8 or 1) with multiplexer
— External clock input (T2CLK)
— 16-bit counter (T2CNTH/L), 16-bit comparator, and 16-bit reference data register (T2DATAH/L)
— Timer 2 interrupt (IRQ1, vector E4H) generation
— Timer 2 control register, T2CON (set 1, Bank 1, FEH, read/write)
FUNCTION DESCRIPTION
Interval Timer Function
The timer 2 can generate an interrupt, the timer 2 match interrupt (T2INT). T2INT belongs to interrupt level
IRQ1, and is assigned the separate vector address, E4H.
The T2INT pending condition should be cleared by software when it has been serviced. Even though T2INT is
disabled, the application’s service routine can detect a pending condition of T2INT by the software and execute
it’s sub-routine. When this case is used, the T2INT pending bit must be cleared by the application subroutine by
writing a “0” to the T2CON.0 pending bit.
In interval timer mode, a match signal is generated when the counter value is identical to the values written to
the Timer 2 reference data registers, T2DATA. The match signal generates a timer 2 match interrupt (T2INT,
vector E4H) and clears the counter.
If, for example, you write the value 0010H to T2DATAH/L and 0EH to T2CON, the counter will increment until it
reaches 10H. At this point, the Timer 2 interrupt request is generated, the counter value is reset, and counting
resumes.
12-1
16-BIT TIMER 2
S3C830A/P830A
TIMER 2 CONTROL REGISTER (T2CON)
You use the timer 2 control register, T2CON, to
— Enable the timer 2 operating (interval timer)
— Select the timer 2 input clock frequency
— Clear the timer 2 counter, T2CNTH/L
— Enable the timer 2 interrupt and clear timer 2 interrupt pending condition
T2CON is located in set 1, bank 1, at address FEH, and is read/write addressable using register addressing
mode.
A reset clears T2CON to "00H". This sets timer 2 to disable interval timer mode, and disables timer 2 interrupt.
You can clear the timer 2 counter at any time during normal operation by writing a “1” to T2CON.3
To enable the timer 2 interrupt (IRQ1, vector E4H), you must write T2CON.2, and T2CON.1 to "1". To detect an
interrupt pending condition when T2INT is disabled, the application program polls pending bit, T2CON.0. When a
"1" is detected, a timer 2 interrupt is pending. When the T2INT sub-routine has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer 2 interrupt pending bit, T2CON.0.
Timer 2 Control Registers
FEH, Set 1, Bank 1
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 0 input clock selection bits:
000 = fxx/256
Timer 2 interrupt pending bit:
0 = No interrupt pending
001 = fxx/64
010 = fxx/8
0 = Clear pending bit (when write)
1 = Interrupt is pending
011 = fxx
111 = External clock (T2CLK) input
Timer 2 interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Not used
Timer 2 count enable bit:
0 = Disable counting operation
1 = Enable counting operation
Timer 2 counter clear bit:
0 = No affect
1 = Clear the timer 2 counter (when write)
Figure 12-1. Timer 2 Control Register (T2CON)
12-2
S3C830A/P830A
16-BIT TIMER 2
BLOCK DIAGRAM
Bits 7, 6, 5
Data Bus
8
Bit 3
T2CLK
(P0.6)
fxx/256
M
U
X
16-bit up-Counter
(Read Only)
R
fxx/64
fxx/8
fxx/1
Clear
Pending
Bit 0
T2INT
IRQ1
16-bit Comparator
Match
Bit 2
Timer 2 Buffer Register
Bit 1
Counter clear signal (T2CON.3)
Timer 2 Data Register
(Read/Write)
8
Data Bus
NOTE:
To be loaded T2DATAH/L value to buffer register for comparing, T2CON.3 bit must be set 1.
Figure 12-2. Timer 2 Functional Block Diagram
12-3
16-BIT TIMER 2
S3C830A/P830A
NOTES
12-4
S3C830A/P830A
WATCH TIMER
13 WATCH TIMER
OVERVIEW
Watch timer functions include real-time and watch-time measurement and interval timing for the system clock.
To start watch timer operation, set bit 6 of the watch timer control register, WTCON.6 to "1".
And if you want to service watch timer overflow interrupt (IRQ3, vector F2H), then set the WTCON.1 to “1”.
The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application’s
interrupt service routine by means of writing a "0" to the WTCON.0 interrupt pending bit.
After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically
set to "1", and interrupt requests commence in 50 ms, 0.5 and 1-second intervals by setting Watch timer speed
selection bits (WTCON.3 – .2).
The watch timer can generate a steady 1 kHz, 1.5 kHz, 3 kHz, or 6 kHz signal to BUZ output pin for Buzzer. By
setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an
interrupt every 50 ms. High-speed mode is useful for timing events for program debugging sequences.
The watch timer supplies the clock frequency for the LCD controller (fLCD). Therefore, if the watch timer is
disabled, the LCD controller does not operate.
Watch timer has the following functional components:
— Real Time and Watch-Time Measurement
— Using a Main System Clock Source only
— Clock Source Generation for LCD Controller (fLCD
)
— I/O pin for Buzzer Output Frequency Generator (P3.0, BUZ)
— Timing Tests in High-Speed Mode
— Watch timer overflow interrupt (IRQ3, vector F2H) generation
— Watch timer control register, WTCON (set 1, bank 0, E8H, read/write)
13-1
WATCH TIMER
S3C830A/P830A
WATCH TIMER CONTROL REGISTER (WTCON)
The watch timer control register, WTCON is used to select the watch timer interrupt time and Buzzer signal, to
enable or disable the watch timer function. It is located in set 1, bank 0 at address E8H, and is read/write
addressable using register addressing mode.
A reset clears WTCON to "00H". This disable the watch timer.
So, if you want to use the watch timer, you must write appropriate value to WTCON.
Watch Timer Control Register (WTCON)
E8H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Watch timer interrupt pending bit:
0 = Interrupt request is not pending
(Clear pending bit when write"0")
1 = Interrupt request is pending
Not used
Watch timer Enable/Disable bit:
0 = Disable watch timer
1 = Enable watch timer
Watch timer INT Enable/Disable bit:
0 = Disable watch timer INT
1 = Enable watch timer INT
Buzzer signal selection bits:
00 = 1 kHz
01 = 1.5 kHz
10 = 3 kHz
11 = 6 kHz
Watch timer speed selection bits:
00 = Set watch timer interrupt to 1 s
01 = Set watch timer interrupt to 0.5 s
11 = Set watch timer interrupt to 50 ms
Figure 13-1. Watch Timer Control Register (WTCON)
13-2
S3C830A/P830A
WATCH TIMER
WATCH TIMER CIRCUIT DIAGRAM
BUZZER Output
WTCON.1
WTCON.5
WTCON.4
WTCON.3
WTCON.2
MUX
WTINT
1 kHz
1.5 kHz
3 kHz
6 kHz
Selector
Circuit
WTCON.0
Enable/Disable
WTCON.6
1 sec
0.5 sec
50 msec
Frequency
Dividing
Circuit
Frequency
Divider
fW
32.768 kHz
fLCD (500 Hz)
fXX = Main system clock (4.5 MHz)
fW = Watch timer clock
fxx
Figure 13-2. Watch Timer Circuit Diagram
13-3
WATCH TIMER
S3C830A/P830A
NOTES
13-4
S3C830A/P830A
LCD CONTROLLER/DRIVER
14 LCD CONTROLLER/DRIVER
OVERVIEW
The S3C830A microcontroller can directly drive an up-to-20-digit (40-segment) LCD panel. The LCD block has
the following components:
— LCD controller/driver
— Display RAM (00H–13H) for storing display data in page 7
— 40 segment output pins (SEG0–SEG39)
— Four common output pins (COM0–COM3)
— Three LCD operating power supply pins (V
V
) and bias pin for LCD driving voltage (V
)
LCD
LC0– LC2
— LCD voltage dividing resistors
Bit settings in the LCD mode register, LMOD, determine the LCD frame frequency, duty and bias, and LCD
voltage dividing resistors.
The LCD control register LCON turns the LCD display on and off and switches current to the LCD voltage
dividing resistors for the display. LCD data stored in the display RAM locations are transferred to the segment
signal pins automatically without program control.
Bias
1
VLC0-VLC2
LCD
3
Controller/
Driver
8
COM0-COM3
SEG0-SEG39
4
40
Figure 14-1. LCD Function Diagram
14-1
LCD CONTROLLER/DRIVER
LCD CIRCUIT DIAGRAM
S3C830A/P830A
13H.7
8
8
13H.6
13H.5
13H.4
SEG39/P4.0
MUX
MUX
MUX
SEG38/P4.1
SEG37/P4.2
SEG36/P4.3
SEG35/P4.4
SEG34/P4.5
05H.1
05H.0
04H.7
04H.6
Segment
Driver
SEG16/P6.7
SEG15/P7.0
SEG14/P7.1
SEG13/P7.2
SEG12/P7.3
SEG11/P7.4
00H.3
00H.2
00H.1
00H.0
8
8
8
SEG0/P8.7
fLCD
COM3
COM2
COM1
COM0
Timing
Controller
COM
Control
LMOD
LCON
VLC0
VLC1
VLC2
Bias
LCD
Voltage
Control
NOTES:
1. fLCD = 500Hz, 250Hz, 125Hz, and 62.5Hz
2. The LCD display registers are in the page 7.
Figure 14-2. LCD Circuit Diagram
14-2
S3C830A/P830A
LCD CONTROLLER/DRIVER
LCD RAM ADDRESS AREA
RAM addresses 00H–13H of page 7 are used as LCD data memory. When the bit value of a display segment is
"1", the LCD display is turned on; when the bit value is "0", the display is turned off.
Display RAM data are sent out through segment pins SEG0–SEG39 using a direct memory access (DMA)
method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display
can be allocated to general-purpose use.
SEG39
713H
70FH
70BH
707H
712H
70EH
70AH
706H
711H
70DH
709H
705H
710H
70CH
708H
704H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
703H
702H
701H
700H
COM3
COM2
COM1
COM0
Figure 14-3. LCD Display Data RAM Organization
14-3
LCD CONTROLLER/DRIVER
S3C830A/P830A
LCD CONTROL REGISTER (LCON), F1H at BANK 0 of SET 1
Table 14-1. LCD Control Register (LCON) Organization
LCON Bit
Setting
Description
LCON.7
0
1
LCD output is low and the current for dividing the resistors is cut off.
If LMOD.3 = “0”, LCD display is turned off. (All LCD segments are off signal output.)
If LMOD.3 = “1”, output COM and SEG signals in display mode.
LCON.6–.4 Not used for the S3C830A.
LCON.3–.0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Select LCD SEG0–39.
Select LCD SEG0–35/P4.0–4.3 as I/O port.
Select LCD SEG0–31/P4 as I/O port.
Select LCD SEG0–27/P4, P5.0–P5.3 as I/O port.
Select LCD SEG0–23/P4, P5 as I/O port.
Select LCD SEG0–19/P4, P5, P6.0–P6.3 as I/O port.
Select LCD SEG0–15/P4, P5, P6 as I/O port.
Select LCD SEG0–11/P4, P5, P6, P7.0–P7.3 as I/O port.
Select LCD SEG0–7/P4, P5, P6, P7 as I/O port.
Select LCD SEG0–3/P4, P5, P6, P7, P8.0–P8.3 as I/O port.
All I/O port (P4–P8)
14-4
S3C830A/P830A
LCD CONTROLLER/DRIVER
LCD MODE REGISTER (LMOD)
The LCD mode control register LMOD is mapped to RAM address F2H at bank 0 of set 1.
LMOD controls these LCD functions:
— Duty and bias selection (LMOD.3–LMOD.0)
— LCDCK clock frequency selection (LMOD.5–LMOD.4)
— LCD voltage dividing resistors selection (LMOD.6)
— LCD common signal enable or disable selection (LMOD.7)
The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output. This
is also referred to as the 'frame frequency.' Since LCDCK is generated by dividing the watch timer clock (fw), the
watch timer must be enabled when the LCD display is turned on. RESET clears the LMOD register values to
logic zero. This produces the following LCD control settings:
— Display is turned off
— LCDCK frequency is 62.5 Hz (at fx = 4.5 MHz) from the watch timer clock.
The LCD display can continue to operate during idle mode.
Table 14-2. LCD Clock Signal (LCDCK) Frame Frequency
LCDCK Frequency
62.5 Hz
Static
62.5 Hz
125 Hz
250 Hz
500 Hz
1/2 Duty
31.3 Hz
62.5 Hz
125 Hz
250 Hz
1/3 Duty
20.8 Hz
41.7 Hz
83.3 Hz
166.7 Hz
1/4 Duty
15.6 Hz
31.3 Hz
62.5 Hz
125 Hz
125 Hz
250 Hz
500 Hz
NOTE: fx = 4.5 MHz
14-5
LCD CONTROLLER/DRIVER
S3C830A/P830A
Table 14-3. LCD Mode Control Register (LMOD) Organization, F2H at Bank 0 of Set 1
LMOD.7
COM Signal Enable/Disable Bit
0
1
Enable COM signal
Disable COM signal
LMOD.6
LCD Voltage Dividing Resistors Control Bit
0
1
Internal voltage dividing resistors
External voltage dividing resistors; Internal voltage dividing resistors are off.
LMOD.5
LMOD.4
LCD Clock (LCDCK) Frequency
0
0
1
1
0
1
0
1
62.5 Hz at fx = 4.5 MHz
125 Hz at fx = 4.5 MHz
250 Hz at fx = 4.5 MHz
500 Hz at fx = 4.5 MHz
LMOD.3
LMOD.2
LMOD.1
LMOD.0
Duty and Bias Selection for LCD Display
0
1
1
1
1
1
x
0
0
0
0
1
x
0
0
1
1
0
x
0
1
1
0
0
LCD display off (LCD off signal output)
1/4 duty, 1/3 bias
1/3 duty, 1/3 bias
1/3 duty, 1/2 bias
1/2 duty, 1/2 bias
Static
Table 14-4. Maximum Number of Display Digits per Duty Cycle
LCD Duty
LCD Bias
Static
1/2
COM Output Pins
COM0
Maximum Seg Display
Static
1/2
40
COM0–COM1
COM0–COM2
COM0–COM2
COM0–COM3
40 x 2
40 x 3
40 x 3
40 x 4
1/3
1/2
1/3
1/3
1/4
1/3
14-6
S3C830A/P830A
LCD CONTROLLER/DRIVER
LCD DRIVE VOLTAGE
The LCD display is turned on only when the voltage difference between the common and segment signals is
greater than VLCD. The LCD display is turned off when the difference between the common and segment signal
voltages is less than VLCD. The turn-on voltage, + VLCD or - VLCD, is generated only when both signals are the
selected signals of the bias. Table 14-5 shows LCD drive voltages for static mode, 1/2 bias, and 1/3 bias.
Table 14-5. LCD Drive Voltage Values
LCD Power Supply
Static Mode
1/2 Bias
1/3 Bias
VLC0
VLCD
VLCD
VLCD
VLC1
VLC2
Vss
1/2 VLCD
1/2 VLCD
0 V
2/3 VLCD
1/3 VLCD
0 V
–
–
0 V
NOTE: The LCD panel display may deteriorate if a DC voltage is applied that lies between the common and segment signal
voltage. Therefore, always drive the LCD panel with AC voltage.
LCD COM/SEG SIGNALS
The 40 LCD segment signal pins are connected to corresponding display RAM locations at 00H–13H at page 7.
The corresponding bits of the display RAM are synchronized with the common signal output pins COM0, COM1,
COM2, and COM3.
When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin.
When the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin. Each bias has select
and no-select signals.
Select
Non-Select
FR
1 Frame
VLC0
VSS
COM
VLC0
VSS
SEG
VLC0
VSS
COM-SEG
-VLC0
Figure 14-4. Select/No-Select Bias Signals in Static Display Mode
14-7
LCD CONTROLLER/DRIVER
S3C830A/P830A
Select
Non-Select
FR
1 Frame
VLC0
VLC1,2
Vss
COM
SEG
VLC0
VLC1,2
Vss
VLC0
VLC1,2
Vss
COM-SEG
-VLC1,2
-VLC0
Figure 14-5. Select/No-Select Bias Signals in 1/2 Duty, 1/2 Bias Display Mode
Select
Non-Select
FR
1 Frame
VLC0
VSS
COM
VLC0
VSS
SEG
VLC0
VSS
COM-SEG
-VLC0
Figure 14-6. Select/No-Select Bias Signals in 1/3 Duty, 1/3 Bias Display Mode
14-8
S3C830A/P830A
LCD CONTROLLER/DRIVER
Static and 1/3 Bias (VLCD = 3 V at VDD = 5 V)
1/2 Bias (VLCD = 2.5 V at VDD = 5 V)
VDD
VDD
LCON.7
LCON.7
Bias Pin
Bias Pin
2R
R
2R
R
VLC0
VLC0
VLC1
VLC2
VLC1
VLC2
VLCD = 3 V
R
VLCD = 2.5 V
R
R
R
U
VSS
VSS
Voltage Dividing Resistors Adjustment
Static and 1/3 Bias (VLCD = 5 V at VDD = 5 V)
VDD
VDD
LCON.7
LCON.7
Bias Pin
Bias Pin
2R
R''
2R
R
VLC0
VLC0
VLC1
VLC2
R
R'
R'
R'
VLC1
VLCD
R
R
VLCD = 5 V
R
VLC2
R
VSS
VSS
3 R' ´ VDD
R'' + 3R'
VLCD =
, when LMOD.6 = "1"
NOTES:
1. R = Internal voltage dividing resistors. These resistors can be disconnected by LMOD.6.
2. R' = External Resistors
3. R'' = External Resistor to adjust VLCD.
Figure 14-7. Voltage Dividing Resistor Circuit Diagram
14-9
LCD CONTROLLER/DRIVER
S3C830A/P830A
NOTES
14-10
S3C830A/P830A
A/D CONVERTER
15 8-BIT ANALOG-TO-DIGITAL CONVERTER
OVERVIEW
The 8-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at
one of the four input channels to equivalent 8-bit digital values. The analog input level must lie between the
AVDD and VSS values. The A/D converter has the following components:
— Analog comparator with successive approximation logic
— D/A converter logic (resistor string type)
— ADC control register (ADCON)
— Four multiplexed analog data input pins (AD0–AD3)
— 8-bit A/D conversion data output register (ADDATA)
— 8-bit digital input port (Alternately, I/O port.)
— AVDD pin is internally connected to VDD
.
FUNCTION DESCRIPTION
To initiate an analog-to-digital conversion procedure, at first you must set with alternative function for ADC input
enable at port 2, the pin set with alternative function can be used for ADC analog input. And you write the
channel selection data in the A/D converter control register ADCON.4–.5 to select one of the four analog input
pins (AD0–3) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located in
set 1, bank 0, at address EFH. The pins witch are not used for ADC can be used for normal I/O.
During a normal conversion, ADC logic initially sets the successive approximation register to 80H (the
approximate half-way point of an 8-bit register). This register is then updated automatically during each
conversion step. The successive approximation block performs 8-bit conversions for one input channel at a time.
You can dynamically select different channels by manipulating the channel selection bit value (ADCON.5–4) in
the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion
is completed, ADCON.3, the end-of-conversion(EOC) bit is automatically set to 1 and the result is dumped into
the ADDATA register where it can be read. The A/D converter then enters an idle state. Remember to read the
contents of ADDATA before another conversion starts. Otherwise, the previous result will be overwritten by the
next conversion result.
NOTE
Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog
level at the AD0–AD3 input pins during a conversion procedure be kept to an absolute minimum. Any change in
the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in
conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after
ADC operation is finished.
15-1
A/D CONVERTER
S3C830A/P830A
CONVERSION TIMING
The A/D conversion process requires 5 steps (5 clock edges) to convert each bit and 10 clocks to set-up A/D
conversion. Therefore, total of 50 clocks are required to complete an 8-bit conversion: When fxx/8 is selected
for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion
requires 5 clocks, the conversion rate is calculated as follows:
5 clocks/bit ´ 8 bits + set-up time = 50 clocks, 50 clock ´ 1.78 us = 89 us at 0.56 MHz (4.5 MHz/8)
Note that A/D converter needs at least 25ms for conversion time.
A/D CONVERTER CONTROL REGISTER (ADCON)
The A/D converter control register, ADCON, is located at address EFH in set 1, bank 0. It has three functions:
— Analog input pin selection (bits 4 and 5)
— End-of-conversion status detection (bit 3)
— ADC clock selection (bits 2 and 1)
— A/D operation start or enable (bit 0 )
After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog
input pins (AD0–AD3) can be selected dynamically by manipulating the ADCON.4–5 bits. And the pins not used
for analog input can be used for normal I/O function.
A/D Converter Control Register (ADCON)
EFH, Set 1, Bank 0, R/W (EOC bit is read-only)
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Always logic zero
Start or enable bit:
0 = Disable operation
1 = Start operation
A/D input pin selection bits:
A/D input pin
.5 .4
Clock Selection bits:
.2.1
Conversion CLK
00 fXX/16
0 0
0 1
1 0
1 1
AD0
AD1
AD2
AD3
01 fXX/8
10 fXX/4
11 fXX/1
End-of-conversion bit:
0 = Not complete Conversion
1 = complete Conversion
Figure 15-1. A/D Converter Control Register (ADCON)
15-2
S3C830A/P830A
A/D CONVERTER
Conversion Data Register ADDATA
F0H, Set 1, Bank 0, Read Only
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Figure 15-2. A/D Converter Data Register (ADDATA)
INTERNAL REFERENCE VOLTAGE LEVELS
In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input
level must remain within the range VSS to AVDD (The AVDD pin is internally connected with VDD).
Different reference voltage levels are generated internally along the resistor tree during the analog conversion
process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AVDD
.
BLOCK DIAGRAM
ADCON.2-.1
ADCON.4-5
(Select one input pin of the assigned pins)
To ADCON.3
(EOC Flag)
Clock
Selector
ADCON.0
(AD/C Enable)
M
U
X
Analog
Comparator
Successive
Approximation
Logic & Register
-
Input Pins
AD0-AD3
(P2.0-P2.3)
.
.
.
+
ADCON.0
Upper 8-bit is loaded to
A/D Conversion
(AD/C Enable)
Data Register
P2CONL
(Assign Pins to ADC Input)
Conversion
Result (ADDATA
F0H, Set 1, Bank 0)
AVDD
8-bit D/A
Converter
VSS
Figure 15-3. A/D Converter Functional Block Diagram
15-3
A/D CONVERTER
S3C830A/P830A
VDD
Reference
Voltage Input
AVDD
+
-
C
10 mF
103
(It is the same voltage
with VDD only.)
VDD
Analog
Input Pin
AD0-AD3
S3C830A
C
101
VSS
Figure 15-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
15-4
S3C830A/P830A
SERIAL I/O INTERFACE
16 SERIAL I/O INTERFACE
OVERVIEW
Serial I/O modules, SIO0 and SIO1 can interface with various types of external device that require serial data
transfer. The components of SIO0 and SIO1 function block are:
— 8-bit control register (SIO0CON, SIO1CON)
— Clock selector logic
— 8-bit data buffer (SIO0DATA, SIO1DATA)
— 8-bit prescaler (SIO0PS, SIO1PS)
— 3-bit serial clock counter
— Serial data I/O pins (SI0, SO0, SI1, SO1)
— External clock input/output pins (SCK0, SCK1)
The SIO modules can transmit or receive 8-bit serial data at a frequency determined by its corresponding control
register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.
PROGRAMMING PROCEDURE
To program the SIO modules, follow these basic steps:
1. Configure the I/O pins at port (SCK0/SI0/SO0, SCK1/SI1/SO1) by loading the appropriate value to the
P3CONH and P3CONL register if necessary.
2. Load an 8-bit value to the SIO0CON and SIO1CON control registers to properly configure the serial I/O
modules. In this operation, SIO0CON.2 and SIO1CON.2 must be set to "1" to enable the data shifters,
respectively.
3. For interrupt generation, set the serial I/O interrupt enable bits (SIO0CON.1, SIO1CON.1) to "1",
respectively.
4. When you transmit data to the serial buffer, write data to SIO0DATA or SIO1DATA and set SIO0CON.3 or
SIO1CON.3 to 1, the shift operation starts.
5. When the shift operation (transmit/receive) is completed, the SIO0 and SIO1 pending bits (SIO0CON.0 and
SIO1CON.0) are set to "1" and SIO interrupt requests are generated, respectively.
16-1
SERIAL I/O INTERFACE
S3C830A/P830A
SIO0 AND SIO1 CONTROL REGISTERS (SIO0CON, SIO1CON)
The control registers for serial I/O interface modules, SIO0CON, is located at E9H and SIO1CON, is located at
ECH in set 1, bank 0. They have the control settings for SIO modules, respectively.
— Clock source selection (internal or external) for shift clock
— Interrupt enable
— Edge selection for shift operation
— Clear 3-bit counter and start shift operation
— Shift operation (transmit) enable
— Mode selection (transmit/receive or receive-only)
— Data direction selection (MSB first or LSB first)
A reset clears the SIO0CON and SIO1CON values to "00H". This configures the corresponding modules with an
internal clock source at the SCK0 and SCK1, selects receive-only operating mode, and clears the 3-bit counter,
respectively. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first.
Serial I/O Module Control Register (SIO0CON)
E9H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
SIO0 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending condition
(when write)
SIO0 shift clock selection bit:
0 = Internal clock (P.S Clock)
1 = External clock (SCK0)
1 = Interrupt is pending
Data direction control bit:
0 = MSB-first mode
1 = LSB-first mode
SIO0 interrupt enable bit:
0 = Disable SIO0 interrupt
1 = Enable SIO0 interrupt
SIO0 mode selection bit:
0 = Receive only mode
1 = Transmit/receive mode
SIO0 shift operation enable bit:
0 = Disable shifter and clock counter
1 = Enable shifter and clock counter
Shift clock edge selection bit:
0 = tX at falling edeges, rx at rising edges.
1 = tX at rising edeges, rx at falling edges.
SIO0 counter clear and shift start bit:
0 = No action
1 = Clear 3-bit counter and start shifting
Figure 16-1. Serial I/O Module Control Register (SIO0CON)
16-2
S3C830A/P830A
SERIAL I/O INTERFACE
Serial I/O Module Control Register (SIO1CON)
ECH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
SIO1 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending condition
(when write)
SIO1 shift clock selection bit:
0 = Internal clock (P.S Clock)
1 = External clock (SCK1)
1 = Interrupt is pending
Data direction control bit:
0 = MSB-first mode
1 = LSB-first mode
SIO1 interrupt enable bit:
0 = Disable SIO0 interrupt
1 = Enable SIO0 interrupt
SIO1 mode selection bit:
0 = Receive only mode
1 = Transmit/receive mode
SIO1 shift operation enable bit:
0 = Disable shifter and clock counter
1 = Enable shifter and clock counter
Shift clock edge selection bit:
0 = tX at falling edeges, rx at rising edges.
1 = tX at rising edeges, rx at falling edges.
SIO1 counter clear and shift start bit:
0 = No action
1 = Clear 3-bit counter and start shifting
Figure 16-2. Serial I/O Module Control Register (SIO1CON)
16-3
SERIAL I/O INTERFACE
S3C830A/P830A
SIO0 AND SIO1 PRE-SCALER REGISTER (SIO0PS, SIO1PS)
The prescaler registers for serial I/O interface modules, SIO0PS and SIO1PS, are located at EBH and EEH in
set 1, bank 0, respectively.
The values stored in the SIO0 and SIO1 pre-scale registers, SIO0PS and SIO1PS, lets you determine the SIO0
and SIO1 clock rate (baud rate) as follows, respectively:
Baud rate = Input clock (fxx/4)/(Pre-scaler value + 1), or SCK0 and SCK1 input clock.
SIO0 Pre-scaler Register (SIO0PS)
EBH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Baud rate = (fXX/4)/(SIO0PS + 1)
Figure 16-3. SIO0 Pre-scaler Register (SIO0PS)
SIO1 Pre-scaler Register (SIO1PS)
EEH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Baud rate = (fXX/4)/(SIO1PS + 1)
Figure 16-4. SIO1 Pre-scaler Register (SIO1PS)
16-4
S3C830A/P830A
SERIAL I/O INTERFACE
SIO0 BLOCK DIAGRAM
SIO0 INT
IRQ2
3-Bit Counter
Clear
SIO0CON.0
Pending
CLK
SIO0CON.1
(Interrupt Enable)
SIO0CON.3
SIO0CON.7
SIO0CON.4
SIO0CON.2
(Edge Select)
(Shift Enable)
SIO0CON.5
M
U
X
SCK0
(Mode Select)
SIO0PS (EBH, bank 0)
CLK
8-Bit SIO0 Shift Buffer
SO0
(SIO0DATA, EAH, bank 0)
fxx/2
8-bit P.S.
1/2
SIO0CON.6
(LSB/MSB First
Mode Select)
8
SI0
Data Bus
Figure 16-5. SIO0 Functional Block Diagram
SIO1 INT
3-Bit Counter
SIO1CON.0
Pending
IRQ2
Clear
CLK
SIO1CON.1
(Interrupt Enable)
SIO1CON.3
SIO1CON.7
SIO1CON.4
SIO1CON.2
(Edge Select)
(Shift Enable)
SIO1CON.5
M
U
X
SCK1
fxx/2
(Mode Select)
SIO1PS (EEH, bank 0)
8-bit P.S. 1/2
CLK
8-Bit SIO1 Shift Buffer
SO1
(SIO1DATA, EDH, bank 0)
SIO1CON.6
(LSB/MSB First
Mode Select)
8
SI1
Data Bus
Figure 16-6. SIO1 Functional Block Diagram
16-5
SERIAL I/O INTERFACE
S3C830A/P830A
SERIAL I/O TIMING DIAGRAM (SIO0, SIO1)
SCK0/SCK1
SI0/SI1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0/SO1
IRQ2
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
Set SIO0CON.3 or SIO1CON.3
Figure 16-7. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIO0CON.4 or SIO1CON.4 = 0)
SCK0/SCK1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SI0/SI1
SO0/SO1
IRQ2
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transmit
Complete
Set SIO0CON.3 or SIO1CON.3
Figure 16-8. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIO0CON.4 or SIO1CON.4 = 1)
16-6
S3C830A/P830A
LOW VOLTAGE RESET
17 LOW VOLTAGE RESET
OVERVIEW
The low voltage reset block is useful for an system reset under the specific voltage of system. The components
of LVR block are:
— LVREN pin
— Reference voltage generator
— Voltage divider
— Comparator
— Glitch filter
LVREN PIN
A LVREN pin is used to enable or disable LVR function.
The LVR function is disabled when the LVREN pin is connected to VSS and is enabled when the LVREN pin is
connected to VDD
.
BLOCK DIAGRAM
Reference
Voltage
Start Up
Generator
Comparator
Glitch Filter
RESET
Voltage
Divider
Figure 17-1. Low Voltage Reset Block Diagram
17-1
LOW VOLTAGE RESET
S3C830A/P830A
NOTES
17-2
S3C830A/P830A
PLL FREQUENCY SYNTHESIZER
18 PLL FREQUENCY SYNTHESIZER
OVERVIEW
The phase locked loop (PLL) frequency synthesizer locks medium frequency (MF), high frequency (HF), and very
high frequency (VHF) signals to a fixed frequency using a phase difference comparison system. As shown in
Figure 18-1, the PLL frequency synthesizer consists of an input selection circuit, programmable divider, phase
detector, reference frequency generator, and a charge pump.
PLLMOD
PLLD (16-bit)
2
NF
1
4
12
PLLMOD.6-.7
Input
Circuit
Swallow
Counter
Prescaler
VCOFM
PLLMOD.7
Programmable
Counter
Input
Circuit
Phase
Comparator
Charge
Pump
Selector
VCOAM
EO0, EO1
PLLMOD.6
Reference Frequency
Generator
Unlock
Detector
PLLREF
ULFG
Figure 18-1. Block Diagram of the PLL Frequency Synthesizer
18-1
PLL FREQUENCY SYNTHESIZER
S3C830A/P830A
PLL FREQUENCY SYNTHESIZER FUNCTION
The PLL frequency synthesizer divides the signal frequency at the VCOAM or VCOFM pin using the programmable
divider. It then outputs the phase difference between the divided frequency and reference frequency at the EO0
and EO1 pin.
NOTE
The PLL frequency synthesizer operates only when the CE pin is High level. When the CE pin is Low
level, the synthesizer is disable.
Input Selection Circuit
The input selection circuit consists of the VCOAM pin and VCOFM pins, an FM/AM selector, and two amplifiers. The
input selection circuit selects the frequency division method and the input pin of the PLL frequency.
You can choose one of two frequency division methods using the PLL mode register: 1) direct frequency division
method, or 2) pulse swallow method. The PLL mode register is also used to select the VCOAM or VCOFM pin as
the frequency input pin.
Programmable Divider
The programmable divider divides the frequency of the signal from the VCOAM and VCOFM pins in accordance
with the values contained in the swallow counter and programmable counter. The programmable divider consists
of prescalers, a swallow counter, and a programmable counter.
When the PLL operation starts, the contents of the PLL data registers (PLLD0–PLLD1) and the NF bit in the
PLLMOD register are automatically loaded into the 12-bit programmable counter and the 5-bit swallow counter.
When the 12-bit programmable down counter reaches zero, the contents of the data register are automatically
reloaded into the programmable counter and the swallow counter for the next counting operation.
If you modify the data register value while the PLL is operating, the new values are not immediately loaded into
the two counters; the new data are loaded into the two counters when the current count operation has been
completed.
The contents of the data register undetermined after initial power-on. However, the data register retains its
current value when the reset operation is initiated by an external reset or a change in level at the CE pin.
The swallow counter is a 5-bit binary down counter; the programmable counter is a 12-bit binary down counter.
The swallow counter is for FM mode only. The swallow counter and programmable counter start counting down
simultaneously. When the swallow counter starts counting down, the 1/33 prescaler is selected. When the
swallow counter reaches zero, it stop operation and selects the 1/32 prescaler.
18-2
S3C830A/P830A
PLL FREQUENCY SYNTHESIZER
PLL DATA REGISTER (PLLD)
The frequency division value of the swallow counter and programmable counter is set in the PLL data register
(PLLD0-PLLD1). PLL data register configuration is shown in Figure 18-2.
Programmable Counter
(Upper 12 bits)
Swallow Counter
(Lower 5 bits)
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PLLMOD.5
(NF)
PLLD b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
PLLD1 (F6H, Bank 0, Set 1)
PLLD0 (F7H, Bank 0, Set 1)
Figure 18-2. PLL Register Configuration
Direct Frequency Division and Pulse Swallow Formulas
In the direct frequency division method, the upper 12 bits are valid. In the pulse swallow method, all 16 bits are
valid. The upper 12 bit are set in the programmable counter and the lower 4 bits and the NF bit are set in the
swallow counter. The frequency division formulas for both methods, as set in the PLL data register, are shown
below:
— Direct frequency division (AM) is
fVCOAM
fR =
N
Where the frequency division value (N) is 12 bits; fVCOAM = input frequency at the VCOAM pin
— Pulse swallow system (FM) is
fVCOFM
fR =
(N´ 32+M)
where the frequency division values (N and M) are 12 bits and 5 bits, respectively; fVCOFM = input frequency at
the VCOFM pin.
18-3
PLL FREQUENCY SYNTHESIZER
S3C830A/P830A
REFERENCE FREQUENCY GENERATOR
The reference frequency generator produce reference frequency which are then compared by the phase
comparator. As shown in Figure 18-3, the reference frequency generator divides a crystal oscillation frequency of
4.5 MHz and generates the reference frequency (fR) for the PLL frequency synthesizer. Using the PLLREF
register, you can select from ten different reference frequencies.
Data Bus
8
PLLREF
4
1 kHz
3 kHz
5 kHz
6.25 kHz
Frequency
Divider
To Phase
Detector
Selector
4.5 MHz
50 kHz
100 kHz
Figure 18-3. Reference Frequency Generator
18-4
S3C830A/P830A
PLL FREQUENCY SYNTHESIZER
PLL MODE REGISTER (PLLMOD)
The PLL mode register (PLLMOD) is used to start and stop PLL operation. PLLMOD values also determine the
frequency dividing method.
PLLMOD PLLMOD.7 PLLMOD.6
NF
Not used PLLMOD.3 PLLMOD.2 PLLMOD.1 PLLMOD.0
PLLMOD.7 selects the frequency dividing method. The basic configuration for the two frequency dividing
methods are as follows:
Direct Method
— Used for AM mode
— Swallow counter is not used
— VCOAM pin is selected for input
Pulse Swallow Method
— Used for FM mode
— Swallow counter is used
— VCOFM pin is selected for input
The input frequency at the VCOAM or VCOFM pin is divided by the programmable divider. The frequency division
value of the programmable divider is written to the PLL data register.
When the pulse swallow method is selected by setting PLLMOD.7, the input signal is first divided by a 1/32 or
1/33 prescaler and the divided frequency is input to the programmable divider. Table 18-1 shows PLLMOD
organization.
18-5
PLL FREQUENCY SYNTHESIZER
S3C830A/P830A
Table 18-1. PLLMOD Organization
PLL Enable and INTIF/INTCE Interrupt Control Bits
PLLMOD.6
PLLMOD.3
PLLMOD.2
0
1
0
1
0
Disable PLL.
Enable PLL.
Disable INTIF interrupt.
Enable INTIF interrupt.
INTIF interrupt is not pending (when read).;
Clear INTIF pending bit (when write).
1
0
1
0
INTIF interrupt is pending (when read).
Disable INTCE interrupt requests at CE pin.
Enable INTCE interrupt requests at CE pin.
PLLMOD.1
PLLMOD.0
INTCE interrupt is not pending (when read).;
Clear INTCE pending bit (when write).
1
INTCE interrupt is pending (when read).
Frequency Division Method Selection Bit
PLLMOD.7
Frequency Division
Method
Selected Pin
Input
Voltage
Input
Frequency
Division Value
16 to (212–1)
VCOAM selected;
VCOFM pulled Low
300mVPP
300mVPP
0
Direct method for AM
0.5–30 MHz
30–150 MHz
210 to (217–2)
VCOFM selected;
VCOAM pulled Low
1
Pulse swallow method
for FM
NOTE: The NF bit, a one-bit frequency division value, is written to bit 0 in the swallow counter.
18-6
S3C830A/P830A
PLL FREQUENCY SYNTHESIZER
PLL REFERENCE FREQUENCY SELECTION REGISTER (PLLREF)
The PLL reference frequency selection register (PLLREF) used to determine the reference frequency. You can
select one of ten reference frequencies by setting bits PLLREF.3-PLLREF.0 to the appropriate value.
PLLREF PLLREF.7 PLLREF.6 PLLREF.5 PLLREF.4 PLLREF.3 PLLREF.2 PLLREF.1 PLLREF.0
You can select one of the reference frequencies by setting bits PLLREF.3–PLLREF.0.
Table 18-2. PLLREF Register Organization
PLLREF.3 PLLREF.2 PLLREF.1 PLLREF.0
Reference Frequency Selection
Select 1 kHz as reference frequency
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Select 3 kHz as reference frequency
Select 5 kHz as reference frequency
Select 6.25 kHz as reference frequency
Select 9 kHz as reference frequency
Select 10 kHz as reference frequency
Select 12.5 kHz as reference frequency
Select 25 kHz as reference frequency
Select 50 kHz as reference frequency
Select 100 kHz as reference frequency
18-7
PLL FREQUENCY SYNTHESIZER
S3C830A/P830A
PHASE DETECTOR, CHARGE PUMP, AND UNLOCK DETECTOR
The phase comparator compare the phase difference between divided frequency (fN) output from the
programmable divider and the reference frequency (fR) output from the reference frequency generator.
The charge pump outputs the phase comparator’s output from error output pins EO0 and EO1. The relation
between the error output pin, divided frequency fN, and reference frequency fR is shown below:
fR > fN = Low level output
fR < fN = High level output
fR = fN = Floating level
A PLL operation starts when a value is loaded to the PLLMOD register, The PLL unlock flag (ULFG) in the PLL
reference register, PLLREF, provides status information regarding the reference frequency and divided
frequency.
The unlock detector detects the unlock state of the PLL frequency synthesizer. The unlock flag in the PLLREF
register is set to “1” in an unlock state. When ULFG = “0”, the PLL locked state is selected.
ULFG
CEFG
POFG
PLLREF.7–.4
IFCFG
F9H at bank 0 of set 1
The ULFG flag is set continuously at a period of reference frequency fR by the unlock detector. You must
therefore read the ULFG flag in the PLLREF register at periods longer than 1/fR of the reference frequency.
ULFG is reset wherever it is read.
PLL operation is controlled by the state of the CE (chip enable) pin. The PLL frequency synthesizer is disabled
and the error output pin is set to floating state whenever the CE pin is Low. When CE pin is High level, the PLL
operates normally.
The chip enable flag in the PLLREF register, CEFG, provides the status of the current level of the CE pin.
Whenever the state of the CE pin goes from Low to High, the CEFG flag is set to “1” and a CE reset operation
occurs. When the CE pin goes from High to Low, the CEFG flag is cleared to “0” and a CE interrupt is generated.
The power on flag in the PLLREF register, POFG, is set by initiated power-on reset, but it is not set when a reset
occurs on the normal operation. The POFG flag is cleared to “0” by writing “0” to POFG flag bit in PLLREF.
18-8
S3C830A/P830A
PLL FREQUENCY SYNTHESIZER
USING THE PLL FREQUENCY SYNTHESIZER
This section describes the steps you should follow when using the PLL direct frequency division method and the
pulse swallow method. In each case, you must make the following selections in this order:
1. Frequency division method:
2. Input pin:
Direct frequency division (AM) or pulse swallow (FM)
VCOAM or VCOFM
fR
3. Reference frequency:
4. Frequency division value:
N
Direct Frequency Division Method
Select the direct frequency division method by writing a “0” to PLLMOD.7.
The VCOAM pin is configured for input when you select the direct frequency division method.
Select the reference frequency by writing the appropriate values to the PLLREF register.
The frequency division value is
fVCOAM
N =
fR
where fVCOAM is the input frequency at the VCOAM pin, and fR is the reference frequency.
Example:
The following data are used to receive an AM-band broadcasting station:
Receive frequency:
Reference frequency:
Intermediate frequency:
1422 kHz
9 kHz
+ 450 kHz
The frequency division value N is calculated as follows:
(1422+450)´ 103
9´ 103
fVCOAM
N =
=
= 208 (decimal)
fR
= 0D0H (hexadecimal)
You would modify the PLL data register and PLLMOD.7–.4 register as follows:
PLLD0
PLMOD.7-.4
PLLD1
0
0
0
0
1
1
0
1
0
0
0
0
x
x
x
x
0
1
x
0
NF
0
D
0
NOTE: In the direct method, the contents of PLLD0.3-PLLD0.0 and NF are not evaluated.
18-9
PLL FREQUENCY SYNTHESIZER
S3C830A/P830A
Pulse Swallow Method
1. Select the pulse swallow method by writing a “1” to PLLMOD.7.
2. The VCOFM pin is configured for input when you select the pulse swallow method.
3. Select the reference frequency by writing the appropriate value to the PLLREF register.
4. Calculate the frequency division value as follows:
fVCOFM
32N + M =
fR
where fVCOFM is the input frequency at the VCOFM pin, and fR is the reference frequency, N is the quotient of
fVCOFM
32fR
fVCOFM
32fR
and M is the remainder of
.
Example:
The following data are used to receive an FM-band broadcasting station:
Receive frequency:
Reference frequency:
Intermediate frequency:
100.0 MHz
25 kHz
10.7 MHz
The frequency division value N and M are calculated as follows:
(100.0 + 10.7) ´ 106
25 ´ 103
fVCOFM
=
= 4428 = 138 ´ 32 + 12
fR
N = 138 (decimal) = 8AH (hexadecimal)
M = 12 (decimal) = 0C (hexadecimal)
You would modify the PLL data register and PLLMOD.7–.4 register as follows:
PLLD1
PLLD0
PLLMOD.7-.4
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
1
0
0
1
1
0
0
NF
0
8
A
C
18-10
S3C830A/P830A
INTERMEDIATE FREQUENCY COUNTER
19 INTERMEDIATE FREQUENCY COUNTER
OVERVIEW
The S3C830A uses an intermediate frequency counter (IFC) to counter the frequency of the AM or FM signal at
FMIF or AMIF pin. The IFC block consists of a 1/2 divider, gate control circuit, IFC mode register (IFMOD) and a
16-bit binary counter. The gate control circuit, which controls the frequency counting time, is programmed using
the IFMOD register. Four different gate times can be selected using IFMOD register settings.
During gate time, the 16-bit IFC counts the input frequency at the FMIF or AMIF pins. The FMIF or AMIF pin
input signal for the 16-bit counter is selected using IFMOD register settings.
The 16-bit binary counter (IFCNT1-IFCNT0) can be read by 8-bit register addressing mode only. When the FMIF
pin input signal is selected, the signal is divided by two. When the AMIF pin input signal is directly connected to
the IFC, it is not divided.
By setting IFMOD register, the gate is opened for 1-ms, 4-ms, or 8-ms periods. During the open period of the
gate, input frequency is counted by the 16-bit counter. When the gate is closed, the counting operation is
complete, and an interrupt is generated.
1/2
Divider
IF Counter
(16 bit)
Selector
FMIF
AMIF
8
Data Bus
Gate Control
Circuit
IRQ7
1 ms
4 ms
8 ms
3
2
1
0
IFMOD
Gate Signal
Generator
Data Bus
1kHz Internal Signal
Figure 19-1. IF Counter Block Diagram
19-1
INTERMEDIATE FREQUENCY COUNTER
S3C830A/P830A
IFC MODE REGISTER (IFMOD)
The IFC mode register (IFMOD) is a 8-bit register that is used to select the input pin and gate time. Setting
IFMOD register reset IFC value and IFC gate flag value, and starts IFC operation. You use the IFMOD register to
select the AMIF or FMIF input pin and the gate time.
IFMOD
IFMOD.3
IFMOD.2
IFMOD.1
IFMOD.0
F3H at bank 0 of set 1
IFC operation starts when you select AMIF or FMIF as the IFC input pin. A reset operation clears all IFMOD
values to “0”.
Table 19-1. IFMOD Organization
Pin Selection Bits
IFMOD.3
IFMOD.2
Effect of Control Setting
0
0
IFC is disabled; FMIF/AMIF are pulled down and FMIF/AMIF's feed-back
resistor are off.
0
1
1
1
0
1
Enable IFC operation; AMIF pin is selected; FMIF is pulled down and FMIF's
feed-back resistor is off.
Enable IFC operation; FMIF is selected; AMIF is pulled down and AMIF's feed-
back resistor is off.
Enable IFC operation; Both AMIF and FMIF are selected.
Gate Time Select Bits
IFMOD.1
IFMOD.0
Select Gate Time
Gate time is 1 ms.
0
0
1
1
0
1
0
1
Gate time is 4 ms.
Gate time is 8 ms.
Gate is open
IFC GATE FLAG REGISTER (PLLREF.5)
IFCFG
PLLREF.7-.4
ULFG
CEFG
POFG
F9H at bank 0 of set 1
When IFC operation is started by setting IFMOD, the IFC gate flag (IFCFG) is cleared to “0”. After a specified
gate time has elapsed, the IFCFG bit is automatically set to “1”. This lets you check whether a IFC counting
operation has been completed or not.
The IFC interrupt can also be used to check whether or not a IFC counting operation is complete.
19-2
S3C830A/P830A
INTERMEDIATE FREQUENCY COUNTER
GATE TIMES
When you write a value to IFMOD, the IFC gate is opened for a 1-millisecond, 4-millisecond, or 8-millisecond
interval, setting with a rising clock edge. When the gate is open, the frequency at the AMIF or FMIF pin is
counted by the 16-bit counter. When the gate closes, the IFC gate flag (IFCFG) is set to “1”. An interrupt is then
generated and the IFC interrupt pending bit (PLLMOD.2) is set.
Figure 19-2 shows gate timings with a 1-kHz internal clock.
Clock (1 kHz)
1 ms
4 ms
8 ms
Counting Period
Gate open here
Counting ends;
IFMOD is written;
IFCFG flag is set to "1" and
IFCFG flag is cleared to "0".
PLLMOD.2 is set to "1".
Figure 19-2. Gate Timing (1,4, or 8 ms)
19-3
INTERMEDIATE FREQUENCY COUNTER
Selecting “Gate Remains Open”
S3C830A/P830A
If you select “gate remain open” (IFMOD.0 and IFMOD.1 = “1”), the IFC counts the input signal during the open
period of the gate. The gate closes the next time a value is written to IFMOD.
Clock (1 kHz)
Gate Time
Counting Period
The gate closes when IFMOD is rewritten
Gate is opened by writing IFMOD
Figure 19-3. Gate Timing (When Open)
When you select “gate remains open” as the gating time, you can control the opening and closing of the gate in
one of two ways:
— Set the gate time to a specific interval (1-ms, 4-ms, or 8-ms) by setting bits IFMOD.1 and IFMOD.0.
Gate Time
Set non-open gate time (1-, 4-, 8-ms) by
Set IFMOD.1 = IFMOD.0 = "1"
bit IFMOD.1 and IFMOD.0
— Disable IFC operation by clearing bits IFMOD.3 and IFMOD.2 to “0”. This method lets the gate remain open,
and stops the counting operation.
Gate Time
Set IFMOD.3 = IFMOD.2 = "0",
Set IFMOD.1 = IFMOD.0 = "1"
IFC counting operation is stopped.
19-4
S3C830A/P830A
INTERMEDIATE FREQUENCY COUNTER
Gate Time Errors
A gate time error occurs whenever the gate signals are not synchronized to the interval instruction clock. That is,
the IFC does not start counter operation until a rising edge of the gate signal is detected, even though the counter
start instruction (setting bits IFMOD.3 and IFMOD.2) has been executed. Therefore, there is a maximum 1-ms
timing error (see Figure 19-4).
After you have executed the IFC start instruction, you can check the gate state at any time. Please note, however
that the IFC does not actually start its counting operation until stabilization time for the gate control signal has
elapsed.
Instruction Execution
(IFMOD Setting)
1ms
Clock (1 kHz)
Actual Gate
Signal (1 ms)
Resulting
Gate Signal
Actual Counting Period
Gate Time Errors
Figure 19-4. Gate Timing (1-ms Error)
Counting Errors
The IF counter counts the rising edges of the input signal in order to determine the frequency. If the input signal
is High level when the gate is open, one additional pulse is counted. When the gate is close, however, counting is
not affected by the input signal status. In other words, the counting error is “+1, 0”.
19-5
INTERMEDIATE FREQUENCY COUNTER
S3C830A/P830A
IF COUNTER (IFC) OPERATION
IFMOD register bits 2 and 3 are used to select the input pin and to start or stop IFC counting operation. You stop
the counting operation by clearing IFMOD.2 and IFMOD.3 to “0”. The IFC retains its previous value until IFMOD
register values are specified.
Setting bits IFMOD.3 and IFMOD.2 starts the frequency counting operation. Counting continues as long as the
gate is open. The 16-bit counter value is automatically cleared to 0000H after it overflows (at FFFFH), and
continues counting from zero. The 16-bit count value (IFCNT1-IFCNT0) can be read by register addressing
mode. A reset operation clears the counter to zero.
IFCNT0
IFCNT1
IFCNT0.7 IFCNT0.6 IFCNT0.5 IFCNT0.4 IFCNT0.3 IFCNT0.2 IFCNT0.1 IFCNT0.0
IFCNT1.7 IFCNT1.6 IFCNT1.5 IFCNT1.4 IFCNT1.3 IFCNT1.2 IFCNT1.1 IFCNT1.0
When the specified gate open time has elapsed, the gate closes in order to complete the counter operation. At
this time, the IFC interrupt pending bit (PLLMOD.2) is automatically set to “1” and an interrupt is generated. The
pending bit must be cleared to “0” by software when the interrupt is serviced. The IFC gate flag (IFCFG) is set to
“1” at the same time the gate is closed. Since the IFCFG flag is cleared to “0” when IFC operation start, you can
check the IFCFG flag to determine when IFC operation stops (that is, when the specified gate open time has
elapsed).
The frequency applied to FMIF or AMIF pin is counted while the gate is open. The frequency applied to FMIF pin
is divided by 2 before counting. The relationship between the count value (N) and input frequencies fAMIF and
fFMIF is shown below.
— FMIF pin input frequency is
N (DEC)
fFMIF =
x 2
TG
when TG = gate time (1 ms, 4 ms, 8 ms)
— AMIF pin input frequency is
N (DEC)
fAMIF =
TG
when TG = gate time (1 ms, 4 ms, 8 ms)
Table 19-2 shows the range of frequency that you can apply to the AMIF and FMIF pins.
Table 19-2. IF Counter Frequency Characteristics
Pin
Voltage Level
Frequency Range
0.1 MHz to 1 MHz
5 MHz to 15 MHz
300 m VPP (min)
AMIF
FMIF
300 m VPP (min)
19-6
S3C830A/P830A
INTERMEDIATE FREQUENCY COUNTER
INPUT PIN CONFIGURATION
The AMIF and FMIF pins have built-in AC amplifiers (see Figure 19-5). The DC component of the input signal
must be stripped off by the external capacitor.
When the AMIF or FMIF pin is selected for the IFC function and the switch is turned on voltage of each pin
increases to approximately 1/2 VDD after a sufficiently long time. If the pin voltage does not increase to
approximately 1/2 VDD, the AC amplifier exceeds its operating range, possibly causing an IFC malfunction. To
prevent this from occurring, you should program a sufficiently long time delay interval before starting the count
operation.
SW
C
External
Frequency
To Internal
Counter
FMIF
AMIF
Figure 19-5. AMIF and FMIF Pin Configuration
19-7
INTERMEDIATE FREQUENCY COUNTER
S3C830A/P830A
IFC DATA CALCULATION
Selecting the FMIF pin for IFC Input
First, divide the signal at the FMIF pin by 2, and then apply this value to the IF counter. This means that the IF
counter value is equal to one-half of the input signal frequency.
FMIF input frequency (fFMIF): 10.7 MHz
Gate time (TG): 8 ms
IFC counter value (N):
N = (fFMIF/2) ´ TG
= 10.7 ´ 106 /2 ´ 8 ´ 10-3
= 42800
= A730H
Bin
Dec
1
0
1
0
0
1
1
1
0
0
1
1
0
0
0
0
A
7
3
0
IFCNT
IFCNT1
IFCNT0
Selecting the AMIF Pin for IFC Input
The signal at AMIF pin is directly input to the IF counter.
AMIF input frequency (fAMIF): 450 kHz
Gate time (TG): 8 ms
IFC counter value (N):
N = (fAMIF) ´ TG
= 450 ´ 103 ´ 8 ´ 10-3
= 3600
= E10H
Bin
Dec
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
E
1
0
IFCNT
IFCNT1
IFCNT0
19-8
S3C830A/P830A
ELECTRICAL DATA
20 ELECTRICAL DATA
OVERVIEW
In this chapter, S3C830A electrical characteristics are presented in tables and graphs.
The information is arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— A.C. electrical characteristics
— Input/output capacitance
— Data retention supply voltage in stop mode
— A/D converter electrical characteristics
— PLL electrical characteristics
— Low voltage reset electrical characteristics
— Serial I/O timing characteristics
— Oscillation characteristics
— Oscillation stabilization time
20-1
ELECTRICAL DATA
S3C830A/P830A
Table 20-1. Absolute Maximum Ratings
°
(TA= 25 C)
Parameter
Symbol
Conditions
Rating
– 0.3 to +6.5
Unit
VDD
VI
Supply voltage
–
V
– 0.3 to VDD + 0.3
Input voltage
Ports 0–8
–
VO
IOH
– 0.3 to VDD + 0.3
– 15
Output voltage
Output current high
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 60
+ 30
IOL
Output current low
Total pin current for port
+ 100
°
C
TA
Operating temperature
Storage temperature
– 25 to + 85
TSTG
– 65 to + 150
Table 20-2. D.C. Electrical Characteristics
(TA = –25 C to + 85 C, VDD = 3.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
fx = 0.4–4.5 MHz
Min.
Typ.
Max.
Unit
VDD
Operating voltage
3.0
–
5.5
V
(except PLL/IFC)
fx = 4.5 MHz (PLL/IFC)
Ports 0–8
4.5
–
–
5.5
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
VOH1
0.8 VDD
VDD
Input high voltage
Input low voltage
Output high voltage
0.8 VDD
VDD–0.1
VDD
VDD
RESET, CE
XIN, XOUT
0.2 VDD
0.2 VDD
0.1
Ports 0–8
–
–
–
RESET, CE
XIN, XOUT
VDD = 4.5 V to 5.5 V
EO0, EO1; IOH = –1 mA
VDD – 2.0
VDD – 1.0
VDD
VOH2
VDD = 4.5 V to 5.5 V
VDD
Other output ports;
IOH = –1 mA
VOL1
VDD = 4.5 V to 5.5 V
EO0, EO1; IOL = 1 mA
Output low voltage
–
–
2.0
2.0
VOL2
VDD = 4.5 V to 5.5 V
–
Other output ports;
IOL = 10 mA
20-2
S3C830A/P830A
ELECTRICAL DATA
Table 20-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = -25 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
VIN = VDD
Min.
Typ.
Max.
Unit
ILIH1
Input high leakage
current
–
–
3
uA
All input pins except
XIN, XOUT
ILIH2
ILIL1
VIN = VDD, XIN
VIN = 0 V
X
,
OUT
20
-3
Input low leakage
current
–
–
All input pins except
RESET, XIN
X
,
OUT
ILIL2
ILOH
VIN = 0 V, XIN
VOUT = VDD
X
,
OUT
-20
3
Output high
leakage current
–
–
–
–
All output pins
VOUT = 0 V
ILOL
RL1
RL2
Output low leakage
current
-3
All output pins
VIN = 0 V; VDD = 5 V
Port 0–8
Pull-up resistor
25
150
50
250
100
400
kW
VIN = 0 V; VDD = 5 V;
RESET
RD
VIN = VDD, VDD = 5 V
Pull-down resistor
15
35
45
kW
kW
VCOFM, VCOAM, AMIF
and FMIF
°
ROSC
Oscillator feed
back resistors
300
750
1500
VDD = 5 V, T = 25 C
A
XIN = VDD, XOUT = 0 V
°
RLCD
VDC
LCD voltage
dividing resistor
70
–
110
45
150
120
kW
TA = 25 C
|VLCD – COMi|
mV
–15 mA per common pin
–15 mA per common pin
VDD = 3.0 V to 5.5 V
voltage drop
(I = 0–3)
|VLCD – SEGx|
VDS
–
45
120
mV
V
voltage drop
(x = 0–39)
Middle output
voltage
VLC0
0.6VDD
0.2
–
0.6VDD
0.6VDD
0.2
+
VLC1
VLC2
0.4VDD
0.2
–
–
0.4VDD
0.2VDD
0.4VDD
0.2
+
+
0.2VDD
0.2
0.2VDD
0.2
20-3
ELECTRICAL DATA
S3C830A/P830A
Table 20-2. D.C. Electrical Characteristics (Concluded)
°
°
(T = -25 C to + 85 C, VDD = 3.0 V to 5.5 V)
A
Parameter
Symbol
Conditions
Run mode:
Min.
Typ.
Max.
Unit
Supply current (1)
IDD1
–
5.0
15
mA
4.5 MHz crystal oscillator
CE = VDD
VDD = 5 V ± 10 %
C1 = C2 = 22pF
IDD2
Run mode:
–
2.6
5.5
4.5 MHz crystal oscillator
CE = 0 V
VDD = 5 V ± 10 %
C1 = C2 = 22pF
IDD3
Idle mode:
4.5 MHz crystal oscillator
VDD = 5 V ± 10 %
–
–
0.6
0.5
2.0
3
(2)
Stop mode (in LVR disable):
CE = 0 V, T = 25 C
A
mA
IDD4
°
VDD = 5 V ± 10 %
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors, PWM, or external output current loads.
2. is current when the main clock oscillation stops.
I
DD4
3. Every values in this table is measured when bits 4–3 of the system clock control register (CLKCON.4–.3) is set to 11B.
20-4
S3C830A/P830A
ELECTRICAL DATA
Table 20-3. A.C. Electrical Characteristics
°
°
(TA = -25 C to +85 C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
P1.0–P1.7, VDD = 5 V
Interrupt input
high, low width
(P1.0–P1.7)
tINTH,
tINTL
200
–
ns
VDD = 5 V
tRSL
10
–
–
us
RESET input low
width
tTIL
tTIH
0.8 VDD
0.2 VDD
0.2 VDD
Figure 20-1. Input Timing for External Interrupts (Ports 1)
t
RSL
RESET
0.2 V
DD
Figure 20-2. Input Timing for RESET
20-5
ELECTRICAL DATA
S3C830A/P830A
Table 20-4. Input/Output Capacitance
°
°
(TA = -25 C to +85 C, VDD = 0 V )
Parameter
Input
capacitance
Symbol
Conditions
Min
Typ
Max
Unit
CIN
f = 1 MHz; unmeasured pins
are returned to VSS
–
–
10
pF
COUT
CIO
Output
capacitance
I/O capacitance
Table 20-5. Data Retention Supply Voltage in Stop Mode
°
°
(TA = -25 C to + 85 C)
Parameter
Symbol
VDDDR
Conditions
Min
Typ
–
Max
Unit
Data retention
supply voltage
3.0
5.5
V
°
IDDDR
Data retention
supply current
–
–
1
uA
VDDDR = 2 V (TA = 25 C)
Stop mode (in LVR disable)
RESET
Occurs
Oscillation
Stabilization
Time
Stop Mode
Normal
Operating Mode
Data Retention Mode
V
DD
V
DDDR
Execution of
STOP Instrction
RESET
0.2 VDD
t
WAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fxx
Figure 20-3. Stop Mode Release Timing Initiated by RESET
20-6
S3C830A/P830A
ELECTRICAL DATA
Oscillation
Stabilization Time
Idle Mode
Stop Mode
Data Retention Mode
VDD
VDDDR
Normal
Execution of
STOP Instruction
Operating Mode
Interrupt
0.2 VDD
tWAIT
NOTE:
tWAIT is the same as 16 x 1/BT clock
Figure 20-4. Stop Mode Release Timing Initiated by Interrupts
Table 20-6. A/D Converter Electrical Characteristics
(T = -25 °C to +85 °C, V
A
= 3.5 V to 5.5 V, VSS = 0 V)
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
A/D converting
resolution
–
–
–
8
–
bits
Absolute accuracy
–
–
–
–
LSB
ms
±2
tCON
A/D conversion time
Conversion clock = fxx
50/fxx
VSS
–
VIAN
RAN
VDD
–
Analog input voltage
–
–
V
VDD = 5 V
Analog input
impedance
2
1000
MW
20-7
ELECTRICAL DATA
S3C830A/P830A
Table 20-7. PLL Electrical Characteristics
= 4.5 V to 5.5 V)
(T = –25 °C to +85 °C, V
A
DD
Parameter
Symbol
Conditions
Sine wave input
Min
Typ
Max
Unit
VIN
VDD
VCOFM, VCOAM,
FMIF and AMIF
input voltage (peak
to peak)
0.3
–
V
fVCOAM
fVCOFM
fAMIF
Frequency
VCOAM mode, sine wave
input; VIN = 0.3VP-P
0.5
30
0.1
5
–
30
150
1.0
15
MHz
VCOFM mode, sine wave
input; VIN = 0.3VP-P
AMIF mode, sine wave
input; VIN = 0.3VP-P
fFMIF
FMIF mode, sine wave
input; VIN = 0.3VP-P
Table 20-8. Low Voltage Reset Electrical Characteristics
(T = –25 °C to +85 °C)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VDET
Detect voltage range
3.0
3.5
4.0
V
IBL
LVR operating
current
–
–
10
25
mA
20-8
S3C830A/P830A
ELECTRICAL DATA
Table 20-9. Synchronous SIO Electrical Characteristics
°
°
(TA = –25 C to +85 C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
tCKY
SCK0/SCK1 cycle time
External SCK0/SCK1 source
1000
–
–
ns
Internal SCK0/SCK1 source
External SCK0/SCK1 source
1000
500
tKH, tKL
SCK0/SCK1 high, low
width
–
–
tKCY/2–
50
Internal SCK0/SCK1 source
tSIK
SI setup time to
External SCK0/SCK1 source
250
–
–
–
–
–
SCK0/SCK1 high
SI hold time to
Internal SCK0/SCK1 source
External SCK0/SCK1 source
250
400
tKSI
SCK0/SCK1 high
Output delay for
Internal SCK0/SCK1 source
External SCK0/SCK1 source
400
–
tKSO
300
250
SCK0/SCK1 to SO
Internal SCK0/SCK1 source
tCKY
tKL
tKH
SCK0/SCK1
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
0.2 VDD
SI0/SI1
Input Data
tKSO
SO0/SO1
Output Data
Figure 20-5. Serial Data Transfer Timing
20-9
ELECTRICAL DATA
S3C830A/P830A
Table 20-10. Main Oscillator Characteristics (fx)
°
°
(T = –25 C to +85 C, V
= 3.0 V to 5.5 V)
DD
A
Oscillator
Crystal
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Crystal oscillation frequency
0.4
–
4.5
MHz
XIN
XOUT
C1
C2
Ceramic
Ceramic oscillation
frequency
0.4
0.4
–
–
4.5
4.5
MHz
MHz
X
IN
XOUT
C1
C2
XIN input frequency
External clock
X
IN
XOUT
Table 20-11. Main Oscillator Clock Stabilization Time (tST1
)
°
°
(TA = -25 C to +85 C, VDD = 3.0 V to 5.5 V)
Oscillator
Crystal
Test Condition
Min
Typ
Max
Unit
VDD = 4.5 V to 5.5 V
–
–
10
ms
Stabilization occurs when VDD is equal to the minimum
oscillator voltage range.
Ceramic
–
–
4
ms
XIN input high and low level width (tXH, tXL)
External clock
111
–
1250
ns
NOTE: Oscillation stabilization time (t
) is the time required for the CPU clock to return to its normal oscillation
ST1
frequency after a power-on occurs, or when Stop mode is ended by a RESET signal.
The RESET should therefore be held at low level until the t time has elapsed
ST1
20-10
S3C830A/P830A
ELECTRICAL DATA
1/fx
tXL
tXH
XIN
VDD-0.1V
0.1V
Figure 20-6. Clock Timing Measurement at XIN
Instruction Clock
1.125 MHZ
Main Oscillator Frequency
4.5 MHZ
25 kHz
400 kHz
1
2
3
4
5
6
7
Supply Voltage (V)
CPU Clock = 1/4n x oscillator frequency (n = 1,2,8,16)
When PLL/IFC operation, operating voltage range is 4.5 V to 5.5 V.
Figure 20-7. Operating Voltage Range
20-11
ELECTRICAL DATA
S3C830A/P830A
NOTES
20-12
S3C830A/P830A
MECHANICAL DATA
21 MECHANICAL DATA
OVERVIEW
The S3C830A microcontroller is currently available in 100-pin-QFP package.
23.90 ± 0.30
20.00 ± 0.20
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
100-QFP-1420C
#100
+ 0.10
- 0.05
#1
0.30
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.65
0.15 MAX
(0.58)
0.10 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 21-1. Package Dimensions (100-QFP-1420C)
21-1
MECHANICAL DATA
S3C830A/P830A
NOTES
21-2
S3C830A/P830A
S3P830A OTP
22 S3P830A OTP
OVERVIEW
The S3P830A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C830A
microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data
format.
The S3P830A is fully compatible with the S3C830A, both in function in D.C. electrical characteristics and in pin
configuration. Because of its simple programming requirements, the S3P830A is ideal as an evaluation chip for
the S3C830A.
22-1
S3P830A OTP
S3C830A/P830A
P1.7/INT7
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AMIF
VSSPLL
VCOAM
VCOFM
VDDPLL1
LVREN
TEST3
BIAS
VLC0
VLC1
VLC2
COM0
COM1
COM2
COM3
SEG0/P8.7
SEG1/P8.6
SEG2/P8.5
SEG3/P8.4
SEG4/P8.3
SEG5/P8.2
SEG6/P8.1
SEG7/P8.0
SEG8/P7.7
SEG9/P7.6
SEG10/P7.5
SEG11/P7.4
SEG12/P7.3
SEG13/P7.2
SEG14/P7.1
P2.5
P2.6
P2.7
AVDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3.0/BUZ
P3.1/SCK0
SDAT/P3.2/SO0
SCLK/P3.3/SI0
VDD/VDD
S3P830A
VSS/VSS
100-QFP-1420C
XOUT
XIN
VPP/TEST1
TEST2
P3.4/SCK1
RESET/RESET
P3.5/SO1
P3.6/SI1
P3.7
P4.0/SEG39
P4.1/SEG38
P4.2/SEG37
P4.3/SEG36
P4.4/SEG35
Figure 22-1. S3P830A Pin Assignments (100-Pin QFP Package)
22-2
S3C830A/P830A
S3P830A OTP
Table 22-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P3.2/SO0
Pin Name
Pin No.
I/O
Function
SDAT
13
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P3.3/SI0
TEST1
SCLK
VPP
14
19
I
I
Serial clock pin. Input only pin.
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
22
I
Chip Initialization
RESET
RESET
VDD/VSS
VDD/VSS
15/16
–
Logic power supply pin. VDD should be tied to
+5 V during programming.
Table 22-2. Comparison of S3P830A and S3C830A Features
S3P830A
Characteristic
S3C830A
Program Memory
48-Kbyte EPROM
3.0 V to 5.5 V
48-Kbyte mask ROM
3.0 V to 5.5 V
Operating Voltage (VDD
)
VDD = 5 V, VPP (TEST1) = 12.5 V
OTP Programming Mode
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST1) pin of the S3P830A, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 21-3 below.
Table 22-3. Operating Mode Selection Criteria
VDD
VPP (TEST1)
Address(A15–A0)
R/W
Mode
EPROM read
REG/MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
22-3
S3P830A OTP
S3C830A/P830A
Instruction Clock
1.125 MHZ
Main Oscillator Frequency
4.5 MHZ
25 kHz
400 kHz
1
2
3
4
5
6
7
Supply Voltage (V)
CPU Clock = 1/4n x oscillator frequency (n = 1,2,8,16)
When PLL/IFC operation, operating voltage range is 4.5 V to 5.5 V.
Figure 22-2. Operating Voltage Range
22-4
S3C830A/P830A
DEVELOPMENT TOOLS
23 DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool
including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for
S3C7, S3C9, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.
Samsung also offers support software that includes debugger, assembler, and a program for setting options.
SHINE
Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked
help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be
sized, moved, scrolled, highlighted, added, or removed completely.
SAMA ASSEMBLER
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates
object code in standard hexadecimal format. Assembled program code includes the object code that is used for
ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and
an auxiliary definition (DEF) file with device specific information.
SASM88
The SASM88 is a relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a
source file containing assembly language statements and translates into a corresponding source code, object
code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating
system. It produces the relocatable object code only, so the user should link object file. Object files can be linked
with other object files and loaded into memory.
HEX2ROM
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by
HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device
automatically.
TARGET BOARDS
Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters
are included with the device-specific target board.
23-1
DEVELOPMENT TOOLS
S3C830A/P830A
IBM-PC AT or Compatible
RS-232C
SMDS2+
PROM/OTP Writer Unit
Target
Application
System
RAM Break/Display Unit
Trace/Timer Unit
Probe
Adapter
TB830A
Target
Board
POD
SAM8 Base Unit
Eva
Chip
Power Supply Unit
Figure 23-1. SMDS Product Configuration (SMDS2+)
23-2
S3C830A/P830A
DEVELOPMENT TOOLS
TB830A TARGET BOARD
The TB830A target board is used for the S3C830A/P830A microcontroller. It is supported with the SMDS2+,
Smart Kit and OPENice.
REV.1
01, 06. 09
TB830A
To User_VCC
u3
J3
On
74NC11
Dip1
RESET
25
Idle
+
Stop
+
J101
J102
1
9
2
51
52
60
70
80
90
100
TB830A
160-QFP
10 59
20 69
30 79
40 89
50 99
19
29
39
49
1
SMDS2
SMDS2+
JP4
SM1344A
Figure 23-2. TB830A Target Board Configuration
23-3
DEVELOPMENT TOOLS
S3C830A/P830A
Table 23-1. Power Selection Settings for TB830A
Operating Mode
"To User_Vcc"
Settings
Comments
The SMDS2/SMDS2+
supplies VCC to the target
To User_VCC
Target
System
TB830A
Off
On
VCC
VSS
board (evaluation chip) and
the target system.
VCC
SMDS2/SMDS2+
The SMDS2/SMDS2+
supplies VCC only to the target
To User_VCC
Off
External
VCC
Target
System
TB830A
On
board (evaluation chip).
The target system must have
its own power supply.
VSS
VCC
SMDS2+
NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration:
23-4
S3C830A/P830A
DEVELOPMENT TOOLS
SMDS2+ SELECTION (SAM8)
In order to write data into program memory that is available in SMDS2+, the target board should be selected to
be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.
Table 23-2. The SMDS2+ Tool Selection Setting
"SW1" Setting
SMDS2 SMDS2+
Operating Mode
R/W R/W
SMDS2+
Target
System
IDLE LED
The Yellow LED is ON when the evaluation chip (S3E8300) is in idle mode.
STOP LED
The Red LED is ON when the evaluation chip (S3E8300) is in stop mode.
23-5
DEVELOPMENT TOOLS
S3C8248/C8245/P8245/C8247/C8249/P8249
J101
J102
P1.7
P2.1
P2.3
P2.5
P2.7
P3.0
P3.2
User_VCC
XOUT
GND
P3.4
P3.5
P3.7
P4.1
P4.3
P4.5
P4.7
P5.1
P5.3
P5.5
P5.7
P6.1
P6.3
P6.5
P6.7
1
3
5
7
2
4
6
P2.0
P2.2
P2.4
P2.6
NC
P3.1
P3.3
GND
XIN
GND
DEMO_RSTB
P3.6
P4.0
P4.2
P4.4
P4.6
P5.0
P5.2
P5.4
P5.6
P6.0
P6.2
P6.4
P6.5
P7.0
P7.1
P7.3
P7.5
P7.7
P8.1
P8.3
P8.5
P8.7
1
3
5
7
2
4
6
P7.2
P7.4
P7.6
P8.0
P8.2
P8.4
P8.6
COM3
COM1
VLC2
VLC0
VDET
VDD
8
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
COM2
COM0
VLC1
BIAS
LVR_EN
VCOFM
GND
FMIF
EO0
VCOAM
AMIF
NC
EO1
CE
P0.1
P0.2
P0.5
P0.7
P1.1
P1.3
P1.5
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
Figure 23-3. 50-Pin Connectors (J101, J102) for TB830A
Target Board
J101 J102
51 52
Target System
J102
51 52
J101
1
2
1
2
Part Name: (AS50D-A)
Order Cods: SM6305
49 50 99 100
99 100 49 50
Figure 23-4. S3C830A/P830A Probe Adapter Cables for 100-QFP Package
23-6
S3C8 SERIES MASK ROM ORDER FORM
Product description:
Device Number: S3C8__________- ___________(write down the ROM code number)
Product Order Form:
Package
Pellet
Wafer
Package Type: __________
Package Marking (Check One):
Standard
Custom A
(Max 10 chars)
Custom B
(Max 10 chars each line)
@ YWW
Device Name
@ YWW
@ YWW
Device Name
SEC
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantities:
Deliverable
ROM code
Required Delivery Date
Quantity
Comments
–
Not applicable
See ROM Selection Form
Customer sample
Risk order
See Risk Order Sheet
Please answer the following questions:
For what kind of product will you be using this order?
+
New product
Upgrade of an existing product
Other
Replacement of an existing product
If you are replacing an existing product, please indicate the former product name
(
)
+
What are the main reasons you decided to use a Samsung microcontroller in your product?
Please check all that apply.
Price
Product quality
Features and functions
Delivery on time
Development system
Used same micom before
Technical support
Quality of documentation
Samsung reputation
Mask Charge (US$ / Won):
Customer Information:
____________________________
Company Name:
___________________
Telephone number
_________________________
Signatures:
________________________
(Person placing the order)
__________________________________
(Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3C8 SERIES
REQUEST FOR PRODUCTION AT CUSTOMER RISK
Customer Information:
Company Name:
Department:
Telephone Number:
Date:
________________________________________________________________
________________________________________________________________
__________________________
__________________________
Fax: _____________________________
Risk Order Information:
Device Number:
S3C8________- ________ (write down the ROM code number)
Package:
Number of Pins: ____________
Package Type: _____________________
Intended Application:
Product Model Number:
________________________________________________________________
________________________________________________________________
Customer Risk Order Agreement:
We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk
order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume
responsibility for any and all production risks involved.
Order Quantity and Delivery Schedule:
Risk Order Quantity:
Delivery Schedule:
_____________________ PCS
Delivery Date (s)
Quantity
Comments
Signatures:
_______________________________
(Person Placing the Risk Order)
_______________________________________
(SEC Sales Representative)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3C830A
MASK OPTION SELECTION FORM
Device Number:
S3C8_______-________(write down the ROM code number)
Attachment (Check one):
Diskette
PROM
Customer Checksum:
Company Name:
________________________________________________________________
________________________________________________________________
________________________________________________________________
Signature (Engineer):
Please answer the following questions:
+
Application (Product Model ID: _______________________)
Audio
Video
Telecom
LCD Databank
Industrials
Remocon
Caller ID
Home Appliance
Other
LCD Game
Office Automation
Please describe in detail its application
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3P8 SERIES OTP FACTORY WRITING ORDER FORM (1/2)
Product Description:
Device Number: S3P8________-________(write down the ROM code number)
Product Order Form:
Package
Pellet
Wafer
If the product order form is package:
Package Type: _____________________
Package Marking (Check One):
Standard
Custom A
Custom B
(Max 10 chars)
(Max 10 chars each line)
@ YWW
@ YWW
@ YWW
Device Name
SEC
Device Name
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantity:
ROM Code Release Date
Required Delivery Date of Device
Quantity
Please answer the following questions:
+
What is the purpose of this order?
New product development
Upgrade of an existing product
Other
Replacement of an existing microcontroller
If you are replacing an existing microcontroller, please indicate the former microcontroller name
(
)
+
What are the main reasons you decided to use a Samsung microcontroller in your product?
Please check all that apply.
Price
Product quality
Features and functions
Delivery on time
Development system
Used same micom before
Technical support
Quality of documentation
Samsung reputation
Customer Information:
Company Name:
___________________
Telephone number
_________________________
Signatures:
________________________
(Person placing the order)
__________________________________
(Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
S3P830A
OTP FACTORY WRITING ORDER FORM (2/2)
Device Number:
S3P8________-__________ (write down the ROM code number)
Customer Checksums:
Company Name:
_______________________________________________________________
________________________________________________________________
________________________________________________________________
Signature (Engineer):
Read Protection (1):
Yes
No
Please answer the following questions:
+
+
Are you going to continue ordering this device?
Yes No
If so, how much will you be ordering? _________________pcs
Application (Product Model ID: _______________________)
Audio
Video
Telecom
LCD Databank
Industrials
Remocon
Caller ID
Home Appliance
Other
LCD Game
Office Automation
Please describe in detail its application
___________________________________________________________________________
NOTES
1. Once you choose a read protection, you cannot read again the programming code from the EPROM.
2. OTP Writing will be executed in our manufacturing site.
3. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors
occurred from the writing program.
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
相关型号：
S3C8454XX-TW
Microcontroller, 8-Bit, MROM, SAM87RC CPU, 25MHz, CMOS, PQFP80, 12 X 12 MM, TQFP-80
SAMSUNG
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