S3C8444 [SAMSUNG]
S3C8444 MICROCONTROLLER; S3C8444微控制器
| 型号： | S3C8444 |
| 厂家： | 
SAMSUNG |
| 描述： | S3C8444 MICROCONTROLLER |
| 文件： | 总44页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Overview
Address Spaces
Addressing Modes
Control Registers
Interrupt Structure
Instruction Set
S3C8444
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's new SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements.
Timer/counters with selectable operating modes are included to support real-time operations. Many SAM8
microcontrollers have an external interface that provides access to external memory and other peripheral
devices.
The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.
S3C8444 MICROCONTROLLER
The S3C8444 single-chip microcontroller is fabricated using a highly advanced CMOS process. Its design is
based on the powerful SAM8 CPU core. Stop and Idle power-down modes were implemented to reduce power
consumption. The size of the internal register file is logically expanded, increasing the addressable on-chip
register space to 1040 bytes. A flexible yet sophisticated external interface is used to access up to 64-Kbytes of
program and data memory. The S3C8444 is a versatile microcontroller that is ideal for use in a wide range of
general-purpose applications such as CD-ROM/DVD-ROM drives.
Using the SAM8 modular design approach, the following peripherals were integrated with the SAM8 CPU core:
1–1
PRODUCT OVERVIEW
S3C8444
— Six configurable 8-bit general I/O ports
The S3C8444 is a versatile microcontroller that is
ideal for use in a wide range of general-purpose
ROM-less applications such as CD-ROM/DVD-ROM
drivers.
— One 8-bit n-channel, open-drain output port
— One 8-bit input port for A/D converter input or
digital input
— Full-duplex serial data port with one
synchronous and three asynchronous (UART)
operating modes
— Two 8-bit timers with interval timer or PWM
mode
— Two 16-bit timer/counters with four
programmable operating modes
— Two programmable 8-bit PWM modules with
corresponding output pins
— One 8-bit capture module with CAP input pin
— A/D converter with 8 selectable input pins
Figure 1–1. S3C8444 Microcontroller
1–2
S3C8444
PRODUCT OVERVIEW
General I/O
FEATURES
•
•
•
Six 8-bit general I/O ports (ports 0,1,2,3,4, and
5)
CPU
One 8-bit n-channel, open-drain output port
(port 6)
•
SAM8 CPU core
One 8-bit input port (for ADC input or port 7
digital input)
Memory
•
•
1040-byte of internal register file
4-kbyte internal program memory area
Serial Port
•
•
Full-duplex serial data port (UART)
Four programmable operating modes
External Interface
•
•
•
64-Kbyte external data memory area
64-Kbyte external program memory (ROMless)
60-Kbyte external program memory (normal)
PWM and Capture
•
•
•
•
Two output channels (PWM0, PWM1)
8-bit resolution with 2-bit prescaler
97.66-kHz frequency (25-MHz CPU clock)
Capture module with CAP input pin
Instruction Set
•
•
78 instructions
IDLE and STOP instructions
Analog-to-Digital Converter
Instruction Execution Time
240 ns at 25 MHz f (minimum)
•
•
•
Eight analog input pins
•
OSC
8-bit conversion resolution
7.68-µs conversion speed (25-MHz CPU clock)
Interrupts
•
•
•
20 interrupt sources and 19 interrupt vectors
Seven interrupt levels
Operating Temperature Range
° °
– 20 C to + 85 C
•
Fast interrupt processing (level0 and 3-7 only)
Operating Voltage Range
4.5 V to 5.5 V
Timer/Counters
•
•
Two 8-bit timers with interval timer or PWM
mode (timers A and B)
Package Type
80-pin QFP, 80–pin TQFP
•
Two 16-bit timer/counters with four
programmable operating modes (timers C and
D)
•
1–3
PRODUCT OVERVIEW
S3C8444
BLOCK DIAGRAM
EXTERNAL ADDRESS/DATA BUS
P0.0–P0.7
(A8–A15)
P1.0–P1.7
(AD0–AD7)
P2.0–P2.5
(Control Signal)
PORT 0
PORT 1
PORT 2
RESET
EA
PORT 3
P3.0–P3.7
SAM8 BUS
P2.6
PORT2
P2.7
PORT I/O & INTERRUPT
CONTROL
PORT 4
P4.0–P4.7
TA
TB
TIMERS
A and B
P5.0–P5.3
P5.4–P5.7
SAM8 CPU
PORT 5
PORT 6
TCCK
TDCK
TCG
TIMERS
C and D
TDG
1040-BYTE
REGISTER FILE
P6.0–P6.7
RxD
TxD
SERIAL
PORT
V
DD1
,V
SS1
SAM8 BUS
V
DD2
,V
SS2
AV
PWM
MODULE
SS
A/D
CONVERTER
CAPTURE (P3.6)
AV
REF
ADC0 /P7.0 –
ADC7 /P7.7
PWM0 PWM1
Figure 1–2. S3C8444 Block Diagram
1–4
S3C8444
PRODUCT OVERVIEW
PIN ASSIGNMENTS
1
P0.1 / A9
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RESET
NC
2
P0.0 / A8
P5.7
3
AS
4
P5.6
VSS1 (int.)
XOUT
5
P5.5
6
P5.4
XIN
7
P5.3
P6.0
8
P5.2
P6.1
9
P5.1
P6.2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P5.0
P6.3
VDD2 (ext. )
P2.7 / TB
P2.6 / TA
P6.4
S3C8444
80-QFP
(TOP VIEW)
P6.5
P6.6
P2.5 /
P2.4 /
P2.3 /
P2.2 /
P2.1 /
P2.0 /
P6.7
PM
MR
DM
MW
DS
P7.7 / ADC7
P7.6 / ADC6
P7.5 / ADC5
P7.4 / ADC4
P7.3 / ADC3
AVSS
AS
RxD
TxD
P7.2 / ADC2
P7.1 / ADC1
AVREF
P7.0 / ADC0
PWM1
PWM0
P3.0 / TCCK / INT0
Figure 1–3. S3C8444 Pin Assignments
1–5
PRODUCT OVERVIEW
S3C8444
PIN ASSIGNMENTS (Continued)
Vss1 (int.)
P0.0 / A8
P5.7
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
X
OUT
X
IN
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.7 / ADC7
P7.6 / ADC6
P7.5 / ADC5
P7.4 / ADC4
P7.3 / ADC3
9
S3C8444
80-TQFP
(TOP VIEW)
V
(ext.
10
11
12
13
14
15
16
17
18
19
20
DD2
)
P2.7 / TB
P2.6 / TA
P2.5 /
P2.4 /
PM
MR
P2.3 / DM
P2.2 /
P2.1 /
P2.0 /
MW
DS
AS
AV
SS
P7.2 / ADC2
P7.1 / ADC1
RxD
TxD
AV
REF
Figure 1–4. S3C8444 Pin Assignments
1–6
S3C8444
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1–1. S3C8444 Pin Descriptions
Pin
Name
Pin
Type
Pin
Description
Circuit
Type
QFP Pin
Number
Share
Pins
P0.0 - P0.7
I/O
Nibble programmable port; input or output mode
selected by software; Schmitt trigger input or push-
pull, open-drain output with software assignable
pull-ups; alternately configurable as external
interface address lines A8 - A15.
3
2, 1,
80-75
A8 - A15
P1.0 - P1.7
P2.0 - P2.7
I/O
I/O
Same general characteristics as port 0; alternately
configurable as external interface address/data
lines AD0 - AD7.
3
5
73-66
AD0 - AD7
General I/O port with Schmitt trigger input or push-
pull output. bit programmable;
19 - 12
AS, DS,
MW, DM,
P2.0 / Address Strobe (AS)
P2.1 / Data Strobe (DS)
MR, PM,
TA, TB
P2.2 / Memory Write (MW)
P2.3 / Data Memory select (DM)
P2.4 / Memory Read (MR)
P2.5 / Program Memory select (PM)
P2.6 / timer A output (TA)
P2.7 / timer B output (TB)
P3.0 - P3.7
I/O
General I/O port with bit programmable pins.
Schmitt trigger input or push-pull output with
software assignable pull-ups. Input or output mode
is selectable by software. P3.0 - P3.3 are alternately
used as inputs for external interrupts INT0-INT3,
respectively (with noise filters and interrupt control):
P3.0 / timer C clock input (TCCK) / INT0
P3.1 / timer D clock input (TDCK) / INT1
P3.2 / timer C gate input (TCG) / INT2
4
24-31
(See pin
description)
P3.3 / timer D gate input (TDG) / INT3
P3.6 / Capture data input (CAP)
P3.7 / WAIT for slow memory interface
P4.0 - P4.7
I/O
General I/O port with bit programmable pins.
Schmitt trigger input or push-pull, open-drain output
with software assignable pull-ups. Input or output
mode is selectable by software. P4.0-P4.7 can
alternately be used as inputs for external interrupts
INT4-INT11, respectively (with noise filters and
interrupt control)
4
33-40
INT4 -
INT11
1–7
PRODUCT OVERVIEW
S3C8444
Table 1–1. S3C8444 Pin Descriptions (Continued)
Pin
Name
Pin
Type
Pin
Description
Circuit
Type
QFP Pin
Number
Share
Pins
I/O
3
10–3
—
P5.0–P5.7
General I/O port with nibble programmable
pins. Schmitt trigger input or push-pull,
open-drain output mode. Mode and pull-ups
are assigned by software.
O
I
8
2
58–51
—
P6.0–P6.7
N-channel, open-drain output port; the pin
circuits can withstand loads up to 9 volts.
41, 43–44, P7.0–P7.7
46–50
ADC0–ADC7
Analog input pins for A/D converter module.
Alternatively used as general-purpose
digital input port 7.
AVREF, AVSS
RxD
—
I/O
O
—
6
42, 45
20
—
A/D converter reference voltage and
ground
—
—
Serial data RxD pin for receive input and
transmit output (mode 0)
7
21
TxD
Serial data TxD pin for transmit output and
shift clock input (mode 0)
O
7
23, 22
—
PWM0,
PWM1
Pulse width modulation output pins
O
I
5
4
13, 12
P2.6, P2.7
TA, TB
Output pins for timer A and timer B
External interrupt input pins
24–27,
33–40
P3.0–P3.3,
P4.0–P4.7
INT0–INT11
I
I
I
I
4
4
4
4
24, 25
26, 27
30
P3.0, P3.1
P3.2, P3.3
P3.6
TCCK, TDCK
TCG, TDG
CAP
External clock input for timer C and timer D
Gate input pins for timer C and timer D
Capture data input for PWM module
31
P3.7
Input pin for the slow memory timing signal
from the external interface
WAIT
I
I
1
64
65
—
—
System reset pin (pull-up resistor: 220 kW)
RESET
—
EA
External access (EA) pin with two modes:
5 V input: normal ROM-less operation with
external interface (0 V is not allowed)
9 V–10 V input: for factory test mode
VDD1, VSS1
—
—
74, 61
—
Power input pins for CPU operation
(internal)
VDD2, VSS2
XIN, XOUT
AS
—
—
O
—
—
7
11, 32
59, 60
62
—
—
—
—
Power input pins for port output (external)
Main oscillator pins
Address strobe
—
No connection pins (connect to V
)
SS
—
62, 63
NC
NOTE VDD1 must be connected to VDD2 in users application circuit, VSS1 & VSS2 also.
1–8
S3C8444
PRODUCT OVERVIEW
PIN CIRCUITS
Table 1–2. Pin Circuit Assignments for the S3C8444
Circuit Number
Circuit Type
S3C8444 Assignments
1
2
3
4
5
Input
Input
I/O
RESET pin
A/D converter input pins, ADC0–ADC7
Port 0, 1, and 5
I/O
Ports 3 and 4, TCCK, TDCK, TCG, TDG, CAP, WAIT, INT0–INT11
I/O
Port 2 (AS, DS, MW, DM, MR, PM, TA,TB)
6
7
I/O
Serial port RxD pin
Output
Serial port TxD pin, PWM0, PWM1 and AS
8
Output
Port 6 (n-channel, open-drain output with high current capability)
1–9
PRODUCT OVERVIEW
S3C8444
INPUT
V
DD
BUFFER
PULL-UP
RESISTOR
(Typical 230 kW)
IN
+
–
ADC
LOGIC
INPUT
V
REF
Figure 1–6. Pin Circuit Type 2 (ADC0–ADC7)
Figure 1–5. Pin Circuit Type 1 (RESET)
1–10
S3C8444
PRODUCT OVERVIEW
V
DD
PULL-UP
RESISTOR
(Typical 46 kW)
PULL-UP
ENABLE
V
DD
DATA
IN / OUT
OPEN-
DRAIN
OUTPUT
DISABLE
V
SS
INPUT
Figure 1–7. Pin Circuit Type 3 (Ports 0,1, and 5)
1–11
PRODUCT OVERVIEW
S3C8444
V
DD
PULL-UP
RESISTOR
W
)
(Typical 46 k
PULL-UP
ENABLE
V
DD
DATA
IN / OUT
OUTPUT
DISABLE
V
SS
INPUT
EXTERNAL
INTERRUPT
INPUT
NOISE
FILTER
Figure 1–8. Pin Circuit Type 4
(Ports 3 and 4, TCCK, TDCK, TCG, TDG, CAP, WAIT, INT0–INT11)
1–12
S3C8444
PRODUCT OVERVIEW
V
DD
SELECTION BITS
FOR PORTS OR
OTHER FUNCTIONS
DATA
IN / OUT
OPEN-
DRAIN
V
SS
OUTPUT
DISABLE
INPUT
OTHER
FUNCTION
Figure 1–9. Pin Circuit Type 5 (Port 2, AS, DS, MW, DM, MR, PM, TA and TB)
1–13
PRODUCT OVERVIEW
S3C8444
V
DD
EDGE DETECTION
V
DD
R
(46 k W)
DATA
IN / OUT
OUTPUT
DISABLE
V
SS
INPUT
NOISE FILTER
a
Figure 1–10. Pin Circuit Type 6 (Serial RxD Pin)
1–14
S3C8444
PRODUCT OVERVIEW
V
DD
OUTPUT
DATA
DATA
OUTPUT
V
SS
:
Circuit type 8 can withstand up to 9-volt loads.
NOTE
V
SS
Figure 1–11. Pin Circuit Type 7
(AS, serial TxD Pin, PWM0, PWM1)
Figure 1–12. Pin Circuit Type 8 (Port 6)
1–15
S3C8444
ELECTRICAL DATA
16 ELECTRICAL DATA
In this section, S3C8444 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— DC electrical characteristics
— AC electrical characteristics
— Input timing for external interrupts (ports 3 and 4)
— Input timing for RESET
— I/O capacitance
— Data retention supply voltage in Stop mode
— Stop mode release timing initiated by RESET
— A./D Converter Electrical Characteristics
— Serial port timing characteristics in mode 0 (10 MHz)
— Serial clock waveform
— Serial port timing in mode 0 (shift register mode)
— External memory timing characteristics (10 MHz)
— External memory read and write timing
— Recommended A/D converter circuit for highest absolute accuracy
— Main oscillator frequency (f
)
OSC1
— Main oscillator clock stabilization time (t
)
ST1
— Clock timing measurement at X
IN
— Suboscillator clock stabilization time (t
)
ST2
— Characteristic curves
16–1
ELECTRICAL DATA
S3C8444
Table 16–1. Absolute Maximum Ratings
Conditions
°
(T = 25 C)
A
Parameter
Symbol
Rating
Unit
V
Supply voltage
Input voltage
V
DD
– 0.3 to +7.0
– 0.3 to +10
V
Port 6 only (open-drain)
All ports except port 6
V
I1
I2
O
V
– 0.3 to V
+ 0.3
DD
Output voltage
V
– 0.3 to V
+ 0.3
V
DD
Output current
high
I
One I/O pin active
– 18
mA
OH
All I/O pins active
– 60
30
Output current low
I
One I/O pin active
mA
OL
Total pin current for ports 0, 2, 3, 4, 6
Total pin current for ports 1 and 5
100
200
Operating
temperature
T
– 20 to + 85
°
°
A
C
Storage
temperature
T
STG
– 65 to + 150
C
Table 16–2. D.C. Electrical Characteristics
°
°
(T = – 20 C to + 85 C, V
= 4.5 V to 5.5 V)
A
DD
Parameter
Input high
Symbol
Conditions
Min
Typ
Max
Unit
V
V
All input pins except V
0.8 V
–
V
DD
V
IH1
IH2
DD
voltage
X
IN
V
– 0.5
IH2
DD
Input low voltage
V
V
All input pins except V
–
–
–
0.2 V
DD
V
V
IL1
IL2
X
V
0.4
–
IL2
IN
Output high
voltage
V
OH1
= 4.5 V to 5.5 V
= – 1 mA
V
V
– 1.0
– 1.0
DD
DD
I
OH
Port 1 only
V
OH2
V
= 4.5 V to 5.5V
= – 200 µA
DD
DD
I
OH
All output pins except port 1
16–2
S3C8444
ELECTRICAL DATA
Table 16–2. D.C. Electrical Characteristics (Continued)
(T = – 20 C to + 85 C, V = 4.5 V to 5.5 V)
°
°
A
DD
Parameter
Output low
voltage
Symbol
Conditions
= 4.5 V to 5.5 V
Min
Typ
Max
Unit
V
V
I
–
–
0.4
V
OL1
OL2
DD
= 2 mA
OL
All output pins except port 5
V
V
I
= 4.5 V to 5.5 V
DD
= 1.5 mA
OL
Port 5
Input high leakage
current
I
I
V
= V
DD
–
–
–
–
3
µA
µA
LIH1
LIH2
IN
All input pins except X
IN
V
IN
X
IN
= V
20
– 3
DD
Input low leakage
current
I
V
IN
= 0 V
LIL1
LIL2
All input pins except X ,
IN
and RESET
I
V
IN
X
IN
= 0 V
– 20
5
Output high
leakage current
I
I
V
OUT
= V
DD
–
–
µA
LOH1
LOH2
All output pins except for
port 6
Port 6 (open-drain)
20
V
OUT
= 9 V
Output low
leakage current
I
V
= 0 V
–
–
– 5
80
µA
LOL
OUT
Pull-up resistor
R
V
IN
= 0 V; V = 5 V ± 10%
DD
30
46
kW
L1
L2
Ports 0, 1, 4, 5, and RxD
R
V
= 0 V; V = 5 V ± 10%
120
–
230
320
50
IN
RESET only
= 5 V ± 10%
DD
(1)
I
V
35
30
11
5
mA
DD1
DD2
DD3
DD
25 MHz crystal oscillator
Supply current
V
= 5 V ± 10%
DD
10 MHz crystal oscillator
I
I
Idle mode: V = 5 V ± 10%
DD
25 MHz crystal oscillator
25
20
Idle mode: V = 5 V ± 10%
10 MHz crystal oscillator
DD
Stop mode;
3
µA
V
DD
= 5 V ± 10%
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
16–3
ELECTRICAL DATA
S3C8444
Table 16–3. A.C. Electrical Characteristics
°
°
(T = – 20 C to + 85 C, V
= 4.5 V to 6.0V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Interrupt input
high, low width
t
t
P3.0–P3.3, P4.0–P4.7
3
–
–
t
INTH,
CPU
INTL
t
Input
22
–
–
t
RSL
CPU
RESET input low
width
NOTES:
1. The unit tCPU means one CPU clock period.
2. The oscillator frequency is the same as CPU clock frequency.
t
t
INTH
INTL
0.8 V
DD
0.2 V
DD
Figure 16–1. Input Timing for External Interrupts (Ports 3 and 4)
t
RSL
RESET
0.2 V
DD
Figure 16–2. Input Timing for RESET
16–4
S3C8444
ELECTRICAL DATA
Table 16–4. Input/Output Capacitance
= 0 V )
°
°
(T = – 20 C to + 85 C, V
A
DD
Parameter
Input
capacitance
Symbol
Conditions
f = 1 MHz; unmeasured pins
are returned to V
Min
Typ
Max
Unit
C
IN
–
–
10
pF
SS
Output
capacitance
C
OUT
I/O capacitance
C
IO
Table 16–5. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 20 C to + 85 C)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention
supply voltage
V
DDDR
2
–
6
V
Data retention
supply current
I
V
DDDR
= 2 V
–
–
5
µA
DDDR
OSCILLATION
STABILIZATION
TIME
RESET
OCCURS
NORMAL
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
V
DD
V
DDDR
EXECUTION OF
STOP INSTRUCTION
RESET
0.2 V
DD
:
t
is the same as 4096 x 32 x 1 / f
.
OSC
NOTE
WAIT
t
WAIT
Figure 16–3. Stop Mode Release Timing Initiated by RESET
16–5
ELECTRICAL DATA
S3C8444
Table 16–6. A/D Converter Electrical Characteristics
°
°
(T = – 20 C to + 85 C, V
= 4.5 V to 6.0 V, V = 0 V)
DD SS
A
Parameter
Resolution
Symbol
Conditions
Min
8
Typ
8
Max
8
Unit
bit
Absolute
accuracy
V
= 5.12 V
–
–
| 3 |
LSB
DD
CPU clock = 18 MHz
AV = 5.12 V
(1)
REF
AV = 0 V
SS
Conversion
time
t
–
–
–
µs
V
t
´
(3)
CON
CPU
(2)
192
Analog reference
voltage
AV
REF
2.56
V
DD
Analog ground
AV
V
–
–
–
V
V
SS
SS
Analog input
voltage
V
IAN
AV
AV
SS
REF
Analog input
impedance
R
AN
2
–
–
M½
NOTES:
1. Excluding quantization error, absolute accuracy equals ± 1/2 LSB.
2. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.
3. is the CPU clock period.
t
CPU
Table 16–7. Serial Port Timing Characteristics in Mode 0 (10 MHz)
°
°
(T = – 20 C to + 85 C, V
= 4.5 V to 6.0V, V = 0 V)
DD SS
A
Parameter
Symbol
Min
Typ
Max
Unit
Serial port clock cycle time
t
500
700
–
ns
t
t
´ 6
SCK
CPU
Output data setup to clock rising edge
Clock rising edge to input data valid
Output data hold after clock rising edge
Input data hold after clock rising edge
Serial port clock high, low width
t
t
300
–
´ 5
S1
S2
H1
H2
CPU
–
300
–
t
t
50
0
t
CPU
–
–
t
,
200
400
t
´ 3
HIGH
CPU
t
LOW
NOTES:
1. All times are in ns and assume a 10 MHz input frequency.
2. The unit t means one CPU clock period.
CPU
3. The oscillator frequency is identical to the CPU clock frequency.
16–6
S3C8444
ELECTRICAL DATA
t
HIGH
0.8 V
DD
0.2 V
DD
t
LOW
t
SCK
Figure 16–4. Serial Clock Waveform
16–7
ELECTRICAL DATA
S3C8444
Figure 16–5. Serial Port Timing in Mode 0 (Shift Register Mode)
16–8
S3C8444
ELECTRICAL DATA
Table 16–8. External Memory Timing Characteristics (10 MHz)
°
°
(T = – 20 C to + 85 C, V
= 4.5 V to 6.0 V)
DD
A
Number
Symbol
Parameter
Normal Timing
Extended Timing
Min
Max
Min
Max
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
(AS)
10
–
50
–
dA
Address valid to AS • delay
AS • to address float delay
AS • to read data required valid
AS low width
(A)
35
–
–
140
–
85
–
–
335
–
dAS
dAS
wAS
3
(DR)
4
35
0
85
0
5
(DS)
–
–
dA
Address float to DS ¯
6a
6b
7
(read)
(write)
(DR)
(DR)
(A)
125
65
–
–
275
165
–
–
wDS
wDS
dDS
hDS
dDS
dDS
dDO
dAS
hDS
dRW
dDS
DS (read) low width
–
–
DS (write) low width
80
–
255
–
DS ¯ to read data required valid
Read data to DS • hold time
DS • to address active delay
DS • to AS ¯ delay
8
0
0
9
20
30
10
–
–
70
80
50
–
–
10
11
12
13
14
15
(AS)
(DS)
(W)
–
–
–
–
Write data valid to DS (write) ¯ delay
AS • to wait delay
90
–
335
–
(W)
0
0
DS • to wait hold time
(AS)
(DW)
20
20
–
70
70
–
R/W valid to AS • delay
DS • to write data not valid delay
–
–
NOTES:
1. All times are in ns and assume a 10 MHz input frequency.
2. Wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7.
3. Auto-wait states add 100 ns to the time of number 12.
16–9
ELECTRICAL DATA
S3C8444
R/
W
14
PORT A
A8–A15,
DM
DM
3
9
PORT AD
A0–A7
D0–D7 OUT
11
D0–D7
IN
8
OUT
10
1
4
2
5
AS
7
DS
6
15
WAIT WINDOW
(P3.7)
WAIT
12
13
Figure 16–6. External Memory Read and Write Timing
(See Table 15–7 for a description of each timing point.)
16–10
S3C8444
ELECTRICAL DATA
V
DD
REFERENCE
VOLTAGE
INPUT
R
AV
REF
+
–
C
10 µF
103
V
DD
ANALOG
INPUT PIN
ADC0–ADC7
S3C8444
C 101
AV
SS
V
SS
: The symbol 'R' signifies an offset resistor with a value of from 50 to 100 Ohms.
NOTE
If this resistor is omitted, the absolute accuracy will be maximum of 4 LSBs.
Figure 16–7. Recommended A/D Converter Circuit for Highest Absolute Accuracy
16–11
ELECTRICAL DATA
S3C8444
Table 16–9. Main Oscillator Frequency (f
)
OSC1
°
°
(T = – 20 C + 85 C, V
= 4.5 V to 6.0 V)
DD
A
Oscillator
Crystal
Clock Circuit
Test Condition
Min
Typ
Max
Unit
CPU clock oscillation
frequency
1
–
18
MHz
C1
XIN
XOUT
C2
C1
Ceramic
CPU clock oscillation
frequency
1
1
–
–
18
18
MHz
MHz
XIN
XOUT
C2
External clock
X
IN
input frequency
a
XIN
XOUT
a
Table 16–10. Recommended Oscillator Constants
°
°
(T = – 20 C + 85 C, V
= 4.5 V to 6.0 V)
DD
A
Manufacturer
Product Name
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
5
C2
5
MIN
4.5
4.5
4.5
MAX
5.5
TDK
CCR20.0MS6
CCR24.0M6
CCR25.0M6
SMD Type
SMD Type
SMD Type
5
5
5.5
–
5
5.5
NOTE: On-chip C: 30pF ±20% built in.
16–12
S3C8444
ELECTRICAL DATA
Table 16–11. Main Oscillator Clock Stabilization Time (t
)
ST1
°
°
(T = – 20 C + 85 C, V
A
= 4.5 V to 6.0 V)
DD
Oscillator
Test Condition
= 4.5 V to 6.0 V
Min
–
Typ
–
Max
20
Unit
ms
Crystal
V
DD
Ceramic
Stabilization occurs when V
oscillator voltage range.
is equal to the minimum
–
–
10
ms
DD
External clock
X
IN
input high and low level width (t , t
)
25
–
500
ns
XH XL
NOTE: Oscillation stabilization time (t
) is the time required for the CPU clock to return to its normal oscillation
ST1
frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. The RESET should therefore
be held at low level until the t
time has elapsed (see Figure 15–3).
ST1
1 / f
OSC1
t
t
XH
XL
V
V
– 0.5
X
DD
IN
0.4 V
Figure 16–8. Clock Timing Measurement at X
IN
16–13
ELECTRICAL DATA
S3C8444
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements. They do
not, however, represent guaranteed operating values.
(T = 25 °C)
A
38
36
34
32
f
= 25 MHz
OSC
f
= 20 MHz
= 10 MHz
OSC
f
30
28
26
24
22
OSC
4.5
5.0
(V)
5.5
V
DD
Figure 16–9. IDD1 vs VDD
16–14
S3C8444
ELECTRICAL DATA
(T = 25 °C)
A
13
12
11
10
9
f
= 25 MHz
= 20 MHz
OSC
f
f
OSC
OSC
8
7
= 10 MHz
6
5
4
4.5
5.0
(V)
5.5
V
DD
Figure 16–10. IDD2 vs VDD
(T = 25 °C)
A
280
260
240
220
200
180
160
140
120
100
4.5
5.0
5.5
V
(V)
DD
Figure 16–11. IDD3 vs VDD
16–15
ELECTRICAL DATA
S3C8444
(T = 25 °C)
A
18
16
14
12
V
DD
= 5.5 V
10
8
V
DD
= 4.5 V
6
4
2
0
0.2
0.4
0.6
(V)
0.8
1.0
1.2
V
OL1
Figure 16–12. IOL vs VOL1
16–16
S3C8444
ELECTRICAL DATA
(T = 25 °C)
A
18
16
14
12
V
DD
= 5.5 V
10
8
V
DD
= 4.5 V
6
4
2
0
0.2
0.4
0.6
(V)
0.8
1.0
1.2
V
OL2
Figure 16–13. IOL vs VOL2
16–17
ELECTRICAL DATA
S3C8444
(T = 25 °C)
A
-12
-11
-10
-9
-8
V
DD
= 5.5 V
-7
-6
-5
-4
-3
-2
-1
0
V
DD
= 4.5 V
2.4
3.0
3.6
(V)
4.2
4.8
5.4
V
OH2
Figure 16–14. IOH vs VOH2
16–18
S3C8444
MECHANICAL DATA
17 MECHANICAL DATA
23.90
20.00
± 0.3
± 0.2
0~8°
+0.10
- 0.05
0.15
0.10 MAX
80-QFP-1420C
#80
0.05 MIN
#1
2.65
± 0.10
0.80
(0.80)
0.35
± 0.1
3.00 MAX
±
0.15 MAX
0.80
± 0.20
: Dimensions are in millimeters.
NOTE
Figure 17–1. S3C8444 QFP Standard Package Dimensions (in Millimeters)
17–1
MECHANICAL DATA
S3C8444
14.00BSC
12.00BSC
0~7°
0.09~0.20
0.10 MAX
80-TQFP-1212-AN
0.25GAUGE PLANE
0.05~0.15
#80
± 0.05
1.00
#1
1.20 MAX
0.50
(1.25)
0.17~0.27
0.08 MAX M
±
NOTE
: Dimensions are in millimeters.
Figure 17–2. S3C8444 TQFP Standard Package Dimensions (in Millimeters)
17–2
S3C8444
DEVELOPMENT TOOLS
18 DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with MS-DOS as its operating system can be used. Two types of debugging
tools including hardware and software are provided: the in-circuit emulator, SMDS2, developed for S3C1, S3C7,
S3C8 families of microcontrollers, and even more sophisticated and powerful in-circuit emulator, SMDS2+, for
S3C7, S3C8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. In the future
SMDS2+ will replace SMDS2 and eventually SMDS2 will not be supported. Samsung also offers support
software that includes debugger, assembler, and a program for setting options.
DEVELOPMENT TOOLS VERSIONS
As of the date of this publication, two versions of the SMDS are being supported:
— SMDS2 Version 5.3 (S/W) and SMDS2 Version 1.3 (H/W); last release: October, 1995.
— SHINE Version 1.0 (S/W) and SMDS2+ Version 1.0 (H/W); last release: January, 1997.
SMDS V5.3
SMDS V5.3 is an assembly level debugger with user-friendly host interfacing that uses in-circuit
emulator,SMDS2.
SHINE
Samsung Host Interface for iN-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked
help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be
sized, moved, scrolled, highlighted, added, or removed completely.
SAMA ASSEMBLER
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates
object code in standard hexadecimal format. Assembled program code includes the object code that is used for
ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and
an auxiliary definition (DEF) file with device specific information.
SASM88
The SASM88 is an relocatable assembler for Samsung's S3C8-series microcontrollers. The SASM88 takes a
source file containing assembly language statements and translates into a corresponding source code, object
code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating
system. It produces the relocatable object code only, so the user should link object file. Object files can be linked
with other object files and loaded into memory.
18–1
DEVELOPMENT TOOLS
HEX2ROM
S3C8444
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by
HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device
automatically.
TARGET BOARDS
Target boards are available for all S3C8-series microcontrollers. All required target system cables and adapters
are included with the device-specific target board.
IBM-PC AT
or
RS-232C
Internal BUS
Compatible
5-Volt
Power
Supply
Personality
Board
Main Board
Front
Panel
Board
POD
TB8444
Target
Board
Target
Application
System
Target Cable
EVA
Chip
Figure 18–1. SMDS Product Configuration (SMDS2)
18–2
S3C8444
DEVELOPMENT TOOLS
IBM-PC AT or Compatible
RS-232C
SMDS2+
Target
Application
System
PROM/MTP Writer Unit
RAM Break/Display Unit
Trace/Timer Unit
Target
Cable
TB8444
Target
Board
POD
SAM8 Base Unit
EVA
Chip
Power Supply Unit
Figure 18–2. SMDS Product Configuration (SMDS2+)
18–3
DEVELOPMENT TOOLS
S3C8444
TB8444 TARGET BOARD
The TB8444 target board is used for the S3C8444 microcontroller. It is supported by the SMDS2 or SMDS2+
development system.
TB8444
To User_VCC
Off
On
RESET1
Stop
+
Idle
+
25
J101
J102
1
2
1
2
144 QFP
S3E8440
EVA Chip
CN1
1
39
40 39
40
External
Triggers
CH1
CH2
SM1296A
Figure 18–3. TB8444Target Board Configuration
18–4
S3C8444
DEVELOPMENT TOOLS
Table 18–1. Power Selection Settings for TB8444
Operating Mode
'To User_Vcc' Settings
Comments
The SMDS2/SMDS2+ main
To User_Vcc
board supplies V
to the
CC
Target
System
TB8444
VCC
VSS
OFF
ON
target board (evaluation chip)
and the target system.
a
VCC
SMDS2/SMDS2+
The SMDS2/SMDS2+ main
To User_Vcc
External
VCC
board supplies V
only to
CC
Target
System
TB8444
OFF
ON
the target board (evaluation
chip). The target system must
have its own power supply.
a
VSS
VCC
SMDS2/SMDS2+
NOTE: The following symbol in the 'To User_Vcc' Setting column indicates the electrical short configuration:
a
Table 18–2. Using Single Header Pins as the Input Path for External Trigger Sources
Target Board Part
Comments
Connector from
external trigger
sources of the
application system
EXTERNAL
TRIGGERS
CH1
CH2
You can connect an external trigger source to one of the two external
trigger channels (CH1 or CH2) for the SMDS2/SMDS2+ breakpoint
and trace functions.
18–5
DEVELOPMENT TOOLS
S3C8444
Table 18–3. Analog Pin Connection Switch Settings (TB8444)
Analog Pin Switch
DIP SW1: ON
Operating Mode
ANALOG SIGNALS
•
•
•
TARGET
BOARD
TARGET
SYSTEM
DIP SW1: OFF
TARGET
BOARD
•
•
•
•
•
•
TARGET
SYSTEM
ADC0
|
ADC7
HOLES DRILLED
FOR DIRECT CONNECTION
NOTE: Analog signals coming into the target board can easily introduce noise into the analog converter circuit. This can
cause invalid conversion results. To reduce noise, you can use the analog pin switches to provide the shortest
possible path for analog signals. To do this, turn all DIP switches to the OFF position. Then, connect the analog
signal lines directly via the holes of the corresponding analog pins.
IDLE LED
The Green LED is ON when the evaluation chip(S3E8440) is in idle mode.
STOP LED
The Red LED is ON when the evaluation chip(S3E8440) is in stop mode.
18–6
S3C8444
DEVELOPMENT TOOLS
J101
J102
1
2
4
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
A9
P5.7
P5.5
P5.3
A8
P7.0/ADC0
P7.1/ADC1
AV
REF
3
P5.6
P5.4
P5.2
P5.0
P2.7/TB
PM
P7.2/ADC2
P7.3/ADC3
P7.5/ADC5
P7.7/ADC7
P6.6
P6.4
P6.2
P6.0
NC(X
NC
RESET
AD7
AD5
AD3
5
6
AV
SS
7
8
P7.4/ADC4
P7.6/ADC6
P6.7
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P5.1
VDD2
P2.6/TA
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P6.5
P6.3
P6.1
DM
DR
DS
DW
AS
PXD
PWM1
NC(X
V
)
)
OUT
IN
TXD
PWM0
P3.1/TDCK/INT1
P3.3/TDG/INT3
P3.5
SS1
NC
P3.0/TCCK/INT0
P3.2/TCG/INT2
P3.4
P3.6/CAP
VSS2
P4.1/INT5
P4.3/INT7
P4.5/INT9
P4.7/INT11
EA
AD6
AD4
AD2
AD0
A15
A13
A11
WAIT
P3.7/
AD1
P4.0/INT4
P4.2/INT6
P4.4/INT8
P4.6/INT10
V
DD1
A14
A12
A10
Figure 18–4. 40-Pin Connectors for TB8444 (S3C8444, 80-QFP Package)
18–7
DEVELOPMENT TOOLS
S3C8444
TARGET BOARD
TARGET SYSTEM
J101
J102
80-QFP Adapter
Order Code: SM6402
1
2
41 42
Target Cable for 80 QFP Adapter
Part Name: CS80QF
Order Code: SM6501
40
79 80
39
:
Two 40-pin flat cables can be used instead of the target cable and the 80-QFP adapter
to connect the target board and the target system.
NOTE
Figure 18–5. TB8444 Cable for 80-QFP Adapter
18–8
相关型号：
S3C8454XX-TW
Microcontroller, 8-Bit, MROM, SAM87RC CPU, 25MHz, CMOS, PQFP80, 12 X 12 MM, TQFP-80
SAMSUNG
S3C8475XX-AQ
Microcontroller, 8-Bit, MROM, SAM87RC CPU, 12MHz, CMOS, PDIP42, 0.600 INCH, SDIP-42
SAMSUNG
©2020 ICPDF网 联系我们和版权申明