S3C8454 [SAMSUNG]
S3C8454 MICROCONTROLLER; S3C8454微控制器
| 型号： | S3C8454 |
| 厂家： | 
SAMSUNG |
| 描述： | S3C8454 MICROCONTROLLER |
| 文件： | 总32页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C8454/P8454
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM87 RC PRODUCT FAMILY
Samsung's new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a
wide range of integrated peripherals, and various mask-programmable ROM sizes. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM87RC microcontrollers have
an external interface that provides access to external memory and other peripheral devices. The sophisticated
interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and
vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.
S3C8454 MICROCONTROLLER
The S3C8454 single-chip microcontroller is fabricated using a highly advanced CMOS process. Its design is
based on the powerful SAM87RC CPU core. Stop and Idle power-down modes were implemented to reduce
power consumption. The size of the internal register file is logically expanded, increasing the addressable on-chip
register space to 1040 bytes. A flexible yet sophisticated external interface is used to access up to 64-Kbytes of
program and data memory. The S3C8454 is a versatile microcontroller that is ideal for use in a wide range of
general-purpose applications such as CD-ROM/DVD-ROM drives.
Using the SAM87RC modular design approach, the following peripherals were integrated with the SAM87RC
CPU core:
— Five configurable 8-bit general I/O ports
— One 2-bit general I/O ports
— Full-duplex serial data port with one synchronous operating modes
— Two 8-bit timers with interval timer
— Two 16-bit timers/counters with PWM operating modes or capture modes
— One voltage level detector pin
— Four embedded chip selection pins (CS0–CS4) or normal I/O ports
— Two programmable 8-bit PWM modules with corresponding output pins
— A/D converter with 4 selectable input pins
OTP
The S3C8454 microcontroller is also available in OTP(One Time Programmable) version, S3P8454
The S3P8454 microcontroller has an on-chip 4K-byte one-time-programmable EPROM instead of masked ROM.
The S3P8454 is comparable to S3C8454, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS88C4504/P4504
FEATURES
CPU
General I/O Ports
•
SAM87RC CPU core
•
•
•
Five 8-bit general I/O ports (port 0, 1, 2, 3, 4)
One 2-bit general I/O port (port 5)
Port 2 can drive LED directly
Memory
•
•
1040-byte internal register file
4-Kbyte internal program memory
Interrupts
•
•
•
Six edge-driven external interrupts
External Interface
Two level-driven external interrupts
Fast interrupt mode processing
•
•
64 Kbyte external data memory
64 Kbyte external program memory area
(ROMless)
PWM
•
60 Kbyte external program memory and 4 Kbyte
internal program memory
•
•
•
Four output channels
(PWM0, PWM1, TCPWM, TDPWM)
8-bit resolution with a 4-bit prescaler
(PWM0, PWM1)
ADC
•
•
Can be used as a general input/output port
From 16-bit counter (Timer C/D)
(TCPWM, TDPWM)
8-bit resolution four channels
SIO
Embedded chip selection
•
•
•
•
8-bit transmit/receive mode
•
To reduce interface glue logic, chip selection
logic is bold
8-bit receive mode
LSB-first or MSB-first transmission selectable
Internal or external clock mode
Voltage level detector
•
To prevent MCU from malfunctioning in an
unstable power level, a voltage level detector
circuit is inserted
8-bit Timers
Two 8-bit timers with interval timer mode
(Timer A and B)
•
Operating Voltage Range
2.7 V to 5.5 volts (@12 MHz)
•
16-bit Timer/Counters
•
•
•
•
Two programmable 16-bit timer/counters
Interval, or event counter mode operation
16-bit capture and 16-bit PWM mode
Internal or external clock source
Operating Temperature Range
° °
– 40 C to + 85 C
•
Package Types
80-pin QFP or TQFP
•
Basic Timer (Watchdog Timer)
Operating frequency
25 MHz (4.5 V to 5.5 V)
•
•
Overflow signal makes a system reset
8-bit timer with interval timer mode
•
1-2
S3C8454/P8454
PRODUCT OVERVIEW
BLOCK DIAGRAM
External Address/Data
(A0-A7)
(A8-A15)
(D0-D7)
External Interface Block
SAM8 BUS
RESET
EA
P0.0-P0.3
P5.1
Port 0
Port 1
Port 2
Port 3
P0.4-P0.7/
ADC0-ADC3
Port 5
P5.0(WAIT
)
Port I/O
& Interrupt
Control
Watchdog
Timer
Port4/
Chip
Selection
Logic
P1.0-P1.4
P1.5-P1.7/
SI, SO, SCK
P4.0-P4.7/
CS0-CS4
Timers
A and B
SAM87 RC CPU
P2.0-P2.7/
INT0-INT7
TCCK
TDCK
TCOUT
TDOUT
Timers
C and D
P3.0-P3.7/
TDCK, TCCK
TDCAP, TCCAP
TCOUT, TDOUT
PWM0, PWM1
1040-Byte
Register File
SO
SI
SCK
Serial
Port
SAM8 BUS
V
DD1,
DD2,
V
SS1
AVSS
V
VSS2
(Internal)
A/D
Converter
4-Kbyte
ROM
PWM
Module
AVREF
ADC0/P0.4-
ADC3/P0.7
PWM0 PWM1
Figure 1-1. S3C8454 Block Diagram
1-3
PRODUCT OVERVIEW
KS88C4504/P4504
PIN ASSIGNMENT
PM
DM
RD
WR
VLD
P5.1
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D7
D6
D5
D4
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P5.0/WAIT
CS3/P4.7
CS2/P4.6
CS1/P4.5
CS0/P4.4
VDD1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
KS88C4504
80-QFP
(Top View)
VSS1
XOUT
XIN
EA
P4.3
P4.2
RESET
P4.1
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
P4.0
PWM1/P3.7
PWM0/P3.6
TDOUT/P3.5
Figure 1-2. S3C8454 Pin Assignments
1-4
S3C8454/P8454
PRODUCT OVERVIEW
PIN ASSIGNMENTS (Continued)
PM
DM
RD
WR
VLD
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
CS1/P4.5
CS0/P4.4
VDD1
9
VSS2
P0.3
KS88C4504
80-TQFP
(Top View)
10
11
12
13
14
15
16
17
18
19
20
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
VSS1
XOUT
XIN
EA
P4.3
P4.2
RESET
P4.1
Figure 1-3. S3C8454 Pin Assignments
1-5
PRODUCT OVERVIEW
KS88C4504/P4504
PIN DESCRIPTIONS
Table 1-1. S3C8454/P8454 Pin Descriptions
Pin Description
Pin
Name
Pin
Type
Circuit
Type
Pin
Number
Share
Pins
P0.0–P0.7
I/O
Bit programmable port; input or output mode
selected by software; normal input or push-pull
output with software assignable pull-up (P0.0–P0.3)
or pull-down (P0.4–P0.7). Alternately, P0.4–P0.7 can
be use as a ADC input port with
2, 3
56–54,
51, 49–46
ADC0–
ADC3
8-bit resolution.
P1.0–P1.7
I/O
Bit programmable port; input or output mode
selected by software; normal input or push-pull
output with software assignable pull-up. P1.5–P1.7
can be used as a synchronous SIO port
P1.5/SI
3
45–38
SI, SO,
SCK
P1.6/SO
P1.7/SCK
P2.0–P2.7
P3.0–P3.7
I/O
I/O
General I/O port with normal input or push-pull output
with software; assignable pull-up. Bit programmable.
Alternately, P2.0–P2.7 can be used as inputs for
external interrupts, INT0–INT7 (with noise filter and
interrupt control). INT0/INT1 is level interrupts.
4
37–30
29–22
INT0–
INT7
General I/O port with bit programmable pins.
Normal input or push-pull output with software
assignable pull-up. Input or output mode is selectable
by software. Respectively, each pin can serve as
(with noise filters):
3, 5
TDCK
TCCK
TDCAP
TCCAP
TDOUT/
TDPWM
TCOUT/
TCPWM
PWM0
P3.0/timer D clock input (TDCK)
P3.1/timer C clock input (TCCK)
P3.2/timer D capture input (TDCAP)
P3.3/timer C capture input (TCCAP)
P3.4/timer C out (TCOUT)/PWM out (TCPWM)
P3.5/timer D out (TDOUT)/PWM out (TDPWM)
P3.6/PWM0 output port
PWM1
P3.7/PWM1 output port
P4.0–P4.7
I/O
General I/O port with bit programmable pins.
Normal input or push-pull output with software
assignable pull-up. Input or output mode is selectable
by software. P4.0–P4.7 can alternately be used as
inputs for embedded chip selection output.
P4.4/CS0
3, 5
21, 20,
18, 17,
11–8
CS0–CS3
P4.5/CS1
P4.6/CS2
P4.7/CS3
1-6
S3C8454/P8454
PRODUCT OVERVIEW
Table 1-1. S3C8454/P8454 Pin Descriptions (Continued)
Pin
Name
Pin
Type
Pin
Description
Circuit
Type
QFP Pin
Number
Share
Pins
P5.0–P5.1
I/O
General I/O port with bit programmable pins.
Normal input or push-pull, output mode.
Alternately It can use as external interface
control signal P5.0/WAIT signal
5
2
7
WAIT
ADC0–ADC3
AVREF
I
Analog input pins for A/D converter module.
Alternatively used as general-purpose I/O
49–46
50
P0.4–P0.7
–
–
A/D converter reference voltage
AVSS is connected to ground internally
PWM0, PWM1
INT0–INT7
TCCK, TDCK
TCCAP,TDCAP
WAIT
O
I
Pulse width modulation output pins
External interrupt input pins
5
4
3
3
5
23,22
37–30
28,29
26,27
7
P3.6, P3.7
P2.0–P2.7
P3.1/P3.0
P3.3/P3.2
P5.0
I
External clock input for timer C and timer D
Timer C/ timer D capture input
I
I
Input pin for the slow memory timing signal
from the external interface
I
I
1
–
19
16
–
–
System reset pin (pull-up resistor: 240 kW)
RESET
EA
5V: ROMless operating
0V: internal 4 K and external 60 K
addressing mode
VDD1, VSS1
–
Power input pins for CPU operation (internal)
and Power input for OTP writing
–
12,13
–
VDD2, VSS2
XIN, XOUT
–
–
Power input pins for port output (external)
Main oscillator pins
–
–
3
53, 52
15, 14
–
–
I/O
synchronous SIO communication port
40,39,38
P1.5/P1.6
P1.7
SI, SO, SCK
A0–A15
D0–D7
O
I/O
O
Address output for external device
Data I/O for external device
6
7
–
65–80
57–64
1, 2
–
–
–
External memory selection output
PM,DM
RD,WR
O
O
Memory read/write output
–
5
3, 4
–
Embedded chip selection output
11–8
P4.4–P4.7
CS0–CS3
TCOUT,TDOUT
VLD
O
–
16-bit timer PWM mode output
Voltage Level Detect Pin
5
–
25, 24
5
P3.4, P3.5
–
NOTE: V
must be connected to V
in users application circuit, V
& V
also.
DD1
DD2
SS1
SS2
1-7
PRODUCT OVERVIEW
KS88C4504/P4504
PIN CIRCUITS
Table 1-2. Pin Circuit Assignments for the S3C8454/P8454
Circuit Number
Circuit Type
S3C8454 Assignments
1
2
3
4
5
Input
I/O
RESET pin
A/D converter input pins, ADC0–ADC3, P0.4–P0.7
Port 0, 1, 3, 4, and 5
I/O
I/O
P2 (INT0–INT7)
I/O
P3 (TDCK, TCCK, TDCAP, TCCAP, TCOUT, TDOUT, TCPWM,
TDPWM, PWM0, PWM1)
6
7
Output
I/O
A0–A15,PM, DM, RD, WR
D0–D7
1-8
S3C8454/P8454
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
(Typical 240 kW)
Input
Figure 1-4. Pin Circuit Type 1 (RESET)
VDD
Data
I/O
Output
Disable
Vss
Normal
Input
ADC Port
Selection
ADC In
Enable ADC
Pull-Down
Enable
Figure 1-5. Pin Circuit Type 2 (ADC0–ADC3)
1-9
PRODUCT OVERVIEW
KS88C4504/P4504
VDD
Pull-Up
Enable
VDD
Data
I/O
Output
Disable
Normal
Input
Noise
Filter
SCK Input
Figure 1-6. Pin Circuit Type 3
VDD
Pull-Up
Resistor
Pull-Up
Enable
VDD
Data
I/O
Output
Disable
Vss
External
Interrupt
Input
Noise Filter
Normal
Input
Figure 1-7. Pin Circuit Type 4
1-10
S3C8454/P8454
PRODUCT OVERVIEW
VDD
Pull-Up
Resistor
Pull-Up
Enable
Selection bits
for ports or
VDD
other function
Data
I/O
Output
Disable
Vss
Input
Other
Function
Figure 1-8. Pin Circuit Type 5
VDD
In
Out
Figure 1-9. Pin Circuit Type 6
1-11
PRODUCT OVERVIEW
KS88C4504/P4504
VDD
Data
I/O
Output
Disable
Normal
Input
Figure 1-10. Pin Circuit Type 7
1-12
S3C8454/P8454
ELECTRICAL DATA
18 ELECTRICAL DATA
OVERVIEW
In this section, S3C8454 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— A.C. electrical characteristics
— I/O capacitance
— Oscillation characteristics
— Oscillation stabilization time
18-1
ELECTRICAL DATA
S3C8454/P8454
Table 18-1. Absolute Maximum Ratings
Conditions
°
(TA = 25 C)
Parameter
Symbol
Rating
Unit
Supply voltage
VDD
– 0.3 to + 6.5
V
Input voltage
VI
VO
IOH
All ports (in input mode)
All ports (in output mode)
One I/O pin active
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 18
Output voltage
Output current high
V
mA
All I/O pins active
One I/O pin active
– 60
+ 30
Output current low
IOL
mA
Total pin current for port
+ 100
Operating
temperature
TA
– 40 to +85
°
°
C
Storage temperature
TSTG
– 65 to +150
C
18-2
S3C8454/P8454
ELECTRICAL DATA
Table 18-2. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
fOSC = 25 MHz
Min
Typ
Max
Unit
Operating voltage
VDD
4.5
–
5.5
V
(instruction clock = 6.25 MHz)
fOSC = 12 MHz
(instruction clock = 3 MHz)
2.7
–
–
5.5
Input high voltage
Input low voltage
VIH1
VIH2
All input pins except VIH2, VIH3
XIN
0.51 VDD
VDD – 0.5
VDD
V
V
VIH3
0.8VDD
–
Test, RESET
VIL1
VIL2
VIL3
All input pins except VIL2, VIL3
XIN
–
–
0.2 VDD
0.4
–
0.2VDD
Test, RESET
Output high voltage
Output low voltage
VOH
VDD= 5 V
IOH = – 1 mA
VDD – 1.0
–
V
V
IOH = – 100 uA
VDD – 0.5
–
–
–
–
VOL1
VDD = 5 V
0.4
IOL = 2 mA
All output pins except port 2
VOL2
ILIH1
ILIH2
ILIL1
VDD = 5 V
IOL = 15 mA, port 2
–
–
0.5
–
1.0
3
Input high leakage
current
VIN = VDD
All input pins except XIN
mA
VIN = VDD
XIN
20
– 3
Input low leakage
current
VIN = 0 V
All input pins except XIN and
–
–
RESET
ILIL2
VIN = 0 V,
– 20
XIN, RESET
Output high leakage
current
ILOH
VOUT = VDD
All I/O pins and output pins
–
–
–
5
Output low leakage
current
I
VOUT = 0 V
All I/O pins and output pins
– 0
46
– 5
80
LOL
Pull-up and pull-down
resistor
R
VIN = 0 V; VDD = 5 V ± 10%
30
kW
L1
L2
°
Ports 0-5, TA = 25 C
R
VIN = 0 V; VDD = 5 V ± 10%
120
240
320
°
TA = 25 C, RESET only
18-3
ELECTRICAL DATA
S3C8454/P8454
Table 18-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
VDD = 5 V ± 10 %
Min
Typ
Max
Unit
Supply current (note)
IDD1
20
40
14
16
6
mA
20 MHz oscillation
VDD = 2.7 V
12 MHz oscillation
7
8
IDD2
Idle mode; VDD = 5 V ± 10 %
20 MHz oscillation
Idle mode; VDD = 2.7 V
12 MHz oscillation
3
IDD3
Stop mode;
VDD = 5 V ± 10 %
110
220
mA
°
LVD enable, TA = 25 C
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Table 18-3. A.C. Electrical Characteristics
°
°
(T = -40 C to + 85 C)
A
Parameter
Symbol
tINTH
tINTL
Conditions
VDD = 5 V
Min
Typ
Max
Unit
Interrupt input high, low
width
(P2.0–P2.7)
180
–
–
nS
,
tRSL
VDD = 5 V
1000
–
–
nS
RESET input low width
NOTES:
1. The unit tCPU means one CPU clock period.
2. The oscillator frequency is the same as the CPU clock frequency.
tINTL
tINTH
0.8 VDD
0.2 VDD
Figure 18-1. Input Timing for External Interrupts (Ports 2)
18-4
S3C8454/P8454
ELECTRICAL DATA
tRSL
RESET
0.2 VDD
Figure 18-2. Input Timing for RESET
Table 18-4. Input/Output Capacitance
°
°
(TA = – 40 C to + 85 C, VDD = 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input capacitance
CIN
f = 1 MHz; unmeasured
pins are connected to VSS
–
–
10
pF
Output capacitance
I/O capacitance
COUT
CIO
Table 18-5. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply
voltage
VDDDR
2
–
5.5
V
Data retention supply
current
IDDDR
Stop mode, VDDDR = 2.0 V
–
–
50
mA
NOTES:
1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped.
2. Supply current does not include drawn through internal pull–up resistors and external output current loads.
18-5
ELECTRICAL DATA
S3C8454/P8454
Oscillation
Stabilization
Time
Reset
Occurs
Normal
Operating
Mode
Stop Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instrction
RESET
0.2 VDD
tWAIT
NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 18-3. Stop Mode Release Timing Initiated by RESET
18-6
S3C8454/P8454
ELECTRICAL DATA
Table 18-6. A/D Converter Electrical Characteristics
°
°
(T = – 40 C to + 85 C)
A
Parameter
Resolution
Symbol
Conditions
Min
–
Typ
8
Max
–
Unit
bit
Total accuracy
VDD = 5 V
–
–
± 2
LSB
Integral linearity error
Integral linearity error
ILE
Conversion time = 5 us
AVREF = 5 V
–
–
± 1
± 1
DLE
Offset error of top
Offset error of bottom
Conversion time (1)
Analog input voltage
Analog input impedance
Analog reference voltage
Analog ground
EOT
AVSS = 0 V
± 1
± 2
EOB
tCON
± 0.5
± 2
17
AVss
2
–
170
ms
VIAN
RAN
–
1000
–
AVREF
V
–
–
VDD
VSS+ 0.3
10
MW
V
AVREF
AVSS
IADIN
IADC
–
–
2.5
VSS
–
–
V
Analog input current
Analog block
AVREF = VDD = 5 V
AVREF = VDD = 5 V
AVREF = VDD = 3 V
–
uA
mA
mA
nA
1
3
current (2)
0.5
100
1.5
AVREF = VDD = 5 V
500
When power down mode
NOTES:
1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.
2. is an operating current during A/D conversion.
I
ADC
18-7
ELECTRICAL DATA
S3C8454/P8454
VDD
Reference
R
Voltage
Input
AVREF
+
C
10 pF
103
-
VDD
Analog
Input Voltage
ADC0-ADC3
S3C8454
C
101
VSS
NOTE: The symbol 'R' signifies an offset resistor with a value of from 50 to 100.
If this resistor is omitted, the absolute accuracy will be maximum of 3 LSBs.
Figure 18-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy
18-8
S3C8454/P8454
ELECTRICAL DATA
Table 18-7. Synchronous SIO Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 4.5 V to 5.5 V, VSS = 0 V, fOSC = 10 MHz oscillator)
Parameter
SCK cycle time
Symbol
Conditions
Min
Typ
Max
Unit
tCYC
–
200
–
–
nS
Serial clock high width
Serial clock low width
tSCKH
TSCKL
TOD
–
–
–
60
60
–
–
–
–
–
–
Serial output data delay
time
50
Serial input data set up
time
TID
TIH
–
–
40
–
–
–
–
Serial input data hold
time
100
tCYC
tSCKL
tSCKH
SCK
0.8 VDD
0.2 VDD
tID
tIH
0.8 VDD
0.2 VDD
SI
Input Data
tOD
SO
Output Data
Figure 18-5. Serial Data Transfer Timing
18-9
ELECTRICAL DATA
S3C8454/P8454
Table 18-8. Main Oscillator Frequency (fOSC1
)
°
°
(TA = – 40 C + 85 C, VDD = 4.5 V to 5.5 V)
Oscillator
Crystal
Clock Circuit
Test Condition
Min
Typ
Max
Unit
CPU clock oscillation
frequency
4
–
25
MHz
XIN
XOUT
C1
C2
Ceramic
CPU clock oscillation
frequency
4
4
–
–
25
MHz
MHz
XIN
XOUT
C1
C2
External clock
X
IN
input frequency
25
XIN
XOUT
Table 18-9. Main Oscillator Clock Stabilization Time (tST1
)
°
°
(TA = -40 C + 85 C, VDD = 4.5 V to 5.5 V)
Oscillator
Crystal
Ceramic
Test Condition
Min
Typ
Max
Unit
VDD = 4.5 V to 5.5 V
–
–
10
ms
Stabilization occurs when VDD is equal to the minimum
oscillator voltage range.
–
–
4
ms
External clock XIN input high and low level width (tXH, tXL)
50
–
–
ns
NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is ended by a RESET signal. The RESET should therefore
be held at low level until the t time has elapsed.
ST1
18-10
S3C8454/P8454
ELECTRICAL DATA
1/fOSC1
tXL
tXH
XIN
VDD - 0.5 V
0.4 V
Figure 18-6. Clock Timing Measurement at XIN
Table 18-10. Characteristics of Voltage Level Detect circuit
°
°
(T = – 40 C + 85 C)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operating Voltage of VLD
VDDVLD
–
2.7
–
5.5
V
Detect Voltage
VVLD
IVLD
–
1.15
–
1.40
100
1.51
200
V
Current consumption
VDD = 5.5 V
uA
18-11
ELECTRICAL DATA
S3C8454/P8454
fOSC
fCPU
B
25 MHz
6.25 MHz
18 MHz
16 MHz
4.5 MHz
4 MHz
14 MHz
12 MHz
3.5 MHz
3 MHz
A
4 MHz
1 MHz
1
2
3
4
5
6
7
4.5
2.7
Supply Voltage (V)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 18-7. Operating Voltage Range
18-12
S3C8454/P8454
MECHANICAL DATA
19 MECHANICAL DATA
OVERVIEW
The S3C8454 microcontroller is available in a 80-pin QFP package (80-QFP-1420C) and a 80-pin TQFP
package (80-TQFP-1212AN).
23.90 ± 0.30
0-8
20.00 ± 0.20
+ 0.10
- 0.05
0.15
0.10 MAX
80-QFP-1420C
#80
#1
0.35 + 0.10
0.05 MIN
0.80
0.15 MAX
(0.80)
2.65 ± 0.10
3.00 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 19-1. 80-QFP-1420C Package Dimensions
19-1
MECHANICAL DATA
S3C8454/P8454
14.00 BSC
12.00 BSC
0-7
0.09-0.20
80-TQFP-1212
#80
#1
0.17-0.27
0.05-0.15
1.00 ± 0.05
1.20 MAX
0.50
(1.25)
NOTE: Dimensions are in millimeters.
Figure 19-2. 80-TQFP-1212AN Package Dimensions
19-2
S3C8454/P8454
S3P8454 OTP
20 S3P8454 OTP
OVERVIEW
The S3P8454 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C8454
microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data
format.
S3P8454 is fully compatible with S3C8454, both in function and in pin configuration. As it has simple
programming requirements, S3P8454 is ideal for use as an evaluation chip for the S3C8454.
20-1
S3P8454 OTP
S3C8454/P8454
PM
DM
RD
WR
VLD
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D7
D6
D5
D4
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
SDAT/CS1/P4.5
SCLK/CS0/P4.4
VDD1/VDD1
VSS1/VSS1
XOUT
XIN
VPP/EA
P4.3
P4.2
RESET/RESET
P4.1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S3P8454
80-QFP
(Top View)
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P1.1
P1.2
P1.3
P1.4
P4.0
PWM1/P3.7
PWM0/P3.6
TDOUT/P3.5
NOTE: The bolds indicates OTP pin name.
Figure 20-1. S3P8454 Pin Assignments (80-QFP Package)
20-2
S3C8454/P8454
S3P8454 OTP
PM
DM
RD
WR
VLD
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
D3
D2
D1
D0
P0.0
P0.1
P0.2
VDD2
VSS2
P0.3
AVREF
P0.4/ADC0
P0.5/ADC1
P0.6/ADC2
P0.7/ADC3
P1.0
P5.1
P5.0/WAIT
CS3/P4.7
CS2/P4.6
9
S3P8454
80-TQFP
(Top View)
SDAT/CS1/P4.5
SCLK/CS0/P4.4
VDD1/VDD1
VSS1/VSS1
XOUT
XIN
VPP/EA
P4.3
P4.2
RESET/RESET
P4.1
10
11
12
13
14
15
16
17
18
19
20
P1.1
P1.2
P1.3
P1.4
Figure 20-2. S3P8454 Pin Assignments (80-TQFP Package)
20-3
S3P8454 OTP
S3C8454/P8454
Table 20-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P4.5
Pin Name
Pin No.
I/O
Function
SDAT
10
I/O
Serial data pin (Output when reading, Input when
writing) Input and push-pull output port can be assigned.
P4.4
EA
SCLK
VPP
11
16
I
I
Serial clock pin (Input only pin)
EPROM cell writing power supply pin (Indicates OTP
mode entering) When writing 12.5 V is applied and
when reading 5 V is applied (Option).
19
I
I
Chip Initialization
RESET
RESET
VDD1/VSS1
VDD/VSS
Logic Power Supply Pin. VDD should be tied to 5 V
during programming.
12/13
Table 20-2. Comparison of S3P8454 and S3C8454 Features
S3P8454
Characteristic
S3C8454
Program Memory
4 Kbyte EPROM
2.7 V to 5.5 V
4 Kbytes mask ROM
2.7 V to 5.5V
Operating Voltage (VDD
)
VDD = 5 V, VPP (TEST) = 12.5V
OTP Programming Mode
Pin Configuration
80 QFP, 80 TQFP
80 QFP, 80 TQFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of S3P8454, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 20-3 below.
Table 20-3. Operating Mode Selection Criteria
V
DD
VPP
(TEST)
REG
/MEM
Address
(A15–A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
20-4
S3C8454/P8454
S3P8454 OTP
D.C. ELECTRICAL CHARACTERISTICS
Table 20-4. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
fOSC = 25 MHz
Min
Typ
Max
Unit
VDD
Operating voltage
4.5
–
5.5
V
(instruction clock = 6.25 MHz)
fOSC = 12 MHz
2.7
–
–
5.5
(instruction clock = 3 MHz)
All input pins except VIH2, VIH3
VIH1
VDD
Input high voltage
Input low voltage
V
0.51 VDD
VIH2
VIH3
VIL1
VIL2
VIL3
VOH
XIN
VDD – 0.5
0.8VDD
–
Test, RESET
All input pins except VIL2, VIL3
0.2 VDD
–
–
V
V
XIN
0.4
–
0.2VDD
Test, RESET
VDD= 5 V
IOH = – 1 mA
VDD – 1.0
Output high voltage
Output low voltage
–
IOH = – 100 uA
VDD – 0.5
–
–
–
–
VOL1
VDD = 5 V, IOL = 2 mA
0.4
V
All output pins except port 2
VDD = 5 V, IOL = 15 mA, port 2
VOL2
ILIH1
–
–
0.5
–
1.0
3
VIN = VDD
Input high leakage
current
mA
All input pins except XIN
ILIH2
ILIL1
VIN = VDD, XIN
20
VIN = 0 V
All input pins except XIN and
Input low leakage
current
–
–
– 3
RESET
ILIL2
ILOH
– 20
5
VIN = 0 V, XIN, RESET
VOUT = VDD
Output high leakage
current
–
–
–
All I/O pins and output pins
VOUT = 0 V
I
Output low leakage
current
– 0
46
– 5
80
LOL
All I/O pins and output pins
VIN = 0 V; VDD = 5 V ± 10%
R
L1
Pull-up and pull-down
resistor
30
kW
°
Ports 0-5, TA = 25 C
R
L2
VIN = 0 V; VDD = 5 V ± 10%
120
240
320
°
TA = 25 C, RESET only
20-5
S3P8454 OTP
S3C8454/P8454
Table 20-4. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
VOUT = VDD
Min
Typ
Max
Unit
ILOH
Output high leakage
current
–
–
5
mA
All I/O pins and output pins
VOUT = 0 V
Output low leakage
current
ILOL
RL1
–
– 0
46
– 5
80
All I/O pins and output pins
Pull-up and pull-
down resistor
30
VIN = 0 V; VDD = 5 V ± 10 %
kW
°
Ports 0-5, TA = 25 C
RL2
120
–
240
320
VIN = 0 V; VDD = 5 V ± 10 %
°
TA = 25 C, RESET only
Supply current (note)
IDD1
VDD = 5 V ± 10 %
20
7
40
14
16
6
mA
20 MHz oscillation
VDD = 2.7 V
12 MHz oscillation
Idle mode; VDD = 5 V ± 10 %
20 MHz oscillation
Idle mode; VDD = 2.7 V
12 MHz oscillation
Stop mode; VDD = 5 V ± 10%,
LVD enable
IDD2
8
3
IDD3
110
220
mA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
20-6
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