K6T4016S6C-ZF10 [SAMSUNG]
Standard SRAM, 256KX16, 100ns, CMOS, PBGA48, 0.75 MM PITCH, MICRO, BGA-48;型号: | K6T4016S6C-ZF10 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 256KX16, 100ns, CMOS, PBGA48, 0.75 MM PITCH, MICRO, BGA-48 静态存储器 内存集成电路 |
文件: | 总9页 (文件大小:167K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K6T4016S6C Family
CMOS SRAM
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No History
Draft Date
Remark
0.0
Initial draft
June 26, 1998
Preliminary
0.01
Errata correction
August 17, 1998
1.0
Finalize
April 30, 1999
Final
- Specified CSP type.
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
April 1999
K6T4016S6C Family
CMOS SRAM
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: TFT
The K6T4016S6C families are fabricated by SAMSUNG¢s
advanced CMOS process technology. The families support
industrial operating temperature ranges and have chip scale
package for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
· Organization: 256K x16
· Power Supply Voltage
K6T4016S6C Family: 2.3~2.7V
· Low Data Retention Voltage: 2.0V(Min)
· Three state output and TTL Compatible
· Dual CS and standby control by UB, LB
· Package Type: 48-mBGA-6.10x8.90
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed(ns)
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
1001)/120
K6T4016S6C-F
Industrial(-40~85°C)
2.3~2.7V
15mA
25mA
48-mBGA
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Clk gen.
Precharge circuit.
A
B
C
D
E
F
LB
OE
UB
A0
A3
A1
A4
A2
CS2
I/O1
I/O3
Vcc
Vss
I/O7
I/O8
N.C
Vcc
Vss
I/O9
CS1
I/O2
I/O4
I/O5
I/O6
WE
Row
Addresses
Memory array
1024 rows
256´ 16 columns
Row
selec
I/O10
Vss
I/O11
I/O12
I/O13
I/O14
N.C
A5
A6
A17
N.C
A14
A12
A9
A7
Data
cont
I/O Circuit
Column select
I/O1~I/O8
Vcc
I/O15
I/O16
N.C
A16
A15
A13
A10
Data
cont
I/O9~I/O16
Data
cont
G
H
Column Addresses
A8
A11
CS1
CS2
OE
48-ball CSP - Top View (Ball Down)
Function Name
Control Logic
WE
UB
Name
Function
CS1,CS2 Chip Select Inputs
Vcc Power
Vss Ground
LB
OE
WE
Output Enable Input
Write Enable Input
Address Inputs
UB
LB
Upper Byte(I/O9~16)
A0~A17
Lower Byte(I/O1~8)
No Connection
I/O1~I/O16 Data Inputs/Outputs
NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
April 1999
K6T4016S6C Family
CMOS SRAM
PRODUCT LIST
Industrial Temp Products(-40~85°C)
Part Name
Function
K6T4016S6C-ZF10
K6T4016S6C-ZF12
48-CSP, 100ns, 2.5V, LL
48-CSP, 120ns, 2.5V, LL
FUNCTIONAL DESCRIPTION
CS1
H
X1)
X1)
L
CS2
X1)
L
OE
X1)
X1)
X1)
H
WE
X1)
X1)
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
Deselected
Deselected
X1)
H
Deselected
X1)
L
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
L
H
H
H
Active
L
H
L
H
H
Active
L
H
L
H
H
L
High-Z
Dout
Active
L
H
L
H
L
L
Dout
Active
X1)
X1)
X1)
L
H
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
L
H
L
H
L
High-Z
Din
Active
L
H
L
L
L
Din
Active
1. X means don¢t care. (Must be low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Ratings
-0.5 to VCC+0.5
-0.3 to 4.6
1.0
Unit
V
VIN,VOUT
VCC
V
PD
W
Storage temperature
TSTG
TA
-65 to 150
-40 to 85
°C
°C
Operating Temperature
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
April 1999
K6T4016S6C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Supply voltage
Ground
Symbol
Vcc
Product
Min
2.3
0
Typ
Max
2.7
0
Unit
V
K6T4016S6C Family
All Family
2.5
Vss
0
-
V
Vcc+0.32)
0.6
Input high voltage
Input low voltage
Note:
VIH
K6T4016S6C Family
K6T4016S6C Family
2.0
V
-0.33)
VIL
-
V
1. TA=-40 to 85°C, otherwise specified
2. Overshoot: VCC+1.0V in case of pulse width £ 10ns
3. Undershoot: -1.0V in case of pulse width £ 10ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
Min
Max
Unit
pF
VIN=0V
VIO=0V
-
-
8
Input/Output capacitance
CIO
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIN=Vss to Vcc
-1
-1
-
-
-
-
1
1
1
mA
mA
Output leakage current
Operating power supply current
ILO
CS1=VIH, CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc
IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL
ICC
mA
Cycle time=1ms, 100%duty, IIO=0mA, CS1£0.2V,
CS2³ Vcc-0.2V, VIN£0.2V or VIN³ VCC-0.2V
ICC1
ICC2
-
-
-
-
4
mA
mA
Average operating current
Cycle time=Min, IIO=0mA, 100% duty,
CS1=VIL, CS2=VIH, VIN=VIL or VIH
25
Output low voltage
Output high voltage
Standby Current(TTL)
VOL
VOH
ISB
IOL = 0.5mA
0.4
V
V
IOH = -0.5mA
2.0
-
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
-
-
0.3
15
mA
CS1³ Vcc-0.2V, CS2³ Vcc-0.2V(CS1 controlled)
or CS2£0.2V(CS2 controlled), Other inputs=0~Vcc
Standby Current(CMOS)
ISB1
-
mA
4
Revision 1.0
April 1999
K6T4016S6C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
)
1
Input and output reference voltage:1.1V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
CL
1.Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=2.3~2.7V, TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
100ns
Max
120ns
Min
100
-
Min
120
-
Max
Read cycle time
tRC
tAA
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
120
Chip select to output
tCO
tOE
tBA
-
100
-
120
Output enable to valid output
LB, UB valid to data output
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Output hold from address change
Chip disable to high-Z output
OE disable to high-Z output
UB, LB disable to high-Z output
Write cycle time
-
50
-
50
-
100
-
120
tLZ
10
5
-
-
10
5
-
-
Read
tOLZ
tBLZ
tOH
tHZ
10
15
0
-
10
15
0
-
-
-
30
30
30
-
35
35
35
-
tOHZ
tBHZ
tWC
tCW
tAS
0
0
0
0
100
80
0
120
100
0
Chip select to end of write
Address set-up time
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
tBW
80
70
0
-
100
80
0
-
-
-
Write
Write recovery time
-
-
Write to output high-Z
0
30
-
0
35
-
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
40
0
50
0
-
-
5
-
5
-
80
-
100
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
2.0
-
Typ
Max
2.7
15
-
Unit
V
CS1³ Vcc-0.2V1)
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
VDR
-
0.5
-
Vcc=2.5V, CS1³ Vcc-0.2V1)
IDR
mA
tSDR
0
See data retention waveform
ms
tRDR
5
-
-
1. CS1³ Vcc-0.2V,CS2³ Vcc-0.2V(CS1 controlled) or CS2³ Vcc-0.2V(CS2 controlled)
5
Revision 1.0
April 1999
K6T4016S6C Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS1
CS2
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
April 1999
K6T4016S6C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS1
tCW(2)
tWR(4)
CS2
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
tWC
Address
tCW(2)
tAW
tAS(3)
tWR(4)
CS1
CS2
tBW
UB, LB
tWP(1)
WE
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
7
Revision 1.0
April 1999
K6T4016S6C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS1
tCW(2)
tAW
tWR(4)
CS2
tBW
UB, LB
tAS(3)
tWP(1)
WE
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1 and low WE. A write begins when CS1 goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS1 going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE going high.
DATA RETENTION WAVE FORM
CS1 controlled
Data Retention Mode
tSDR
tRDR
VCC
2.3V
2.0V
VDR
CS1³ VCC - 0.2V
CS, LB/UB
GND
CS2 controlled
Data Retention Mode
VCC
2.3V
CS2
tSDR
tRDR
VDR
CS2£0.2V
0.4V
GND
8
Revision 1.0
April 1999
K6T4016S6C Family
CMOS SRAM
PACKAGE DIMENSIONS
Units : millimeters
48 BALL MICRO BALL GRID ARRAY- 0.75mm ball pitch
Top View
B
Bottom View
B
Ball #A1
6
5
4
3
2
1
A
B
C
D
E
F
Ball #A1
G
H
B1
B/2
B/2
SRAM Die
Elastomer
Detail A
Detail A
A
Side View
D
Y
C
Elastomer
0.3/Typ.
Die
Min
Typ
Max
A
B
-
0.75
6.10
3.75
8.90
5.25
0.35
0.93
0.68
0.25
-
-
6.20
-
Notes.
1. Bump counts: 48(8row x 6column)
6.00
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
B1
C
-
8.80
9.00
-
C1
D
-
4. Typ : Typical
0.30
0.40
0.94
-
5. Y is coplanarity: 0.08(Max)
E
-
-
-
-
E1
E2
Y
-
0.08
9
Revision 1.0
April 1999
相关型号:
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