K6T4016U3B-TB100 [SAMSUNG]
Standard SRAM, 256KX16, 100ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;型号: | K6T4016U3B-TB100 |
厂家: | SAMSUNG |
描述: | Standard SRAM, 256KX16, 100ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 静态存储器 光电二极管 |
文件: | 总9页 (文件大小:149K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
K6T4016V3B, K6T4016U3B Family
CMOS SRAM
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No.
History
Draft Data
Remark
0.0
Initial draft
June 28, 1996
Advance
0.1
Revise
September 19, 1996
Preliminary
- Die name change: A to B
1.0
2.0
Finalize
December 17, 1996
February 17, 1997
Final
Final
Revise
- Operating current update and release.
ICC(Read/Write) = 20/40 ® 10/45mA
ICC1(Read/Write) = 20/40 ® 10/45mA
ICC2 = 90 ® 70mA
3.0
Revise
January 14, 1998
Final
- Change datasheet format
- Erase 70ns part from KM616V4000BI, KM616U4000B and
KM616U4000BI Family
- Power dissipation improved 0.7 to 1.0W
- VIL(MAX) improved 0.4 to 0.6V.
- ICC2 decreased 70 to 60mA.
- Erase 100ns from KM616V4000B commercial product
Error correction
3.01
3.02
August 7, 1998
Final
Final
Revise
October 15, 2001
- Improved VOH(output high voltage) from 2.2V to 2.4V.
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 3.02
1
October 2001
K6T4016V3B, K6T4016U3B Family
CMOS SRAM
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
GENERAL DESCRIPTION
FEATURES
· Process Technology: TFT
· Organization: 256K x16
The K6T4016V3B and K6T4016U3B families are fabricated by
SAMSUNG¢s advanced CMOS process technology. The fami-
lies support various operating temperature range and have
small package types for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.
· Power Supply Voltage
K6T4016V1B Family: 3.0~3.6V
K6T4016U1B Family: 2.7~3.3V
· Low Data Retention Voltage: 2V(Min)
· Three State Outputs
· Package Type: 44-TSOP2-400F/R
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
701)/851)ns
851)/100ns
K6T4016V3B-B
K6T4016U3B-B
K6T4016V3B-F
K6T4016U3B-F
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
Commercial(0~70°C)
Industrial(-40~85°C)
15mA
20mA
60mA
44-TSOP2-400F/R
851)/100ns
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A4
A3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
A4
A5
A5
A6
Clk gen.
Precharge circuit.
2
A3
A6
A2
3
3
A2
A7
A7
A13
A14
A0
A1
4
4
A1
OE
OE
Vcc
Vss
A0
5
5
UB
A0
UB
CS
6
6
LB
CS
LB
I/O1
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
7
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
7
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
I/O16
I/O15
I/O14
I/O13
Vss
A1
8
8
Memory array
1024 rows
256´ 16 columns
9
9
A15
A16
A17
A2
Row
select
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
44-TSOP2
Forward
44-TSOP2
Reverse
Vcc
I/O12
I/O11
I/O10
I/O9
NC
A3
A4
Data
cont
I/O Circuit
Column select
A8
I/O1~I/O8
A9
A9
A10
A11
A12
A10
Data
cont
A11
A12
I/O9~I/O16
Data
cont
Name
CS
Function
Name
LB
Function
A8 A9 A10 A5 A6 A7 A4 A12
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Lower Byte (I/O1~8)
Upper Byte(I/O9~16)
OE
UB
WE
Vcc Power
Vss Ground
WE
OE
UB
LB
A0~A17
Control
logic
I/O1~I/O16 Data Inputs/Outputs
NC
No Connection
CS
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 3.02
October 2001
2
K6T4016V3B, K6T4016U3B Family
CMOS SRAM
PRODUCT LIST
Commercial Temperature Product(0~70°C)
Industrial Temperature Products(-40~85°C)
Part Name
Function
Part Name
Function
K6T4016V3B-TB70
K6T4016V3B-TB85
K6T4016V3B-RB70
K6T4016V3B-RB85
44-TSOP2-F, 70ns, 3.3V,LL
44-TSOP2-F, 85ns, 3.3V,LL
44-TSOP2-R, 70ns, 3.3V,LL
44-TSOP2-R, 85ns, 3.3V,LL
K6T4016V3B-TF85
K6T4016V3B-TF10
K6T4016V3B-RF85
K6T4016V3B-RF10
44-TSOP2-F, 85ns, 3.3V,LL
44-TSOP2-F, 100ns, 3.3V,LL
44-TSOP2-R, 85ns, 3.3V,LL
44-TSOP2-R, 100ns, 3.3V,LL
K6T4016U3B-TB85
K6T4016U3B-TB10
K6T4016U3B-RB85
K6T4016U3B-RB10
44-TSOP2-F, 85ns, 3.0V,LL
44-TSOP2-F, 100ns, 3.0V,LL
44-TSOP2-R, 85ns, 3.0V,LL
44-TSOP2-R, 100ns, 3.0V,LL
K6T4016U3B-TF85
K6T4016U3B-TF10
K6T4016U3B-RF85
K6T4016U3B-RF10
44-TSOP2-F, 85ns, 3.0V,LL
44-TSOP2-F, 100ns, 3.0V,LL
44-TSOP2-R, 85ns, 3.0V,LL
44-TSOP2-R, 100ns, 3.0V,LL
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X1)
H
WE
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
X1)
H
L
L
L
H
L
L
H
H
L
High-Z
Dout
L
L
H
L
L
Dout
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
L
L
H
L
High-Z
Din
L
L
L
L
Din
1. X means don¢t care. (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
Ratings
-0.5 to VCC+0.5
-0.3 to 4.6
1.0
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN,VOUT
VCC
-
V
-
PD
W
°C
°C
°C
-
-
Storage temperature
TSTG
-65 to 150
0 to 70
-
Commercial
Industrial
-
Operating Temperature
TA
-40 to 85
Soldering temperature and time
TSOLDER
260°C, 10sec (Lead Only)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Revision 3.02
3
October 2001
K6T4016V3B, K6T4016U3B Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Supply voltage
Symbol
Product
Min
Typ
Max
Unit
K6T4016V3B Family
K6T4016U3B Family
3.0
2.7
3.3
3.0
3.6
3.3
Vcc
V
Ground
Vss
VIH
VIL
All Family
0
0
-
0
V
V
V
Vcc+0.32)
0.6
Input high voltage
Input low voltage
K6T4016V3B, K6T4016U3B Family
K6T4016V3B, K6T4016U3B Family
2.2
-0.33)
-
Note:
1. Commercial Product: TA=0 to 70°C, otherwise specified
Industrial Product: TA=-40 to 85°C, otherwise specified
2. Overshoot: VCC+3.0V in case of pulse width £ 30ns
3. Undershoot: -3.0V in case of pulse width £ 30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
-
-
8
pF
pF
Input/Output capacitance
CIO
VIO=0V
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Min Typ Max Unit
Test Conditions
Input leakage current
Output leakage current
Operating power supply current
VIL=Vss to Vcc
-1
-
-
-
-
-
-
-
-
-
-
1
1
mA
mA
ILO
CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read
-1
ICC
-
10
10
45
60
0.4
-
mA
Read
Write
-
Cycle time=1ms, 100% duty, IIO=0mA
CS£0.2V, VIN£0.2V or VIN³ Vcc-0.2V
ICC1
mA
Average operating current
-
ICC2
VOL
VOH
ISB
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
IOL=2.1mA
-
mA
V
Output low voltage
-
2.4
-
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
IOH=-1.0mA
V
CS=VIH, Other inputs=VIL or VIH
CS³ Vcc-0.2V, Others inputs = 0~Vcc
0.5
mA
mA
151)
ISB1
-
1. Industrial product = 20mA
Revision 3.02
October 2001
4
K6T4016V3B, K6T4016U3B Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage: 1.5V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
)
1
CL
1.Including scope and jig capacitance
AC CHARACTERISTICS (K6T4016V3B Family: Vcc=3.0~3.6V, K6T4016U3B Family: Vcc=2.7~3.3V,
Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
70ns1)
85ns1)
100ns
Min
Max
Min
Max
Min
Max
Read cycle time
tRC
tAA
70
-
-
70
70
35
-
85
-
-
85
85
40
-
100
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
Chip select to output
tCO
tOE
-
-
-
100
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
UB, LB enable to low-Z output
Chip disable to high-Z output
OE disable to high-Z output
Output hold from address change
LB, UB valid to data output
UB, LB disable to high-Z output
Write cycle time
-
-
-
50
-
tLZ
10
5
10
5
10
5
tOLZ
tBLZ
tHZ
-
-
-
Read
5
-
5
-
5
-
0
25
25
-
0
25
25
-
0
30
30
-
tOHZ
tOH
tBA
0
0
0
10
-
10
-
15
-
35
25
-
40
25
-
50
30
-
tBHZ
tWC
tCW
tAS
0
0
0
70
60
0
85
70
0
100
80
0
Chip select to end of write
Address set-up time
-
-
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
60
55
0
-
70
55
0
-
80
70
0
-
-
-
-
Write
Write recovery time
-
-
-
Write to output high-Z
0
25
-
0
25
-
0
30
-
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
30
0
35
0
40
0
-
-
-
tOW
tBW
5
-
5
-
5
-
60
-
70
-
80
-
1. The parameter is measured with 30pF test load.
DATA RETENTION CHARACTERISTICS
Item
Symbol
Min
2.0
-
Typ
Max
Unit
V
Test Condition
CS³ Vcc-0.2V
Vcc for data retention
Data retention current
Data retention set-up time
VDR
-
0.5
-
3.6
151)
IDR
Vcc=3.0V, CS³ Vcc-0.2V
mA
tSDR
0
-
-
See data retention waveform
ms
Recovery time
tRDR
5
-
1. Industrial product = 20mA
Revision 3.02
October 2001
5
K6T4016V3B, K6T4016U3B Family
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 3.02
October 2001
6
K6T4016V3B, K6T4016U3B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS
tWR(4)
tCW(2)
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
WE
tWP(1)
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
Revision 3.02
October 2001
7
K6T4016V3B, K6T4016U3B Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS
tCW(2)
tWR(4)
tAW
tBW
UB, LB
WE
tAS(3)
tWP(1)
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
3.0/2.7V
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
Revision 3.02
October 2001
8
K6T4016V3B, K6T4016U3B Family
CMOS SRAM
Unit: millimeters(inches)
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8°
0.25
0.010
(
)
#44
#23
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
0.020
(
)
#1
#22
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41±0.10
0.725±0.004
0.10
0.004
MAX
0.35± 0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
0~8°
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0.25
0.010
(
)
#1
#22
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
)
(
0.020
#44
#23
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41± 0.10
0.725±0.004
0.10
0.004
MAX
0.35±0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
Revision 3.02
October 2001
9
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