K6T4016S3C-TF120 [SAMSUNG]
Standard SRAM, 256KX16, 120ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44;
| 型号： | K6T4016S3C-TF120 |
| 厂家： | 
SAMSUNG |
| 描述： | Standard SRAM, 256KX16, 120ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
K6T4016S3C Family
CMOS SRAM
Document Title
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
Revision History
Revision No. History
Draft Date
Remark
0.0
Initial draft
June 16, 1998
Preliminary
0.01
Errata correction
August 10, 1998
1.0
Finalize
April 30, 1999
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will anwswer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
April 1999
K6T4016S3C Family
CMOS SRAM
256Kx16 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
· Process Technology: TFT
The K6T4016S3C families are fabricated by SAMSUNG¢s
advanced CMOS process technology. The families support
industrial operating temperature ranges and have small pack-
age types for user flexibility of system design. The families also
support low data retention voltage for battery back-up operation
with low data retention current.
· Organization: 256K x16
· Power Supply Voltage: 2.3~2.7V
· Low Data Retention Voltage: 2V(Min)
· Three state output and TTL Compatible
· Package Type: 44-TSOP2-400F/R
PRODUCT FAMILY
Power Dissipation
Product Family
Operating Temperature
Vcc Range
Speed
PKG Type
Standby
(ISB1, Max)
Operating
(ICC2, Max)
1001)/120ns
K6T4016S3C-F
Industrial(-40~85°C)
2.3~2.7V
15mA
25mA
44-TSOP2-F/R
1. The parameter is measured with 30pF test load.
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A4
A3
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
A4
A5
A5
A6
Clk gen.
Precharge circuit.
2
A3
A6
A2
3
3
A2
A7
A7
A1
4
A0
4
A1
OE
OE
A0
Vcc
Vss
5
5
A0
UB
UB
A1
CS
6
6
LB
CS
LB
A2
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
7
7
I/O16
I/O15
I/O14
I/O13
Vss
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
I/OI
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
I/O7
I/O8
WE
A17
A16
A15
A14
A13
I/O16
I/O15
I/O14
I/O13
Vss
8
8
A3
9
9
Memory array
1024 rows
256´ 16 columns
A4
Row
selec
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
19
20
21
22
A13
A14
A15
A16
A17
44-TSOP2
Forward
44-TSOP2
Reverse
Vcc
I/O12
I/O11
I/O10
I/O9
N.C
A8
I/O Circuit
Column select
Data
cont
I/O1~I/O8
A9
A9
A10
A11
A12
A10
Data
cont
A11
A12
I/O9~I/O16
Data
cont
Name
CS
Function
Chip Select Input
Name Function
A5 A6 A7 A8 A9 A10A11A12
Vcc Power
OE
Output Enable Input Vss Ground
WE
Write Enable Input
Address Inputs
UB
LB
Upper Byte(I/O9~16)
Lower Byte (I/O1~8)
WE
OE
UB
LB
Control
logic
A0~A17
I/O1~I/O16 Data Input/Output
N.C No Connection
CS
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.0
April 1999
K6T4016S3C Family
CMOS SRAM
PRODUCT LIST
Industrial Temperature Products(-40~85°C)
Part Name
Function
K6T4016S3C-TF10
K6T4016S3C-TF12
K6T4016S3C-RF10
K6T4016S3C-RF12
44-TSOP2-F, 100ns, 2.5V, LL
44-TSOP2-F, 120ns, 2.5V, LL
44-TSOP2-R, 100ns, 2.5V, LL
44-TSOP2-R, 120ns, 2.5V, LL
FUNCTIONAL DESCRIPTION
CS
H
L
OE
X1)
H
WE
X1)
H
LB
X1)
X1)
H
UB
X1)
X1)
H
I/O1~8
High-Z
High-Z
High-Z
Dout
I/O9~16
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
L
X1)
H
L
L
L
H
L
L
H
H
L
High-Z
Dout
L
L
H
L
L
Dout
X1)
X1)
X1)
L
L
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
L
L
H
L
High-Z
Din
L
L
L
L
Din
1. X means don¢t care. (Must be in low or high state)
ABSOLUTE MAXIMUM RATINGS1)
Item
Symbol
VIN,VOUT
VCC
Ratings
Unit
V
Remark
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
-0.5 to VCC+0.5
-0.3 to 4.6
1.0
-
-
-
-
V
PD
W
Storage temperature
TSTG
TA
-65 to 150
-40 to 85
°C
Operating Temperature
°C
Industrial Product
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
April 1999
K6T4016S3C Family
CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS1)
Item
Supply voltage
Symbol
Vcc
Product
K6T4016S3C Family
All Family
Min
2.3
0
Typ
Max
2.7
0
Unit
V
2.5
Ground
Vss
0
-
V
Vcc+0.32)
0.6
Input high voltage
Input low voltage
Note:
VIH
All Family
2.0
V
-0.33)
VIL
All Family
-
V
1. TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+1.0V in case of pulse width £ 20ns
3. Undershoot : -1.0V in case of pulse width £ 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1)(f=1MHz, TA=25°C)
Item
Input capacitance
Symbol
CIN
Test Condition
VIN=0V
Min
Max
Unit
-
-
8
pF
pF
Input/Output capacitance
CIO
VIO=0V
10
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Item
Symbol
ILI
Test Conditions
Min Typ Max Unit
Input leakage current
VIL=Vss to Vcc
-1
-
-
-
-
-
-
-
-
-
1
1
mA
mA
mA
mA
mA
V
Output leakage current
Operating power supply current
ILO
CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc
IIO=0mA, CS=VIL, VIN=VIL or VIH, Read
-1
ICC
-
1
Cycle time=1ms, 100% duty, IIO=0mA, CS£0.2V, VIN£0.2V or VIN³ Vcc-0.2V
Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL
IOL=0.5mA
ICC1
ICC2
VOL
VOH
ISB
-
4
Average operating current
-
25
0.4
-
Output low voltage
-
2.0
-
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
IOH=-0.5mA
V
CS=VIH, Other inputs = VIL or VIH
CS³ Vcc-0.2V, Other inputs=0~Vcc
0.3
mA
mA
ISB1
-
15
4
Revision 1.0
April 1999
K6T4016S3C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
)
1
Input and output reference voltage: 1.1V
Output load(see right): CL=100pF+1TTL
CL=30pF+1TTL
CL
1.Including scope and jig capacitance
AC CHARACTERISTICS (VCC=2.3~2.7V, TA=-40 to 85°C)
Speed Bins
Parameter List
Symbol
Units
100ns
Max
120ns
Min
100
-
Min
120
-
Max
Read cycle time
tRC
tAA
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
100
120
Chip select to output
tCO
tOE
-
100
-
120
Output enable to valid output
LB, UB valid to data output
Chip select to low-Z output
Output enable to low-Z output
LB, UB enable to low-Z output
Output hold from address change
Chip disable to high-Z output
OE disable to high-Z output
UB, LB disable to high-Z output
Write cycle time
-
50
50
-
-
60
60
-
tBA
-
-
tLZ
10
5
10
5
Read
tOLZ
tBLZ
tOH
tHZ
-
-
5
-
5
-
15
0
-
15
0
-
30
30
30
-
35
35
35
-
tOHZ
tBHZ
tWC
tCW
tAS
0
0
0
0
100
80
0
120
100
0
Chip select to end of write
Address set-up time
-
-
-
-
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
80
70
0
-
100
80
0
-
-
-
Write
Write recovery time
-
-
Write to output high-Z
0
30
-
0
35
-
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
40
0
50
0
-
-
tOW
tBW
5
-
5
-
80
-
100
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
2.0
-
Typ
Max
2.7
15
-
Unit
V
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
VDR
CS³ Vcc-0.2V
-
0.5
-
IDR
Vcc=2.5V, CS³ Vcc-0.2V
mA
tSDR
0
See data retention waveform
ms
tRDR
5
-
-
5
Revision 1.0
April 1999
K6T4016S3C Family
CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL)
tRC
Address
tAA
tOH
Data Valid
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH
tAA
tCO
CS
tHZ
tBA
UB, LB
OE
tBHZ
tOHZ
tOE
tOLZ
tBLZ
tLZ
Data out
High-Z
Data Valid
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
April 1999
K6T4016S3C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS
tCW(2)
tWR(4)
tAW
tBW
UB, LB
tWP(1)
WE
tAS(3)
tDW
tDH
High-Z
High-Z
Data in
Data Valid
tWHZ
tOW
Data Undefined
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
tWC
Address
tAS(3)
tCW(2)
tWR(4)
CS
tAW
tBW
UB, LB
WE
tWP(1)
tDW
tDH
Data Valid
Data in
Data out
High-Z
High-Z
7
Revision 1.0
April 1999
K6T4016S3C Family
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)
tWC
Address
CS
tCW(2)
tWR(4)
tAW
tBW
UB, LB
WE
tAS(3)
tWP(1)
tDH
tDW
Data in
Data Valid
High-Z
Data out
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB
or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-
tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high.
DATA RETENTION WAVE FORM
CS controlled
Data Retention Mode
tSDR
tRDR
VCC
2.3V
2.2V
VDR
CS³ VCC - 0.2V
CS
GND
8
Revision 1.0
April 1999
K6T4016S3C Family
CMOS SRAM
Units: millimeters(inches)
PACKAGE DIMENSIONS
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)
0~8°
0.25
0.010
(
)
#44
#23
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
0.020
(
)
#1
#22
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41±0.10
0.725±0.004
0.10
0.004
MAX
0.35± 0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
0~8°
44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)
0.25
0.010
(
)
#1
#22
0.45 ~0.75
0.018 ~ 0.030
11.76±0.20
0.463±0.008
0.50
)
(
0.020
#44
#23
1.00±0.10
0.039±0.004
18.81
0.741
1.20
0.047
MAX.
MAX.
18.41± 0.10
0.725±0.004
0.10
0.004
MAX
0.35±0.10
0.014±0.004
0.80
0.0315
0.805
0.032
(
)
9
Revision 1.0
April 1999
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