BD9B305QUZ_技术文档

Datasheet

2.7 V to 5.5 V Input, 3.0 A Integrated MOSFET

Single Synchronous Buck DC/DC Converter

BD9B305QUZ

General Description

Key Specifications

BD9B305QUZ is a synchronous buck DC/DC converter

with built-in low on-resistance power MOSFETs. It is

capable of providing current up to 3 A. It features fast

transient response due to constant on-time control

system. The Light Load Mode control improves efficiency

in light-load conditions. It is ideal for reducing standby

power consumption of equipment. Power Good function

makes it possible for system to control sequence. It

achieves the high power density and offer a small

footprint on the PCB by employing small package.

◼ Input Voltage Range:

◼ Output Voltage Range:

◼ Output Current:

◼ Switching Frequency:

◼ High-Side FET ON Resistance:

◼ Low-Side FET ON Resistance:

◼ Shutdown Current:

2.7 V to 5.5 V

0.6 V to V_INx 0.8 V

3.0 A (Max)

1 MHz (Typ)

50 mΩ (Typ)

40 mΩ (Typ)

0 μA (Typ)

Package

VMMP08LZ2020

W (Typ) x D (Typ) x H (Max)

2.00 mm x 2.00 mm x 0.40 mm

Features

◼

Single Synchronous Buck DC/DC Converter

Constant On-time Control

Light Load Mode Control

Adjustable Soft Start

Power Good Output

Output Capacitor Discharge Function

Over Voltage Protection (OVP)

Over Current Protection (OCP)

Short Circuit Protection (SCP)

Thermal Shutdown Protection (TSD)

Under Voltage Lockout Protection (UVLO)

VMMP08LZ2020 Package

Backside Heat Dissipation

0.5 mm Pitch

VMMP08LZ2020

Applications

◼ Step-down Power Supply for SoC, FPGA,

Microprocessor

◼ Laptop PC / Tablet PC / Server

◼ LCD TV

◼ Storage Device (HDD / SSD)

◼ Printer, OA Equipment

◼ Distributed Power Supply, Secondary Power Supply

Typical Application Circuit

BD9B305QUZ

V_IN

VIN

PGD

BOOT

C_IN

0.1 µF

L₁

V_OUT

GND

SW

R₁

V_EN

C_FB

EN

SS

C_OUT

FB

R₂

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.

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Pin Configuration

(TOP VIEW)

EXP-PAD

BOOT

1

8

GND

SW

PGD

FB

2

3

4

7

6

5

VIN

EN

SS

Pin Descriptions

Pin No. Pin Name

Function

Pin for bootstrap. Connect a bootstrap capacitor of 0.1 µF between this pin and the SW pin.

The voltage of this pin is the gate drive voltage of the High-Side FET.

1

2

3

4

5

6

7

8

-

BOOT

SW

Switch pin. This pin is connected to the source of the High-Side FET and the drain of the

Low-Side FET. Connect a bootstrap capacitor of 0.1 µF between this pin and the BOOT pin.

In addition, connect an inductor considering the direct current superimposition characteristic.

Power Good pin. This pin is an open drain output that requires a pull-up resistor. See page

17 for setting the resistance. If not used, this pin can be left floating or connected to the

ground.

PGD

FB

Output voltage feedback pin. See page 31 for how to calculate the resistances of the output

voltage setting.

Pin for setting the soft start time of output voltage. The soft start time is 1 ms (Typ) when the

SS pin is left floating. A ceramic capacitor connected to the SS pin makes the soft start time

more than 1 ms. See page 31 for how to calculate the capacitance.

SS

Enable pin. The device starts up with setting V_ENto 0.920 V (Typ) or more. The device enters

the shutdown mode with setting V_ENto 0.875 V (Typ) or less. This pin must be terminated.

EN

Power supply pin. Connecting 0.1 µF (Typ) and 22 µF (Typ) ceramic capacitors is

recommended. The detail of a selection is described in page 31.

VIN

GND

Ground pin.

A backside heat dissipation exposed pad. Connecting to the PCB power ground plane by

EXP-PAD using thermal vias provides excellent heat dissipation characteristics. See page 34 to 35 for

the detailed PCB layout design.

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Block Diagram

6

7

EN

SS

VREF

VIN

Error

Amplifier

Main

Comparator

5

4

Soft Start

On Time

1

2

BOOT

SW

High-Side

FET

FB

EN

UVLO

TSD

Control

Logic

VIN

Low-Side

FET

OVP

SCP

8

GND

OCP

PGOOD

ZXCMP

3

PGD

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Description of Blocks

1. VREF

The VREF block generates the internal reference voltage.

2. Soft Start

The Soft Start circuit slows down the rise of output voltage during start-up and controls the current, which allows the

prevention of output voltage overshoot and inrush current. The internal soft start time is 1 ms (Typ) when the SS pin is

left floating. A capacitor connected to the SS pin makes the rising time more than 1 ms.

3. Error Amplifier

The Error Amplifier adjusts the Main Comparator input voltage to make the internal reference voltage equal to FB

voltage.

4. Main Comparator

The Main Comparator compares the Error Amplifier output voltage and FB voltage (V_FB). When V_FBbecomes lower than

the Error Amplifier output voltage, the output turns high and reports to the On Time block that the output voltage has

dropped below the control voltage.

5. On Time

This block generates On Time. The designed On Time is generated after the Main Comparator output turns high. The

On Time is adjusted to control the frequency to be fixed even with I/O voltage is changed.

6. PGOOD

The PGOOD block is for power good function. When the output voltage reaches within ±10 % (Typ) of the setting

voltage, the built-in open drain Nch MOSFET connected to the PGD pin is turned off and the PGD pin becomes Hi-Z

(High impedance). When the output voltage reaches outside ±15 % (Typ) of the setting voltage, the open drain Nch

MOSFET is turned on and PGD pin is pulled down with 100 Ω (Typ).

7. UVLO

The UVLO block is for under voltage lockout protection. The device is shut down when input voltage (V_IN) falls to 2.45 V

(Typ) or less. The threshold voltage has the 100 mV (Typ) hysteresis.

8. TSD

The TSD block is for thermal protection. The device is shut down when the junction temperature Tj reaches to 175 °C

(Typ) or more. The device is automatically restored to normal operation with a hysteresis of 25 °C (Typ) when the Tj

goes down.

9. OVP

The OVP block is for output over voltage protection. When the FB voltage (V_FB) exceeds 115 % (Typ) or more of FB

threshold voltage V_FBTH, the output MOSFETs are turned off. After V_FBfalls 110 % (Typ) or less of V_FBTH, the output

MOSFETs are returned to normal operation condition.

10. OCP

The OCP block is for over current protection. This function operates by limiting the current that flows through the

High-Side FET and the Low-Side FET at each cycle of the switching frequency.

11. SCP

The SCP is for short circuit protection. When 256 times OCP are counted on the condition where the device completes

the soft start and the output voltage falls below 85 % (Typ) of the setting voltage, the device is shut down for 128 ms

(Typ). After 128 ms shutdown, the device restarts. (HICCUP operation)

12. ZXCMP

The ZXCMP is a comparator that monitors the inductor current. When inductor current falls below 0A (Typ) while the

Low-Side FET is on, it turns the FET off.

13. Control Logic

The Control Logic controls the switching operation and protection function operation.

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Absolute Maximum Ratings (Ta = 25 °C)

Parameter

Symbol

Rating

Unit

Input Voltage

V_IN

V_EN

-0.3 to +7

-0.3 to +V_IN

-0.3 to +7

-0.3 to +V_IN

-0.3 to +7

-0.3 to V_IN+ 0.3

-0.3 to +14

-0.3 to +7

3.5

V

EN Voltage

FB Voltage

V_FB

V

SS Voltage

V_SS

V

PGD Voltage

V_PGD

V_SW

V

SW Voltage

V

Voltage from GND to BOOT

Voltage from SW to BOOT

Output Current

V_BOOT

ΔV_BOOT-SW

I_OUT

V

A

Maximum Junction Temperature

Storage Temperature Range

Tjmax

Tstg

150

°C

-55 to +150

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by

increasing board size and copper area so as not to exceed the maximum junction temperature rating.

Thermal Resistance ^{(Note 1)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s ^{(Note 3)}

2s2p ^{(Note 4)}

VMMP08LZ2020

Junction to Ambient

Junction to Top Characterization Parameter ^{(Note 2)}

θ_JA

208.30

28.00

90.30

22.00

°C/W

Ψ_JT

(Note 1) Based on JESD51-2A (Still-Air).

(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 3) Using a PCB board based on JESD51-3.

(Note 4) Using a PCB board based on JESD51-5, 7.

Layer Number of

Measurement Board

Material

Board Size

Single

FR-4

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

70 μm

Footprints and Traces

Layer Number of

Measurement Board

Thermal Via ^{(Note 5)}

Material

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

Pitch

Diameter

4 Layers

FR-4

1.20 mm

Φ0.30 mm

Top

Copper Pattern

Bottom

Thickness

70 μm

Copper Pattern

Thickness

35 μm

Copper Pattern

Thickness

70 μm

Footprints and Traces

74.2 mm x 74.2 mm

(Note 5) This thermal via connects with the copper pattern of all layers.

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Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltage

V_IN

Ta

2.7

-40

0

-

5.5

+85

V

°C

A

Operating Temperature ^{(Note 1)}

Output Current ^{(Note 1)}

Output Voltage Setting

I_OUT

V_OUT

3.0

0.6

V_INx 0.8

V

(Note 1) Tj must be lower than 150 °C under the actual operating environment.

Electrical Characteristics (Unless otherwise specified Ta = 25 °C, V_IN= 5 V, V_EN= 5 V)

Parameter

Input Supply

Symbol

Min

Typ

Max

Unit

Conditions

Shutdown Current

I_SDN

I_Q

V_UVLO1

V_UVLO2

-

0

10

30

µA

V_EN= 0 V

I_OUT= 0 A,

No switching

Quiescent Current at No Load

15

UVLO Detection Threshold Voltage

UVLO Release Threshold Voltage

UVLO Hysteresis Voltage

Enable

2.350

2.425

50

2.450

2.550

100

2.550

2.700

200

V

V_INfalling

V_INrising

V_UVLOHYS

mV

EN Threshold Voltage High

EN Threshold Voltage Low

EN Hysteresis Voltage

EN Input Current

V_ENH

V_ENL

0.875

0.830

27

0.920

0.875

45

0.965

0.920

63

V

V_ENrising

V_ENfalling

V_ENHYS

I_EN

mV

µA

-

0

10

V_EN= 5 V

Reference Voltage, Error Amplifier, Soft Start

FB Threshold Voltage

FB Input Current

V_FBTH

I_FB

0.591

-

0.600

-

0.609

100

1.4

V

PWM mode

nA

ms

µA

V_FB= 0.6 V

Soft Start Time

t_SS

0.6

1.0

SS pin is left floating.

Soft Start Charge Current

On Time

I_SS

1.4

t_ON

270

360

450

ns

V_OUT= 1.8 V, PWM mode

On Time

SW (MOSFET)

High-Side FET ON Resistance

Low-Side FET ON Resistance

High-Side FET Leakage Current

Low-Side FET Leakage Current

Power Good

R_ONH

R_ONL

I_LKH

-

50

40

0

100

80

mΩ

µA

V_BOOT- V_SW= 5 V

10

No switching

I_LKL

0

10

µA

V_FBrising,

V_PGDGR= V_FB/ V_FBTHx 100

V_FBfalling,

V_PGDGF= V_FB/ V_FBTHx 100

V_FBrising,

V_PGDFR= V_FB/ V_FBTHx 100

V_FBfalling,

Power Good Rising

Threshold Voltage

Power Good Falling

Threshold Voltage

Power Fault Rising

Threshold Voltage

Power Fault Falling

Threshold Voltage

V_PGDGR

V_PGDGF

V_PGDFR

V_PGDFF

85

105

110

80

90

110

115

85

95

115

120

90

%

V_PGDFF= V_FB/ V_FBTHx 100

PGD Output Leakage Current

PGD MOSFET ON Resistance

PGD Output Low Level Voltage

I_LKPGD

R_PGD

-

0

5

µA

Ω

V_PGD= 5 V

100

0.1

200

0.2

V_PGDL

V

I_PGD= 1 mA

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Typical Performance Curves

10

8

30

25

20

15

10

5

= 5.0 V

V_IN= 5.0 V

V_IN= 3.3 V

V_IN

V_IN= 3.3 V

6

4

2

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 1. Shutdown Current vs Temperature

Figure 2. Quiescent Current at No Load vs Temperature

2.70

0.97

V_IN= 5.0 V

0.95

2.65

2.60

2.55

2.50

2.45

2.40

2.35

V_ENH( V_ENrising)

0.93

0.91

0.89

0.87

0.85

0.83

UVLO Release ( V_INrising)

UVLO Detection ( V_INfalling)

V_ENL( V_ENfalling)

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 3. UVLO Threshold Voltage vs Temperature

Figure 4. EN Threshold Voltage vs Temperature

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Typical Performance Curves – continued

10

0.610

0.608

0.606

0.604

0.602

0.600

0.598

0.596

0.594

0.592

0.590

V

_IN= 5.0 V

V_IN= 5.0 V, V_EN= 5.0 V

8

_IN= 3.3 V

6

4

2

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 5. EN Input Current vs Temperature

Figure 6. FB Threshold Voltage vs Temperature

100

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

V

_IN= 5.0 V

_IN= 3.3 V

80

60

40

20

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 7. FB Input Current vs Temperature

Figure 8. Soft Start Time vs Temperature

(SS pin is left floating.)

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Typical Performance Curves – continued

1.4

460

440

420

400

380

360

340

320

300

280

260

V

_IN= 5.0 V

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

_IN= 3.3 V

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 9. Soft Start Charge Current vs Temperature

Figure 10. On Time vs Temperature

(V_IN= 5.0 V, V_OUT= 1.8 V, I_OUT= 1.0 A)

1.3

100

90

80

70

60

50

40

30

20

10

0

V

_IN= 5.0 V

_IN= 3.3 V

1.2

1.1

1.0

0.9

0.8

0.7

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 11. Switching Frequency vs Temperature

(V_IN= 5.0 V, V_OUT= 1.8 V, I_OUT= 1.0 A)

Figure 12. High-Side FET ON Resistance vs Temperature

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Typical Performance Curves – continued

80

120

115

110

105

100

95

V

V_IN= 5.0 V

_IN= 5.0 V

Power Fault (V_FBrising)

Power Good (V_FBfalling)

70

60

50

40

30

20

10

0

_IN= 3.3 V

Power Good (V_FBrising)

Power Fault (V_FBfalling)

90

85

80

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 13. Low-Side FET ON Resistance vs Temperature

Figure 14. Power Good / Fault Threshold Voltage vs

Temperature

200

0.20

V_IN= 5.0 V

180

V_IN= 5.0 V

0.18

160

140

120

100

80

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

60

40

20

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature : Ta [°C]

Figure 15. PGD MOSFET ON Resistance vs Temperature

Figure 16. PGD Output Low Level Voltage vs Temperature

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Typical Performance Curves – continued

Time: 500 µs/div

V_IN: 3 V/div

Time: 2 ms/div

V_IN: 3 V/div

V_EN: 3 V/div

V_OUT: 1 V/div

V_PGD: 5 V/div

V_OUT: 1 V/div

V_PGD: 5 V/div

Figure 17. Start-up at No Load: V_EN= 0 V to 5 V

Figure 18. Shutdown at No Load: V_EN= 5 V to 0 V

(V_IN= 5.0 V, V_OUT= 1.8 V, C_SS= OPEN)

Time: 500 µs/div

V_IN: 3 V/div

Time: 2 ms/div

V_IN: 3 V/div

V_EN: 3 V/div

V_OUT: 1 V/div

V_PGD: 5 V/div

V_OUT: 1 V/div

V_PGD: 5 V/div

Figure 19. Start-up at R_Load= 0.6 Ω: V_EN= 0 V to 5 V

Figure 20. Shutdown at R_Load= 0.6 Ω: V_EN= 5 V to 0 V

(V_IN= 5.0 V, V_OUT= 1.8 V, C_SS= OPEN)

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Typical Performance Curves – continued

Time: 500 µs/div

V_IN: 3 V/div

Time: 2 ms/div

V_IN: 3 V/div

V_EN: 3 V/div

V_OUT: 1 V/div

V_EN: 3 V/div

V_OUT: 1 V/div

V_PGD: 5 V/div

Figure 21. Start-up at No Load: V_IN= V_EN= 0 V to 5 V

Figure 22. Shutdown at No Load: V_IN= V_EN= 5 V to 0 V

(V_OUT= 1.8 V, C_SS= OPEN)

Time: 500 µs/div

V_IN: 3 V/div

Time: 2 ms/div

V_IN: 3 V/div

V_EN: 3 V/div

V_OUT: 1 V/div

V_EN: 3 V/div

V_OUT: 1 V/div

V_PGD: 5 V/div

Figure 23. Start-up at R_Load= 0.6 Ω: V_IN= V_EN= 0 V to 5 V

Figure 24. Shutdown at R_Load= 0.6 Ω: V_IN= V_EN= 5 V to 0 V

(V_OUT= 1.8 V, C_SS= OPEN)

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Typical Performance Curves – continued

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-60 -40 -20

0

20

40

60

80 100

-60 -40 -20

0

20

40

60

80 100

Temperature : Ta [°C]

Figure 25. Output Current vs Temperature ^{(Note 1)}

Figure 26. Output Current vs Temperature ^{(Note 1)}

Operating Range: Tj < 150 °C (V_IN= 5.0 V, V_OUT= 1.8 V)

Operating Range: Tj < 150 °C (V_IN= 3.3 V, V_OUT= 1.8 V)

100

95

90

85

80

75

70

65

100

95

90

85

80

75

70

65

60

V

_OUT= 3.3 V (L=1.5 μH)

_OUT= 1.8 V (L=1.0 μH)

_OUT= 1.2 V (L=1.0 μH)

_OUT= 1.0 V (L=1.0 μH)

60

55

50

45

40

= 1.8 V (L=1.0 μH)

V_OUT

55

50

45

40

V

_OUT= 1.2 V (L=1.0 μH)

V

_OUT= 1.0 V (L=1.0 μH)

V

_OUT= 0.6 V (L=1.0 μH)

V

_OUT= 0.6 V (L=1.0 μH)

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current : I_OUT[A]

Figure 27. Efficiency vs Output Current

(V_IN= 5.0 V, L: FDSD0518 series; Murata)

Figure 28. Efficiency vs Output Current

(V_IN= 3.3 V, L: FDSD0518 series; Murata)

(Note 1) Measured on FR-4 board 67.5 mm x 67.5 mm, Copper Thickness: Top and Bottom 70 μm, 2 Internal Layers 35 μm.

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Typical Performance Curves – continued

1.30

1.20

1.10

1.00

0.90

0.80

0.70

1.83

1.82

1.81

1.80

1.79

1.78

1.77

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Input Voltage : V_IN[V]

Figure 29. Output Voltage vs Input Voltage (Line Regulation)

(V_OUT= 1.8 V, I_OUT= 1.0 A)

Figure 30. Switching Frequency vs Input Voltage

(V_OUT= 1.8 V, I_OUT= 1.0 A)

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.83

1.82

1.81

1.80

1.79

1.78

1.77

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Output Current : I_OUT[A]

Figure 31. Output Voltage vs Output Current (Load Regulation)

(V_IN= 5.0 V, V_OUT= 1.8 V)

Figure 32. Switching Frequency vs Output Current

(V_IN= 5.0 V, V_OUT= 1.8 V)

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Typical Performance Curves – continued

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.83

1.82

1.81

1.80

1.79

1.78

1.77

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Output Current : I_OUT[A]

Figure 33. Output Voltage vs Output Current (Load Regulation)

(V_IN= 3.3 V, V_OUT= 1.8 V)

Figure 34. Switching Frequency vs Output Current

(V_IN= 3.3 V, V_OUT= 1.8 V)

Time: 200 µs/div

V_OUT: 2 V/div

Time: 50 ms/div

V_OUT: 2 V/div

V_PGD: 5 V/div

V_SW: 5 V/div

V_PGD: 5 V/div

V_SW: 5 V/div

I_L: 3 A/div

Figure 35. OCP Operation (V_IN= 5.0 V, V_OUT= 1.8 V to 0 V)

Figure 36. SCP Operation (V_IN= 5.0 V, V_OUT= 1.8 V to 0 V)

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Function Explanations

1. Basic Operation

(1) DC/DC Converter Operation

BD9B305QUZ is a synchronous buck DC/DC converter that achieves faster load transient response due to constant

on-time control. The device performs switching operation in PWM (Pulse Width Modulation) control at heavy load. It

operates in Light Load Mode control at lighter load to improve efficiency.

Light Load Mode Control

PWM Control

Output Current [A]

Figure 37. Efficiency Image between Light Load Mode Control and PWM Control

(2) Enable Control

The startup and shutdown can be controlled by the EN voltage (V_EN). When V_ENbecomes 0.920 V (Typ) or more, the

internal circuit is activated and the device starts up. When V_ENbecomes 0.875 V (Typ) or less, the device is shut down.

In this shutdown mode, the High-Side FET and the Low-Side FET are turned off and the SW pin is connected to GND

through an internal resistor 100 Ω (Typ) to discharge the output. The start-up with V_ENmust be at the same time of the

input voltage V_IN(V_IN= V_EN) or after supplying V_IN.

V_IN

0 V

V_EN

V_ENH

V_ENL

0 V

V_OUT

0 V

Startup

Shutdown

Figure 38. Startup and Shutdown with Enable Control Timing Chart

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Function Explanations – continued

(3) Soft Start

When V_ENgoes high, soft start function operates and output voltage gradually rises. This soft start function can

prevent overshoot of the output voltage and excessive inrush current. The soft start time t_SSis 1 ms (Typ) when the SS

pin is left floating. A capacitor connected to the SS pin makes t_SSmore than 1 ms. See page 31 for how to set the soft

start time.

V_IN

0 V

V_EN

0 V

V_OUT

0 V

V_FBTHx 90 %

0.6 V

(Typ)

V_FB

0 V

V_PGD

0 V

t_SS

Figure 39. Soft Start Timing Chart

(4) Power Good Output

When the output voltage V_OUTreaches within ±10 % (Typ) of the voltage setting, the built-in open drain Nch MOSFET

connected to the PGD pin is turned off, and the PGD pin goes Hi-Z (High impedance). When V_OUTreaches outside

±15 % (Typ) of the voltage setting, the open drain Nch MOSFET is turned on and PGD pin is pulled down with 100 Ω

(Typ). It is recommended to connect a pull-up resistor of 10 kΩ to 100 kΩ.

Table 1. PGD Output

State

Before Supply Input Voltage

Shutdown

Condition

V_IN< 0.7 V (Typ)

PGD Output

Hi-Z

V_EN≤ 0.875 V (Typ)

Low (Pull-down)

Hi-Z

90 % (Typ) ≤ V_FB/ V_FBTH≤ 110 % (Typ)

V_FB/ V_FBTH≤ 85 % (Typ) or 115 % (Typ) ≤ V_FB/ V_FBTH

0.7 V (Typ) < V_IN≤ 2.45 V (Typ)

Tj ≥ 175 °C (Typ)

Enable

V_EN≥ 0.920 V (Typ)

Low (Pull-down)

UVLO

TSD

Complete Soft Start

V_FB/ V_FBTH≤ 85 % (Typ)

OCP 256 counts

SCP

Low (Pull-down)

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Function Explanations – continued

V_IN

0 V

V_EN

0 V

+15 % (Typ)

-15 % (Typ)

+10 % (Typ)

-10 % (Typ)

V_OUT

0 V

V_FBTHx 115 % (Typ)

V_FBTHx 85 % (Typ)

V_FBTHx 110 % (Typ)

V_FBTHx 90 % (Typ)

V_FB

0 V

t_SS

V_PGD

0 V

Figure 40. Power Good Timing Chart

(Connecting a pull-up resistor to the PGD pin)

(5) Output Capacitor Discharge Function

When even one of the following conditions is satisfied, output is discharged with 100 Ω (Typ) resistor through the SW

pin.

• Shutdown: V_EN≤ 0.875 V (Typ)

• UVLO: V_IN≤ 2.45 V (Typ)

• TSD: Tj ≥ 175 °C (Typ)

• SCP: Complete Soft Start, V_FB/ V_FBTH≤ 85 % (Typ), and OCP 256 counts

When all of the above conditions are released, output discharge is stopped.

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Function Explanations – continued

2. Protection

The protection circuits are intended for prevention of damage caused by unexpected accidents. Do not use the

continuous protection.

(1) Over Current Protection (OCP) / Short Circuit Protection (SCP)

Over Current Protection (OCP) restricts the flowing current through the Low-Side FET and the High-Side FET for every

switching period. If the inductor current exceeds the Low-Side OCP I_LOCP= 4.5 A (Typ) while the Low-Side FET is on,

the Low-Side FET remains on even with FB voltage V_FBfalls to V_FBTH= 0.6 V (Typ) or lower. If the inductor current

becomes lower than I_LOCP, the High-Side FET is able to be turned on. When the inductor current becomes the

High-Side OCP I_HOCP= 6.5 A (Typ) or more while the High-Side FET is on, the High-Side FET is turned off. Output

voltage may decrease by changing frequency and duty due to the OCP operation.

Short Circuit Protection (SCP) function is a Hiccup mode. When Low-Side OCP operates 256 cycles while V_FBis V_FBTH

x 85 % or less (V_PGD= Low), the device stops the switching operation for 128 ms (Typ). After the 128 ms (Typ), the

device restarts. SCP does not operate during the soft start even if the device is in the SCP conditions. Do not exceed

the maximum junction temperature (Tjmax = 150 °C) during OCP and SCP operation.

Table 2. The Operating Condition of OCP and SCP

V_EN

V_FB

Start-up

OCP

SCP

≤ V_FBTHx 85 % (Typ)

> V_FBTHx 85 % (Typ)

≤ V_FBTHx 85 % (Typ)

-

During Soft Start

Enable

Disable

Enable

Disable

≥ 0.920 V (Typ)

≤ 0.875 V (Typ)

Complete Soft Start

Shutdown

V_OUT

V_FBTHx 90 % (Typ)

V_FBTHx 85 % (Typ)

V_FB

V_PGD

V_SW

High-Side FET

Internal Gate Signal

Low-Side FET

Internal Gate Signal

I_HOCP

I_LOCP

Inductor Current

High-Side OCP

Internal Signal

Low-Side OCP

Internal Signal

OCP 256 counts

Less than

OCP 256 counts

SCP

Internal Signal

128 ms (Typ)

Figure 41. OCP and SCP Timing Chart

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Function Explanations – continued

(2) Under Voltage Lockout Protection (UVLO)

When input voltage V_INfalls to 2.45 V (Typ) or lower, the device is shut down. When V_INbecomes 2.55 V (Typ) or more,

the device starts up. The hysteresis is 100 mV (Typ).

V_IN

(=V_EN

)

Hysteresis

V_UVLOHYS= 100 mV (Typ)

V_OUT

UVLO Release

V_UVLO2= 2.55 V (Typ)

UVLO Detect

V_UVLO1= 2.45 V (Typ)

0 V

V_OUT

0 V

t_SS

Figure 42. UVLO Timing Chart

(3) Thermal Shutdown Protection (TSD)

Thermal shutdown circuit prevents heat damage to the IC. The device should always operate within the IC’s maximum

junction temperature rating (Tjmax = 150 °C). However, if it continues exceeding the rating and the junction

temperature Tj rises to 175 °C (Typ), the TSD circuit is activated and it turns the output MOSFETs off. When the Tj falls

below the TSD threshold, the circuits are automatically restored to normal operation. The TSD threshold has a

hysteresis of 25 °C (Typ). Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings.

Therefore, under no circumstances, should the TSD circuit be used in a set design or for any purpose other than

protecting the IC from heat damage.

(4) Over Voltage Protection (OVP)

When the FB voltage V_FBexceeds V_FBTHx 115 % (Typ) or more, the output MOSFETs are turned off to prevent the

increase in the output voltage. After the V_FBfalls V_FBTHx 110 % (Typ) or less, the output MOSFETs are returned to

normal operation condition. Switching operation will restart after V_FBfalls below V_FBTH

.

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Application Examples

1. V_IN= 5 V, V_OUT= 3.3 V

Table 3. Specification of Application (V_IN= 5 V, V_OUT= 3.3 V)

Parameter

Symbol

V_IN

Specification Value

Input Voltage

5 V (Typ)

3.3 V (Typ)

3.0 A

Output Voltage

V_OUT

I_OUTMAX

f_SW

Maximum Output Current

Switching Frequency

Soft Start Time

1.0 MHz (Typ)

1 ms (Typ)

25 °C

t_SS

Temperature

Ta

R₃

R₄

R₂

5

6

7

8

SS

EN

FB

4

3

2

1

C₆

C₄

R₆

R₁

R₀

C₇

PGD

SW

PGD

EN

R₅

BD9B305QUZ

L₁

VIN

VOUT

GND

C₃

C₂

C₁

C₅

C₈

GND

BOOT

EXP-PAD

GND

Figure 43. Application Circuit

Table 4. Recommended Component Values (V_IN= 5 V, V_OUT= 3.3 V)

Part No.

Value

1.5 μH

Part Name

FDSD0518-H-1R5M

GRM033R61C104KE14

GRM188R61A226ME15

-

Size Code (mm)

Manufacturer

Murata

-

L₁

5249

0603

1608

-

(Note 1)

C₁

C₂

C₃

0.1 μF (16V, X5R, ±10 %)

22 μF (10V, X5R, ±20 %)

-

(Note 2)

C₄

-

(Note 3)

C₅

0.1 μF (16V, X5R, ±10 %)

100 pF (50 V, C0G, ±5 %)

22 μF (10V, X5R, ±20 %)

200 kΩ (1 %, 1/16 W)

12 kΩ (1 %, 1/16 W)

47 kΩ (1 %, 1/16 W)

100 kΩ (1 %, 1/16 W)

1.8 MΩ (1 %, 1/16 W)

470 kΩ (1 %, 1/16 W)

Short

GRM033R61C104KE14

GRM0335C1H101JA01

GRM188R61A226ME15

MCR01MZPF2003

MCR01MZPF1202

MCR01MZPF4702

MCR01MZPF1003

MCR01MZPF1804

MCR01MZPF4703

-

0603

1608

1005

-

Murata

ROHM

-

C₆

(Note 4)

C₇

C₈

(Note 4)

R₁

R₂

R₃

R₄

R₅

R₆

(Note 5)

R₀

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C₁as close as possible to the VIN pin and the GND

pin if needed.

(Note 2) For the input capacitor C₂and C₃, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual

capacitance of no less than 4.7 μF.

(Note 3) For the bootstrap capacitor C₅, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance

of no less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C₇and

C₈, the loop response characteristics may change. Confirm with the actual application. The total capacitance of 10 μF to 47 x 2 μF is

recommended for the output capacitor.

(Note 5) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, use this resistor pattern in short-circuit

mode.

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1. V_IN= 5 V, V_OUT= 3.3 V – continued

Time: 2 µs/div

V_OUT: 20 mV/div

V_SW: 2 V/div

Figure 44. Output Ripple Voltage (I_OUT= 0.1 A)

Figure 45. Output Ripple Voltage (I_OUT= 3.0 A)

80

180

135

90

Gain

Time: 100 µs/div

V_OUT: 200 mV/div

60

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 500 mA/div

1

10

100

1000

Frequency [kHz]

Figure 46. Frequency Characteristics (I_OUT= 3.0 A)

Figure 47. Load Transient Response (I_OUT= 0.1 A to 1.0 A)

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Application Examples – continued

2. V_IN= 5 V, V_OUT= 1.8 V

Table 5. Specification of Application (V_IN= 5 V, V_OUT= 1.8 V)

Parameter

Input Voltage

Symbol

V_IN

Specification Value

5 V (Typ)

1.8 V (Typ)

3.0 A

Output Voltage

V_OUT

I_OUTMAX

f_SW

Maximum Output Current

Switching Frequency

Soft Start Time

1.0 MHz (Typ)

1 ms (Typ)

25 °C

t_SS

Temperature

Ta

R₃

R₄

R₂

5

6

7

8

SS

EN

FB

4

3

2

1

C₆

C₄

R₆

R₁

R₀

C₇

PGD

SW

PGD

EN

R₅

BD9B305QUZ

L₁

VIN

VOUT

GND

C₃

C₂

C₁

C₅

C₈

GND

BOOT

EXP-PAD

GND

Figure 48. Application Circuit

Table 6. Recommended Component Values (V_IN= 5 V, V_OUT= 1.8 V)

Part No.

Value

1.0 μH

Part Name

Size Code (mm)

Manufacturer

L₁

FDSD0518-H-1R0M

5249

Murata

(Note 1)

C₁

C₂

C₃

0.1 μF (16V, X5R, ±10 %)

GRM033R61C104KE14

0603

Murata

(Note 2)

22 μF (10V, X5R, ±20 %)

GRM188R61A226ME15

1608

Murata

-

C₄

-

(Note 3)

C₅

0.1 μF (16V, X5R, ±10 %)

GRM033R61C104KE14

0603

Murata

C₆

100 pF (50 V, C0G, ±5 %)

GRM0335C1H101JA01

0603

Murata

(Note 4)

C₇

C₈

47 μF (4 V, X5R, ±20 %)

AMK107BBJ476MA-RE

1608

TAIYO YUDEN

(Note 4)

-

R₁

R₂

R₃

R₄

R₅

200 kΩ (1 %, 1/16 W)

MCR01MZPF2003

1005

ROHM

Short

-

100 kΩ (1 %, 1/16 W)

MCR01MZPF1003

1005

ROHM

100 kΩ (1 %, 1/16 W)

MCR01MZPF1003

1005

ROHM

-

R₆

(Note 5)

R₀

Short

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C₁as close as possible to the VIN pin and the GND

pin if needed.

(Note 2) For the input capacitor C₂and C₃, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual

capacitance of no less than 4.7 μF.

(Note 3) For the bootstrap capacitor C₅, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance

of no less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C₇and

C₈, the loop response characteristics may change. Confirm with the actual application. The total capacitance of 10 μF to 47 x 2 μF is

recommended for the output capacitor.

(Note 5) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, use this resistor pattern in short-circuit

mode.

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2. V_IN= 5 V, V_OUT= 1.8 V – continued

Time: 2 µs/div

V_OUT: 20 mV/div

V_SW: 2 V/div

Figure 49. Output Ripple Voltage (I_OUT= 0.1 A)

Figure 50. Output Ripple Voltage (I_OUT= 3.0 A)

80

180

135

90

Gain

Time: 100 µs/div

V_OUT: 100 mV/div

60

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 500 mA/div

1

10

100

1000

Frequency [kHz]

Figure 51. Frequency Characteristics (I_OUT= 3.0 A)

Figure 52. Load Transient Response (I_OUT= 0.1 A to 1.0 A)

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Application Examples – continued

3. V_IN= 5 V, V_OUT= 1.2 V

Table 7. Specification of Application (V_IN= 5 V, V_OUT= 1.2 V)

Parameter

Input Voltage

Symbol

V_IN

Specification Value

5 V (Typ)

1.2 V (Typ)

3.0 A

Output Voltage

V_OUT

I_OUTMAX

f_SW

Maximum Output Current

Switching Frequency

Soft Start Time

1.0 MHz (Typ)

1 ms (Typ)

25 °C

t_SS

Temperature

Ta

R₃

R₄

R₂

5

6

7

8

SS

EN

FB

4

3

2

1

C₆

C₄

R₆

R₁

R₀

C₇

PGD

SW

PGD

EN

R₅

BD9B305QUZ

L₁

VIN

VOUT

GND

C₃

C₂

C₁

C₅

C₈

GND

BOOT

EXP-PAD

GND

Figure 53. Application Circuit

Table 8. Recommended Component Values (V_IN= 5 V, V_OUT= 1.2 V)

Part No.

Value

1.0 μH

Part Name

Size Code (mm)

Manufacturer

L₁

FDSD0518-H-1R0M

5249

Murata

(Note 1)

C₁

C₂

C₃

0.1 μF (16V, X5R, ±10 %)

GRM033R61C104KE14

0603

Murata

(Note 2)

22 μF (10V, X5R, ±20 %)

GRM188R61A226ME15

1608

Murata

-

C₄

-

(Note 3)

C₅

0.1 μF (16V, X5R, ±10 %)

GRM033R61C104KE14

0603

Murata

C₆

120 pF (50 V, C0G, ±5 %)

GRM0335C1H121JA01

0603

Murata

(Note 4)

C₇

C₈

47 μF (4 V, X5R, ±20 %)

AMK107BBJ476MA-RE

1608

TAIYO YUDEN

(Note 4)

-

R₁

R₂

R₃

R₄

R₅

150 kΩ (1 %, 1/16 W)

MCR01MZPF1503

1005

ROHM

Short

-

150 kΩ (1 %, 1/16 W)

MCR01MZPF1503

1005

ROHM

100 kΩ (1 %, 1/16 W)

MCR01MZPF1003

1005

ROHM

-

R₆

(Note 5)

R₀

Short

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C₁as close as possible to the VIN pin and the GND

pin if needed.

(Note 2) For the input capacitor C₂and C₃, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual

capacitance of no less than 4.7 μF.

(Note 3) For the bootstrap capacitor C₅, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance

of no less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C₇and

C₈, the loop response characteristics may change. Confirm with the actual application. The total capacitance of 10 μF to 47 x 2 μF is

recommended for the output capacitor.

(Note 5) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, use this resistor pattern in short-circuit

mode.

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3. V_IN= 5 V, V_OUT= 1.2 V – continued

Time: 2 µs/div

V_OUT: 20 mV/div

V_SW: 2 V/div

Figure 54. Output Ripple Voltage (I_OUT= 0.1 A)

Figure 55. Output Ripple Voltage (I_OUT= 3.0 A)

80

180

135

90

Gain

Time: 100 µs/div

V_OUT: 100 mV/div

60

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 500 mA/div

1

10

100

1000

Frequency [kHz]

Figure 56. Frequency Characteristics (I_OUT= 3.0 A)

Figure 57. Load Transient Response (I_OUT= 0.1 A to 1.0 A)

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Application Examples – continued

4. V_IN= 5 V, V_OUT= 1.0 V

Table 9. Specification of Application (V_IN= 5 V, V_OUT= 1.0 V)

Parameter

Input Voltage

Symbol

V_IN

Specification Value

5 V (Typ)

1.0 V (Typ)

3.0 A

Output Voltage

V_OUT

I_OUTMAX

f_SW

Maximum Output Current

Switching Frequency

Soft Start Time

1.0 MHz (Typ)

1 ms (Typ)

25 °C

t_SS

Temperature

Ta

R₃

R₄

R₂

5

6

7

8

SS

EN

FB

4

3

2

1

C₆

C₄

R₆

R₁

R₀

C₇

PGD

SW

PGD

EN

R₅

BD9B305QUZ

L₁

VIN

VOUT

GND

C₃

C₂

C₁

C₅

C₈

GND

BOOT

EXP-PAD

GND

Figure 58. Application Circuit

Table 10. Recommended Component Values (V_IN= 5 V, V_OUT= 1.0 V)

Part No.

Value

1.0 μH

Part Name

Size Code (mm)

Manufacturer

L₁

FDSD0518-H-1R0M

5249

Murata

(Note 1)

C₁

C₂

C₃

0.1 μF (16V, X5R, ±10 %)

GRM033R61C104KE14

0603

Murata

(Note 2)

22 μF (10V, X5R, ±20 %)

GRM188R61A226ME15

1608

Murata

-

C₄

-

(Note 3)

C₅

0.1 μF (16V, X5R, ±10 %)

GRM033R61C104KE14

0603

Murata

C₆

120 pF (50 V, C0G, ±5 %)

GRM0335C1H121JA01

0603

Murata

(Note 4)

C₇

C₈

47 μF (4 V, X5R, ±20 %)

AMK107BBJ476MA-RE

1608

TAIYO YUDEN

(Note 4)

-

R₁

R₂

R₃

R₄

R₅

100 kΩ (1 %, 1/16 W)

MCR01MZPF1003

1005

ROHM

Short

-

150 kΩ (1 %, 1/16 W)

MCR01MZPF1503

1005

ROHM

100 kΩ (1 %, 1/16 W)

MCR01MZPF1003

1005

ROHM

-

R₆

(Note 5)

R₀

Short

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C₁as close as possible to the VIN pin and the GND

pin if needed.

(Note 2) For the input capacitor C₂and C₃, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual

capacitance of no less than 4.7 μF.

(Note 3) For the bootstrap capacitor C₅, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance

of no less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C₇and

C₈, the loop response characteristics may change. Confirm with the actual application. The total capacitance of 10 μF to 47 x 2 μF is

recommended for the output capacitor.

(Note 5) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, use this resistor pattern in short-circuit

mode.

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4. V_IN= 5 V, V_OUT= 1.0 V – continued

Time: 2 µs/div

V_OUT: 20 mV/div

V_SW: 2 V/div

Figure 59. Output Ripple Voltage (I_OUT= 0.1 A)

Figure 60. Output Ripple Voltage (I_OUT= 3.0 A)

80

180

135

90

Gain

Time: 100 µs/div

V_OUT: 100 mV/div

60

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 500 mA/div

1

10

100

1000

Frequency [kHz]

Figure 61. Frequency Characteristics (I_OUT= 3.0 A)

Figure 62. Load Transient Response (I_OUT= 0.1 A to 1.0 A)

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Application Examples – continued

5. V_IN= 5 V, V_OUT= 0.6 V

Table 11. Specification of Application (V_IN= 5 V, V_OUT= 0.6 V)

Parameter

Input Voltage

Symbol

V_IN

Specification Value

5 V (Typ)

Output Voltage

V_OUT

I_OUTMAX

f_SW

0.6 V (Typ)

3.0 A

Maximum Output Current

Switching Frequency

Soft Start Time

1.0 MHz (Typ)

1 ms (Typ)

25 °C

t_SS

Temperature

Ta

R₃

R₄

R₂

5

6

7

8

SS

EN

FB

4

3

2

1

C₆

C₄

R₆

R₁

R₀

PGD

SW

PGD

EN

R₅

BD9B305QUZ

L₁

VIN

VOUT

GND

C₃

C₂

C₁

C₅

C₇

C₈

GND

BOOT

EXP-PAD

GND

Figure 63. Application Circuit

Table 12. Recommended Component Values (V_IN= 5 V, V_OUT= 0.6 V)

Part No.

Value

1.0 μH

Part Name

Size Code (mm)

Manufacturer

L₁

FDSD0518-H-1R0M

5249

Murata

(Note 1)

C₁

C₂

C₃

0.1 μF (16V, X5R, ±10 %)

GRM033R61C104KE14

0603

Murata

(Note 2)

22 μF (10V, X5R, ±20 %)

GRM188R61A226ME15

1608

Murata

-

C₄

-

(Note 3)

C₅

0.1 μF (16V, X5R, ±10 %)

GRM033R61C104KE14

0603

Murata

C₆

120 pF (50 V, C0G, ±5 %)

GRM0335C1H121JA01

0603

Murata

(Note 4)

C₇

C₈

47 μF (4 V, X5R, ±20 %)

AMK107BBJ476MA-RE

1608

TAIYO YUDEN

(Note 4)

-

R₁

R₂

R₃

R₄

R₅

100 kΩ (1 %, 1/16 W)

MCR01MZPF1003

1005

ROHM

Short

-

100 kΩ (1 %, 1/16 W)

MCR01MZPF1003

1005

ROHM

-

R₆

(Note 5)

R₀

Short

(Note 1) In order to reduce the influence of high frequency noise, connect a 0.1 μF ceramic capacitor C₁as close as possible to the VIN pin and the GND

pin if needed.

(Note 2) For the input capacitor C₂and C₃, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual

capacitance of no less than 4.7 μF.

(Note 3) For the bootstrap capacitor C₅, take temperature characteristics, DC bias characteristics, etc. into consideration to set to the actual capacitance

of no less than 0.022 μF.

(Note 4) In case of changing the actual capacitance value due to temperature characteristics, DC bias characteristics, etc. of the output capacitor C₇and

C₈, the loop response characteristics may change. Confirm with the actual application. The total capacitance of 10 μF to 47 x 2 μF is

recommended for the output capacitor.

(Note 5) R₀is an option, used for feedback’s frequency response measurement. By inserting a resistor at R₀, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, use this resistor pattern in short-circuit

mode.

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5. V_IN= 5 V, V_OUT= 0.6 V – continued

Time: 2 µs/div

V_OUT: 20 mV/div

V_SW: 2 V/div

Figure 64. Output Ripple Voltage (I_OUT= 0.1 A)

Figure 65. Output Ripple Voltage (I_OUT= 3.0 A)

80

180

135

90

Gain

Time: 100 µs/div

V_OUT: 100 mV/div

60

Phase

40

20

45

0

-20

-40

-60

-80

-45

-90

-135

-180

I_OUT: 500 mA/div

1

10

100

1000

Frequency [kHz]

Figure 66. Frequency Characteristics (I_OUT= 3.0 A)

Figure 67. Load Transient Response (I_OUT= 0.1 A to 1.0 A)

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Selection of Components Externally Connected

Contact us if not use the recommended component values in Application Examples.

1. Input Capacitor

Use ceramic type capacitor for the input capacitor. The input capacitor is used to reduce the input ripple noise and it is

effective by being placed as close as possible to the VIN pin. Set the capacitor value so that it does not fall to 4.7 μF

considering the capacitor value variances, temperature characteristics, DC bias characteristics, aging characteristics, and

etc. The PCB layout and the position of the capacitor may lead to IC malfunction. Refer to the notes on the PCB layout on

page 34 to 35 when designing PCB layout. In addition, the capacitor with value 0.1 μF can be connected as close as

possible to the VIN pin and the GND pin in order to reduce the high frequency noise.

2. Output Voltage Setting

The output voltage can be set by the feedback resistance ratio connected to the FB pin. For stable operation, the parallel

resistance of feedback resistors R₁and R₂should be set to 20 kΩ or more.

V_OUT

The output voltage V_OUTcan be calculated as below.

C_FB

R₁

푅 +푅

1

²× 0.6 [V]

푅

2

Error Amplifier

푉_푂푈푇

=

FB

R₂

0.6 V

(Typ)

0.6 ≤ 푉_푂푈푇≤ (푉 × 0.8) [V]

퐼푁

ꢁ

ꢀ⁄(_푅^ꢁꢂ _푅) ≥ ꢃ0 [kΩ]

1

2

Figure 68. Feedback Resistor Circuit

3. Soft Start Capacitor (Soft Start Time Setting)

The soft start time t_SSdepends on the value of the capacitor connected to the SS pin. The t_SSis 1 ms (Typ) when the SS

pin is left floating. The capacitor connected to the SS pin makes t_SSmore than 1 ms. The t_SSand C_SScan be calculated

using below equation. The C_SSshould be set in the range between 3300 pF and 0.1 μF.

퐶

×ꢅ.ꢆ

ꢄꢄ

푡_푆푆=

[s]

퐼

ꢄꢄ

where:

ꢇ_푆푆is the Soft Start Charge Current 1.0 µA (Typ).

With C_SS= 8200 pF, t_SScan be calculated as below.

ꢈꢉꢅꢅ 푝퐹×ꢅ.ꢆ

푡_푆푆=

= 4.9 [ms]

ꢁ.ꢅ 휇퐴

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Selection of Components Externally Connected – continued

4. Output LC Filter

In order to supply a continuous current to the load, the DC/DC converter requires an LC filter for smoothing the output

voltage. Use the inductor with value 1.0 μH to 1.5 μH.

V_IN

I_L

Inductor saturation current > I_OUTMAX+ ∆I_L/2

L₁

V_OUT

Driver

∆I_L

Maximum Output Current I_OUTMAX

C_OUT

t

Figure 69. Waveform of Inductor Current

Figure 70. Output LC Filter Circuit

For example, given that V_IN= 5 V, V_OUT= 1.8 V, L₁= 1.0 μH, and the switching frequency f_SW= 1.0 MHz, Inductor current

ΔI_Lcan be represented by the following equation.

ꢁ

(

)

×

∆ꢇ_퐿= 푉_푂푈푇× 푉 − 푉_푂푈푇

= ꢀ.ꢀ5 [A]

퐼푁

ꢊ

ꢋꢌ

×푓 ×퐿

ꢄ푊

1

The rated current of the inductor (Inductor saturation current) must be larger than the sum of the maximum output current

I_OUTMAXand 1/2 of the inductor ripple current ΔI_L.

Use ceramic type capacitor for the output capacitor C_OUT.The capacitance value of C_OUTis recommended in the range

between 10 μF and 47 x 2 μF. C_OUTaffects the output ripple voltage. Select C_OUTso that it must satisfy the required ripple

voltage characteristics.

The output ripple voltage can be estimated by the following equation.

ꢁ

∆푉_푅푃퐿= ∆ꢇ_퐿× ꢍꢎ_퐸푆푅ꢂ _ꢈ×퐶

ꢒ [V]

ꢄ푊

×푓

ꢏꢐꢑ

where:

ꢎ_퐸푆푅is the Equivalent Series Resistance (ESR) of the output capacitor.

For example, given that C_OUT= 47 μF and R_ESR= 3 mΩ, ΔV_RPLcan be calculated as below.

ꢁ

∆푉_푅푃퐿= ꢀ.ꢀ5 ꢓ × ꢍ3 푚훺 ꢂ _{ꢈ×ꢔ7 휇퐹×ꢁ 푀퐻푧}ꢒ = 6.5 [mV]

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4. Output LC Filter – continued

In addition, the total capacitance connected to V_OUTneeds to satisfy the value obtained by the following equation.

ꢖ

ꢕ_{푂푈푇푀퐴푋}

<

^{ꢄꢄꢗꢋꢌ}× (3.ꢀ ꢂ ^∆퐼^ꢘ− ꢇ_{푂푈푇푆푆}) [F]

ꢊ

ꢉ

ꢏꢐꢑ

where:

푡_{푆푆푀퐼푁}is the minimum soft start time.

푉_푂푈푇is the output voltage.

∆I_Lis the inductor current.

I_OUTSSis the maximum output current during soft start.

For example, given that V_IN= 5 V, V_OUT= 1.8 V, L₁= 1.0 µH, f_SW= 1 MHz (Typ), t_SSMIN= 0.6 ms (C_SS= OPEN), and I_OUTSS

3 A, C_OUTMAXcan be calculated as below.

=

ꢕ_{푂푈푇푀퐴푋}

<

^{ꢅ.ꢆ ꢙ푠}× (3.ꢀ ꢂ ^{ꢁ.ꢁꢚ 퐴}− 3 ꢓ) = ꢃꢃ5 [µF]

ꢁ.ꢈ ꢊ ꢉ

If the total capacitance connected to V_OUTis larger than C_OUTMAX, over current protection may be activated by the inrush

current at startup and prevented to turn on the output. Confirm this on the actual application.

5. FB Capacitor

The Constant On-time Control required the sufficient ripple voltage on FB voltage for the operation stability. This device is

designed to correspond to low ESR output capacitors by injecting the ripple voltage to FB voltage inside the IC. The FB

capacitor C_FB(Figure 68) should be set within the range of the following expression in order to inject an appropriate ripple.

ꢜ

ꢊ

ꢋꢌ

ꢊ

×(ꢁꢛꢊ

ꢊ

ꢋꢌ

)

ꢊ

×(ꢁꢛꢊ

)

ꢏꢐꢑ

< ꢕ_퐹퐵

<

[F]

ꢝ

푓

×ꢉꢁ×ꢁꢅ

푓

×ꢞ.ꢞ×ꢁꢅ

ꢄ푊

where:

is the input voltage.

푉

퐼푁

푉_푂푈푇is the output voltage.

f_SWis the switching frequency 1.0 MHz (Typ).

Load transient response and the loop stability depends on L₁, C_OUT, and C_FB. Actually, these characteristics may change

depending on PCB layout, wiring, the type of components, and the conditions (temperature, etc.). Be sure to check them

on the actual application.

6. Bootstrap Capacitor

The bootstrap capacitor 0.1μF is recommended. Connect the capacitor between the SW pin and the BOOT pin. For the

capacitance, take temperature characteristics, DC bias characteristics, and etc. into consideration to set to the actual

capacitance of no less than 0.022 μF.

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PCB Layout Design

PCB layout design for DC/DC converter is very important. Appropriate layout can avoid various problems concerning power

supply circuit. Figure 71-a to Figure 71-c show the current path in a buck DC/DC converter circuit. The Loop 1 in Figure 71-a is

a current path when H-side switch is ON and L-side switch is OFF, the Loop 2 in Figure 71-b is when H-side switch is OFF and

L-side switch is ON. The thick line in Figure 71-c shows the difference between Loop1 and Loop2. The current in thick line

change sharply each time the switching element H-side and L-side switch change from OFF to ON, and vice versa. These

sharp changes induce a waveform with harmonics in this loop. Therefore, the loop area of thick line that is consisted by input

capacitor and IC should be as small as possible to minimize noise. For more details, refer to application note of switching

regulator series “PCB Layout Techniques of Buck Converter”.

Loop1

V_IN

V_OUT

L

H-side Switch

C_IN

C_OUT

L-side Switch

GND

Figure 71-a. Current Path when H-side Switch = ON, L-side Switch = OFF

V_IN

V_OUT

L

H-side Switch

C_IN

C_OUT

Loop2

L-side Switch

GND

Figure 71-b. Current Path when H-side Switch = OFF, L-side Switch = ON

V_IN

V_OUT

L

C_IN

C_OUT

High-Side FET

Low-Side FET

GND

Figure 71-c. Difference of Current and Critical Area in Layout

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PCB Layout Design – continued

When designing the PCB layout, pay attention to the following points:

• Connect the input capacitor C_IN1and C_IN2as close as possible to the VIN pin and GND pin on the same plane as the IC.

• Switching nodes such as SW are susceptible to noise due to AC coupling with other nodes. Route the inductor pattern L₁as

thick and as short as possible.

• Feedback line connected to the FB pin far from the SW nodes.

• Place the output capacitor C_OUTaway from input capacitor C_IN1and C_IN2to avoid harmonics noise from the input.

• Separate the reference ground and the power ground and connect them through VIA. The reference ground should be

connected to the power ground that is close to the output capacitor C_OUT. It is because C_OUThas less high frequency

switching noise.

• R₀is provided for the measurement of feedback frequency characteristics (optional). By inserting a resistor into R₀, it is

possible to measure the frequency characteristics of feedback (phase margin) using FRA etc. R₀is short-circuited for

normal use.

R₂

R₁

R₀

R_PGD

5

6

7

8

SS

FB

4

3

2

1

C_SS

C_FB

PGD

EN

PGD

EN

BD9B305QUZ

L₁

VIN

GND

SW

VOUT

GND

C_IN2

(22 μF)

C_IN1

(0.1 μF)

C_BOOT

(0.1 μF)

C_OUT

(47 μF)

BOOT

GND

EXP-PAD

Figure 72. Application Circuit

Reference Ground

VIN

Pin 1

L₁

VOUT

BD9B305QUZ

C_BOOT

Power Ground

Thermal VIA

Signal VIA

Figure 73. Example of PCB Layout

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I/O Equivalence Circuits

1. BOOT

3. PGD

5. SS

2. SW

BOOT

VIN

BOOT

SW

93 Ω

SW

4. FB

VIN

PGD

10 kΩ

FB

6. EN

VIN

10 kΩ

EN

SS

10 kΩ

(Note) Resistor values are typical.

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Operational Notes

1.

2.

3.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. However,

pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go below ground

due to back EMF or electromotive force. In such cases, the user should make sure that such voltages going below

ground will not cause the IC and the system to malfunction by examining carefully all relevant factors and conditions

such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few.

4.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

6.

Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and

routing of connections.

7.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

8.

9.

Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

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Operational Notes – continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 74. Example of Monolithic IC Structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

12. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

13. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

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Ordering Information

B D 9 B 3

0

5

Q U Z -

E 2

Package

VMMP08LZ2020

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagram

VMMP08LZ2020 (TOP VIEW)

Part Number Marking

D 9 B

3 0 5

LOT Number

Pin 1 Mark

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TSZ22111 • 15 • 001

TSZ02201-0F3F0AJ00250-1-2

20.Feb.2023 Rev.002

39/41

BD9B305QUZ

Physical Dimension and Packing Information

Package Name

VMMP08LZ2020

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0F3F0AJ00250-1-2

40/41

20.Feb.2023 Rev.002

BD9B305QUZ

Revision History

Date

Revision

001

Changes

08.Mar.2019

20.Feb.2023

New Release

Change the recommended components C₆, C₇and C₈in Table 4.

Update Figure 44, Figure 45, Figure 46 and Figure 47.

002

www.rohm.com

TSZ22111 • 15 • 001

TSZ02201-0F3F0AJ00250-1-2

41/41

20.Feb.2023 Rev.002

Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.004


型号：	BD9B305QUZ
厂家：	ROHM
描述：	BD9B305QUZ是一款同步整流降压DC/DC转换器，内置低导通电阻功率MOSFET。可以输出高达3A的输出电流。采用固定导通时间控制方法，具有高速负载响应性能。采用轻负载模式控制方式，可提高轻负载时的效率，适用于需要降低待机时功耗的设备。具有电源良好输出功能，可实现系统的时序控制。采用小型封装，可实现高功率和减小安装面积。Power Supply Reference BoardFor Xilinx’s FPGA Spartan-7 转换器
文件：	总44页 (文件大小：2952K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD9B305QUZ [ROHM]

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