BD9B333GWZ_技术文档

Datasheet

2.7V to 5.5V Input, 3.0A Integrated MOSFET

Single Synchronous Buck DC/DC Converter

BD9B333GWZ

General Description

Key Specifications

BD9B333GWZ is a synchronous buck DC/DC converter

with built-in low on-resistance power MOSFETs. This IC,

which is capable of providing current up to 3A, features

fast transient response by employing constant on-time

control system. It offers high oscillating frequency at low

inductance. With its original constant on-time control

method which operates low consumption at light load,

this product is ideal for equipment and devices that

demand minimal standby power consumption.

BD9B333GWZ achieves the high power density and offer

a small footprint on the PCB by employing small CSP

package.



Input Voltage Range:

Output Voltage Range:

Output Current:

Switching Frequency:

High-Side MOSFET ON Resistance: 23mΩ (Typ)

Low-Side MOSFET ON Resistance: 23mΩ (Typ)

2.7V to 5.5V

0.6 V to V_INx 0.8 V

3A (Max)

1.3MHz (Typ)

Standby Current:

0μA (Typ)

Package

W (Typ) x D (Typ) x H (Max)

1.98mm x 1.80mm x 0.40mm

UCSP35L1

Features



Single Synchronous Buck DC/DC Converter

Constant On-time Control Suitable to Deep-SLLM

Over Current Protection

Short Circuit Protection

Over Voltage Protection

Thermal Shutdown Protection

Under Voltage Lockout Protection

Adjustable Soft Start

Power Good Output

UCSP35L1 Package (Resin Coating)

UCSP35L1

Applications

 Step-down Power Supply for DSPs, FPGAs,

Microprocessors, etc.

 Laptop PCs/Tablet PCs/Servers

 LCD TVs

 Storage Devices (HDDs/SSDs)

 Printers, OA Equipment

 Distributed Power Supplies, Secondary Power

Supplies

Typical Application Circuit

V_IN

V_PGD

V_OUT

C_OUT

C_IN

PVIN

AVIN

PGD

BOOT

SW

Enable

EN

C_BST

BD9B333GWZ

MODE

SS

L

R₁

R₂

C_FB

FB

AGND

PGND

Figure 1. Application Circuit (MODE=L)

〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays

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Pin Configuration

(BOTTOM VIEW)

D3

D4

D1

D2

PVIN

D

C

B

A

AVIN

BOOT

C1

EN

C3

SW

C4

SW

C2

SS

B1

PGD

B2

MODE

B3

SW

B4

SW

A1

FB

A4

PGND

A2

AGND

A3

PGND

1

2

3

4

Figure 2. Pin Configuration

Pin Descriptions

Name

Pin No.

Function

An inverting input node for the error amplifier and main comparator.

See page 31 for how to calculate the resistance of the output voltage setting.

A1

FB

A2

AGND

PGND

Ground terminal for the control circuit.

A3, A4

Ground terminals for the output stage of the switching regulator.

Power Good terminal. A pull-up resistor is needed due to an open drain output. See page 17

for how to specify the resistance. When the FB terminal voltage reaches more than 90% of

0.6V (Typ), the internal Nch MOSFET turns off and the output turns High.

B1

B2

PGD

Terminal for setting switching control mode. Connecting this terminal to AVIN forces the

device to operate in the fixed frequency PWM mode. Connecting this terminal to ground

MODE enables the Deep-SLLM control and the mode is automatically switched between the

Deep-SLLM control and fixed frequency PWM mode. Please fix this terminal to AVIN or

ground. Do not change the control mode during operation.

Switch terminals. These terminals are connected to the source of the High-Side MOSFET

B3, B4

C3, C4

and drain of the Low-Side MOSFET. Connect a bootstrap capacitor of 0.1µF between these

terminals and BOOT terminal. In addition, connect an inductor considering the direct current

SW

superimposition characteristic.

Enable terminal. Turning this terminal signal Low (0.5V or less) forces the device to enter the

C1

C2

EN

SS

shutdown mode. Turning this terminal signal High (1.5V or more) enables the device. This

terminal must be properly terminated.

Terminal for setting the soft start time. Rising time of output voltage is 1ms (Typ) when SS

terminal is open. A capacitor connected to the SS terminal makes rising time more than 1ms.

See page 32 for how to calculate the capacitance.

Terminal for supplying power to the control circuit of the switching regulator.

This terminal is connected to PVIN.

D1

D2

AVIN

Terminal for bootstrap. Connect a bootstrap capacitor of 0.1µF between this terminal and SW

terminals. The voltage of this terminal is the gate drive voltage of the High-Side MOSFET.

BOOT

Power supply terminals for the switching regulator.

D3, D4

PVIN

These terminals supply power to the output stage of the switching regulator.

Connecting a 22µF ceramic capacitor is recommended.

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Block Diagram

AVIN

PVIN

D3

D4

D1

HOCP

LOCP

SCP

EN

C1

UVLO

BOOT

SW

D2

FB

A1

Main

Comparator

On Time

Modulation

Error

Amplifier

Control

Logic

+

SS

B3

B4

C3

C4

On Time

C2

Soft Start

DRV

OVP

VREF

PGND

AGND

A3

A4

TSD

PGOOD

A2

B2

B1

PGD

MODE

Figure 3. Block Diagram

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Description of Blocks

1. VREF

The VREF block generates the internal reference voltage.

2. UVLO

The UVLO block is for under voltage lockout protection. It will shut down the IC when AVIN falls to 2.45 V (Typ) or less.

The threshold voltage has a hysteresis of 100mV (Typ).

3. TSD

The TSD block is for thermal protection. The thermal protection circuit shuts down the device when the internal

temperature of IC rises to 175°C (Typ) or more. Thermal protection circuit resets when the temperature falls. The circuit

has a hysteresis of 25°C (Typ).

4. Soft Start

The Soft Start circuit slows down the rise of output voltage during start-up and controls the current, which allows the

prevention of output voltage overshoot and inrush current. The internal soft start time is set to 1ms (Typ) when the SS

terminal is open. A capacitor connected to the SS terminal makes the rising time more than 1ms.

5. Error Amplifier

Error Amplifier adjusts Main Comparator input voltage to make the internal reference voltage equal to FB terminal

voltage.

6. Main Comparator

Main comparator compares Error Amplifier output voltage and FB terminal voltage. When FB terminal voltage becomes

lower than Error Amplifier output voltage, it outputs High and reports to the On Time block that the output voltage has

dropped below the control voltage.

7. On Time

This is a block which generates On Time. Designed On Time is generated when Main Comparator output becomes

High. On Time is adjusted to restrict frequency change even with Input and Output voltage change.

8. Control Logic + DRV

This block is a DC/DC driver. A signal from On Time block is applied to drive the MOSFETs.

9. PGOOD

When the output voltage reaches 90% (Typ) or more of the voltage setting, the open drain Nch MOSFET, internally

connected to the PGD terminal, turns off and the PGD terminal turns to Hi-Z condition. When the output voltage falls

85% (Typ) or less of the voltage setting, the open drain Nch MOSFET turns on and PGD terminal pulls down with 100Ω

(Typ).

10. HOCP/LOCP/SCP

After soft start is completed and in condition where output voltage is below 85% (Typ) of the voltage setting, this block

counts the number of times of which current flowing in High-Side MOSFET or Low-Side MOSFET reaches over current

limit. When 512 times is counted, it stops operation for 3ms (Typ) and re-operates. Counting is reset when output

voltage is above 90% (Typ) of voltage setting or when IC re-operates by EN, UVLO, SCP function.

11. OVP

The over voltage protection function (OVP) compares FB terminal voltage with the internal reference voltage. When the

FB terminal voltage exceeds 0.72V (Typ), it turns the output MOSFETs off. The output voltage returns with hysteresis

after the output voltage drops to normal operation level.

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Absolute Maximum Ratings (Ta = 25°C)

Parameter

Symbol

Rating

Unit

Input Voltage

V_PVIN, V_AVIN

V_EN

-0.3 to +7

-0.3 to +14

-0.3 to +7

-0.3 to V_PVIN+ 0.3

3.5

V

EN Terminal Voltage

MODE Terminal Voltage

Voltage from GND to BOOT

Voltage from SW to BOOT

FB Terminal Voltage

V_MODE

V_BOOT

ΔV_BOOT

V_FB

V

SW Terminal Voltage

Output Current

V_SW

V

I_OUT

A

Maximum Junction Temperature

Tjmax

150

°C

Storage Temperature Range

Tstg

-55 to +150

°C

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB boards with thermal resistance taken into consideration by

increasing board size and copper area so as not to exceed the maximum junction temperature rating.

Thermal Resistance^{(Note 1)}

Thermal Resistance

Parameter

Symbol

Unit

(Typ)^{(Note 3)}

UCSP35L1

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 2)}

θ_JA

153.8

1.6

°C/W

Ψ_JT

(Note 1) Based on JESD51-2A (Still-Air).

(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 3) Using the specified PCB board.

Evaluation board

Layout of Board for

Measurement

Top Layer (Top View)

Glass epoxy resin (9 layers)

62 mm x 54 mm x 1.6 mmt

Bottom Layer (Bottom View)

Board Material

Board Size

Top layer

Bottom layer

Metal (GND) wiring rate: Approx. 81.6%

Metal (GND) wiring rate: Approx. 82.3%

Wiring

Rate

Outer layer L1,L9 : 27μm

Inner layer L8 : 27μm, L2~L7 : 18μm

Diameter 0.1mm x 256 holes

Diameter 0.6mm x 266 holes

Copper Foil Thickness

Through Hole

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Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltage

V_PVIN, V_AVIN

Topr

2.7

-40

0

-

5.5

+85

V

°C

A

Operating Temperature Range

Output Current

I_OUT

3

Output Voltage Range

V_RANGE

0.6

V_PVIN× 0.8

V

Electrical Characteristics (Unless otherwise specified Ta = 25°C, V_PVIN= V_AVIN= 5V, V_EN= 5V, V_MODE= GND)

Parameter

Input Supply

Symbol

Min

Typ

Max

Unit

Conditions

Standby Supply Current

Operating Supply Current

I_STB

I_CC

V_UVLO1

V_UVLO2

-

0

10

75

µA V_EN= GND

I_OUT= 0mA

µA

50

Non switching

UVLO Detection Threshold Voltage

UVLO Release Threshold Voltage

UVLO Hysteresis

2.350

2.425

50

2.450

2.550

100

2.550

2.700

200

V

V_AVINfalling

V_AVINrising

V_UVLOHYS

mV

Enable

EN Input High Level Voltage

EN Input Low Level Voltage

EN Input Current

V_ENH

V_ENL

I_EN

1.5

GND

-

V_AVIN

0.5

6

V

3

µA V_EN= 5V

Reference Voltage, Error Amplifier

FB Terminal Voltage

V_FB

I_FB

t_SS

I_SS

0.591

-

0.600

-

0.609

1

V

FB Input Current

µA V_FB= 0.6V

ms SS terminal is open.

µA

Internal Soft Start Time

Soft Start Terminal Current

Control

0.5

1.0

1.2

2.0

1.8

MODE Input High Level Voltage

MODE Input Low Level Voltage

V_MODEH

V_MODEL

V_AVIN- 0.3

GND

-

V_AVIN

0.3

V

V_OUT= 1.2V,

V_MODE= V_AVIN

On Time

t_ONT

140

185

230

ns

Power Good

Power Good Rising Threshold

Power Good Falling Threshold

PGD Output Leakage Current

Power Good On Resistance

Power Good Low Level Voltage

SW

V_PGDH

V_PGDL

I_LKPGD

R_PGD

85

80

-

90

85

0

95

90

1

%

V_FBrising

V_FBfalling

µA V_PGD= 5V

-

100

0.1

200

0.2

Ω

V_PGDVL

-

V

I_PGD= 1mA

High Side FET On Resistance

Low Side FET On Resistance

High Side Output Leakage Current

Low Side Output Leakage Current

R_ONH

R_ONL

I_LH

-

23

0

50

10

mΩ V_BOOT- V_SW= 5V

mΩ

µA No switching

I_LL

0

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Typical Performance Curves

75

60

45

30

15

0

10

9

V_PVIN= V_AVIN= 5V

8

7

6

5

V_PVIN= V_AVIN= 3.3V

4

V_PVIN= V_AVIN= 5V

V_PVIN= V_AVIN= 3.3V

3

2

1

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 4. Standby Supply Current vs Temperature

Figure 5. Operating Supply Current vs Temperature

2.70

2.65

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

V_PVIN= V_AVIN= 5V

2.60

Release

2.55

2.50

2.45

V_PVIN= V_AVIN= 3.3V

Detection

2.40

2.35

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 6. UVLO Threshold Voltage vs Temperature

Figure 7. EN High Threshold Voltage vs Temperature

(V_ENSweep Up)

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Typical Performance Curves - continued

6

5

4

3

2

1

0

1.5

1.4

V_PVIN= V_AVIN= 5V

1.3

V_PVIN= V_AVIN= 5V

1.2

1.1

1.0

0.9

0.8

V_PVIN= V_AVIN= 3.3V

0.7

0.6

0.5

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 8. EN Low Threshold Voltage vs Temperature

(V_ENSweep Down)

Figure 9. EN Input Current vs Temperature

(V_EN= 5V)

0.610

1.0

0.8

0.6

0.4

0.2

0.0

V_PVIN= V_AVIN= 5V

0.608

0.606

0.604

0.602

0.600

0.598

0.596

0.594

0.592

0.590

V_PVIN= V_AVIN= 5V

V_PVIN= V_AVIN= 3.3V

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 10. FB Terminal Voltage vs Temperature

Figure 11. FB Input Current vs Temperature

(V_FB= 0.6V)

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Typical Performance Curves - continued

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

2.0

1.5

V_PVIN= V_AVIN= 3.3V

1.0

V_PVIN= V_AVIN= 5V

0.5

0.0

V_PVIN= V_AVIN= 3.3V

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 13. Soft Start Terminal Current vs Temperature

Figure 12. Internal Soft Start Time vs Temperature

(C_SS= OPEN)

3.5

V_PVIN= V_AVIN= 5V

VIN=5V

3.0

2.5

2.0

1.5

1.0

0.5

3.0

2.5

2.0

1.5

1.0

0.5

V_PVIN= V_AVIN= 3.3V

VIN=3.3V

V_PVIN= V_AVIN= 5V

V_PVIN= V_AVIN= 3.3V

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 14. MODE High Threshold Voltage vs Temperature

Figure 15. MODE Low Threshold Voltage vs Temperature

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Typical Performance Curves - continued

1.0

230

215

200

185

170

155

140

V_PVIN= V_AVIN= 5V

0.8

0.6

0.4

0.2

0.0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 16. MODE Input Current vs Temperature

(V_MODE= 5V)

Figure 17. On Time vs Temperature

(V_PVIN= V_AVIN= 5V, V_OUT= 1.2V, V_MODE= V_AVIN

)

1.0

0.8

0.6

0.4

0.2

0.0

100

V_PVIN= V_AVIN= 5V

V_PGD= 5V

V_PVIN= V_AVIN= 5V

95

90

85

80

V_FBrising

V_FBfalling

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 18. Power Good Threshold vs Temperature

Figure 19. PGD Output Leakage Current vs Temperature

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Typical Performance Curves - continued

200

180

160

140

0.20

0.18

0.16

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00

V_PVIN= V_AVIN= 5V

I_PGD= 1mA

V_PVIN= V_AVIN= 3.3V

120

100

80

V_PVIN= V_AVIN= 5V

60

40

20

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 20. Power Good On Resistance vs Temperature

Figure 21. Power Good Low Level Voltage vs Temperature

50

45

40

35

30

50

45

40

35

30

V_PVIN= V_AVIN= 3.3V

25

V_PVIN= V_AVIN= 3.3V

25

20

15

V_PVIN= V_AVIN= 5V

10

V_PVIN= V_AVIN= 5V

10

5

0

5

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

Temperature [°C]

Figure 22. High Side FET On Resistance vs Temperature

Figure 23. Low Side FET On Resistance vs Temperature

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Typical Performance Curves - continued

V_EN3V/div

V_OUT0.5V/div

V_SW3V/div

V_OUT0.5V/div

V_SW3V/div

V_PGD3V/div

Time 500μs/div

Figure 24. Start-up Waveform (V_EN= 0V to 3.3V)

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V, V_MODE= 0V, R_LOAD= 1Ω, C_SS= OPEN)

Figure 25. Shutdown Waveform (V_EN= 3.3V to 0V)

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V, V_MODE= 0V, R_LOAD= 1Ω, C_SS= OPEN)

V_AVIN3V/div

V_OUT0.5V/div

V_SW3V/div

V_OUT0.5V/div

V_SW3V/div

V_PGD3V/div

Time 500μs/div

Figure 26. Start-up Waveform (V_PVIN= V_AVIN= V_EN

)

Figure 27. Shutdown Waveform (V_PVIN= V_AVIN= V_EN)

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V, V_MODE= 0V, R_LOAD= 1Ω, C_SS= OPEN)

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Typical Performance Curves - continued

V_OUT20mV/div

V_SW2V/div

Time 1μs/div

Figure 28. Switching Waveform

Figure 29. Switching Waveform

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V, V_MODE= 0V, I_OUT= 0.1A)

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V, V_MODE= 3.3V, I_OUT= 0.1A)

V_OUT20mV/div

V_SW2V/div

Time 1μs/div

Figure 30. Switching Waveform

Figure 31. Switching Waveform

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V, V_MODE= 0V, I_OUT= 3A)

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V, V_MODE= 3.3V, I_OUT= 3A)

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Typical Performance Curves - continued

1600

1700

1600

1500

1400

1300

1200

1100

1000

900

V_MODE= V_AVIN

1400

1200

V_MODE= 0V

1000

800

600

400

200

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Output Current [A]

Input Voltage [V]

Figure 32. Switching Frequency vs Output Current

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V)

Figure 33. Switching Frequency vs Input Voltage

(V_OUT= 0.9V, V_MODE= 0V, I_OUT= 1A)

2.0

1.5

2.0

1.5

1.0

0.5

V_MODE= V_AVIN

0.0

V_MODE= 0V

-0.5

-1.0

-1.5

-2.0

-0.5

-1.0

-1.5

-2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Output Current [A]

Input Voltage [V]

Figure 34. Load Regulation

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V)

Figure 35. Line Regulation

(V_OUT= 0.9V, V_MODE= 0V, I_OUT= 1A)

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Typical Performance Curves - continued

V_OUT100mV/div

I_OUT1A/div

Time 1ms/div

Figure 36. Load Transient Response I_OUT= 0.1A - 2A

(V_PVIN=V_AVIN=3.3V, V_OUT=0.9V, V_MODE=0V, C_OUT=22µF)

Figure 37. Load Transient Response I_OUT= 0.1A - 2A

(V_PVIN=V_AVIN=3.3V, V_OUT=0.9V, V_MODE=V_AVIN, C_OUT=22µF)

100

V_MODE= 0V

90

80

70

60

50

40

V_MODE= V_AVIN

30

20

10

0

0.001

0.01

0.1

1

10

Output Current [A]

Figure 38. Efficiency vs Output Current

(V_PVIN=V_AVIN=3.3V, V_OUT=0.9V, L=1.0µH)

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Function Explanations

1. Basic Operation

(1) DC/DC Converter Operation

BD9B333GWZ is a synchronous rectifying step-down switching regulator that achieves faster load transient response

by employing constant on-time control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode

for heavier load, while it utilizes Deep-SLLM (Simple Light Load Mode) control for lighter load to improve efficiency.

① Deep-SLLM Control

② PWM Control

Output Current [A]

Figure 39. Efficiency (Deep-SLLM Control and PWM Control)

② PWM Control Waveform

① Deep-SLLM Control Waveform

V_OUT20mV/div

V_SW2.0V/div

Time 1μs/div

Figure 40. Switching Waveform at Deep-SLLM Control

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V, I_OUT= 0.1A)

Figure 41. Switching Waveform at PWM Control

(V_PVIN= V_AVIN= 3.3V, V_OUT= 0.9V, I_OUT= 3A)

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(2) Enable Control

The shutdown can be controlled by the voltage applied to the EN terminal. When V_ENreaches 1.5V (Min), the internal

circuit is activated and the device starts up. To enable shutdown control with the EN terminal, the shutdown interval

(Low level interval of EN) must be set to 100µs or more. Startup by EN must be at the same time or after the input of

power supply voltage.

V_EN

V_ENH

V_ENL

0

t

V_OUT

0

t

Start-up

Shutdown

Figure 42. Start-up and Shutdown with Enable

(3) Soft Start

When EN terminal is turned High, Soft Start operates and output voltage gradually rises. With the Soft Start Function,

over shoot of output voltage and rush current can be prevented. Rising time of output voltage is 1ms (Typ) when SS

terminal is open. A capacitor connected to SS terminal makes rising time more than 1ms. Please refer to Page 32 for

the method of setting rising time.

EN

V_OUT

0.6V x 90%

0.6V

FB

1ms (Typ) ^(Note)

(Note) SS terminal is open.

Figure 43. Soft Start Timing Chart

(4) Power Good

When the output voltage reaches to 90% (Typ) or more of the voltage setting, the open drain Nch MOSFET, internally

connected to the PGD terminal, turns off and the PGD terminal turns to Hi-Z condition. When the output voltage falls

to 85% (Typ) or less of the voltage setting, the open drain Nch MOSFET turns on and PGD terminal pulls down with

100Ω (Typ). Connecting a pull up resistor (10kΩ to 100kΩ) is recommended.

EN

Voltage Setting x 90% (Typ)

Voltage Setting x 85% (Typ)

V_OUT

PGD

Figure 44. Power Good Timing Chart

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2. Protection

The protective circuits are intended for prevention of damage caused by unexpected accidents. Do not use them

for continuous protective operation.

(1) Over Current Protection (OCP) / Short Circuit Protection (SCP)

Setting value of Low Side OCP is 5.1A (Typ). Setting value of High Side OCP is 7.1A (Typ). When OCP is triggered,

over current protection is realized by restricting On / Off Duty of current flowing in upper and lower MOSFET by each

switching cycle. Also, if Over current protection operates 512 cycles in a condition where FB terminal voltage reaches

below 85% of internal reference voltage (PGD = L), Short Circuit protection (SCP) operates and stops switching for

3ms (Typ) before it initiates restart. However, during startup, Short circuit protection will not operate even if the IC is

still in the SCP condition. Do not to exceed the maximum junction temperature rating during OCP and SCP operation.

Table 1. Over Current Protection / Short Circuit Protection Function

Over Current

Protection

Short Circuit

Protection

EN terminal

PGD

Startup

During start-up

Completed start-up

*

Valid

Invalid

Valid

L

More than 1.5V

Less than 0.5V

H

L

Valid

Invalid

Shutdown

Invalid

3ms(Typ)

V_OUT

V_FB

High Side

MOSFET Gate

Low Side

MOSFET Gate

High Side OCP

Low Side OCP

Inductor Current

High Side OCP Signal

Low Side OCP Signal

512 Cycle

PGD

Figure 45. Short Circuit Protection (SCP) Timing Chart

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(2) Under Voltage Lockout Protection (UVLO)

The Under Voltage Lockout Protection circuit monitors the AVIN terminal voltage. The operation enters standby when

the AVIN terminal voltage is 2.45V (Typ) or less. The operation starts when the AVIN terminal voltage is 2.55V (Typ)

or more.

UVLO Release

V_AVIN

Hysteresis

UVLO Detection

0V

V_OUT

Soft Start

V_FB

High Side

MOSFET Gate

Low Side

MOSFET Gate

Normal operation

UVLO

Normal operation

Figure 46. UVLO Timing Chart

(3) Thermal Shutdown (TSD)

When the chip temperature exceeds Tj=175°C (Typ), the DC/DC converter output is stopped. Thermal protection

circuit resets and the output voltage returns to the normal operation level when the temperature falls. The circuit has

a hysteresis of 25°C (Typ). The thermal shutdown circuit is intended for shutting down the IC from thermal runaway in

an abnormal state with the temperature exceeding Tjmax=150°C. It is not meant to protect or guarantee the reliability

of the application. Do not use this function of the circuit for application protection design.

(4) Over Voltage Protection (OVP)

The over voltage protection (OVP) compares the FB terminal voltage with the internal reference voltage. When the

FB terminal voltage exceeds 0.72V (Typ), it turns the output MOSFETs off. The output voltage returns to normal

operation level with hysteresis after the output voltage drops.

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Application Example (V_OUT= 0.9V)

Parameter

Input Voltage

Symbol

V_IN

Value

5V

Output Voltage

V_OUT

f_SW

0.9V

Switching Frequency

Maximum Output Current

Operating Temperature Range

1.3MHz (Typ)

3A

I_OUTMAX

Topr

-40°C to +85°C

C₇

R₃

EN

V_IN

C₁

C₂

PVIN

AVIN

EN

R₄

BOOT

PGD

MODE

SS

PGD

C₆

BD9B333GWZ

V_OUT

SW

FB

L₁

MODE

SS

JP1

C₉

C₃

R₁

R₂

C₅

AGND

PGND

C₈

Figure 47. Application Circuit

Table 2. Recommended Component Values

Part No.

Value

Company

Part Name

Size (mm)

L₁

(Note 1)

1.0μH

22μF

-

Murata

DFE252012F-1R0M

2520

2012

-

C₁

C₂

C₃

Murata

GRM21BR61A226ME44

(Note 2)

(Note 3)

-

22μF

100pF

0.1μF

-

Murata

GRM188R60G226MEA0

1608

1005

C₅

(Note 4)

Murata

GRM15 series

C₆

C₇

Murata

GRM155R61A104MA01

(Note 5)

-

C₈

C₉

R₁

-

100kΩ

200kΩ

Short

100kΩ

Short

ROHM

-

MCR01MZPD1003

1005

-

R₂

(Note 5)

MCR01MZPD2003

R₃

-

R₄

ROHM

-

MCR01MZPD1003

-

1005

-

JP1 ^{(Note 6)}

(Note 1) For the capacitance of input capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set to a minimum

value of no less than 8μF.

(Note 2) In order to reduce the influence of high frequency noise, connect a 0.1μF ceramic capacitor as close as possible to the PVIN pin and the

PGND pin if needed.

(Note 3) In case capacitance value fluctuates due to temperature characteristics, DC bias characteristics, etc. of the output capacitor, loop response

characteristics may change. Please confirm on the actual equipment. When selecting a capacitor, confirm the characteristics of the capacitor

in its datasheet. A ceramic capacitor of 22μF to 47μF is recommended for the output capacitor.

(Note 4) For the capacitance of bootstrap capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set minimum

value to no less than 0.047μF.

(Note 5) AVIN is connected to PVIN by using R₃resistor pattern. By adding R₃=100Ω and C₇=1000pF between the PVIN pin and the AVIN pin as the

low pass filter, Load Regulation and Line Regulation can be improved. Please add the low pass filter after confirming on actual equipment if

needed.

(Note 6) JP1 is an option, used for feedback’s frequency response measurement. By inserting a resistor at JP1, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, please use this resistor pattern in

short-circuit mode.

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100

90

80

70

60

50

40

30

20

10

80

60

180

135

90

V_MODE= 0V

Phase

40

20

45

0

V_MODE= V_IN

Gain

-20

-40

-60

-80

-45

-90

-135

-180

Phase Margin

56.2deg

0

0.001

0.01

0.1

1

10

1

10

100

Frequency[kHz]

1000

10000

Output Current : IOUT [A]

Figure 49. Closed Loop Response I_OUT= 1A

Figure 48. Efficiency vs Output Current

(V_IN= 5V, V_OUT= 0.9V, L = 1.0μH, C_OUT= 22μF)

(V_IN= 5V, V_OUT= 0.9V, L = 1.0μH)

V_OUT= 100mV/div

V_OUT= 20mV/div

V_SW= 2V/div

I_OUT= 1A/div

Time = 2μs/div

Time = 500μs/div

Figure 50. Load Transient Response

Figure 51. V_OUTRipple I_OUT= 3A

I_OUT= 0.1A – 2.0A

(V_IN= 5V, V_OUT= 0.9V, L = 1.0μH, C_OUT= 22μF)

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Application Example (V_OUT= 1.0V)

Parameter

Input Voltage

Symbol

V_IN

Value

5V

Output Voltage

V_OUT

f_SW

1.0V

Switching Frequency

Maximum Output Current

Operating Temperature Range

1.3MHz (Typ)

3A

I_OUTMAX

Topr

-40°C to +85°C

C₇

R₃

EN

V_IN

C₁

C₂

PVIN

AVIN

EN

R₄

BOOT

PGD

MODE

SS

PGD

C₆

BD9B333GWZ

V_OUT

SW

FB

L₁

MODE

SS

JP1

C₉

C₃

R₁

R₂

C₅

AGND

PGND

C₈

Figure 52. Application Circuit

Table 3. Recommended Component Values

Part No.

Value

Company

Part Name

Size (mm)

L₁

(Note 1)

1.0μH

22μF

-

Murata

DFE252012F-1R0M

2520

2012

-

C₁

C₂

C₃

Murata

GRM21BR61A226ME44

(Note 2)

(Note 3)

-

22μF

100pF

0.1μF

-

Murata

GRM188R60G226MEA0

1608

1005

C₅

(Note 4)

Murata

GRM15 series

C₆

C₇

Murata

GRM155R61A104MA01

(Note 5)

-

C₈

C₉

R₁

-

100kΩ

150kΩ

Short

100kΩ

Short

ROHM

-

MCR01MZPD1003

1005

-

R₂

(Note 5)

MCR01MZPD1503

R₃

-

R₄

ROHM

-

MCR01MZPD1003

-

1005

-

JP1 ^{(Note 6)}

(Note 1) For the capacitance of input capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set to a minimum

value of no less than 8μF.

(Note 2) In order to reduce the influence of high frequency noise, connect a 0.1μF ceramic capacitor as close as possible to the PVIN pin and the

PGND pin if needed.

(Note 3) In case capacitance value fluctuates due to temperature characteristics, DC bias characteristics, etc. of the output capacitor, loop response

characteristics may change. Please confirm on the actual equipment. When selecting a capacitor, confirm the characteristics of the capacitor

in its datasheet. A ceramic capacitor of 22μF to 47μF is recommended for the output capacitor.

(Note 4) For the capacitance of bootstrap capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set minimum

value to no less than 0.047μF.

(Note 5) AVIN is connected to PVIN by using R₃resistor pattern. By adding R₃=100Ω and C₇=1000pF between the PVIN pin and the AVIN pin as the

low pass filter, Load Regulation and Line Regulation can be improved. Please add the low pass filter after confirming on actual equipment if

needed.

(Note 6) JP1 is an option, used for feedback’s frequency response measurement. By inserting a resistor at JP1, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, please use this resistor pattern in

short-circuit mode.

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100

90

80

70

60

50

40

30

20

10

80

60

180

135

90

V_MODE= 0V

Phase

40

20

45

0

V_MODE= V_IN

Gain

-20

-40

-60

-80

-45

-90

-135

-180

Phase Margin

56.1deg

0

0.001

0.01

0.1

1

10

1

10

100

Frequency[kHz]

1000

10000

Output Current : IOUT [A]

Figure 54. Closed Loop Response I_OUT= 1A

Figure 53. Efficiency vs Output Current

(V_IN= 5V, V_OUT= 1.0V, L = 1.0μH, C_OUT= 22μF)

(V_IN= 5V, V_OUT= 1.0V, L = 1.0μH)

V_OUT= 100mV/div

V_OUT= 20mV/div

V_SW= 2V/div

I_OUT= 1A/div

Time = 2μs/div

Time = 500μs/div

Figure 55. Load Transient Response

Figure 56. V_OUTRipple I_OUT= 3A

I_OUT= 0.1A – 2.0A

(V_IN= 5V, V_OUT= 1.0V, L = 1.0μH, C_OUT= 22μF)

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Application Example (V_OUT= 1.2V)

Parameter

Input Voltage

Symbol

V_IN

Value

5V

Output Voltage

V_OUT

f_SW

1.2V

Switching Frequency

Maximum Output Current

Operating Temperature Range

1.3MHz (Typ)

3A

I_OUTMAX

Topr

-40°C to +85°C

C₇

R₃

EN

V_IN

C₁

C₂

PVIN

AVIN

EN

R₄

BOOT

PGD

MODE

SS

PGD

C₆

BD9B333GWZ

V_OUT

SW

FB

L₁

MODE

SS

JP1

C₉

C₃

R₁

R₂

C₅

AGND

PGND

C₈

Figure 57. Application Circuit

Table 4. Recommended Component Values

Part No.

Value

Company

Part Name

Size (mm)

L₁

(Note 1)

1.0μH

22μF

-

Murata

DFE252012F-1R0M

2520

2012

-

C₁

C₂

C₃

Murata

GRM21BR61A226ME44

(Note 2)

(Note 3)

-

22μF

100pF

0.1μF

-

Murata

GRM188R60G226MEA0

1608

1005

C₅

(Note 4)

Murata

GRM15 series

C₆

C₇

Murata

GRM155R61A104MA01

(Note 5)

-

C₈

C₉

R₁

-

150kΩ

Short

100kΩ

Short

ROHM

-

MCR01MZPD1503

1005

-

R₂

(Note 5)

MCR01MZPD1503

R₃

-

R₄

ROHM

-

MCR01MZPD1003

-

1005

-

JP1 ^{(Note 6)}

(Note 1) For the capacitance of input capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set to a minimum

value of no less than 8μF.

(Note 2) In order to reduce the influence of high frequency noise, connect a 0.1μF ceramic capacitor as close as possible to the PVIN pin and the

PGND pin if needed.

(Note 3) In case capacitance value fluctuates due to temperature characteristics, DC bias characteristics, etc. of the output capacitor, loop response

characteristics may change. Please confirm on the actual equipment. When selecting a capacitor, confirm the characteristics of the capacitor

in its datasheet. A ceramic capacitor of 22μF to 47μF is recommended for the output capacitor.

(Note 4) For the capacitance of bootstrap capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set minimum

value to no less than 0.047μF.

(Note 5) AVIN is connected to PVIN by using R₃resistor pattern. By adding R₃=100Ω and C₇=1000pF between the PVIN pin and the AVIN pin as the

low pass filter, Load Regulation and Line Regulation can be improved. Please add the low pass filter after confirming on actual equipment if

needed.

(Note 6) JP1 is an option, used for feedback’s frequency response measurement. By inserting a resistor at JP1, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, please use this resistor pattern in

short-circuit mode.

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100

90

80

70

60

50

40

30

20

10

80

60

180

135

90

V_MODE= 0V

Phase

40

20

45

0

V_MODE= V_IN

Gain

-20

-40

-60

-80

-45

-90

-135

-180

Phase Margin

57.1deg

0

0.001

0.01

0.1

1

10

1

10

100

Frequency[kHz]

1000

10000

Output Current : IOUT [A]

Figure 59. Closed Loop Response I_OUT= 1A

Figure 58. Efficiency vs Output Current

(V_IN= 5V, V_OUT= 1.2V, L = 1.0μH, C_OUT= 22μF)

(V_IN= 5V, V_OUT= 1.2V, L = 1.0μH)

V_OUT= 100mV/div

V_OUT= 20mV/div

V_SW= 2V/div

I_OUT= 1A/div

Time = 2μs/div

Time = 500μs/div

Figure 60. Load Transient Response

Figure 61. V_OUTRipple I_OUT= 3A

I_OUT= 0.1A – 2.0A

(V_IN= 5V, V_OUT= 1.2V, L = 1.0μH, C_OUT= 22μF)

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Application Example (V_OUT= 1.8V)

Parameter

Input Voltage

Symbol

V_IN

Value

5V

Output Voltage

V_OUT

f_SW

1.8V

Switching Frequency

Maximum Output Current

Operating Temperature Range

1.3MHz (Typ)

3A

I_OUTMAX

Topr

-40°C to +85°C

C₇

R₃

EN

V_IN

C₁

C₂

PVIN

AVIN

EN

R₄

BOOT

PGD

MODE

SS

PGD

C₆

BD9B333GWZ

V_OUT

SW

FB

L₁

MODE

SS

JP1

C₉

C₃

R₁

R₂

C₅

AGND

PGND

C₈

Figure 62. Application Circuit

Table 5. Recommended Component Values

Part No.

Value

Company

Part Name

Size (mm)

L₁

(Note 1)

1.0μH

22μF

-

Murata

DFE252012F-1R0M

2520

2012

-

C₁

C₂

C₃

Murata

GRM21BR61A226ME44

(Note 2)

(Note 3)

-

22μF

120pF

0.1μF

-

Murata

GRM188R60G226MEA0

1608

1005

C₅

(Note 4)

Murata

GRM15 series

C₆

C₇

Murata

GRM155R61A104MA01

(Note 5)

-

C₈

C₉

R₁

-

200kΩ

100kΩ

Short

100kΩ

Short

ROHM

-

MCR01MZPD2003

1005

-

R₂

(Note 5)

MCR01MZPD1003

R₃

-

R₄

ROHM

-

MCR01MZPD1003

-

1005

-

JP1 ^{(Note 6)}

(Note 1) For the capacitance of input capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set to a minimum

value of no less than 8μF.

(Note 2) In order to reduce the influence of high frequency noise, connect a 0.1μF ceramic capacitor as close as possible to the PVIN pin and the

PGND pin if needed.

(Note 3) In case capacitance value fluctuates due to temperature characteristics, DC bias characteristics, etc. of the output capacitor, loop response

characteristics may change. Please confirm on the actual equipment. When selecting a capacitor, confirm the characteristics of the capacitor

in its datasheet. A ceramic capacitor of 22μF to 47μF is recommended for the output capacitor.

(Note 4) For the capacitance of bootstrap capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set minimum

value to no less than 0.047μF.

(Note 5) AVIN is connected to PVIN by using R₃resistor pattern. By adding R₃=100Ω and C₇=1000pF between the PVIN pin and the AVIN pin as the

low pass filter, Load Regulation and Line Regulation can be improved. Please add the low pass filter after confirming on actual equipment if

needed.

(Note 6) JP1 is an option, used for feedback’s frequency response measurement. By inserting a resistor at JP1, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, please use this resistor pattern in

short-circuit mode.

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100

90

80

70

60

50

40

30

20

10

80

60

180

135

90

Phase

V_MODE= 0V

40

20

45

0

V_MODE= V_IN

Gain

-20

-40

-60

-80

-45

-90

-135

-180

Phase Margin

48.4deg

0

0.001

0.01

0.1

1

10

1

10

100

Frequency[kHz]

1000

10000

Output Current : IOUT [A]

Figure 64. Closed Loop Response I_OUT= 1A

Figure 63. Efficiency vs Output Current

(V_IN= 5V, V_OUT= 1.8V, L = 1.0μH, C_OUT= 22μF)

(V_IN= 5V, V_OUT= 1.8V, L = 1.0μH)

V_OUT= 100mV/div

V_OUT= 20mV/div

V_SW= 2V/div

I_OUT= 1A/div

Time = 2μs/div

Time = 500μs/div

Figure 65. Load Transient Response

Figure 66. V_OUTRipple I_OUT= 3A

I_OUT= 0.1A – 2.0A

(V_IN= 5V, V_OUT= 1.8V, L = 1.0μH, C_OUT= 22μF)

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Application Example (V_OUT= 3.3V)

Parameter

Input Voltage

Symbol

V_IN

Value

5V

Output Voltage

V_OUT

f_SW

3.3V

Switching Frequency

Maximum Output Current

Operating Temperature Range

1.3MHz (Typ)

3A

I_OUTMAX

Topr

-40°C to +85°C

C₇

R₃

EN

V_IN

C₁

C₂

PVIN

AVIN

EN

R₄

BOOT

PGD

MODE

SS

PGD

C₆

BD9B333GWZ

V_OUT

SW

FB

L₁

MODE

SS

JP1

C₉

C₃

R₁

R₂

C₅

AGND

PGND

C₈

Figure 67. Application Circuit

Table 6. Recommended Component Values

Part No.

Value

Company

Part Name

Size (mm)

L₁

(Note 1)

1.5μH

22μF

-

Murata

DFE322512F-1R5M

3225

2012

-

C₁

C₂

C₃

Murata

GRM21BR61A226ME44

(Note 2)

(Note 3)

-

22μF

120pF

0.1μF

-

Murata

GRM188R61A226ME15

1608

1005

C₅

(Note 4)

Murata

GRM15 series

C₆

C₇

Murata

GRM155R61A104MA01

(Note 5)

-

C₈

C₉

R₁

-

150kΩ

33kΩ

Short

100kΩ

Short

ROHM

-

MCR01MZPD1503

1005

-

R₂

(Note 5)

MCR01MZPD3302

R₃

-

R₄

ROHM

-

MCR01MZPD1003

-

1005

-

JP1 ^{(Note 6)}

(Note 1) For the capacitance of input capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set to a minimum

value of no less than 8μF.

(Note 2) In order to reduce the influence of high frequency noise, connect a 0.1μF ceramic capacitor as close as possible to the PVIN pin and the

PGND pin if needed.

(Note 3) In case capacitance value fluctuates due to temperature characteristics, DC bias characteristics, etc. of the output capacitor, loop response

characteristics may change. Please confirm on the actual equipment. When selecting a capacitor, confirm the characteristics of the capacitor

in its datasheet. A ceramic capacitor of 22μF to 47μF is recommended for the output capacitor.

(Note 4) For the capacitance of bootstrap capacitor, take temperature characteristics, DC bias characteristics, etc. into consideration to set minimum

value to no less than 0.047μF.

(Note 5) AVIN is connected to PVIN by using R₃resistor pattern. By adding R₃=100Ω and C₇=1000pF between the PVIN pin and the AVIN pin as the

low pass filter, Load Regulation and Line Regulation can be improved. Please add the low pass filter after confirming on actual equipment if

needed.

(Note 6) JP1 is an option, used for feedback’s frequency response measurement. By inserting a resistor at JP1, it is possible to measure the frequency

response (phase margin) using a FRA. However, the resistor will not be used in actual application, please use this resistor pattern in

short-circuit mode.

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100

90

80

70

60

50

40

30

20

10

80

60

180

135

90

Phase

V_MODE= 0V

40

20

45

0

V_MODE= V_IN

Gain

-20

-40

-60

-80

-45

-90

-135

-180

Phase Margin

45.8deg

0

0.001

0.01

0.1

1

10

1

10

100

Frequency[kHz]

1000

10000

Output Current : IOUT [A]

Figure 69. Closed Loop Response I_OUT= 1A

Figure 68. Efficiency vs Output Current

(V_IN= 5V, V_OUT= 3.3V, L = 1.5μH, C_OUT= 22μF)

(V_IN= 5V, V_OUT= 3.3V, L = 1.5μH)

V_OUT= 100mV/div

V_OUT= 20mV/div

V_SW= 2V/div

I_OUT= 1A/div

Time = 2μs/div

Time = 500μs/div

Figure 70. Load Transient Response

Figure 71. V_OUTRipple I_OUT= 3A

I_OUT= 0.1A – 2.0A

(V_IN= 5V, V_OUT= 3.3V, L = 1.5μH, C_OUT= 22μF)

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Selection of Components Externally Connected

About the application except the recommendation, please contact us.

1. Output LC Filter

In order to supply a continuous current to the load, the DC/DC converter requires an LC filter for smoothing the output

voltage. Use inductors of value from 0.47µH to 1.5µH.

PVIN

I_L

Inductor saturation current > I_OUTMAX+ ΔI_L/2

V_OUT

L

I_OUT

ΔI_L

Driver

Average inductor current

C_OUT

t

Figure 72. Waveform of current through inductor

Figure 73. Output LC filter circuit

Inductor ripple current ΔI_L

1

ΔI_L=V_OUT×(V_IN-V_OUT)×

=702



mA



V_IN× f_SW× L

Where:

V_IN= 5V

V_OUT= 1.2V

L = 1.0µH

fsw = 1.3MHz

The saturation current of the inductor must be larger than the sum of the maximum output current and 1/2 of the inductor

ripple current ∆I_L.

The output capacitor C_OUTaffects the output ripple voltage characteristics. The output capacitor C_OUTmust satisfy the

required ripple voltage characteristics.

The output ripple voltage can be represented by the following equation.

1

ΔV_RPL= ΔI_L× (R_ESR

+

)

V

 

8 × C_OUT× f_SW

Where:

R_ESRis the Equivalent Series Resistance (ESR) of the output capacitor.

* The capacitor rating must allow a sufficient margin with respect to the output voltage.

The output ripple voltage is decreased with a smaller R_ESR

.

Considering temperature and DC bias characteristics, please use ceramic capacitor of about 22µF to 47µF.

* Be careful of total capacitance value, when additional capacitor C_LOADis connected in addition to output capacitor C_OUT

Use maximum additional capacitor C_LOAD(Max) which satisfies the following condition.

.

Maximumstarting inductor bottom ripplecurrent I_LSTART< Low sideOCP 3.3 [A](Min)

Maximum starting inductor ripple current I_LSTARTcan be expressed using the following equation.

ΔI_L

I_LSTART= Maximum starting output current(I_OSS)+Chargecurrent to output capacitor(I_CAP)-

2

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Charge current to output capacitor I_CAPcan be expressed using the following equation.

(C_OUT+C _LOAD) ×V_OUT

t _SS

I_CAP

=

A

 

For example, given V_IN= 5V, V_OUT= 1.2V, L = 1.0µH, switching frequency f_SW= 0.98MHz (Min), Output capacitor C_OUT

=

22µF, Soft Start time t_SS= 0.5ms (Min), and load current during soft start I_OSS= 3A, maximum C_LOADcan be computed

using the following equation.

(3.3- I_OSSΔI_L/2)× t_SS

C_LOAD(max)<

-C_OUT 296.9



μF



V_OUT

* C_LOADhas an effect on the stability of the DC/DC converter.

To ensure the stability of the DC/DC converter, make sure that a sufficient phase margin is provided.

If the value of C_LOADis large, and cannot meet the above equation, adjust the value of the capacitor C_SSto meet the

condition below.

(3.3- I_OSSΔI_L/2)×V

C_LOAD(max)<

^FB×C_SS-C_OUT

V_OUT× I_SS

(Refer to the following items “3.Soft Start Setting” about the equation of soft start time t_SSand the capacitor C_SS.)

For example, given V_IN= 5V, V_OUT= 1.2V, L = 1.0µH, load current during soft start I_OSS= 3A, switching frequency fsw =

1.62MHz (Max), Output capacitor C_OUT= 22µF, V_FB= 0.609V (Max), I_SS= 1.8µA (Max), with C_LOAD= 470µF, capacitor C_SS

is computed as follows.

V_OUT× I_SS

(3.3- I_OSSΔI_L/2)×V_FB

C_SS>

×(C_LOAD+C_OUT) = 3001



pF



2. Output Voltage Setting

The output voltage value can be set by the feedback resistance ratio.

For stable operation, use feedback resistance R₁more than 20kΩ.

V_OUT

R₁

R +R

1

²×0.6

V

 

Error Amplifier

VOUT

=

R

2

FB

R₂

0.6V

0.6

V



VOUT (VPVIN 0.8)

V

Figure 74. Feedback Resistor Circuit

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3. Soft Start Setting

Turning the EN terminal signal High activates the soft start function. This makes output voltage to rise gradually while

controlling current at start-up. This prevents output voltage overshoot and inrush current. The rise time depends on the

value of the capacitor connected to the SS terminal. Please use less than 0.01µF capacitor value.

tSS =(CSS ×VFB)/ISS

Where:

t_SSis the Soft Start Time

C_SSis the Capacitor connected to SS terminal

V_FBis the FB Terminal Voltage (0.6V (Typ))

I_SSis the Soft Start Terminal Current (1.2µA (Typ))

With C_SS= 5600pF,

t

SS=(5600



pF



×0.6



V



)/1.2



μA



= 2.8

msec



Rising time of output voltage is 1ms (Typ) by turning the EN terminal signal High with the SS terminal open (no capacitor

connected).

4. FB Capacitor

Generally, in fixed ON time control, sufficient ripple voltage in FB voltage is needed to operate main comparator stably.

Regarding this IC, by injecting ripple voltage to FB voltage inside IC, it is designed to correspond to low ESR output

capacitor. Please set the FB capacitor (C_FB) within the range of the following expression to inject an appropriate ripple.

V_OUT

V_IN

V_OUT

V_IN

V_OUT×(1-

)

V_OUT×(1-

)

< C_FB<

F

 

f_SW×9.0 × 10³

f_SW× 3.3 × 10³

Where:

V_INis the Input Voltage [V]

V_OUTis the Output Voltage [V]

f_SWis the Switching Frequency [Hz]

5. Bootstrap Capacitor

Connect a 0.1µF ceramic capacitor between SW terminal and BOOT terminal. For the capacitance of bootstrap capacitor,

take temperature characteristics, DC bias characteristics, etc. into consideration to set minimum value to no less than

0.047μF.

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PCB Layout Design

PCB layout design for DC/DC converter power supply IC is as important as the circuit design. Appropriate layout can avoid

various problems caused by power supply circuit. Figure 75-a to 75-c show the current path in a buck converter circuit. The

Loop1 in Figure 75-a is a current path when H-side switch is ON and L-side switch is OFF, the Loop2 in Figure 75-b is when

H-side switch is OFF and L-side switch is ON. The thick line in Figure 75-c shows the difference between Loop1 and Loop2.

The current in thick line changes sharply each time the switching element H-side and L-side switch change from OFF to ON,

and vice versa. These sharp changes induce several harmonics in the waveform. Therefore, the loop area of thick line that

is consisted by input capacitor and IC should be as small as possible to minimize noise. For more detail, refer to application

note of switching regulator series “PCB Layout Techniques of Buck Converter”.

Loop1

V_IN

V_OUT

L

H-side switch

C_IN

C_OUT

L-side switch

GND

Figure 75-a. Current path when H-side switch = ON, L-side switch = OFF

V_IN

V_OUT

L

H-side switch

C_IN

C_OUT

Loop2

L-side switch

GND

V_IN

GND

Figure 75-b. Current path when H-side switch = OFF, L-side switch = ON

V_OUT

L

H-side FET

C_IN

C_OUT

L-side FET

GND

Figure 75-c. Difference of current and critical area in layout

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PCB Layout Design - continued

When designing the PCB layout, please pay extra attention to the following points:

- Place input capacitor on the same PCB surface as the IC and as close as possible to the IC’s PVIN terminal.

- Switching nodes should be traced as thick and short as possible to the inductor, because they may induce the noise

to the other nodes due to AC coupling.

- Please keep the lines connected to FB away from the SW node as far as possible.

- Please place output capacitor away from input capacitor to avoid harmonics noise from the input.

- Please connect AGND to PGND that are close to the output capacitor. It can avoid harmonic noise.

PGD

Pull Up

Resistors

Enable

Control

Feedback

Resistors

AVIN Low

Pass Filter

(Option)

D1

AVIN

C1

EN

B1

PGD

A1

FB

Capacitor

Bootstrap

Capacitor

D2

BOOT

B2

MODE

A2

AGND

C2

SS

AGND

D3

B3

A3

C3

PVIN

SW

PGND

SW

A4

D4

C4

B4

PGND

PVIN

SW

V_IN

PGND

SW

Input Bypass Capacitor

(Option)

Input Bulk Capacitor

(22μF)

Output

Capacitor

V_OUT

Output

Inductor

Signal VIA

Bottom Layer Line

Figure 76. Example of PCB Layout (TOP VIEW)

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I/O Equivalence Circuits

A1. FB

B1. PGD

AVIN

PGD

10kΩ

FB

B2. MODE

B3, B4, C3, C4. SW

PVIN BOOT

100kΩ

MODE

1000kΩ

SW

C1. EN

C2. SS

AVIN

EN

405kΩ

10kΩ

SS

935kΩ

265kΩ

D2. BOOT

PVIN

BOOT

SW

Figure 77. I/O Equivalence Circuits

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Operational Notes

1.

2.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3.

4.

Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

However, pins that drive inductive loads (e.g. motor driver outputs, DC-DC converter outputs) may inevitably go

below ground due to back EMF or electromotive force. In such cases, the user should make sure that such voltages

going below ground will not cause the IC and the system to malfunction by examining carefully all relevant factors

and conditions such as motor characteristics, supply voltage, operating frequency and PCB wiring to name a few.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

6.

Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may

flow instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring,

and routing of connections.

7.

8.

Operation Under Strong Electromagnetic Field

Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

9.

Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment)

and unintentional solder bridge deposited in between pins during assembly to name a few.

10. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

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Operational Notes – continued

11. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should

be avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 78. Example of monolithic IC structure

12. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

13. Area of Safe Operation (ASO)

Operate the IC such that the output voltage, output current, and the maximum junction temperature rating are all

within the Area of Safe Operation (ASO).

14. Thermal Shutdown Circuit(TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls

below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

15. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

16. Disturbance Light

In a device where a portion of silicon is exposed to light such as in a WL-CSP and chip products, IC characteristics

may be affected due to photoelectric effect. For this reason, it is recommended to come up with countermeasures

that will prevent the chip from being exposed to light.

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Ordering Information

B D 9 B 3 3 3 G W Z -

E 2

Part Number

Package

UCSP35L1

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagram

UCSP35L1 (TOP VIEW)

Pin 1 Mark

Part Number Marking

LOT Number

B 3 3 3

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Physical Dimension and Packing Information

Package Name (Product Name)

UCSP35L1 (BD9B333GWZ)

< Tape and Reel Information >

Tape

Embossed carrier tape

Quantity

3000pcs

E2

Direction of feed

The direction is the pin 1 of product is at the upper left when you

hold reel on the left hand and you pull out the tape on the right hand

引

1234

き

Direction of feed

Pin 1

Reel

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Revision History

Date

Revision

001

Changes

16.Jun.2017

New Release

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of

flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning

residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.003

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.003


型号：	BD9B333GWZ
厂家：	ROHM
描述：	BD9B333GWZ是内置低导通电阻的功率MOSFET的同步整流降压型DC/DC转换器。最大可输出3A的电流。采用轻负载时进行低功耗工作的独创恒定时间控制方式，适用于要降低待机功耗的设备。振荡频率高，适用于小型电感。是恒定时间控制DC/DC转换器，具有高速负载响应性能。BD9B333GWZ 采用小型CSP封装，可在大功率密度下减少贴装面积。转换器
文件：	总43页 (文件大小：4301K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD9B333GWZ [ROHM]

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