BD3507HFV_08 [ROHM]
Ultra Low Dropout Linear Regulators for PC Chipsets; 超低压差线性稳压器的PC芯片组
| 型号： | BD3507HFV_08 |
| 厂家： | 
ROHM |
| 描述： | Ultra Low Dropout Linear Regulators for PC Chipsets |
| 文件： | 总16页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Ultra Low Dropout
Linear Regulators for PC Chipsets
BD3507HFV
●Description
The BD3507HFV is suited for power supply for chipset bus. Though small in size, BD3507HFV adopts power PKG with
radiation fins, and it therefore can be used for a regulator up to 550mA. Because it adopts Nch MOSFET and can form a
ultra low dropout power supply of RON=300mΩ (TYP), BD3507HFV can compose a high-efficiency system, though it is of a
linear type power supply. The output voltage can be set by VREF terminal and can be synchronized with other power
supply. In addition, it can be used as a high side switch (RON = 300mΩ/lo = 550mA) of low-voltage power supply line.
Because ceramic capacitors can be used for output capacitors, BD3507HFV contributes to downsizing and reduced
thickness not only of IC but also of sets.
●Features
1) Built-in high-accuracy buffer circuit (can be set to 0.65-2.7V)
2) Adoption of ceramic capacitors
3) Built-in enable function (0μA at standby)
4) Built-in current limiting circuit (550mA Max)
5) Built-in undervoltage lockout circuit (UVLO)
6) Built-in thermal shutdown circuit (TSD)
7)
Adoption of ultra-small-size high-power HVSOF6 package (3.0 x 1.6 x 0.75 mm)
●Applications
Notebook PC, desktop PC, digital camera, digital home appliances
Oct. 2008
●ABSOLUTE MAXIMUM RATINGS (Ta=25℃)
Parameter Symbol
Input Voltage1
Limit
6.0 *1 *2
6.0 *1 *2
Unit
V
VCC
VIN
Input Voltage2
V
Enable Input Voltage
Power Dissipation1
VEN
6.0 *1 *2
V
Pd1
Pd2
Topr
Tstg
Tjmax
512.5 *3
850.0 *4
-10～+100
-55～+150
+150
mW
mW
℃
Power Dissipation2
Operating Temperature Range
Storage Temperature Range
℃
Maximum Junction Temperature
℃
*1 However, not exceeding Pd.
*2 Maximum rating that can stand instantaneous voltage application such as surge, back EMF, or continuous pulse application whose duty ratio lowers 10%.
*3 In the case of Ta≥25°C (when mounting to 70mmx70mmx1.6mm glass epoxy substrate), derated at 4.1 mW/°C.
*4 In the case of Ta≥25°C (when mounting to 70mmx70mmx1.6mm glass epoxy substrate (copper foil area: 100 mm2)), derated at 6.8 mW/°C.
●OPERATING CONDITIONS (Ta=25℃)
Parameter
Input Voltage1
Symbol
VCC
VIN
MIN
4.5
1.2
0.65
-0.3
0
MAX
5.5
Unit
V
Input Voltage2
Vcc-1
2.7
V
VREF Setup Voltage
EN Input Voltage
Output Current
VREF
VEN
IO
V
5.5
V
550
mA
★ No radiation-resistant design is adopted for the present product.
●ELECTRICAL CHARACTERISTICS (unless otherwise noted, Ta=25℃, VCC=5V, VIN=1.8V, VREF=1.2V, VEN=3V)
Standard Value
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
Bias Current
ICC
ISTB
-
0.4
0
0.7
10
mA
μA
μA
V
Standby Current1
Standby Current2
Output Voltage1
Output Voltage2
-
VEN=0V
VEN=0V
Io=0mA
Io=300mA
IINSTB
VO1
VO2
-
0
10
1.188
1.188
1.200
1.200
1.212
1.212
V
Io=0mA to 550mA
Vcc=4.5V to 5.5V
Ta=-10℃ to 100℃
Output Voltage3
VO3
1.176
1.200
1.224
V
*5
Output Voltage4
Output Voltage5
Vo4
Vo5
2.475
2.475
2.500
2.500
2.525
2.525
V
V
VIN=3.3V,VREF=2.5V Io=0mA
VIN=3.3V,VREF=2.5V
Io=300mA
VIN=3.3V,VREF=2.5V
Io=0mA to 550mA
Vcc=4.5V to 5.5V
Output Voltage6
Vo6
2.450
2.500
2.550
V
*5
Ta=-10℃ to 100℃
Over Current Protect
ICL
RON
600
-
-
-
550
-
mA
mΩ
V
Output ON Resistance
300
High Level Enable Input Voltage
Low Level Enable Input Voltage
Enable Pin Input Current
ENHigh
ENLOW
IEN
2.0
-0.2
-
-
-
EN:Sweep-up
EN:Sweep-down
VEN=3V
0.8
10
V
7
μA
UVLO OFF Voltage
VUVLO
VHYS
3.5
3.8
4.1
V
Vcc:Sweep-up
UVLO Hysteresis Voltage
100
160
220
mV
Vcc:Sweep-down
*5
VREF Pin Bias Current
IVREF
RONREF
RONDIS
-0.1
-
0.1
2.0
0.3
μA
kΩ
kΩ
VREF=0→2.7 V
VREF Discharge ON Resistance
Output Discharge ON Resistance
*5 Design Guarantee
-
-
1.0
0.1
2/15
●Reference Data
1.75
1.70
1.65
1.60
1.55
1.50
1.45
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
280
240
200
160
120
80
40
0
-55
-15
25
65
105
145
-10
10
30
50
70
90
-10
10
30
50
70
90
Ta(
)
℃
Ta(
)
℃
Ta(℃)
Fig.2 Ta-ISTB
(Vcc)
Fig.3 Ta-IIN
(VIN)
Fig.1 Ta-Icc
(Vcc)
35
32
29
26
23
20
240
200
160
120
80
Vo=1.2V
1.208
1.203
1.198
1.193
1.188
40
0
-55
-15
25
65
Ta(℃)
105
145
-10
10
30
50
70
90
-10
10
30
50
Ta(℃)
70
90
Ta(
℃
)
Fig.4 Ta-IINSTB
(VIN)
Fig.6 Ta-IODIS
Fig.5 Ta-Vo
2.180
2.175
2.170
2.165
2.160
2.155
2.150
8
7
6
5
4
3
2
1
0
500
450
400
350
300
250
200
VREF=1.2V
2.5V
1.8V
1.2V
4
4.5
5
5.5
6
-60
-20
20
60
Ta(℃)
100
140
-10
10
30
50
70
90
VCC[V]
Ta(℃)
Fig.7 Ta-IrefDIS
Fig.9 Vcc-Ron
Fig.8 Ta-IEN
400
350
300
250
200
150
100
50
EN
EN
VREF
VO
VREF
VO
0
-10
10
30
50
70
90
Ta(℃)
Fig.11 Startup Wave Form
Fig.12 Shutdown Wave Form
Fig.10 Ta-Ron
3/15
VCC
EN
VCC
VCC
EN
EN
VREF
VREF
VREF
VO
VO
VO
Fig.15 Input Sequence 3
Fig.14 Input Sequence 2
Fig.13 Input Sequence 1
VCC
VCC
EN
VCC
EN
EN
VREF
VREF
VO
VREF
VO
VO
Fig.18 Input Sequence 6
Fig.17 Input Sequence 5
Fig.16 Input Sequence 4
VO
VO
IO
IO
Fig.20 Transient Response
Fig.19 Transient Response
(550→0mA/μs)
(0→550mA/μs)
4/15
●BLOCK DIAGRAM
VCC
VCC
VIN
VIN
UVLO
UVLO
Current
Limit
CL
VREF
VREF
+
-
EN
UVLO
VO
VO
TSD
UVLO
EN
Ceramic Capacitor
EN
EN
EN
Enable
EN
EN
UVLO
GND
TSD
TSD
●PIN FUNCTION
Pin No.
PIN NAME
PIN FUNCTION
1
2
3
4
5
6
VCC
EN
VCC Pin
Enable Input Pin
Input Voltage Pin
Output Pin
VIN
Vo
VREF
GND
Reference Voltage Input Pin
Ground Pin
●PIN CONFIGRATION
VCC
EN
1
2
3
6
GND
VREF
VO
5
4
VIN
5/15
・AMP
An error amplifier that compares reference voltage (VREF) to Vo and drives Nch FET (Ron=300 mꢀ) of output. The
frequency characteristics are optimized so that ceramic capacitors can be used for output capacitors and high-speed
transient response can be achieved. The input voltage range at the AMP section is GND-2.7V and the output voltage
range of the AMP section is GND-VCC. At the time of EN OFF or UVLO, the output is brought to the LOW level and the
output NchFET is turned OFF.
・EN
By the logic input pin, regulator ON/OFF is controlled. At the time of OFF, the circuit current is controlled to be 0µA to
reduce the standby current consumption of the apparatus. In addition, EN turns ON FET that can discharge VREF and Vo
and removes excess electric charge to prevent maloperation of IC on the load side. Since there is no electrical connection
with the Vcc terminal as is the case of Di for electrostatic measures, it does not depend on the input sequence.
・UVLO
UVLO turned OFF output to prevent output voltage from making maloperation at the time of Vcc reduced voltage. Same
as EN, UVLO discharges VREF and Vo. When voltage exceeds the threshold voltage (TYP 3.8V), UVLO starts output.
・CURRENT LIMIT
In the event the output current that exceeds the current (0.6A or more) set inside the IC flows when output is turned ON,
output voltage is attenuated to protect the IC on the load side. When current reduces, output voltage returns to the set
voltage.
・SOFT START
Adding external resistor and capacitor to VREF pin can achieve soft-start. By the time constant that is determined by the
time constant of CR, VREF pin becomes dull, and output rises in synchronism with VREF pin. Overshoot of output voltage
or inrush current can be prevented.
・VREF
VREF is a reference voltage input pin and sets output voltage. Since there is no electrical connection with the Vcc terminal
as is the case of Di for electrostatic measures, it does not depend on the input sequence.
・TSD(Thermal Shut down)
In order to prevent thermal breakdown and thermal runaway of the IC, the output is turned OFF when chip temperature
becomes high. In addition, when temperature returns to the specified temperature, the output is recovered. However,
since the temperature protection circuit is originally built in to protect the IC itself, thermal design within Tj(max) is
requested.
・VIN
This is a large-current supply line. The VIN terminal is connected to the rain of output NchFET. Since there is no
electrical connection with the Vcc terminal as is the case of Di for electrostatic measures, it does not depend on the input
sequence. However, because there is body Di of output NchFET between VIN and Vo, there is electrical connection
(Di-connection) between VIN and Vo. Consequently, when the output is turned ON/OFF by VIN, reverse current flows
from Vo to VIN, to which care must be taken.
6/15
●TIMING CHART
EN ON/OFF
VIN
VCC
EN
Vref
Vo
t
VCC ON/OFF
VIN
hysterisis
VCC
EN
Vref
Vo
t
Vref Synchronous Action
VIN
VCC
EN
Vref
Vo
t
7/15
●Application setting method
Vcc
VR
C4
GND
VREF
Vcc
EN
C1
R1
R2
VREF
ON/OFF
VIN
C2
VIN
VO
Vo
Ceramic Capacitor
C3
Part No
R1/R2
Value
22k/11k
Notes for Use
The present IC can set output voltage by external reference voltage (VR) and value of output
voltage setting resistors (R1, R2). Output voltage can be set by VRxR2/(R1+R2) but it is
recommended to use at the resistance value (total: about 10 kꢀ) which is not susceptible to
VREF bias current (±100nA).
C3
22μF
Connect the output capacitor between Vo terminal and GND terminal without fail in order to
stabilize output voltage. The output capacitor has a role to compensate for the phase of loop
gain and to reduce output voltage fluctuation when load is rapidly changed. When there is an
insufficient capacity value, there is a possibility to cause oscillation, and when the equivalent
serial resistance (ESR) of the capacitors is large, output voltage fluctuation is increased when
load is rapidly changed. About 22µF ceramic capacitors are recommended but output
capacitor greatly depends on temperature and load conditions. In addition, when various
capacitors are connected in series, the total phase allowance of loop gain becomes not
sufficient, and oscillation may result. Thoroughgoing confirmation at application temperature
and under load range conditions is requested.
C1
0.1μF
The input capacitor plays a part to lower output impedance of a power supply connected to
input terminals (Vcc). When output impedance of this power supply increases, the input
voltages (Vcc, VIN) become unstable and there is a possibility of giving rise to oscillation and
degraded ripple rejection characteristics. The use of capacitors of about 10μF with low ESR,
which provide less capacity value changes caused by temperature changes, is recommended,
but since input capacitor greatly depends on characteristics of the power supply used for input,
substrate wiring pattern, thoroughgoing confirmation under the application temperature and
load range, is requested.
C2
10μF
The input capacitor plays a part to lower output impedance of a power supply connected to
input terminals (VIN). When output impedance of this power supply increases, the input
voltages (Vcc, VIN) become unstable and there is a possibility of giving rise to oscillation and
degraded ripple rejection characteristics. The use of capacitors of about 10μF with low ESR,
which provide less capacity value changes caused by temperature changes, is recommended,
but since input capacitor greatly depends on characteristics of the power supply used for input,
substrate wiring pattern, thoroughgoing confirmation under the application temperature and
load range, is requested.
C4
1μF
The present IC can set the output voltage buildup time by VREF terminal capacitor (C4) and R1
and R2 values. When EN terminal is “High” or UVLO is reset, output voltage is built up by the
time constant determined by C4, R1, and R2. It is recommended to use capacitors (B
special) with little capacity value change caused by temperature change for C4.
8/15
●Directions for pattern layout of PCB
■ BD3507HFV Evaluation Board Circuit
U1
GND
BD3507HFV
VCC
6
1
2
VCC
GND
VREF
Vo
C1
VCC
EN
VREF
VR
R5_1
SW
5
EN
C5
R5_2
VIN
Vo
3
4
VIN
C4_1
C3
C4_2
■ BD3507HFV Evaluation Board Application Components
Part No
U1
Value
Company
ROHM
Parts Name
BD3507HFV
Part No
C1
Value
1μF
Company
ROHM
Parts Name
-
MCH184CN105K
MCH218CN106K
MCH318CN226K
R5_1
R5_2
22k
11k
ROHM
MCR03EZPF2202
MCR03EZPF1102
C3
10μF
22μF
ROHM
ROHM
C4_1
C4_2
C5
ROHM
1μF
ROHM
MCH184CN105K
■ BD3507HFV Evaluation Board Layout
TOP Layer
Silk Screen
Mid Layer 1
Bottom Layer
Mid Layer 2
9/15
●About heat loss
In designing heat, operate the apparatus within the following conditions.
(Because the following temperatures are warranted temperature, be sure to take margin, etc. into account.)
1. Ambient temperature Ta shall be not more than 100°C.
2. Chip junction temperature Tj shall be not more than 150°C.
Chip junction temperature Tj can be considered under the following two cases.
①Chip junction temperature Tj is found
from IC surface temperature TC under
actual application conditions:
Tj=TC+θj-c×W
②Chip junction temperature Tj is found from ambient temperature Ta:
Tj=Ta+θj-a×W
＜Reference value＞
θj-c:HVSOF6 30℃/W
＜Reference value＞
θj-a:HVSOF6 243.9℃/W
Single-layer substrate
(substrate surface copper foil area: less 3%)
Single-layer substrate
147.1℃/W
(substrate surface copper foil area:100mm2)
Single-layer substrate
89.3℃/W
(substrate surface copper foil area:900mm2)
Single-layer substrate
(substrate surface copper foil area:2500mm2)
Substrate size 70×70×1.6mm3
73.5℃/W
When multilayer substrates are used, if any GND pattern is present in the inner layer, arrange heat radiation vias on the
package rear side. Because the present package size is as small as 1.0 x 1.6 mm and vias are unable to be arranged in a
large quantity at the lower part of IC, the pattern is expanded as illustrated below and the number of vias is increased to
obtain superb heat radiation characteristics (the figure below is an image figure only, and the size and the quantity of vias
that match the condition must be designed into patterns).
Most of heat loss in BD3507HFV occurs at the output N-channel FET. The power lost is determined by multiplying the
voltage between VIN and Vo by the output current. Confirm the VIN and Vo voltages used and output current conditions,
and check with the thermal derating characteristics. As this IC employs the power PKG, the thermal derating characteristics
significantly depends on the pc board conditions. When designing, care must be taken to the size of a pc board to be used.
Power dissipation (W) = {Input voltage (VIN) – Output voltage (V0≒VREF)}×Io (averaged)
Ex.) If VIN = 1.8 volts, V0=1.2 volts, and Io (averaged)=0.5 A, the power dissipation is given by the following:
Power dissipation (W) =(1.8 volts – 1.2 volts) × 0.5 (A)
= 0.3 W
10/15
●Example of applied circuit
Specifications: High side switch of low-voltage power supply line (1.2-2.5V)
Characteristics: RON = 300 mꢀ, lo max) = 550 mA, with soft start function and overheat protection circuit equipped.
Example Circuit
VCC
VCC
R1
GND
VCC
C1
VREF
VREF
EN
VIN
ON/OFF
C4
VIN
C2
VO
Vo
C3
Ceramic Capacitor
●EQUIVALENT CIRCUIT
2pin (EN)
1pin (VCC
)
Vcc
VIN
3pin (VIN)
4pin (Vo)
5pin (VREF
)
11/15
●NOTE FOR USE
1.Absolute maximum ratings
For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working
temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. Because it
is unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute maximum
rating, physical safety measures are requested to be taken, such as fuses, etc.
2.GND potential
Bring the GND terminal potential to the minimum potential in any operating condition.
3. Thermal design
Consider permissible dissipation (Pd) under actual working condition and carry out thermal design with sufficient margin
provided.
4.Terminal-to-terminal short-circuit and erroneous mounting
When the present IC is mounted to a printed circuit board, take utmost care to direction of IC and displacement. In the
event that the IC is mounted erroneously, IC may be destroyed. In the event of short-circuit caused by foreign matter that
enters in a clearance between outputs or output and power-GND, the IC may be destroyed.
5.Operation in strong electromagnetic field
The use of the present IC in the strong electromagnetic field may result in maloperation, to which care must be taken.
6. Built-in thermal shutdown protection circuit
The present IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175°C
(standard value) and has a -15°C (standard value) hysteresis width. When the IC chip temperature rises and the TSD
circuit operates, the output terminal is brought to the OFF state. The built-in thermal shutdown protection circuit (TSD
circuit) is first and foremost intended for interrupt IC from thermal runaway, and is not intended to protect and warrant the IC.
Consequently, never attempt to continuously use the IC after this circuit is activated or to use the circuit with the activation of
the circuit premised.
7. Capacitor across output and GND
In the event a large capacitor is connected across output and GND, when Vcc and VIN are short-circuited with 0V or GND
for some kind of reasons, current charged in the capacitor flows into the output and may destroy the IC. Use a capacitor
smaller than 1000 μF between output and GND.
8.Inspection by set substrate
In the event a capacitor is connected to a pin with low impedance at the time of inspection with a set substrate, there is a
fear of applying stress to the IC. Therefore, be sure to discharge electricity for every process. As electrostatic measures,
provide grounding in the assembly process, and take utmost care in transportation and storage. Furthermore, when the
set substrate is connected to a jig in the inspection process, be sure to turn OFF power supply to connect the jig and be sure
to turn OFF power supply to remove the jig.
9. IC terminal input
The present IC is a monolithic IC and has a P substrate and P+ isolation between elements.
With this P layer and N layer of each element, PN junction is formed, and when the potential relation is
GND>terminal A>terminal B, PN junction works as a diode, and
Terminal B>GND terminal A, PN junction operates as a parasitic transistor.
The parasitic element is inevitably formed because of the IC construction. The operation of the parasitic element gives rise
to mutual interference between circuits and results in malfunction, and eventually, breakdown. Consequently, take utmost
care not to use the IC to operate the parasitic element such as applying voltage lower than GND (P substrate) to the input
terminal.
Resistor
Transistor (NPN)
B
Pin A
Pin B
Pin B
C
E
Pin A
B
C
E
N
N
N
P+
P+
P+
P+
N
P
P
Parasitic
element
N
N
Parasitic
element
P substrate
P substrate
GND
GND
GND
GND
Parasitic element
Parasitic element
Other adjacent elements
12/15
10.GND wiring pattern
If there are a small signal GND and a high current GND, it is recommended to separate the patterns for the high current
GND and the small signal GND and provide a proper grounding to the reference point of the set not to affect the voltage at
the small signal GND with the change in voltage due to resistance component of pattern wiring and high current. Also for
GND wiring pattern of component externally connected, pay special attention not to cause undesirable change to it.
11. Input terminals(Vcc,VIN,EN,VREF)
In the present IC, EN terminal, VIN terminal, VCC terminal, and VREF terminal have an independent construction. In
addition, in order to prevent malfunction at the time of low input, the UVLO function is equipped with the VCC terminal.
They begin to start output voltage when all the terminals reach threshold voltage without depending on the input order of
input terminals.
12. Heat sink
Heatsink is connected to SUB, which should be short-circuited to GND. Solder the heatsink to a pc board properly, which
offers lower thermal resistance.
13. Operating range
Within the operating range, the operation and function of the circuits are generally guaranteed at an ambient temperature
within the range specified. The values specified for electrical characteristics may not be guaranteed, but drastic change
may not occur to such characteristics within the operating range.
14. For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working
temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. Because it
is unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute
maximum rating, physical safety measures are requested to be taken, such as fuses, etc.
15. In the event that load containing a large inductance component is connected to the output terminal, and generation of
back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode.
(Example)
OUTPUT PIN
HVSOF6 land patarn
MIE
E3
L2
Unit:mm
Land Pitch
Land Space
MIE
Land Length
Land Width
b2
e
l2
0.50
2.20
0.55
0.25
Pad Length
D3
Pad Width
E3
1.60
1.60
In actually designing, optimize in accordance with the condition.
13/15
●POWER DISSIPATION
HVSOF 6
3
PCB size : 70mm×70mm×1.6mm
①:PCB 1st layer (Cu-area : 100mm2)
θja = 147.1℃/W
2.5
2
②:PCB 1st layer (Cu-area : 900mm2)
θja = 89.3℃/W
③:PCB 1st layer (Cu-area : 2500mm2)
θja = 73.5℃/W
③1.70W
②1.40W
1.5
1
①0.85W
0.5
0
0
25
50
75
100
125
150
Ambient Temperature:Ta
14/15
●Ordering part number
―
F
D
3
5
0
7
H
V
B
T
R
TR : Embossed carrier tape
Part Number
Package Type
・BD3507
・HFV : HVSOF6
HVSOF6
<Dimension>
<Tape and Reel information>
Tape
Embossed carrier tape
(MAX 1.8 include BURR)
1.6 0.1
Quantity
3000pcs
TR
6
5
4
Direction
of feed
(The direction is the 1pin of product is at the upper light when you hold
reel on the left hand and you pull out the tape on the right hand)
(1.2)
(1.4)
1
2
3
0.145 0.05
S
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0.1 S
0.22 0.05
0.5
1Pin
Direction of feed
Reel
(Unit:mm)
※When you order , please order in times the amount of package quantity.
Catalog No.08T435A '08.10 ROHM ©
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no respon-
sibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or
exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no
responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended
to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact your nearest sales office.
THE AMERICAS / EUROPE / ASIA / JAPAN
ROHM Customer Support System
Contact us : webmaster@ rohm.co.jp
www.rohm.com
TEL : +81-75-311-2121
FAX : +81-75-315-0172
Copyright © 2008 ROHM CO.,LTD.
21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan
Appendix1-Rev3.0
相关型号：
BD3508EKN-E2
Adjustable Positive LDO Regulator, 0.65V Min, 2.7V Max, 4.20 X 4.20 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, HQFN-20
ROHM
©2020 ICPDF网 联系我们和版权申明