RN80532KC056512 [ROCHESTER]
32-BIT, 2400MHz, MICROPROCESSOR, CPGA603, INTERPOSER, MICRO, PGA-603;
| 型号： | RN80532KC056512 |
| 厂家： | 
Rochester Electronics |
| 描述： | 32-BIT, 2400MHz, MICROPROCESSOR, CPGA603, INTERPOSER, MICRO, PGA-603 时钟 外围集成电路 |
| 文件： | 总130页 (文件大小：2324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® Xeon™ Processor with 512-KB L2 Cache
at 1.80GHz to 3 GHz
Datasheet
Product Features
• Available at 1.80, 2, 2.20, 2.40, 2.60, 2.80, and
3 GHz
• 512 KB Advanced Transfer L2 Cache (on-die,
full speed Level 2 cache) with 8-way
associativity and Error Correcting Code (ECC)
• Dual processing server/workstation support
• Enables system support of up to 64 GB of
• Binary compatible with applications running on
previous members of Intel’s IA32
microprocessor line
physical memory
• Streaming SIMD Extensions 2 (SSE2)
• Intel® NetBurst™ micro-architecture
• Hyper-Threading Technology
— 144 new instructions for double-precision
floating point operations, media/video
streaming, and secure transactions
— Hardware support for multithreaded
applications
• Enhanced floating point and multimedia unit for
enhanced video, audio, encryption, and 3D
performance
• Power Management capabilities
— System Management mode
— Multiple low-power states
• 400 MHz Front Side Bus
— Bandwidth up to 3.2 GB/second
• Rapid Execution Engine: Arithmetic Logic
Units (ALUs) run at twice the processor core
frequency
• Hyper Pipelined Technology
• Advance Dynamic Execution
— Very deep out-of-order execution
— Enhanced branch prediction
• Advanced System Management Features
— System Management Bus
— Processor Information ROM (PIROM)
— OEM Scratch EEPROM
— Thermal Monitor
• Level 1 Execution Trace Cache stores 12 K
micro-ops and removes decoder latency from
main execution loops
— Machine Check Architecture (MCA)
— Includes 8 KB Level 1 data cache
The Intel® Xeon™ processor with 512 KB L2 cache is designed for high-performance dual-
processor workstation and server applications. Based on the Intel® NetBurst™ micro-
architecture and the new Hyper-Threading Technology, it is binary compatible with previous
Intel Architecture (IA-32) processors. The Intel Xeon processor with 512 KB L2 cache is
scalable to two processors in a multiprocessor system providing exceptional performance for
applications running on advanced operating systems such as Windows XP*, Windows* 2000,
Linux*, and UNIX*. The Intel Xeon processor with 512 KB L2 cache delivers compute power at
unparalleled value and flexibility for powerful workstations, internet infrastructure, and
departmental server applications. The Intel® NetBurst™ micro-architecture and Hyper-
Threading Technology deliver outstanding performance and headroom for peak internet server
workloads, resulting in faster response times, support for more users, and improved scalability.
Order Number: 298642-006
March 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL
ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO
SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel® Xeon™ processor may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained
by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademark or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries.
Copyright © Intel Corporation, 2002-2003
Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................11
1.1
1.2
1.3
Terminology......................................................................................................................12
State of Data.....................................................................................................................13
References .......................................................................................................................14
2.0 Electrical Specifications.................................................................................................................15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Front Side Bus and GTLREF............................................................................................15
Power and Ground Pins ...................................................................................................15
Decoupling Guidelines......................................................................................................15
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking .............................................16
PLL Filter ..........................................................................................................................17
Voltage Identification .......................................................................................................20
Reserved Or Unused Pins................................................................................................22
Front Side Bus Signal Groups..........................................................................................22
Asynchronous GTL+ Signals............................................................................................24
Maximum Ratings.............................................................................................................24
Processor DC Specifications ............................................................................................25
AGTL+ Front Side Bus Specifications ..............................................................................31
Front Side Bus AC Specifications.....................................................................................32
Processor AC Timing Waveforms.....................................................................................36
2.9
2.10
2.11
2.12
2.13
2.14
3.0 Front Side Bus Signal Quality Specifications ................................................................................45
3.1
Front Side Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines.
..........................................................................................................................................45
Front Side Bus Signal Quality Specifications and Measurement Guidelines....................46
Front Side Bus Signal Quality Specifications and Measurement Guidelines....................50
3.2
3.3
4.0 Mechanical Specifications .............................................................................................................57
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Mechanical Specifications ................................................................................................58
Processor Package Load Specifications ..........................................................................62
Insertion Specifications.....................................................................................................63
Mass Specifications..........................................................................................................63
Materials...........................................................................................................................63
Markings...........................................................................................................................64
Pin-Out Diagram...............................................................................................................65
5.0 Pin Listing and Signal Definitions ..................................................................................................67
5.1
5.2
Processor Pin Assignments..............................................................................................67
Signal Definitions .............................................................................................................84
6.0 Thermal Specifications ..................................................................................................................95
6.1
6.2
Thermal Specifications .....................................................................................................96
Measurements for Thermal Specifications .......................................................................98
7.0 Features ........................................................................................................................................99
7.1
7.2
7.3
7.4
Power-On Configuration Options......................................................................................99
Clock Control and Low Power States ...............................................................................99
Thermal Monitor .............................................................................................................102
System Management Bus (SMBus) Interface.................................................................103
8.0 Boxed Processor Specifications..................................................................................................115
8.1
8.2
8.3
Introduction.....................................................................................................................115
Mechanical Specifications ..............................................................................................116
1U Rack Mount Server Solution .....................................................................................125
Datasheet
3
Contents
8.4
Thermal Specifications ...................................................................................................127
9.0 Debug Tools Specifications.........................................................................................................128
9.1
Logic Analyzer Interface (LAI) ........................................................................................128
4
Datasheet
Contents
Figures
1
2
3
4
5
6
7
8
Typical VCCIOPLL, VCCA and VSSA Power Distribution ........................................................18
Phase Lock Loop (PLL) Filter Requirements ............................................................................19
Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID =1.5V)........................27
Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID = 1.525V)...................28
Electrical Test Circuit.................................................................................................................37
TCK Clock Waveform................................................................................................................37
Differential Clock Waveform......................................................................................................38
Differential Clock Crosspoint Specification................................................................................38
Front Side Bus Common Clock Valid Delay Timing Waveform.................................................39
Front Side Bus Source Synchronous 2X (Address) Timing Waveform.....................................39
Front Side Bus Source Synchronous 4X (Data) Timing Waveform...........................................40
Front Side Bus Reset and Configuration Timing Waveform......................................................41
Power-On Reset and Configuration Timing Waveform .............................................................41
TAP Valid Delay Timing Waveform...........................................................................................42
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform.........................42
THERMTRIP# to VCC Timing...................................................................................................42
SMBus Timing Waveform..........................................................................................................43
SMBus Valid Delay Timing Waveform ......................................................................................43
Example 3.3 VDC/SM_VCC Sequencing..................................................................................44
BCLK[1:0] Signal Integrity Waveform........................................................................................46
Low-to-High Front Side Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+
Buffers ......................................................................................................................................47
High-to-Low Front Side Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+
Buffers ......................................................................................................................................48
Low-to-High Front Side Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers........48
High-to-Low Front Side Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers.49
Maximum Acceptable Overshoot/Undershoot Waveform .........................................................55
INT-mPGA Processor Package Assembly Drawing (Includes Socket).....................................57
INT-mPGA Processor Package Top View: Component Placement Detail................................58
INT-mPGA Processor Package Drawing ..................................................................................59
INT-mPGA Processor Package Top View: Component Height Keep-in ...................................60
INT-mPGA Processor Package Cross Section View: Pin Side Component Keep-in................60
INT-mPGA Processor Package: Pin Detail ...............................................................................61
IHS Flatness and Tilt Drawing...................................................................................................62
Processor Top-Side Markings...................................................................................................64
Processor Bottom-Side Markings..............................................................................................64
Processor Pin Out Diagram: Top View......................................................................................65
Processor Pin Out Diagram: Bottom View ................................................................................66
Processor with Thermal and Mechanical Components - Exploded View..................................95
Processor Thermal Design Power vs Electrical Projections for VID = 1.500V..........................96
Processor Thermal Design Power vs Electrical Projections for VID = 1.525V..........................97
Thermal Measurement Point for Processor TCASE..................................................................98
Stop Clock State Machine.......................................................................................................100
Logical Schematic of SMBus Circuitry ....................................................................................104
Mechanical Representation of the Boxed Processor Passive Heatsink for 3 GHz processors
................................................................................................................................................115
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Datasheet
5
Contents
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sors
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Mechanical Representation of the Boxed Processor Passive Heatsink for 2 - 2.80 GHz proces-
................................................................................................................................................116
Retention Mechanism .............................................................................................................118
Boxed Processor Clip.............................................................................................................119
Multiple View Space Requirements for the Boxed Processor.................................................120
Fan Connector Electrical Pin Sequence .................................................................................121
Processor Wind Tunnel General Dimensions .........................................................................123
Processor Wind Tunnel Detailed Dimensions.........................................................................124
Exploded View of the 1U Thermal Solution.............................................................................125
Assembled View of the 1U Thermal Solution..........................................................................126
6
Datasheet
Contents
Tables
1
2
3
4
5
6
7
8
Front Side Bus-to-Core Frequency Ratio ......................................................................................17
Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]..............................................17
Voltage Identification Definition .....................................................................................................21
Front Side Bus Signal Groups.......................................................................................................23
Processor Absolute Maximum Ratings..........................................................................................24
Voltage and Current Specifications ...............................................................................................26
Front Side Bus Differential BCLK Specifications...........................................................................28
AGTL+ Signal Group DC Specifications........................................................................................29
TAP and PWRGOOD Signal Group DC Specifications.................................................................29
Asynchronous GTL+ Signal Group DC Specifications ..................................................................30
SMBus Signal Group DC Specifications........................................................................................30
BSEL[1:0] and VID[4:0] DC Specifications....................................................................................31
AGTL+ Bus Voltage Definitions.....................................................................................................31
Front Side Bus Differential Clock Specifications ...........................................................................32
Front Side Bus Common Clock AC Specifications........................................................................33
Front Side Bus Source Synchronous AC Specifications ...............................................................33
Miscellaneous Signals+ AC Specifications....................................................................................34
Front Side Bus AC Specifications (Reset Conditions)...................................................................35
TAP Signal Group AC Specifications ............................................................................................35
SMBus Signal Group AC Specifications........................................................................................35
BCLK Signal Quality Specifications...............................................................................................45
Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers .........................................46
Ringback Specifications for TAP Buffers.......................................................................................47
Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance...........53
Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance...........53
Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance....................54
Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot/Undershoot Tolerance ..54
INT-mPGA Processor Package Dimensions.................................................................................59
Package Dynamic and Static Load Specifications ........................................................................62
Processor Mass.............................................................................................................................63
Processor Material Properties .......................................................................................................63
Pin Listing by Pin Name ................................................................................................................67
Pin Listing by Pin Number .............................................................................................................76
Signal Definitions...........................................................................................................................84
Processor Thermal Design Power.................................................................................................96
Power-On Configuration Option Pins ............................................................................................99
Processor Information ROM Format............................................................................................105
Read Byte SMBus Packet ...........................................................................................................107
Write Byte SMBus Packet ...........................................................................................................107
Write Byte SMBus Packet ...........................................................................................................108
Read Byte SMBus Packet ...........................................................................................................108
Send Byte SMBus PacketReceive Byte SMBus Packet..............................................................109
ARA SMBus Packet.....................................................................................................................109
SMBus Thermal Sensor Command Byte Bit Assignments..........................................................109
Thermal Reference Register Values ...........................................................................................110
SMBus Thermal Sensor Status Register.....................................................................................111
SMBus Thermal Sensor Configuration Register .........................................................................112
SMBus Thermal Sensor Conversion Rate Registers ..................................................................112
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Datasheet
7
Contents
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Thermal Sensor SMBus Addressing ...........................................................................................114
Memory Device SMBus Addressing............................................................................................114
Fan Cable Connector Requirements...........................................................................................122
Fan Power and Signal Specifications..........................................................................................122
8
Datasheet
Revision History
Revision
Date of Release
Description
No.
January 2002
April 2002
-001
-002
Initial datasheet release.
Addition of 2.40 GHz Data
Updated Figures 10 and 11
Made PWRGOOD updates
May 2002
-003
-004
Addition of 2.60 and 2.80 GHz Data
Updated Thermal Requirements
September 2002
Updated Thermal Requirements
Updated Table 6, 7
September 2002
February 2003
-005
-006
Added Table 12
Added 3 GHz information.
Edited definitions with current terminology.
Added two TDP loadline figures in chapter 6.
Added notes to signal definition tables for symmetric agents.
Changed text., figures and tables for the boxed processor section.
Datasheet
9
10
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
1.0
Introduction
The Intel® Xeon™ processor with 512 KB L2 cache is based on the Intel® NetBurst™ micro-
architecture, which operates at significantly higher clock speeds and delivers performance levels
that are significantly higher than previous generations of IA-32 processors. While based on the
Intel NetBurst micro-architecture, it maintains the tradition of compatibility with IA-32 software.
The Intel NetBurst micro-architecture features begin with innovative techniques that enhance
processor execution such as Hyper Pipelined Technology, a Rapid Execution Engine, Advanced
Dynamic Execution, enhanced Floating Point and Multimedia unit, and Streaming SIMD
Extensions 2 (SSE2). The Hyper Pipelined Technology doubles the pipeline depth in the processor,
allowing the processor to reach much higher core frequencies. The Rapid Execution Engine allows
the two integer ALUs in the processor to run at twice the core frequency, which allows many
integer instructions to execute in one half of the internal core clock period. The Advanced Dynamic
Execution improves speculative execution and branch prediction internal to the processor. The
floating point and multi-media units have been improved by making the registers 128 bits wide and
adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for double-
precision floating point, SIMD integer, and memory management for improvements in video/
multimedia processing, secure transactions, and visual internet applications.
Also part of the Intel NetBurst micro-architecture, the front side bus and caches on the Intel Xeon
processor with 512 KB L2 cache provide tremendous throughput for server and workstation
workloads. The 400 MHz front side bus provides a high-bandwidth pipeline to the system memory
and I/O. It is a quad-pumped bus running off a 100 MHz front side bus clock making 3.2 Gigabytes
per second (3,200 Megabytes per second) data transfer rates possible. The Execution Trace Cache
is a level 1 cache that stores approximately twelve thousand decoded micro-operations, which
removes the decoder latency from the main execution path and increases performance. The
Advanced Transfer Cache is a 512 KB on-die level 2 cache running at the speed of the processor
core providing increased bandwidth over previous micro-architectures.
In addition to the Intel NetBurst micro-architecture, the Intel Xeon processor with 512 KB L2
cache includes a groundbreaking new technology called Hyper-Threading technology, which
enables multi-threaded software to execute tasks in parallel within the processor resulting in a more
efficient, simultaneous use of processor resources. Server applications can realize increased
performance from Hyper-Threading technology today, while workstation applications are expected
to benefit from Hyper-Threading technology in the future through software and processor
evolution. The combination of Intel NetBurst micro-architecture and Hyper-Threading technology
delivers outstanding performance, throughput, and headroom for peak software workloads
resulting in faster response times and improved scalability.
The Intel Xeon processor with 512 KB L2 cache is intended for high performance workstation and
server systems with up to two processors on a single bus. The processor supports both uni- and
dual-processor designs and includes manageability features. Components of the manageability
features include an OEM EEPROM and Processor Information ROM that are accessible through a
SMBus interface. The Processor Information ROM includes information that is relevant to the
particular processor and system in which it is installed.
The Intel Xeon processor with 512 KB L2 cache is packaged in a 603-pin interposer micro-PGA
(INT-mPGA) package, and utilizes a surface mount ZIF socket with 603 pins. Mechanical
components used for attaching thermal solutions to the baseboard should have a high degree of
commonality with the thermal solution components enabled for the Intel Xeon processor.
Heatsinks and retention mechanisms have been designed with manufacturability as a high priority.
Hence, mechanical assembly can be completed from the top of the baseboard.
Datasheet
11
Intel® Xeon™ Processor with 512 KB L2 Cache
The Intel Xeon processor with 512 KB L2 cache uses a scalable front side bus protocol referred to
as the “front side bus” in this document. The processor front side bus utilizes a split-transaction,
deferred reply protocol similar to that introduced by the Pentium® Pro processor front side bus, but
is not compatible with the Pentium Pro processor front side bus. The Intel Xeon processor with
512 KB L2 cache front side bus is compatible with the Intel Xeon processor front side bus. The
front side bus uses Source-Synchronous Transfer (SST) of address and data to improve
performance, and transfers data four times per bus clock (4X data transfer rate). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
‘double-clocked’ or 2X address bus. In addition, the Request Phase completes in one clock cycle.
Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2
Gigabytes per second. Finally, the front side bus also introduces transactions that are used to
deliver interrupts.
Signals on the front side bus use Assisted GTL+ (AGTL+) level voltages which are fully described
in the appropriate platform design guide (refer to Section 1.3).
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front Side Bus (FSB)” refers to the electrical interface that connects the processor to the chipset.
Also referred to as the processor system bus or the system bus. All memory and I/O transactions as
well as interrupt messages pass between the processor and chipset over the FSB.
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
• 603-pin socket - The connector which mates the Intel® Xeon™ processor with 512 KB L2
cache to the baseboard. The 603-pin socket is a surface mount technology (SMT), zero
insertion force (ZIF) socket utilizing solder ball attachment to the platform. See the 603-Pin
Socket Design Guidelines for details regarding this socket.
• Central Agent - The central agent is the host bridge to the processor and is typically known as
the chipset.
• Flip Chip Ball Grid Array (FCBGA) - Microprocessor packaging using “flip chip” design,
where the processor is attached to the substrate face-down for better signal integrity, more
efficient heat removal and lower inductance.
• Front Side Bus - Front Side Bus (FSB) is the electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All memory and
I/O transactions as well as interrupt messages pass between the processor and chipset over the
FSB.
• Intel® Xeon™ processor with 512 KB L2 cache - The entire processor in its INT-mPGA
package, including processor core in its FC-BGA package, integrated heat spreader (IHS), and
interposer.
12
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
• Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal
solution to the processor.
• Interposer - The structure on which the processor core package and I/O pins are mounted.
• OEM - Original Equipment Manufacturer.
• Processor core - The processor’s execution engine. All AC timing and signal integrity
specifications are to the pads of the processor core.
• Processor Information ROM (PIROM) - An SMBus accessible memory device located on
the processor interposer. This memory device contains information regarding the processor’s
features. This device is shared with a scratch EEPROM. The PIROM is programmed during
the manufacturing and is write-protected. See Section 7.4 for details on the PIROM.
• Retention mechanism - The support components that are mounted through the baseboard to
the chassis to provide mechanical retention for the processor and heatsink assembly.
• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory) - An
SMBus accessible memory device located on the processor interposer. This memory device
can be used by the OEM to store information useful for system management. See Section 7.4
for details on the Scratch EEPROM.
• SMBus - System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the system. It is based on
the principals of the operation of the I2C two-wire serial bus from Philips Semiconductor.
Note: “I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a
subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/
protocol or the SMBus bus/protocol may require licenses from various entities, including
Philips Electronics N.V. and North American Philips Corporation.”
• Symmetric Agent - A symmetric agent is a processor which shares the same I/O subsystem
and memory array, and runs the same operating system as another processor in a system.
Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems.
Intel® Xeon™ (DP - Dual Processor) processors should only be used in SMP systems which
have two or fewer symmetric agents.
1.2
State of Data
The data contained in this document is subject to change. It is the best information that Intel is able
to provide at the publication date of this document.
Datasheet
13
Intel® Xeon™ Processor with 512 KB L2 Cache
1.3
References
The reader of this specification should also be familiar with material and concepts presented in the
following documents:.
1
Document
Intel Order Number
AP-485, Intel® Processor Identification and the CPUID Instruction
241618
IA-32 Intel ® Architecture Software Developer's Manual
• Volume I: Basic Architecture
245470
245471
245472
• Volume II: Instruction Set Reference
• Volume III: System Programming Guide
TM
®
Intel ® Xeon Processor and Intel 860 Chipset Platform Design Guide
Intel® Xeon™ Processor Thermal Design Guidelines
603 -Pin Socket Design Guidelines
298252
298348
249672
249678
249206
249205
298646
Intel® Xeon™ Processor Specification Update
CK00 Clock Synthesizer/Driver Design Guidelines
VRM 9.0 DC-DC Converter Design Guidelines
VRM 9.1 DC-DC Converter Design Guidelines
Dual Intel® XeonTM Processor Voltage Regulator Down (VRD) Design
Guidelines
298644
249679
ITP700 Debug Port Design Guide
Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility
Guidelines
298645
2
Intel® Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models
http://developer.intel.com
Intel® Xeon™ Processor with 512 KB L2 Cache Mechanical Models in ProE*
Format
http://developer.intel.com
http://developer.intel.com
http://developer.intel.com
http://developer.intel.com
Intel® Xeon™ Processor with 512 KB L2 Cache Mechanical Models in IGES*
Format
Intel® Xeon™ Processor with 512 KB L2 Cache Thermal Models (FloTherm*
and ICEPAK* format)
Intel® Xeon™ Processor with 512 KB L2 Cache Core Boundary Scan
Descriptor Language (BSDL) Model
http://www.sbs-forum.org/
smbus
System Management Bus Specification, rev 1.1
Wired for Management 2.0 Design Guide
Boxed Integration Notes
http://developer.intel.com
http://support.intel.com/
support/processors/xeon
NOTES:
1. Contact your Intel representative for the latest revision of documents without order numbers.
2. The signal integrity models are in IBIS format.
14
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
2.0
Electrical Specifications
2.1
Front Side Bus and GTLREF
Most Intel® Xeon™ processor with 512 KB L2 cache front side bus signals use Assisted Gunning
Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved
noise margins and reduced ringing through low voltage swings and controlled edge rates. The
processor termination voltage level is VCC, the operating voltage of the processor core. The use of a
termination voltage that is determined by the processor core allows better voltage scaling on the
processor front side bus. Because of the speed improvements to data and address busses, signal
integrity and platform design methods become more critical than with previous processor families.
Front side bus design guidelines are detailed in the appropriate platform design guide (refer to
Section 1.3).
The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See
Table 13 for GTLREF specifications). Termination resistors are provided on the processor silicon
and are terminated to its core voltage (VCC). The on-die termination resistors are a selectable
feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination
can be enabled to control reflections on the transmission line. For middle bus agents, on-die
termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating
the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to Section 2.12 for
details on ODTEN resistor termination requirements.
Note: Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard.
See Table 4 for details regarding these signals.
The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
front side bus, including trace lengths, is highly recommended when designing a system. Please
refer to http://developer.intel.com to obtain the Intel® Xeon™ Processor with 512 KB L2 Cache
Signal Integrity Models.
2.2
2.3
Power and Ground Pins
For clean on-chip power distribution, the Intel Xeon processor with 512 KB L2 cache has 190 VCC
(power) and 189 VSS (ground) inputs. All VCC pins must be connected to the system power plane,
while all VSS pins must be connected to the system ground plane. The processor VCC pins must be
supplied the voltage determined by the processor VID (Voltage ID) pins.
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This may cause
voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting
changes in current demand by the component, such as coming out of an idle condition. Similarly,
they act as a storage well for current when entering an idle condition from a running condition.
Datasheet
15
Intel® Xeon™ Processor with 512 KB L2 Cache
Care must be taken in the baseboard design to ensure that the voltage provided to the processor
remains within the specifications listed in Table 6. Failure to do so can result in timing violations or
reduced lifetime of the component. For further information and guidelines, refer to the appropriate
platform design guidelines.
2.3.1
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and the baseboard designer must ensure a low interconnect resistance from the regulator (or VRM
pins) to the 603-pin socket. Bulk decoupling may be provided on the voltage regulation module
(VRM) to meet help meet the large current swing requirements. The remaining decoupling is
provided on the baseboard. The power delivery path must be capable of delivering enough current
while maintaining the required tolerances (defined in Table 6). For further information regarding
power delivery, decoupling, and layout guidelines, refer to the appropriate platform design
guidelines.
2.3.2
Front Side Bus AGTL+ Decoupling
The Intel® Xeon™ processor with 512 KB L2 cache integrates signal termination on the die as well
as part of the required high frequency decoupling capacitance on the processor package. However,
additional high frequency capacitance must be added to the baseboard to properly decouple the
return currents from the front side bus. Bulk decoupling must also be provided by the baseboard for
proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate platform
design guidelines.
2.4
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor core frequency is a multiple of the
BCLK[1:0] frequency. The maximum processor bus ratio multiplier will be set during
manufacturing. The default setting will equal the maximum speed for the processor.
The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The
processor core frequency is configured during reset by using values stored internally during
manufacturing. The stored value sets the highest bus fraction at which the particular processor can
operate.
Clock multiplying within the processor is provided by the internal PLL, which requires a constant
frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC
specifications for the BCLK[1:0] inputs are provided in Table 7 and Table 14, respectively. These
specifications must be met while also meeting signal integrity requirements as outlined in Chapter
3.0. The processor utilizes a differential clock. Details regarding BCLK[1:0] driver specifications
are provided in the CK00 Clock Synthesizer/Driver Design Guidelines. Table 1 contains the
supported bus fraction ratios and their corresponding core frequencies.
16
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 1. Front Side Bus-to-Core Frequency Ratio
Front Side Bus-to-Core
Frequency Ratio
Core Frequency
1/16
1/17
1/18
1/19
1/20
1/21
1/22
1/24
1/26
1/28
1/30
1.60 GHz
1.70 GHz
1.80 GHz
1.90 GHz
2 GHz
2.10 GHz
2.20 GHz
2.40 GHz
2.60 GHz
2.80 GHz
3 GHz
2.4.1
Bus Clock
The front side bus frequency is set to the maximum supported by the individual processor.
BSEL[1:0] are outputs used to select the front side bus frequency. Table 2 defines the possible
combinations of the signals and the frequency associated with each combination. The frequency is
determined by the processor(s), chipset, and clock synthesizer. All front side bus agents must
operate at the same frequency. Individual processors will only operate at their specified front side
bus clock frequency, (100 MHz for present generation processors).
Baseboards designed for the Intel® XeonTM processor employ a 100 MHz front side bus clock. On
these baseboards, BSEL[1:0] are considered ‘reserved’ at the processor socket. No change is
required for operation with the Intel® Xeon™ processor with 512 KB L2 cache. Operation will
default to 100 MHz.
Table 2. Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]
BSEL1
BSEL0
Bus Clock Frequency
L
L
L
H
L
100 MHz
Reserved
Reserved
Reserved
H
H
H
2.5
PLL Filter
VCCA and VCCIOPLL are power sources required by the processor PLL clock generator. This
requirement is identical to that of the Intel Xeon processor. Since these PLLs are analog in nature,
they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades
external I/O timings as well as internal core timings (i.e. maximum frequency). To prevent this
degradation, these supplies must be low pass filtered from VCC. A typical filter topology is shown
in Figure 1.
Datasheet
17
Intel® Xeon™ Processor with 512 KB L2 Cache
The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or
IO in Figure 1), is as follows:
C
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter
refer to the appropriate platform design guidelines.
Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution
Trace < 0.02 Ω
Processor interposer "pin"
VCC
L1/L2
R-Socket
R-Socket
R-Trace
R-Trace
VCCA
PLL
C
Baseboard via that connects
filter to VCC plane
Socket pin
Processor
VSSA
C
R-Socket
VCCIOPLL
L1/L2
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Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 2. Phase Lock Loop (PLL) Filter Requirements
0.2 dB
0 dB
-0.5 dB
forbidden
zone
-28 dB
-34 dB
forbidden
zone
DC
passband
1 Hz
fpeak
1 MHz
66 MHz
fcore
high frequency
band
NOTES:
1. Diagram not to scale.
2. No specifications for frequencies beyond f
(core frequency).
core
3. f
, if existent, should be less than 0.05 MHz.
peak
2.5.1
Mixing Processors
Intel only supports those processor combinations operating with the same front side bus frequency,
core frequency, VID settings, and cache sizes. Not all operating systems can support multiple
processors with mixed frequencies. Intel does not support or validate operation of processors with
different cache sizes. Mixing processors of different steppings but the same model (as per CPUID
instruction) is supported, and is outlined in the Intel® Xeon™ Processor Specification Update.
Additional details are provided in AP-485, the Intel Processor Identification and the CPUID
Instruction application note.
Unlike previous Intel® Xeon™ processors, the Intel Xeon processor with 512 KB L2 cache does
not sample the pins IGNNE#, LINT[0]/INTR, LINT[1]/NMI, and A20M# to establish the core to
front side bus ratio. Rather, the processor runs at its tested frequency at initial power-on. If the
processor needs to run at a lower core frequency, as must be done when a higher speed processor is
added to a system that contains a lower frequency processor, the system BIOS is able to effect the
change in the core to front side bus ratio.
Datasheet
19
Intel® Xeon™ Processor with 512 KB L2 Cache
2.6
Voltage Identification
The VID specification for the processor is defined in this datasheet, and is supported by power
TM
delivery solutions designed according to the Dual Intel® Xeon
Processor Voltage Regulator
Down (VRD) Design Guidelines, VRM 9.0 DC-DC Converter Design Guidelines, and VRM 9.1
DC-DC Converter Design Guidelines. The minimum voltage is provided in Table 6, and varies
with processor frequency. This allows processors running at a higher frequency to have a relaxed
minimum voltage specification. The specifications have been set such that one voltage regulator
design can work with all supported processor frequencies.
Note that the VID pins will drive valid and correct logic levels when the Intel® Xeon™ processor
with 512 KB L2 cache is provided with a valid voltage applied to the SM_VCC pins. SM_VCC
must be correct and stable prior to enabling the output of the VRM that supplies VCC
.
Similarly, the output of the VRM must be disabled before SM_VCC becomes invalid. Refer to
Figure 19 for details.
The processor uses five voltage identification pins, VID[4:0], to support automatic selection of
processor voltages. Table 3 specifies the voltage level corresponding to the state of VID[4:0]. A ‘1’
in this table refers to a high voltage and a ‘0’ refers to low voltage level. If the processor socket is
empty (VID[4:0] = 11111), or the VRD or VRM cannot supply the voltage that is requested, it must
disable its voltage output. For further details, see the Dual Intel® XeonTM Processor Voltage
Regulator Down (VRD) Design Guidelines, or VRM 9.0 DC-DC Converter Design Guidelines or
the VRM 9.1 DC-DC Converter Design Guidelines.
20
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 3. Voltage Identification Definition
Processor Pins
VID2 VID1
VID4
VID3
VID0
VCC_VID (V)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VRM output off
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
2.6.1
Mixing Processors of Different Voltages
Mixing processors operating with different VID settings (voltages) is not supported and will not be
validated by Intel.
Datasheet
21
Intel® Xeon™ Processor with 512 KB L2 Cache
2.7
Reserved Or Unused Pins
All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to
VCC, VSS, or to any other signal (including one another) can result in component malfunction or
incompatibility with future processors. See Chapter 5.0 for a pin listing of the processor and for the
location of all Reserved pins.
For reliable operation, unused inputs or bidirectional signals should always be connected to an
appropriate signal level. In a system-level design, on-die termination has been included on the
processor to allow signal termination to be accomplished by the processor silicon. Most unused
AGTL+ inputs should be left as no connects, as AGTL+ termination is provided on the processor
silicon. However, see Table 4 for details on AGTL+ signals that do not include on-die termination.
Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs
can be left unconnected, however this may interfere with some TAP functions, complicate debug
probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional
signals to power or ground. When tying any signal to power or ground, a resistor will also allow for
system testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value
for the on-die termination resistors (RTT). See Table 13.
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and all used outputs must be terminated on the baseboard. Unused outputs may
be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated
may interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design
Guide.
All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor which
matches the trace impedance within ±10 Ω. TESTHI[3:0] and TESTHI[6:5] may all be tied
together and pulled up to VCC with a single resistor if desired. However, utilization of boundary
scan test will not be functional if these pins are connected together. TESTHI4 must always be
pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-up
resistor values used for TESTHI[6:0] pins should have a resistance value within 20 percent of the
impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 Ω,
then a pull-up resistor value between 40 and 60 Ω should be used. The TESTHI[6:0] termination
recommendations provided in the Intel® XeonTM Processor Datasheet are also suitable for the
Intel® Xeon™ processor with 512 KB L2 cache. However, Intel recommends new designs or
designs undergoing design updates follow the trace impedance matching termination guidelines
outlined in this section.
2.8
Front Side Bus Signal Groups
In order to simplify the following discussion, the front side bus signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as
a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals whose timings are specified with respect to
rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address) as well as
22
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle. Table 4 identifies which signals are common
clock, source synchronous and asynchronous.
Table 4. Front Side Bus Signal Groups
1
Signal Group
Type
Signals
3,4
4
BPRI#, BR[3:1]# , DEFER#, RESET# ,
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
7
7
ADS#, AP[1:0]#, BINIT# , BNR# ,
2
2
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
BPM[5:0]# , BR0# , DBSY#, DP[3:0]#,
DRDY#, HIT# , HITM# , LOCK#, MCERR#
7
7
7
Signals
Associated Strobe
REQ[4:0]#,A[16:3]#6
A[35:17]#5
ADSTB0#
ADSTB1#
AGTL+ Source Synchronous
I/O
Synchronous to assoc.
strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
AGTL+ Strobes
Synchronous to BCLK[1:0]
Asynchronous
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
5
5
6
5
A20M# , IGNNE# , INIT# , LINT0/INTR ,
4
Asynchronous GTL+ Input
5
6
LINT1/NMI , SMI# , SLP#, STPCLK#
4
Asynchronous GTL+ Output
Front Side Bus Clock
Asynchronous
Clock
FERR#, IERR#, THERMTRIP#, PROCHOT#
BCLK1, BCLK0
TCK, TDI, TMS, TRST#
TDO
2
TAP Input
Synchronous to TCK
Synchronous to TCK
2
TAP Output
SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT,
SM_CLK, SM_ALERT#, SM_WP
8
SMBus Interface
Synchronous to SM_CLK
BSEL[1:0], COMP[1:0], GTLREF, ODTEN,
Reserved, SKTOCC#, TESTHI[6:0],VID[4:0],
Power/Other
Power/Other
9
V
V
, SM_V
, V
, V
, V
, V
,
CC
CCSENSE
CC
CCA
CCIOPLL
SSA
SS
, V
PWRGOOD
SSSENSE,
1. Refer to Section 5.2 for signal descriptions.
2. These signal groups are not terminated by the processor. Refer the ITP700 Debug Port Design Guide and
corresponding Design Guide for termination requirements and further details.
®
3. The Intel Xeon™ processor with 512 KB L2 cache utilizes only BR0# and BR1#. BR2# and BR3# are not
driven by the processor but must be terminated to VCC. For additional details regarding the BR[3:0]# signals,
see Section 5.2 and Section 7.1 and the appropriate Platform Design Guidelines.
4. These signals do not have on-die termination. Refer to corresponding Platform Design Guidelines for
termination requirements.
®
5. Note that Reset initialization function of these pins is now a software function on the Intel Xeon™
processor with 512 KB L2 cache.
6. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration
options. See Section 7.1 for details.
7. These signals may be driven simultaneously by multiple agents (wired-or).
8. These signals are not terminated by the processor’s on-die termination. However, some signals in this group
include termination on the processor interposer. See Section 7.4 for details.
Datasheet
23
Intel® Xeon™ Processor with 512 KB L2 Cache
®
9. SM_Vcc is required for correct VID logic operation of the Intel Xeon™ processor with 512 KB L2 cache.
Refer to Figure 19 for details.
2.9
Asynchronous GTL+ Signals
The Intel® Xeon™ processor with 512 KB L2 cache does not utilize CMOS voltage levels on any
signals that connect to the processor silicon. As a result, legacy input signals such as A20M#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+ input
buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals IERR#, THERMTRIP# and
PROCHOT# utilize GTL+ output buffers. All of these asynchronous GTL+ signals follow the same
DC requirements as AGTL+ signals, however the outputs are not driven high (during the logical 0-
to-1 transition) by the processor (the major difference between GTL+ and AGTL+). Asynchronous
GTL+ signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all
of the asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for
the processor to recognize them. See Table 10 and Table 17 for the DC and AC specifications for
the asynchronous GTL+ signal groups.
SMBus signals are derived from components mounted on the processor interposer along with the
processor silicon. The required SM_VCC for these signals is 3.3 volts. See Section 7.4 for further
details.
2.10
Maximum Ratings
Table 5 lists the processor’s maximum environmental stress ratings. Functional operation at the
absolute maximum and minimum is neither implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating parameters are listed in
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from static
electric discharge, one should always take precautions to avoid high static voltages or electric
fields.
Table 5. Processor Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
TSTORAGE
Processor storage temperature
-40
85
°C
2
Any processor supply voltage with
respect to VSS
VCC
-0.3
-0.1
-0.1
-0.3
1.75
1.75
1.75
V
V
V
1
AGTL+ buffer DC input voltage with
respect to VSS
VinAGTL+
VinGTL+
VinSMBus
IVID
Async GTL+ buffer DC input voltage
with respect to Vss
SMBus buffer DC input voltage with
respect to Vss
6.0
5
V
Max VID pin current
mA
1. This rating applies to any pin of the processor.
2. Contact Intel for storage requirements in excess of one year.
24
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless
noted otherwise. See Section 5.1 for the processor pin listings and Section 5.2 for the signal
definitions. The voltage and current specifications for all versions of the processor are detailed in
Table 6. For platform planning refer to Figure 3. Notice that the graphs include Thermal Design
Power (TDP) associated with the maximum current levels. The DC specifications for the AGTL+
signals are listed in Table 8.
The front side bus clock signal group and the SMBus interface signal group are detailed in Table 7
and Table 11, respectively. The DC specifications for these signal groups are listed in Table 9.
Table 6 through Table 11 list the processor DC specifications and are valid only while meeting
specifications for case temperature (TCASE as specified in Chapter 6.0), clock frequency, and input
voltages. Care should be taken to read all notes associated with each parameter.
Datasheet
25
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 6. Voltage and Current Specifications
Core
Freq
1
Symbol
Parameter
Min
Typ
Max
VID
Unit
Notes
1.80 GHz
2.0 GHz
2.20 GHz
2.40 GHz
2.60 GHz
2.80 GHz
3 GHz
1.361
1.357
1.352
1.347
1.339
1.335
1.356
1.465
1.463
1.46
1.5
1.5
V
V
V
V
V
V
V
2, 3, 4, 11, 12
2, 3, 4, 11, 12
2, 3, 4, 11, 12
2, 3, 4, 11, 12
2, 3, 4, 11, 12
2, 3, 4, 11, 12
2, 3, 4, 11, 12
1.5
V
for Intel Xeon
processor with
CC
Refer to
Figure 3
V
1.458
1.453
1.450
1.467
1.5
CC
512 KB L2 cache
1.5
1.5
1.525
SMBus supply
voltage
SM_V
All freq.
3.135
3.30
3.465
V
8
CC
1.8 GHz
2 GHz
A
A
A
A
A
A
A
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
42.4
45.3
48.1
51
2.20 GHz
2.40 GHz
2.60 GHz
2.80 GHz
3 GHz
I
for Intel Xeon
CC
I
processor with
512 KB L2 cache
CC
56.1
59.1
69.1
I
for PLL power
pins
CC
I
I
All freq
All freq.
60
mA
mA
9
8
CC_PLL
I
I
for SMBus power
supply
CC
100.0
122.5
CC_SMBus
I
I
I
I
for GTLREF pins
Stop-Grant/Sleep
All freq
All freq
All freq
15
25
µA
A
10
6
CC_GTLREF
CC
/I
SGnt SLP
CC
I
TCC active
CC
18.6
A
7
TCC
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processors.
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.6 and Table 3 for more information.
3. The voltage specification requirements are measured across vias on the platform for the V
and
CC_SENSE
V
pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
SS_SENSE
capacitance, and 1 milliohm minimum impedance. The maximum length of ground wire on the probe should
be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
4. The processor should not be subjected to any static V level that exceeds the V
associated with any
CC
CC_MAX
particular current. Moreover, Vcc should never exceed V
shorten the processor lifetime.
. Failure to adhere to this specification can
CC_VID
5. Maximum current is defined at V
.
CC_MAX
6. The current specified is also for AutoHALT State.
7. The maximum instantaneous current the processor will draw while the thermal control circuit is active as
indicated by the assertion of PROCHOT#.
8. SM_V is required for correct operation of the processor VID logic. Refer to Figure 19 for details.
CC
9. This specification applies to the PLL power pins VCCA and VCCIOPLL. See Section 2.5 for details. This
parameter is based on design characterization and is not tested
10.This specification applies to each GTLREF pin.
11.The loadlines specify voltage limits at the die measured at V
and V
pins. Voltage
CC_SENSE
SS_SENSE
regulation feedback for voltage regulator circuits must be taken from processor V and V pins.
CC
SS
12.Adherence to this loadline specification is required to ensure reliable processor operation.
26
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 3. Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID =1.5V)
1.51
1.50
1.49
1.48
1.47
1.46
1.45
1.44
0
10
20
30
40
50
60
70
Processor Current (A)
Datasheet
27
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 4. Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID =
1.525V)
Table 7. Front Side Bus Differential BCLK Specifications
Notes
Symbol
Parameter
Min
Typ
Max
Unit Figure
1
Input Low
Voltage
V
-.150
0.660
0.000
0.710
N/A
N/A
V
V
V
7
7
L
Input High
Voltage
V
0.850
H
V
V
Absolute
Crossing Point
CROSS(
abs)
0.250
0.550
7, 8
2,8
0.250 +
0.550 +
Relative
Crossing Point
CROSS(
rel)
N/A
N/A
V
V
7, 8
7, 8
2,3,8,9
0.5(V
-
0.5(V
-
Havg
Havg
0.710)
0.710)
Range of
Crossing Points
∆V
N/A
0.140
2,10
CROS
S
V
Overshoot
N/A
N/A
N/A
V
+ 0.3
H
V
V
7
7
4
5
OV
US
V
Undershoot
-0.300
N/A
NOTES:.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
falling edge of BCLK1.
3. V
is the statistical average of the V measured by the oscilloscope.
Havg
H
28
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
9. V
can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.
Havg
10.∆V
is defined as the total variation of all crossing voltages as defined in note 2.
CROSS
Table 8. AGTL+ Signal Group DC Specifications
Notes
Symbol
Parameter
Min
Max
Unit
1,7
V
V
V
Input High Voltage
Input Low Voltage
Output High Voltage
1.10 * GTLREF
V
V
V
V
2, 4, 6
3, 6
IH
CC
0.0
0.90 * GTLREF
IL
N/A
V
4, 6
OH
CC
VCC /
(0.50 * R
+ R
)
ON_min
I
Output Low Current
N/A
mA
6
TT_min
OL
= 50
I
I
Pin Leakage High
Pin Leakage Low
N/A
N/A
7
100
500
11
µA
µA
Ω
9
8
HI
LO
R
Buffer On Resistance
5, 7
ON
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. V is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
IH
value.
3. V is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
IL
4. V and V may experience excursions above V . However, input signal drivers must comply with the
IH
ON
CC
signal quality specifications in Chapter 3.0.
®
5. Refer to the Intel Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
6. The V referred to in these specifications refers to instantaneous VCC
.
CC
7. V
of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with R enabled.
OL_MAX
TT
8. Leakage to V with pin held at 300 mV.
CC
9. Leakage to V with pin held at V
.
SS
CC
Table 9. TAP and PWRGOOD Signal Group DC Specifications
1, 2
Symbol
Parameter
Min
Max
Unit Notes
V
TAP Input Hysteresis
200
300
8
HYS
TAP input low to high
threshold voltage
V
0.5 * (V + V
)
)
0.5 * (V + V )
HYS_MAX
5
5
T+
CC
HYS_MIN
CC
TAP input high to low
threshold voltage
V
V
0.5 * (V - V
0.5 * (V - V
)
HYS_MIN
T-
CC
HYS_MAX
CC
Output High Voltage
Output Low Current
Pin Leakage High
Pin Leakage Low
N/A
V
V
mA
µA
µA
Ω
3, 5
6, 7
10
9
OH
CC
I
I
I
40
OL
N/A
N/A
8.75
100
500
HI
LO
R
Buffer On Resistance
13.75
4
ON
NOTES:.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All outputs are open drain
Datasheet
29
Intel® Xeon™ Processor with 512 KB L2 Cache
3. TAP signal group must meet the system signal quality specification in Chapter 3.0.
®
4. Refer to the Intel Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
5. The V referred to in these specifications refers to instantaneous V
.
CC
CC
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
7. V
8. V
of 0.300V is guaranteed when driving a test load.
represents the amount of hysteresis, nominally centered about 0.5*V , for all TAP inputs.
OL_MAX
HYS
CC
9. Leakage to V with Pin held at 300 mV.
CC
10.Leakage to V with pin held at V
.
SS
CC
Table 10. Asynchronous GTL+ Signal Group DC Specifications
1, 7
Symbol
Parameter
Min
Max
Unit
Notes
V
V
V
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Current
Pin Leakage High
Pin Leakage Low
1.10 * GTLREF
V
V
V
3, 5, 7
4, 6
2, 5, 7
8, 9
11
IH
CC
0.0
0.90 * GTLREF
IL
N/A
VCC
50
V
OH
I
I
I
mA
µA
µA
Ω
OL
N/A
N/A
7
100
500
11
HI
10
LO
R
Buffer On Resistance
6
ON
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All outputs are open drain
3. V is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
IH
value.
4. V is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
IL
5. V and V
may experience excursions above V . However, input signal drivers must comply with the
IH
OH
CC
signal quality specifications in Chapter 3.0.
®
6. Refer to the Intel Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
7. The V referred to in these specifications refers to instantaneous V
.
CC
CC
8. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
9. V
of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with R enabled.
OL_MAX
TT
10. Leakage to V with Pin held at 300 mV.
CC
11.Leakage to V with pin held at V
.
SS
CC
Table 11. SMBus Signal Group DC Specifications
1, 2, 3
Symbol
Parameter
Min
Max
Unit
Notes
V
V
V
Input Low Voltage
Input High Voltage
-0.30
0.30 * SM_V
3.465
0.400
3.0
V
V
IL
CC
0.70 * SM_V
IH
OL
CC
Output Low Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
SMBus Pin Capacitance
0
V
I
I
I
N/A
N/A
N/A
mA
µA
µA
pF
OL
± 10
LI
± 10
LO
C
15.0
4
SMB
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All DC specifications for the SMBus signal group are measured at the processor pins.
4. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine
maximum rise and fall times for SMBus signals.
30
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 12. BSEL[1:0] and VID[4:0] DC Specifications
1
Symbol
Parameter
Min
Max
Unit
Notes
Buffer On
Resistance
Ron (BSEL)
9.2
14.3
Ω
2
Ron
(VID)
Buffer On
Resistance
7.8
12.8
100
Ω
2
3
I
Pin Leakage Hi
N/A
µA
HI
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50V.
2.12
AGTL+ Front Side Bus Specifications
Routing topologies are dependent on the number of processors supported and the chipset used in
the design. Please refer to the appropriate platform design guidelines. In most cases, termination
resistors are not required as these are integrated into the processor. See Table 4 for details on which
AGTL+ signals do not include on-die termination.The termination resistors are enabled or disabled
through the ODTEN pin. To enable termination, this pin should be pulled up to VCC through a
resistor and to disable termination, this pin should be pulled down to VSS through a resistor. For
optimum noise margin, all pull-up and pull-down resistor values used for the ODTEN pin should
have a resistance value within 20 percent of the impedance of the baseboard transmission line
traces. For example, if the trace impedance is 50 Ω, then a value between 40 and 60 Ω should be
used. The processor's on-die termination must be enabled for the end agent only. Please refer to
Table 13 for termination resistor values. For more details on platform design see the appropriate
platform design guidelines.
Valid high and low levels are determined by the input buffers via comparing with a reference
voltage called GTLREF.
Table 13 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be
generated on the baseboard using high precision voltage divider circuits. It is important that the
baseboard impedance is held to the specified tolerance, and that the intrinsic trace capacitance for
the AGTL+ signal group traces is known and well-controlled. For more details on platform design
see the appropriate platform design guidelines.
Table 13. AGTL+ Bus Voltage Definitions
1
Symbol
Parameter
Min
Typ
Max
2/3 * V + 2%
Units Notes
GTLREF
Bus Reference Voltage
2/3 * V - 2% 2/3 * V
V
V
Ω
2, 3, 6
CC
CC
CC
GTLREF
New Design
Bus Reference Voltage
Termination Resistance
0.63*VCC - 2% 0.63*VCC 0.63*VCC + 2%
2, 3, 6,
4
R
R
36
45
41
50
46
55
TT
TT
Termination Resistance
Ω
Ω
4, 8
5, 7
New
Design
COMP[1:0] COMP Resistance
42.77
43.2
43.63
Datasheet
31
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 13. AGTL+ Bus Voltage Definitions
COMP[1:0]
New
COMP Resistance
49.55
50
50.45
Ω
5, 7, 8
Design
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The tolerances for this specification have been stated generically to enable system designer to calculate the
minimum values across the range of V
.
CC
3. GTLREF is generated from V
on the baseboard by a voltage divider of 1 percent resistors. Refer to the
CC
appropriate platform design guidelines for implementation details.
4. R is the on-die termination resistance measured from V to 1/3 V at the AGTL+ output driver. Refer to
TT
CC
CC
®
the Intel Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
5. COMP resistors are pull downs to V provided on the baseboard with 1% tolerance. See the appropriate
SS
platform design guidelines for implementation details.
6. The V referred to in these specifications refers to instantaneous V
.
CC
CC
7. The COMP resistance value varies by platform. Refer to the appropriate platform design guideline for the
recommended COMP resistance value.
®
8. The values for R and COMP noted as ‘New Designs’ apply to designs that are optimized for the Intel
TT
Xeon™ processor with 512 KB L2 cache. Refer to the appropriate platform design guideline for the
recommended COMP resistance value.
9. This specification applies to the Intel® Xeon™Processor with 512 KB L2 Cache when implemented in
platforms that do not include forward compatibility with future processors.
10.This specification applies to the Intel Xeon Processor with 512 KB L2 Cache when implemented in platforms
that include forward compatibility with future processors.
2.13
Front Side Bus AC Specifications
The processor front side bus timings specified in this section are defined at the processor core
(pads). See Section 5.0 for the pin listing and signal definitions.
Table 14 through Table 20 list the AC specifications associated with the processor front side bus.
All AGTL+ timings are referenced to GTLREF for both ‘0’ and ‘1’ logic levels unless otherwise
specified.
The timings specified in this section should be used in conjunction with the signal integrity models
provided by Intel. These signal integrity models, which include package information, are available
for the Intel® Xeon™ processor with 512 KB L2 cache in IBIS format. AGTL+ layout guidelines
are also available in the appropriate platform design guidelines.
Note: Care should be taken to read all notes associated with a particular timing parameter
Table 14. Front Side Bus Differential Clock Specifications
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
Front Side Bus Clock Frequency
T1: BCLK[1:0] Period
100.0
10.20
150
MHz
nS
pS
nS
nS
pS
pS
1, 2
1, 3
10.00
N/A
7
T2: BCLK[1:0] Period Stability
1, 4, 5
1
T3: T BCLK[1:0] Pulse High Time
3.94
3.94
175
5
5
6.12
6.12
700
7
7
7
7
PH
1
T4: T BCLK[1:0] Pulse Low Time
PL
T5: BCLK[1:0] Rise Time
T6: BCLK[1:0] Fall Time
1, 6
1, 6
175
700
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
32
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
2. The processor core clock frequency is derived from BCLK.
3. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2).
4. For the clock jitter specification, refer to the CK00 Clock Synthesizer/Driver Design Guidelines.
5. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
6. Slew rate is measured between the 35% and 65% points of the clock swing (V and V ).
L
H
.
Table 15. Front Side Bus Common Clock AC Specifications
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T10: Common Clock Output Valid Delay
T11: Common Clock Input Setup Time
T12: Common Clock Input Hold Time
T13: RESET# Pulse Width
0.12
0.65
0.40
1.00
1.27
N/A
nS
nS
nS
mS
9
9
4
5
5
N/A
9
10.00
12
6, 7, 8
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V
) of the
CROSS
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
4. Valid delay timings for these signals are specified into the test circuit described in Figure 5 and with GTLREF
at 2/3 * V ± 2%.
CC
5. Specification is for a minimum swing defined between AGTL+ V
of 0.3 V/nS to 4.0 V/nS.
to V
. This assumes an edge rate
IL_MAX
IH_MIN
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. This should be measured after VCC and BCLK[1:0] become stable.
8. Maximum specification applies only while PWRGOOD is asserted.
.
Table 16. Front Side Bus Source Synchronous AC Specifications (Page 1 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
T20: Source Sync. Output Valid Delay (first data/
address only)
1, 2, 3, 4,
5
0.20
1.30
nS
10, 11
T21: T
Data Strobe
Source Sync. Data Output Valid Before
1, 2, 3, 4,
5, 8
VBD
0.85
0.85
1.88
1.88
0.21
0.21
0.65
nS
nS
11
11
T22: T Source Sync. Data Output Valid After
Data Strobe
1, 2, 3, 4,
5, 8
VAD
T23: T Source Sync. Address Output Valid
Before Address Strobe
1, 2, 3, 4,
5, 8
VBA
nS
10
T24: T Source Sync. Address Output Valid After
Address Strobe
1, 2, 3, 4,
5, 9
VAA
nS
10
1, 2, 3, 4,
6
T25: T
T26: T
Source Sync. Input Setup Time
nS
10, 11
10, 11
10, 11
10
SUSS
1, 2, 3, 4,
6
Source Sync. Input Hold Time
nS
HSS
T27: T
BCLK
Source Sync. Input Setup Time to
1, 2, 3, 4,
7
SUCC
nS
T28: T
Strobe
First Address Strobe to Second Address
1, 2, 3, 4,
10, 14
FASS
1/2
BCLKs
Datasheet
33
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 16. Front Side Bus Source Synchronous AC Specifications (Page 2 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
1, 2, 3, 4,
11, 12,
14
T29: T
Strobes
: First Data Strobe to Subsequent
FDSS
n/4
BCLKs
11
1, 2, 3,
4, 13
T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay
T31: Address Strobe Output Valid Delay
8.80
2.27
10.20
4.23
nS
nS
11
10
1, 2, 3, 4
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source
synchronous data signals are referenced to the falling edge of their associated data strobe. Source
synchronous address signals are referenced to the rising and falling edge of their associated address strobe.
All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core.
4. Unless otherwise noted, these specifications apply to both data and address timings.
5. Valid delay timings for these signals are specified into the test circuit described in Figure 5 and with GTLREF
at 2/3 * V ± 2%.
CC
6. Specification is for a minimum swing defined between AGTL+ V
to V
. This assumes an edge rate
IH_MIN
IL_MAX
of 0.3 V/nS to 4.0 V/nS.
7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each
respective strobe.
8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the
appropriate platform design guidelines for more information on the definitions and use of these specifications.
9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the
appropriate platform design guidelines for more information on the definitions and use of these specifications.
10.The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 nS) after the falling edge of
ADSTB#.
11.For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.
12.The second data strobe (the falling edge of DSTBn#) must come approximately 1/4 BCLK period (2.5 nS)
after the first falling edge of DSTBp#. The third data strobe (the falling edge of DSTBp#) must come
approximately 2/4 BCLK period (5 nS) after the first falling edge of DSTBp#. The last data strobe (the falling
edge of DSTBn#) must come approximately 3/4 BCLK period (7.5 nS) after the first falling edge of DSTBp#.
13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
14.This specification reflects a typical value, not a minimum or maximum..
Table 17. Miscellaneous Signals+ AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
T35: Async GTL+ input pulse width
2
1
N/A
10
BCLKs
mS
1, 2, 3, 4
1, 2, 3, 4
T36: PWRGOOD to RESET# de-assertion time
13
13
1, 2, 3, 4,
5
T37: PWRGOOD inactive pulse width
10
N/A
BCLKs
1, 2, 3, 4,
6
T38: PROCHOT# pulse width
500
µS
S
15
16
T39: THERMTRIP# to Vcc Removal
0.5
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing
Voltage (V
). All Asynchronous GTL+ signal timings are referenced at GTLREF.
CROSS
3. These signals may be driven asynchronously.
4. Refer to Section 7.2 for additional timing requirements for entering and leaving low power states.
5. Refer to the PWRGOOD signal definition in Section 5.2 for more detail information on behavior of the signal.
6. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the
assertion of PROCHOT# for the processor to complete current instruction execution.
34
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 18. Front Side Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Reset Configuration Signals (A[31:3]#,
BR[3:0]#, INIT#, SMI#) Setup Time
4
BCLKs
12
1
T46: Reset Configuration Signals (A[31:3]#,
BR[3:0]#, INIT#, SMI#) Hold Time
2
20
BCLKs
12
2
1. Before the de-assertion of RESET#
2. After the clock that de-asserts RESET#.
Table 19. TAP Signal Group AC Specifications
Notes
1,2,3,9
T# Parameter
Min
Max
Unit
Figure
T55: TCK Period
60.0
nS
nS
nS
nS
nS
nS
nS
nS
6
6
T56: TCK Rise Time
9.5
9.5
8.5
8.5
4
4
T57: TCK Fall Time
6
T58: TMS, TDI Rise Time
T59: TMS, TDI Fall Time
T61: TDI, TMS Setup Time
T62: TDI, TMS Hold Time
T63: TDO Clock to Output Delay
T64: TRST# Assert Time
6
4
6
4
0
14
14
14
15
5, 7
5, 7
6
3.0
0.5
2.0
3.5
T
8
TCK
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5 * V at the processor pins. All
CC
TAP signal timings (TMS, TDI, etc) are referenced at the 0.5 * V processor pins.
CC
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
5. Referenced to the rising edge of TCK.
6. Referenced to the falling edge of TCK.
7. Specification for a minimum swing defined between TAP 20% to 80%. This assumes a minimum edge rate of
0.5 V/nS.
8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
9. It is recommended that TMS be asserted while TRST# is being deasserted..
Table 20. SMBus Signal Group AC Specifications (Page 1 of 2)
T# Parameter
T70: SM_CLK Frequency
Min
Max
Unit
Figure
Notes
10
10
100
100
N/A
N/A
1.0
KHz
µS
µS
µS
µS
µS
µS
nS
nS
1, 2, 3
1, 2, 3
T71: SM_CLK Period
T72: SM_CLK High Time
T73: SM_CLK Low Time
T74: SMBus Rise Time
4.0
17
17
17
17
18
17
17
1, 2, 3
4.7
1, 2, 3
0.02
0.02
0.1
1, 2, 3, 5
1, 2, 3, 5
1, 2, 3
T75: SMBus Fall Time
0.3
T76: SMBus Output Valid Delay
T77: SMBus Input Setup Time
T78: SMBus Input Hold Time
4.5
250
300
N/A
N/A
1, 2, 3
1, 2, 3
Datasheet
35
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 20. SMBus Signal Group AC Specifications (Page 2 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
1, 2, 3, 4,
6
T79: Bus Free Time
4.7
N/A
µS
17
T80: Hold Time after Repeated Start Condition
T81: Repeated Start Condition Setup Time
T82: Stop Condition Setup Time
4.0
4.7
4.0
N/A
N/A
N/A
µS
µS
µS
17
17
17
1, 2, 3
1, 2, 3
1, 2, 3
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All AC timings for the SMBus signals are referenced at V
pins. Refer to Figure 17.
or V
and measured at the processor
IL_MAX
IL_MIN
4. Minimum time allowed between request cycles.
5. Rise time is measured from (V
- 0.15V) to (V
+ 0.15V). Fall time is measured from (0.9 *
IH_MIN
IL_MAX
SM_V ) to (V
- 0.15V). DC parameters are specified in Table 11.
CC
IL_MAX
6. Following a write transaction, an internal device write cycle time of 10ms must be allowed before starting the
next transaction.
2.14
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 14 through Table
20.
Note: For Figure 6 through Figure 15, the following apply:
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage
(VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal
timings are referenced at GTLREF at the processor core (pads).
2. All source synchronous AC timings for AGTL+ signals are referenced to their associated
strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the
falling edge of their associated data strobe. Source synchronous address signals are referenced
to the rising and falling edge of their associated address strobe. All source synchronous
AGTL+ signal timings are referenced at GTLREF at the processor core (pads).
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All
AGTL+ strobe signal timings are referenced at GTLREF at the processor core (pads).
4. All AC Timing for he TAP signals are referenced to the TCK signal at 0.5 * VCC at the
processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at the 0.5 * VCC at the
processor core (pads).
5. All AC timings for the SMBus signals are referenced to the SM_CLK signal at 0.5 * SM_VCC
at the processor pins. All SMBus signal timings (SM_DAT, SM_ALERT#, etc.) are referenced
at VIL_MAX or VIL_MIN at the processor pins.
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Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 5. Electrical Test Circuit
Vtt
Vtt
Rload = 50 ohms
Zo = 50 ohms, d=420mils, So=169ps/in
L = 2.4nH
C = 1.2pF
AC Timings
specified at pad.
Figure 6. TCK Clock Waveform
tr
*V2
*V3
CLK
*V1
tf
tp
Tr = T56, T58 (Rise Time)
Tf = T57, T59 (Fall Time)
Tp = T55 (Period)
V1, V2: For rise and fall times, TCK is measured between 20%to 80%points on the waveform.
V3: TCK is referenced to 0.5* Vcc.
Datasheet
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Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 7. Differential Clock Waveform
Tph
Overshoot
VH
BCLK1
Rising Edge
Ringback
Crossing
Voltage
Crossing
Voltage
Ringback
Margin
Threshold
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
Tpl
Tp
Tp = T1 (BCLK[1:0] period)
T2 = BCLK[1:0] Period stability (not shown)
Tph =T3 (BCLK[1:0] pulse high time)
Tpl = T4 (BCLK[1:0] pulse low time)
T5 = BCLK[1:0] rise time through the threshold region
T6 = BCLK[1:0] fall time through the threshold region
Figure 8. Differential Clock Crosspoint Specification
Crosspoint Specification
650
600
550
500
450
400
350
300
250
200
550 mV
550 + 0.5 (VHavg - 710)
250 + 0.5 (VHavg - 710)
250 mV
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
Vhavg (mV)
38
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 9. Front Side Bus Common Clock Valid Delay Timing Waveform
T0
T1
T2
BCLK1
BCLK0
TP
Common Clock
Signal (@ driver)
valid
valid
TQ
TR
Common Clock
Signal (@ receiver)
valid
TP = T10: Common Clock Output Valid Delay
TQ = T11: Common Clock Input Setup
TR = T12: Common Clock Input Hold Time
Figure 10. Front Side Bus Source Synchronous 2X (Address) Timing Waveform
T1
T2
1/4
1/2
3/4
BCLK BCLK BCLK
BCLK1
BCLK0
TP
ADSTB# (@ driver)
A# (@ driver)
TR
TH
TJ
TH
TJ
valid
valid
TS
ADSTB# (@ receiver)
A# (@ receiver)
TK
valid
valid
TN
TM
TH = T23: Source Sync. Address Output Valid Before Address Strobe
TJ = T24: Source Sync. Address Output Valid After Address Strobe
TK = T27: Source Sync. Input Setup to BCLK
TM = T26: Source Sync. Input Hold Time
TN = T25: Source Sync. Input Setup Time
T
T
T
P = T28: First Address Strobe to Second Address Strobe
S = T20: Source Sync. Output Valid Delay
R = T31: Address Strobe Output Valid Delay
Datasheet
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Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 11. Front Side Bus Source Synchronous 4X (Data) Timing Waveform
T0
T1
T2
1/4
1/2
3/4
BCLK BCLK BCLK
BCLK1
BCLK0
DSTBp# (@ driver)
DSTBn# (@ driver)
TH
TD
TA TB TA
D# (@ driver)
TJ
DSTBp# (@ receiver)
DSTBn# (@ receiver)
D# (@ receiver)
TC
TE TG TE TG
TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe
T
T
T
T
T
T
B = T22: Source Sync. Data Output Valid Delay After Data Strobe
C = T27: Source Sync. Setup Time to BCLK
D = T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay
E = T25: Source Sync. Input Setup Time
G = T26: Source Sync. Input Hold Time
H = T29: First Data Strobe to Subsequent Strobes
TJ = T20: Source Sync. Data Output Valid Delay
40
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 12. Front Side Bus Reset and Configuration Timing Waveform
BLCK
T
u
T
t
RESET#
T
v
T
x
Configuration
Safe
Valid
Valid
(A[31:3]#, BR0#,
SMI#, INIT#)
Tw
Configuration
(A[31:3]#, BR0#,
SMI#, INIT#)
T
v
=
=
T13 (RESET# Pluse Width)
T
T45 (Reset Configuration Signals (A[14:5]#, BR0#, SMI#, INIT#) Setup Time)
w
T
T46 (Reset Configuration signals (A[14:5]#, BR0#, SMI#, INIT#) Hold Time)
x
=
Figure 13. Power-On Reset and Configuration Timing Waveform
BLCK
VCC
PWRGOOD
T
a
T
b
RESET#
Ta = T37 (PWRGOOD Inactive Pluse Width)
Tb = T36 (PWRGOOD to RESET# de-assertion time)
Datasheet
41
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 14. TAP Valid Delay Timing Waveform
V
TCK
Tx
Ts
Th
Signal
V Valid
Tx = T63 (Valid Time)
Ts = T61 (Setup Time)
Th = T62 (Hold Time)
V = 0.5 * Vcc
Figure 15. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform
V
T
q
T64 (TRST# Pulse Width), V=0.5*Vcc
T38 (PROCHOT# Pulse Width), V=GTLREF
T
=
q
Figure 16. THERMTRIP# to V Timing
CC
THERMTRIP# Power Down Sequence
T39
THERMTRIP#
Vcc
T39 < 0.5 seconds
Note: THERMTRIP# is undefined when RESET is active
42
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 17. SMBus Timing Waveform
t
t
F
t
HD;STA
R
t
LOW
Clk
t
t
SU;STO
t
t
t
HIGH
t
HD;STA
SU;STA
HD;DAT
SU;DAT
Data
t
BUF
S
S
P
P
STOP
START
START
STOP
t
t
t
t
t
t
t
t
t
=
=
=
=
T80
T78
T79
T77
= T73
=T81
=T82
LOW
HD;STA
HD;DAT
BUF
SU;STA
SU;STD
t
HIGH = T72
R
F
=
T74
= T75
SU;DAT
Figure 18. SMBus Valid Delay Timing Waveform
SM_CLK
TAA
DATA VALID
SM_DAT
DATA OUTPUT
TAA = T76
Datasheet
43
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 19. Example 3.3 VDC/SM_V Sequencing
CC
Power Up
T0=95% 3.3 volt level
3.3 VDC/SM_VCC
OUTEN
PWR_OK /
> T0 + 100ms
VID_OUT
T0 + 10mS
VRM
PWRGD
> 10ms
Processor
PWRGOOD
Processor
RESET
1ms<T36<10ms
VID[4:0]
PWRGD
VRM
PWRGOOD
OUTEN
Processor
SM_VCC
PWR_OK
Power
Supply
3.3 VDC
95% 3.3 volt level
Power Down
3.3 VDC/SM_VCC
PWROK
OUTEN
Power Down Warning > 1ms
44
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
3.0
Front Side Bus Signal Quality Specifications
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation. All specifications are made at the processor core (pad measurements).
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can degrade timing due to the build up of inter-symbol interference (ISI) effects. For
these reasons, it is crucial that the designer assure acceptable signal quality across all systematic
variations encountered in volume manufacturing.
Specifications for signal quality are for measurements at the processor core only and are only
observable through simulation. The same is true for all front side bus AC timing specifications in
Section 2.13. Therefore, proper simulation of the processor front side bus is the only means to
verify proper timing and signal quality metrics.
3.1
Front Side Bus Clock (BCLK) Signal Quality Specifications
and Measurement Guidelines
Table 21 describes the signal quality specifications at the processor pads for the processor front
side bus clock (BCLK) signals. Figure 20 describes the signal quality waveform for the front side
bus clock at the processor pads.
Table 21. BCLK Signal Quality Specifications
Parameter
Min
N/A
N/A
0.20
N/A
Max
0.30
0.30
N/A
Unit
V
Figure
20
Notes
BCLK[1:0] Overshoot
BCLK[1:0] Undershoot
BCLK[1:0] Ringback Margin
BCLK[1:0] Threshold Region
1
1
V
20
V
20
1
0.10
V
20
1, 2
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Datasheet
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Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 20. BCLK[1:0] Signal Integrity Waveform
Overshoot
VH
BCLK1
Rising Edge
Ringback
Crossing
Voltage
Crossing
Voltage
Ringback
Margin
Threshold
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
3.2
Front Side Bus Signal Quality Specifications and
Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the appropriate platform design guidelines.
Table 22 provides the signal quality specifications for all processor signals for use in simulating
signal quality at the processor pads.
Maximum allowable overshoot and undershoot specifications for a given duration of time are
detailed in Table 24 through Table 27. Figure 21 shows the front side bus ringback tolerance for
low-to-high transitions and Figure 22 shows ringback tolerance for high-to-low transitions.
Table 22. Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers
Maximum Ringback
(with Input Diodes Present)
Notes
Signal Group
Transition
Unit
Figure
AGTL+, Asynch GTL+
AGTL+, Asynch GTL+
L → H
H → L
GTLREF + 0.100*GTLREF
GTLREF - 0.100*GTLREF
V
V
21
22
1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0 V/nS at the receiver.
4. All values specified by design characterization.
5. Please see Section 3.0 for maximum allowable overshoot.
6. Ringback between GTLREF + 100 mV and GTLREF - 100 mV is not supported.
7. Intel recommends simulations not exceed a ringback value of GTLREF ± 200 mV to allow margin for other
sources of system noise
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Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 23. Ringback Specifications for TAP Buffers
Maximum Ringback
Transition (with Input Diodes Present)
Signal
Group
Threshold
Notes
Unit
Figure
TAP and
PWRGOO
D
L → H
H → L
VT+(max) TO VT-(max)
VT+(max)
V
23
1, 2, 3, 4, 5
1, 2, 3, 4, 5
TAP and
PWRGOO
D
VT-(min) TO VT+(min)
VT-(min)
V
24
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0 V/nS.
4. All values specified by design characterization.
5. Please see section 3.3 for maximum allowable overshoot.
Figure 21. Low-to-High Front Side Bus Receiver Ringback Tolerance for AGTL+ and
Asynchronous GTL+ Buffers
VCC
Noise Margin
+10% Vcc
GTLREF
-10% Vcc
VSS
Datasheet
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Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 22. High-to-Low Front Side Bus Receiver Ringback Tolerance for AGTL+ and
Asynchronous GTL+ Buffers
VCC
+10% Vcc
GTLREF
-10% Vcc
Noise Margin
VSS
Figure 23. Low-to-High Front Side Bus Receiver Ringback Tolerance for PWRGOOD TAP
Buffers
Vcc
Threshold Region to switch
receiver to a logic 1.
Vt+ (max)
Vt+ (min)
0.5 * Vcc
Vt- (max)
Allowable Ringback
Vss
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Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 24. High-to-Low Front Side Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers
Vcc
Allowable Ringback
Vt+ (min)
0.5 * Vcc
Vt- (max)
Vt- (min)
Threshold Region to switch
receiver to a logic 0.
Vss
Datasheet
49
Intel® Xeon™ Processor with 512 KB L2 Cache
3.3
Front Side Bus Signal Quality Specifications and
Measurement Guidelines
3.3.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS. The
overshoot/undershoot specifications limit transitions beyond VCC or VSS due to the fast signal edge
rates. The processor can be damaged by single and/or repeated overshoot or undershoot events on
any input, output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great
enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the
magnitude, the pulse direction, and the activity factor (AF). Permanent damage to the processor is
the likely result of excessive overshoot/undershoot.
When performing simulations to determine impact of overshoot and undershoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel’s signal integrity models do
not clamp undershoot or overshoot and will yield correct simulation results. If other signal integrity
models are being used to characterize the processor front side bus, care must be taken to ensure that
ESD models do not clamp extreme voltage levels. Intel’s signal integrity models also contain I/O
capacitance characterization. Therefore, removing the ESD diodes from a signal integrity model
will impact results and may yield excessive overshoot/undershoot.
3.3.2
Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference
level (VSS). It is important to note that overshoot and undershoot conditions are separate and their
impact must be determined independently.
Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed
in Table 24 through Table 27. These specifications must not be violated at any time regardless of
bus activity or system state. Within these specifications are threshold levels that define different
allowed pulse duration. Provided that the magnitude of the overshoot/undershoot is within the
absolute maximum specifications, the pulse magnitude, duration and activity factor must all be
used to determine if the overshoot/undershoot pulse is within specifications.
3.3.3
Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/
undershoot reference voltage (VCC). The total time could encompass several oscillations above the
reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot
event may need to be measured to determine the total pulse duration.
Note 1: Oscillations below the reference voltage can not be subtracted from the total overshoot/
undershoot pulse duration.
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Intel® Xeon™ Processor with 512 KB L2 Cache
3.3.4
Activity Factor
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of any common clock signal is every other clock, an
AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock
cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs
one time in every 200 clock cycles.
For source synchronous signals (address, data, and associated strobes), the activity factor is in
reference to the strobe edge. The highest frequency of assertion of any source synchronous signal is
every active edge of its associated strobe. So, an AF = 1 indicates that the specific overshoot (or
undershoot) waveform occurs every strobe cycle.
The specifications provided in Table 24 through Table 27 show the maximum pulse duration
allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is
independent of all others, meaning that the pulse duration reflects the existence of overshoot/
undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just
meets the pulse duration for a specific magnitude where the AF < 1, means that there can be no
other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event
occurs at all times and no other events can occur).
NOTE:
1. Activity factor for common clock AGTL+ signals is referenced to BCLK[1:0] frequency.
2. Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#.
3. Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]#and DSTBN[3:0]#.
3.3.5
Reading Overshoot/Undershoot Specification Tables
The processor overshoot/undershoot specification is not a simple single value. Instead, many
factors are needed to determine what the overshoot/undershoot specification is. In addition to the
magnitude of the overshoot, the following parameters must also be known: the width of the
overshoot and the activity factor (AF). To determine the allowed overshoot for a particular
overshoot event, the following must be done:
1. Determine the signal group that particular signal falls into. For AGTL+ signals operating in
the 4X source synchronous domain, Table 24 should be used. For AGTL+ signals operating in
the 2X source synchronous domain, Table 25 should be used. If the signal is an AGTL+ signal
operating in the common clock domain, Table 26 should be used. Finally, for all other signals
residing in the 33 MHz domain (asynchronous GTL+, TAP, etc.), Table 27 should be used.
2. Determine the magnitude of the overshoot or the undershoot (relative to VSS).
3. Determine the activity factor (how often does this overshoot occurs).
4. Next, from the appropriate specification table, determine the maximum pulse duration (in
nanoseconds) allowed.
5. Compare the specified maximum pulse duration to the signal being measured. If the pulse
duration measured is less than the pulse duration shown in the table, then the signal meets the
specifications.
Undershoot events must be analyzed separately from overshoot events as they are mutually
exclusive.
Datasheet
51
Intel® Xeon™ Processor with 512 KB L2 Cache
3.3.6
Determining if a System Meets the Overshoot/Undershoot
Specifications
The overshoot/undershoot specifications listed in the following tables specify the allowable
overshoot/undershoot for a single overshoot/undershoot event. However most systems will have
multiple overshoot and/or undershoot events that each have their own set of parameters (duration,
AF and magnitude). While each overshoot on its own may meet the overshoot specification, when
the total impact of all overshoot events are considered, the system may fail. A guideline to ensure a
system passes the overshoot and undershoot specifications is shown below:
•
•
Ensure that no signal ever exceeds VCC or -0.25 V OR
If only one overshoot/undershoot event magnitude occurs, ensure it meets the overshoot/
undershoot specifications in the following tables OR
•
If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse
duration for each magnitude and compare the results against the AF = 1 specifications. If all of
these worst case overshoot or undershoot events meet the specifications (measured time <
specifications) in the table (where AF=1), then the system passes.
The following notes apply to Table 24 through Table 27:
•
•
Absolute Maximum Overshoot magnitude of 1.8V must never be exceeded.
Absolute Maximum Overshoot is measured referenced to VSS, Pulse Duration of overshoot is
measured relative to VCC
.
•
•
•
•
•
Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS
Ringback below VCC cannot be subtracted from overshoots/undershoots.
Lesser undershoot does not allocate longer or larger overshoot.
.
System designers are strongly encouraged to follow Intel’s layout guidelines.
All values specified by design characterization.
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Intel® Xeon™ Processor with 512 KB L2 Cache
Table 24. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot
Tolerance
Absolute
Maximum
Overshoot (V)
Absolute
Maximum
Undershoot (V)
Pulse Duration
(ns) AF = 1
Pulse Duration
(ns) AF = 0.1
Pulse Duration
(ns) AF = 0.01
1.80
1.75
1.70
1.65
1.60
1.55
- 0.320
- 0.270
- 0.220
- 0.170
- 0.120
- 0.070
0.01
0.03
0.09
0.25
0.76
2.54
0.15
0.45
1.28
3.71
5.00
5.00
1.58
4.60
5.00
5.00
5.00
5.00
NOTES:
1. These specifications are measured at the processor pad.
2. Assumes a BCLK period of 10 nS.
3. AF is referenced to associated source synchronous strobes.
Table 25. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot
Tolerance
Absolute
Maximum
Overshoot (V)
Absolute
Maximum
Undershoot (V)
Pulse Duration
(ns) AF = 1
Pulse Duration
(ns) AF = 0.1
Pulse Duration
(ns) AF = 0.01
1.80
1.75
1.70
1.65
1.60
1.55
- 0.320
- 0.270
- 0.220
- 0.170
- 0.120
- 0.07
0.03
0.06
0.18
0.51
1.52
5.08
0.29
0.62
2.88
6.25
1.75
10.00
10.00
10.00
10.00
5.06
10.00
10.00
NOTES:
1. These specifications are measured at the processor pad.
2. Assumes a BCLK period of 10 ns.
3. AF is referenced to associated source synchronous strobes.
Datasheet
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Intel® Xeon™ Processor with 512 KB L2 Cache
Table 26. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Pulse
Pulse
Duration (ns) Duration (ns) Duration (ns)
AF = 1
AF = 0.1
AF = 0.01
1.80
1.75
1.70
1.65
1.60
1.55
- 0.320
- 0.270
- 0.220
- 0.170
- 0.120
- 0.07
0.06
0.12
0.35
1.01
3.04
10.16
0.58
1.25
5.77
12.49
20.00
20.00
20.00
20.00
3.50
10.12
20.00
20.00
NOTES:
1. These specifications are measured at the processor pad.
2. BCLK period is 10 nS.
3. WIRED OR processor signals can tolerate upto 1 V of overshoot/undershoot.
4. AF is referenced to BCLK[1:0].
Table 27. Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot/Undershoot
Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse
Pulse
Pulse
Duration (ns) Duration (ns) Duration (ns)
AF = 1
AF = 0.1
AF = 0.01
1.80
1.75
1.70
1.65
1.60
1.55
- 0.320
- 0.270
- 0.220
- 0.170
- 0.120
- 0.07
0.17
0.37
1.05
3.04
9.13
30.48
1.73
3.75
17.30
37.48
60.00
60.00
60.00
60.00
10.51
30.37
60.00
60.00
NOTES:
1. These specifications are measured at the processor pad.
2. These signals are assumed in a 33 MHz time domain.
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Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 25. Maximum Acceptable Overshoot/Undershoot Waveform
Maximum
Absolute
Overshoot
Time-dependent
Overshoot
VMAX
VCC
GTLREF
VOL
VSS
VMIN
Time-dependent
Undershoot
Maximum
Absolute
Undershoot
000588
Datasheet
55
Intel® Xeon™ Processor with 512 KB L2 Cache
56
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
4.0
Mechanical Specifications
The Intel® Xeon™ processor with 512 KB L2 cache uses Interposer Micro Pin Grid Array (INT-
mPGA) package technology. Components of the package include a flip-chip ball grid array (FC-
BGA) package containing the processor die covered by an integrated heat spreader (IHS) mounted
to a pinned FR4 interposer. Mechanical specifications for the processor are given in this section.
See Section 1.1 for terminology definitions. Figure 26 provides a basic assembly drawing and
includes the components which make up the entire processor. In addition to the package
components, several components are located on the FR4 interposer, including an EEPROM and a
thermal sensor. Package dimensions are provided in Table 28.
The Intel® Xeon™ processor with 512 KB L2 cache utilizes a surface mount 603-pin zero-
insertion force (ZIF) socket for installation into the baseboard. See the 603-Pin Socket Design
Guidelines for further details on the processor socket.
For Figure 28 through Figure 32, the following notes apply:
1. Unless otherwise specified, the following drawings are dimensioned in millimeters.
2. All dimensions are not tested, but are guaranteed by design characterization.
3. Figures and drawings labelled as “Reference Dimensions” are provided for informational
purposes only. Reference Dimensions are extracted from the mechanical design database and
are nominal dimensions with no tolerance information applied. Reference Dimensions are
NOT checked as part of the processor manufacturing process. Unless noted as such,
dimensions in parentheses without tolerances are Reference Dimensions.
4. Drawings are not to scale.
Figure 26.
INT-mPGA Processor Package Assembly Drawing (Includes Socket)
1
2
5
6
3
7
4
8
9
Note: This drawing is not to scale and is for reference only. The 603-pin socket is supplied as a
reference only.
1. Integrated Heat Spreader (IHS)
2. Thermal Interface Material (TIM) between processor die and IHS
3. Processor die
4. Flip Chip interconnect
5. FCBGA (Flip Chip Ball Grid Array) package
6. FCBGA solder joints
7. Processor interposer
8. 603-pin socket
9. 603-pin socket solder joints
Datasheet
57
Intel® Xeon™ Processor with 512 KB L2 Cache
4.1
Mechanical Specifications
Figure 27.
INT-mPGA Processor Package Top View: Component Placement Detail
Pin A1
CPU
58
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 28.
INT-mPGA Processor Package Drawing
Table 28. INT-mPGA Processor Package Dimensions
Symbol
Milimeters
Nominal
53.34
35.00
31.00
2.00
Notes
Min
53.19
34.90
30.90
1.37
9.02
4.55
18.82
13.74
Max
53.49
35.10
31.10
2.64
9.32
5.45
19.28
14.20
A
B
C
D
E
G
H
J
K
L
M
N
9.17
5.00
19.05
13.97
1.27
18.09
14.63
19.36
0.31
Nominal
17.83
14.50
19.10
0.28
18.34
14.76
19.61
0.36
P
Pin Diameter
φ
Pin Tp
0.25
Figure 29 details the keep-in zone for components mounted to the top side of the processor
interposer. The components include the EEPROM, thermal sensor, resistors and capacitors.
Datasheet
59
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 29.
INT-mPGA Processor Package Top View: Component Height Keep-in
Figure 30 details the keep-in specification for pin-side components. The processor may contain pin
side capacitors mounted to the processor package. These capacitors will be exposed within the
opening of the interposer cavity.
Figure 30.
INT-mPGA Processor Package Cross Section View: Pin Side Component Keep-in
IHS
FCBGA
Interposer
1.270mm
Component
Keepin
13.411mm
Component Keepin
Socket must allow clearance
for pin shoulders and mate
flush with this surface
60
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 31.
INT-mPGA Processor Package: Pin Detail
1. Kovar pin with plating of 0.2 micrometers Au over 2.0 micrometer Ni.
2. 0.254 Diametric true position, pin to pin.
Datasheet
61
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 32 details the flatness and tilt specifications for the IHS of the Intel Xeon processor,
respectively. Tilt is measured with the reference datum set to the bottom of the processor
interposer.
Figure 32.
IHS Flatness and Tilt Drawing
4.2
Processor Package Load Specifications
Table 29 provides dynamic and static load specifications for the processor IHS. These mechanical
load limits should not be exceeded during heat sink assembly, mechanical stress testing, or
standard drop and shipping conditions. The heat sink attach solutions must not induce continuous
stress onto the processor with the exception of a uniform load to maintain the heat sink-to-
processor thermal interface. It is not recommended to use any portion of the processor interposer as
a mechanical reference or load bearing surface for thermal solutions.
Table 29. Package Dynamic and Static Load Specifications
Parameter
Max
Unit
Unit
Static
50
lbf
1, 2, 3
50 + 1 lb * 50G input * 1.8 (AF)
= 140
Dynamic
lbf
1, 2, 4, 5
NOTES:
1. This specification applies to a uniform compressed load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface.
3. These parameters are based on design characterization and not tested.
4. Dynamic loading specifications are defined assuming a maximum duration of 11ms.
5. The heatsink weight is assumed to be one pound. Shock input to the system during shock testing is assumed
to be 50 G’s. AF is the amplification factor.
62
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
4.3
4.4
Insertion Specifications
The processor can be inserted and removed 15 times from a 603-pin socket meeting the 603-Pin
Socket Design Guidelines document. Note that this specification is based on design
characterization and is not tested.
Mass Specifications
Table 30 specifies the processors mass. This includes all components which make up the entire
processor product.
Table 30. Processor Mass
Processor
Mass (grams)
Intel® Xeon™ processor with 512 KB L2 cache
25
4.5
Materials
The processor is assembled from several components. The basic material properties are described
in Table 31.
Table 31. Processor Material Properties
Component
Material
Integrated Heat Spreader
FC-BGA
Nickel plated copper
BT Resin
Interposer
FR4
Interposer pins
Kovar with Gold over nickel
Datasheet
63
Intel® Xeon™ Processor with 512 KB L2 Cache
4.6
Markings
The following section details the processor top-side laser markings. It is provided to aid in the
identification of the processor.
Figure 33.
Processor Top-Side Markings
INTEL CONFIDENTIAL
i m c ‘00
{ATPO}
NOTE:
1. Character size for laser markings is: height 0.050" (1.27mm), width 0.032" (0.81mm).
2. All characters will be in upper case.
Figure 34.
Processor Bottom-Side Markings
64
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
4.7
Pin-Out Diagram
This section provides two view of the processor pin grid. Figure 35 and Figure 36 detail
the coordinates of the processor pins.
Figure 35.
Processor Pin Out Diagram: Top View
COMMON
CLOCK
COMMON
CLOCK
Async /
ADDRESS
JTAG
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
A
B
A
B
C
D
C
D
E
E
F
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
T
T
U
V
U
V
W
Y
W
Y
AA
AA
AB
AC
AD
AB
AC
AD
AE
AE
2
4
6
8
10
12
14
16
18
20
22
24
26
28
CLOCKS
DATA
SMBus
= Signal
= Power
= Ground
= SM_VCC
= GTLREF
= Reserved
Datasheet
65
Intel® Xeon™ Processor with 512 KB L2 Cache
Figure 36.
Processor Pin Out Diagram: Bottom View
Async /
JTAG
COMMON
CLOCK
COMMON
CLOCK
ADDRESS
31
29
27
25 23 21
19 17 15
13 11
9
7
5
3
1
A
B
A
B
C
C
D
D
E
E
F
F
G
G
H
J
H
J
K
L
K
L
M
N
P
R
M
N
P
R
T
T
U
V
W
U
V
W
Y
Y
AA
AA
AB
AC
AB
AC
AD
AD
AE
AE
28 26 24
22 20
18 16
14 12 10
= SM_VCC
8
6
4
2
SMBus
DATA
CLOCKS
= Signal
= Power
= Ground
= GTLREF
= Reserved
66
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
5.0
Pin Listing and Signal Definitions
5.1
Processor Pin Assignments
Section 2.8 contains the front side bus signal groups in Table 4 for the Intel® Xeon™ processor with
512 KB L2 cache. This section provides a sorted pin list in Table 38 and Table 39. Table 38 is a
listing of all processor pins ordered alphabetically by pin name. Table 39 is a listing of all processor
pins ordered by pin number.
5.1.1
Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name
Signal
Buffer Type
Table 38. Pin Listing by Pin Name
Pin Name
Pin No.
Direction
Signal
Buffer Type
Pin Name
Pin No.
Direction
A28#
A29#
E13
D12
C11
B7
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Async GTL+
Common Clk
Source Sync
Source Sync
Common Clk
Common Clk
Sys Bus Clk
Sys Bus Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
A3#
A4#
A22
A20
B18
C18
A19
C17
D17
A13
B16
B14
B13
A12
C15
C14
D16
D15
F15
A10
B10
B11
C12
E14
D13
A9
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
A30#
A31#
A5#
A32#
A6
A6#
A33#
A7
A7#
A34#
C9
A8#
A35#
C8
A9#
A20M#
ADS#
F27
D19
F17
F14
E10
D9
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
ADSTB0#
ADSTB1#
AP0#
AP1#
BCLK0
BCLK1
BINIT#
BNR#
Y4
W5
F11
F20
F6
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
BR0#
F8
E7
F5
E8
E4
D23
D20
Input/Output
B8
Source Sync Input/Output
Datasheet
67
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 38. Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
Common Clk
Common Clk
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
BR1#
BR2# 1
BR3# 1
BSEL0
BSEL1
COMP0
COMP1
D0#
F12
E11
Input
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBSY#
DEFER#
DBI0#
DBI1#
DBI2#
DBI3#
DP0#
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11
AE9
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
D10
Input
AA3
Output2
AB3
Output2
AD16
E16
Input
Input
Y26
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
D1#
AA27
Y24
D2#
D3#
AA25
AD27
Y23
D4#
D5#
D6#
AA24
AB26
AB25
AB23
AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD19
AB17
AD10
AD8
D7#
D8#
AC9
D9#
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10
AC8
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
AD7
AE7
AC6
AC5
AA8
Y9
AB6
F18
C23
AC27
AD22
AE12
AB9
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
AC18
68
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Tabl1e 38. Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
Common Clk
Common Clk
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Async GTL+
Async GTL+
Async GTL+
Async GTL+
Async GTL+
Common Clk
Common Clk
Power/Other
Async GTL+
Async GTL+
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Power/Other
Async GTL+
SMBus
DP1#
DP2#
AE19
AC15
AE17
E18
Y21
Y18
Y15
Y12
Y20
Y17
Y14
Y11
E27
W23
W9
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RESET#
RS0#
B1
C5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Input
DP3#
D25
W3
DRDY#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FERR#
Y3
Y27
Y28
AC1
AD1
AE4
AE15
AE16
Y8
GTLREF
GTLREF
GTLREF
GTLREF
HIT#
Input
E21
D22
F21
C6
Input
Input
RS1#
Input
F23
F9
Input
RS2#
Input
Input
RSP#
Input
E22
A23
E5
Input/Output
Input/Output
Output
SKTOCC#
SLP#
A3
Output
HITM#
AE6
AD28
AC28
AC29
AA29
AB29
AB28
AA28
Y29
AE28
AE29
AD29
C27
D4
Input
IERR#
SM_ALERT#
SM_CLK
SM_DAT
SM_EP_A0
SM_EP_A1
SM_EP_A2
SM_TS1_A0
SM_TS1_A1
SM_VCC
SM_VCC
SM_WP
SMI#
Output
SMBus
IGNNE#
INIT#
C26
D6
Input
Input
SMBus
Input
Input/Output
Input
SMBus
LINT0
B24
G23
A17
D7
Input
SMBus
LINT1
Input
Input
SMBus
LOCK#
Input/Output
Input/Output
Input
Input
SMBus
MCERR#
ODTEN
PROCHOT#
PWRGOOD
REQ0#
Input
SMBus
B5
Input
Power/Other
Power/Other
SMBus
B25
AB7
B19
B21
C21
C20
B22
A1
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Reserved
Reserved
Reserved
Reserved
Reserved
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Async GTL+
Async GTL+
TAP
REQ1#
REQ2#
STPCLK#
TCK
REQ3#
E24
C24
E25
W6
TAP
REQ4#
TDI
TAP
Reserved
Reserved
Reserved
Reserved
Reserved
TDO
Reserved
Power/Other
Power/Other
Power/Other
Power/Other
A4
TESTHI0
TESTHI1
TESTHI2
TESTHI3
Reserved
A15
A16
A26
W7
Reserved
W8
Reserved
Y6
Datasheet
69
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 38. Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
Power/Other
Power/Other
Power/Other
Async GTL+
TAP
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TESTHI4
TESTHI5
TESTHI6
THERMTRIP#
TMS
AA7
AD5
AE5
F26
A25
E19
F24
A2
Input
Input
Input
Output
Input
Input
Input
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E26
E28
E30
F1
F4
Common Clk
TAP
TRDY#
TRST#
VCC
F10
F16
F22
F29
F31
G2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
A8
VCC
A14
A18
A24
A28
A30
B4
VCC
VCC
G4
VCC
G6
VCC
G8
VCC
G24
G26
G28
G30
H1
VCC
B6
VCC
B12
B20
B26
B29
B31
C2
VCC
VCC
VCC
H3
VCC
H5
VCC
H7
VCC
C4
H9
VCC
C10
C16
C22
C28
C30
D1
H23
H25
H27
H29
H31
J2
VCC
VCC
VCC
VCC
VCC
VCC
D8
J4
VCC
D14
D18
D24
D29
D31
E2
J6
VCC
J8
VCC
J24
J26
J28
J30
K1
VCC
VCC
VCC
VCC
E6
VCC
E12
E20
K3
VCC
K5
70
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 38. Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
K7
K9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
P24
P26
P28
P30
R1
K23
K25
K27
K29
K31
L2
R3
R5
R7
L4
R9
L6
R23
R25
R27
R29
R31
T2
L8
L24
L26
L28
L30
M1
M3
M5
M7
M9
M23
M25
M27
M29
M31
N1
T4
T6
T8
T24
T26
T28
T30
U1
U3
U5
U7
N3
U9
N5
U23
U25
U27
U29
U31
V2
N7
N9
N23
N25
N27
N29
N31
P2
V4
V6
V8
P4
V24
V26
V28
P6
P8
Datasheet
71
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 38. Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V30
W1
VCC
VCC
VCCA
VCCIOPLL
VCCSENSE
VID0
VID1
VID2
VID3
VID4
VSS
AE18
AE24
AB4
AD4
B27
F3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
W25
W27
W29
W31
Y10
Input
Input
Power/Other
Power/Other
Output
Output
Output
Output
Output
Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
E3
Y16
D3
Y2
C3
Y22
B3
Y30
A5
AA1
VSS
A11
A21
A27
A29
A31
B2
AA4
VSS
AA6
VSS
AA12
AA20
AA26
AA31
AB2
VSS
VSS
VSS
VSS
B9
VSS
B15
B17
B23
B28
B30
C1
AB8
VSS
AB14
AB18
AB24
AB30
AC3
VSS
VSS
VSS
VSS
VSS
C7
AC4
VSS
C13
C19
C25
C29
C31
D2
AC10
AC16
AC22
AC31
AD2
VSS
VSS
VSS
VSS
VSS
AD6
VSS
D5
AD12
AD20
AD26
AD30
AE3
VSS
D11
D21
D27
D28
D30
E1
VSS
VSS
VSS
VSS
AE8
VSS
AE14
VSS
E9
72
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 38. Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E15
E17
E23
E29
E31
F2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K2
K4
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
K6
K8
K24
K26
K28
K30
L1
F7
F13
F19
F25
F28
F30
G1
L3
L5
L7
L9
G3
L23
L25
L27
L29
L31
M2
M4
M6
M8
M24
M26
M28
M30
N2
G5
G7
G9
G25
G27
G29
G31
H2
H4
H6
H8
H24
H26
H28
H30
J1
N4
N6
N8
J3
N24
N26
N28
N30
P1
J5
J7
J9
J23
J25
J27
J29
J31
P3
P5
P7
P9
Datasheet
73
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 38. Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P23
P25
P27
P29
P31
R2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V29
V31
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
W2
W4
W24
W26
W28
W30
Y1
R4
R6
R8
R24
R26
R28
R30
T1
Y5
Y7
Y13
Y19
Y25
T3
Y31
T5
AA2
AA9
AA15
AA17
AA23
AA30
AB1
AB5
AB11
AB21
AB27
AB31
AC2
AC7
AC13
AC19
AC25
AC30
AD3
AD9
AD15
AD17
AD23
AD31
T7
T9
T23
T25
T27
T29
T31
U2
U4
U6
U8
U24
U26
U28
U30
V1
V3
V5
V7
V9
V23
V25
V27
74
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 38. Pin Listing by Pin Name
Table 38. Pin Listing by Pin Name
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VSS
VSS
VSS
VSS
VSSA
AE2
AE11
AE21
AE27
AA5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSSSENSE
D26
Power/Other
Output
1. These are “Reserved” pins on the Intel Xeon processor. In
systems utilizing the Intel Xeon processor, the system
designer must terminate these signals to the processor VCC
2. Baseboard treating AA3 and AB3 as Reserved will operate
correctly with a bus clock of 100 MHz.
.
Input
Datasheet
75
Intel® Xeon™ Processor with 512 KB L2 Cache
5.1.2
Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number
Signal
Buffer Type
Pin No.
Pin Name
Direction
Signal
Buffer Type
Pin No.
Pin Name
Direction
B2
B3
VSS
VID4
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Input
A1
A2
Reserved
VCC
Reserved
Power/Other
Power/Other
Reserved
Reserved
B4
B5
OTDEN
VCC
A3
SKTOCC#
Reserved
VSS
Output
B6
A4
Reserved
B7
A31#
A27#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A5
Power/Other
B8
A6
A32#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
B9
A7
A33#
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
C1
A21#
A22#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A8
VCC
A9
A26#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
B1
A20#
A13#
A12#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
A14#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A10#
A11#
VSS
Source Sync Input/Output
Power/Other
VCC
Reserved
Reserved
LOCK#
VCC
Reserved
Reserved
Reserved
Reserved
A5#
Source Sync Input/Output
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Async GTL+
REQ0#
VCC
Input/Output
Common Clk
Power/Other
Input/Output
REQ1#
REQ4#
VSS
Input/Output
Input/Output
A7#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A4#
VSS
LINT0
Input
A3#
Source Sync Input/Output
PROCHOT# Power/Other
VCC Power/Other
VCCSENSE Power/Other
Output
HITM#
VCC
Common Clk
Power/Other
TAP
Input/Output
Output
TMS
Input
VSS
VCC
VSS
VCC
VSS
VCC
VID3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
VSS
Reserved
Reserved
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
VCC
VSS
VCC
C2
VSS
C3
Output
Reserved
Reserved
76
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 39. Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
C4
C5
VCC
Reserved
RSP#
VSS
Power/Other
Reserved
D12
D13
D14
D15
D16
D17
D18
A29#
A25#
VCC
A18#
A17#
A9#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Reserved
Input
C6
Common Clk
Power/Other
C7
Source Sync Input/Output
Source Sync Input/Output
Source Sync Input/Output
Power/Other
C8
A35#
A34#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
D1
VCC
A30#
A23#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Common
Input/Output
Clk
D19
D20
ADS#
BR0#
Common
Input/Output
Clk
A16#
A15#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
E1
VSS
RS1#
Power/Other
Common Clk
Common Clk
Power/Other
Reserved
Input
Input
BPRI#
VCC
A8#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A6#
Reserved
Reserved
Output
VSS
VSSSENSE Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
TAP
REQ3#
REQ2#
VCC
Input/Output
Input/Output
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
VCC
DEFER#
TDI
Input
Input
Input
Input
Input
VSS
VCC
VSS
Power/Other
Async GTL+
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Async GTL+
Power/Other
Async GTL+
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
VSS
IGNNE#
SMI#
VCC
E2
VCC
E3
VID1
Output
Input/Output
Output
E4
BPM5#
IERR#
VCC
VSS
E5
VCC
E6
VSS
E7
BPM2#
BPM4#
VSS
Input/Output
Input/Output
VCC
E8
D2
VSS
E9
D3
VID2
Output
Input
E10
E11
E12
E13
E14
E15
E16
E17
E18
AP0#
BR2# 1
VCC
Input/Output
Input
D4
STPCLK#
VSS
D5
D6
INIT#
MCERR#
VCC
Input
A28#
A24#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D7
Input/Output
D8
D9
AP1#
BR3# 1
VSS
Input/Output
Input
COMP1
VSS
Power/Other
Power/Other
Common Clk
Input
D10
D11
DRDY#
Input/Output
Datasheet
77
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 39. Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
TAP
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
F1
TRDY#
VCC
Input
F27
F28
F29
F30
F31
G1
A20M#
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
LINT1
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
RS0#
HIT#
Input
Input/Output
VSS
TCK
Input
TDO
TAP
Output
G2
VCC
Power/Other
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
G3
FERR#
VCC
Output
G4
G5
VSS
G6
VCC
G7
VSS
G8
VCC
G9
F2
VSS
G23
G24
G25
G26
G27
G28
G29
G30
G31
H1
Input
F3
VID0
Output
F4
VCC
F5
BPM3#
BPM0#
VSS
Input/Output
Input/Output
F6
F7
F8
BPM1#
GTLREF
VCC
Input/Output
Input
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
BINIT#
BR1#
VSS
Input/Output
Input
H2
H3
ADSTB1#
A19#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
H4
H5
VCC
H6
ADSTB0#
DBSY#
VSS
Source Sync Input/Output
H7
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
TAP
Input/Output
H8
H9
BNR#
RS2#
VCC
Input/Output
Input
H23
H24
H25
H26
H27
H28
H29
GTLREF
TRST#
VSS
Input
Input
Power/Other
THERMTRIP
#
F26
Async GTL+
Output
78
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 39. Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
H30
H31
J1
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
L2
L3
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
L4
J2
L5
J3
L6
J4
L7
J5
L8
J6
L9
J7
L23
L24
L25
L26
L27
L28
L29
L30
L31
M1
J8
J9
J23
J24
J25
J26
J27
J28
J29
J30
J31
K1
M2
M3
M4
K2
M5
K3
M6
K4
M7
K5
M8
K6
M9
K7
M23
M24
M25
M26
M27
M28
M29
M30
M31
N1
K8
K9
K23
K24
K25
K26
K27
K28
K29
K30
K31
L1
N2
N3
N4
Datasheet
79
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 39. Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
N5
N6
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
R8
R9
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
N7
R23
R24
R25
R26
R27
R28
R29
R30
R31
T1
N8
N9
N23
N24
N25
N26
N27
N28
N29
N30
N31
P1
T2
T3
T4
P2
T5
P3
T6
P4
T7
P5
T8
P6
T9
P7
T23
T24
T25
T26
T27
T28
T29
T30
T31
U1
P8
P9
P23
P24
P25
P26
P27
P28
P29
P30
P31
R1
U2
U3
U4
R2
U5
R3
U6
R4
U7
R5
U8
R6
U9
R7
U23
80
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 39. Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
U24
U25
U26
U27
U28
U29
U30
U31
V1
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
W27
W28
W29
W30
W31
Y1
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
Y2
VCC
VCC
Y3
Reserved
BCLK0
VSS
Reserved
Input
VSS
Y4
Sys Bus Clk
Power/Other
Power/Other
Power/Other
Common Clk
V2
VCC
Y5
V3
VSS
Y6
TESTHI3
VSS
Input
Input
V4
VCC
Y7
V5
VSS
Y8
RESET#
D62#
V6
VCC
Y9
Source Sync Input/Output
Power/Other
V7
VSS
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
AA1
AA2
AA3
VCC
V8
VCC
DSTBP3#
DSTBN3#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
V9
VSS
V23
V24
V25
V26
V27
V28
V29
V30
V31
W1
W2
W3
W4
W5
W6
W7
W8
W9
W23
W24
W25
W26
VSS
VCC
DSTBP2#
DSTBN2#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
VCC
VSS
DSTBP1#
DSTBN1#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
VSS
VCC
DSTBP0#
DSTBN0#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
VCC
VSS
D5#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Reserved
VSS
Reserved
D2#
Power/Other
Sys Bus Clk
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
BCLK1
TESTHI0
TESTHI1
TESTHI2
GTLREF
GTLREF
VSS
Input
Input
Input
Input
Input
Input
D0#
Source Sync Input/Output
Reserved
Reserved
SM_TS1_A1
VCC
Reserved
Reserved
Reserved
Reserved
Input
SMBus
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VCC
VCC
VSS
VSS
BSEL0
Output2
Datasheet
81
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 39. Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
AA4
AA5
VCC
VSSA
VCC
Power/Other
Power/Other
Power/Other
Power/Other
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AC1
D51#
D52#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Input
Input
AA6
AA7
TESTHI4
D61#
VSS
D37#
D32#
D31#
VCC
Source Sync Input/Output
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AA8
Source Sync Input/Output
Power/Other
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AB1
D54#
D53#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D14#
D12#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D48#
D49#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D13#
D9#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D33#
VSS
Source Sync Input/Output
Power/Other
VCC
D8#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D24#
D15#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D7#
VSS
SM_EP_A2
SM_EP_A1
VCC
SMBus
Input
Input
D11#
D10#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
SMBus
Power/Other
Power/Other
Reserved
VSS
D6#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Reserved
VSS
Reserved
D3#
AC2
Power/Other
Power/Other
Power/Other
VCC
AC3
VCC
D1#
Source Sync Input/Output
AC4
VCC
SM_TS1_A0
SM_EP_A0
VSS
SMBus
Input
Input
AC5
D60#
D59#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
SMBus
AC6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
AC7
VCC
AC8
D56#
D47#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
AC9
AB2
VCC
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AB3
BSEL1
VCCA
VSS
Output2
Input
D43#
D41#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AB4
AB5
AB6
D63#
D50#
DP2#
VCC
Source Sync Input/Output
AB7
PWRGOOD Power/Other
Input
Common Clk
Input/Output
AB8
VCC
DBI3#
D55#
VSS
Power/Other
Power/Other
AB9
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D34#
DP0#
VSS
Source Sync Input/Output
AB10
AB11
Common Clk
Input/Output
Power/Other
82
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 39. Pin Listing by Pin Number
Table 39. Pin Listing by Pin Number
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AD1
D25#
D26#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AD26
AD27
AD28
AD29
AD30
AD31
AE2
VCC
D4#
Power/Other
Source Sync Input/Output
SM_ALERT#
SM_WP
VCC
SMBus
Output
Input
D23#
D20#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
SMBus
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
VSS
D17#
DBI0#
SM_CLK
SM_DAT
VSS
Source Sync Input/Output
Source Sync Input/Output
VSS
AE3
VCC
SMBus
Input
AE4
Reserved
TESTHI6
SLP#
Reserved
Input
SMBus
Output
AE5
Power/Other
Async GTL+
Power/Other
Power/Other
Reserved
AE6
Input
VCC
AE7
D58#
Source Sync Input/Output
Power/Other
Reserved
VCC
Reserved
AE8
VCC
AD2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AE9
D44#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AD3
VSS
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
D42#
AD4
VCCIOPLL
TESTHI5
VCC
Input
Input
VSS
AD5
DBI2#
D35#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AD6
AD7
D57#
D46#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
AD8
Reserved
Reserved
DP3#
Reserved
Reserved
Reserved
Reserved
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
D45#
D40#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Common Clk
Power/Other
Common Clk
Input/Output
VCC
DP1#
Input/Output
D38#
D39#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D28#
Source Sync Input/Output
Power/Other
VSS
D27#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
COMP0
VSS
Power/Other
Power/Other
Input
D22#
VCC
D36#
D30#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D19#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D16#
VSS
D29#
DBI1#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
SM_VCC
SM_VCC
Power/Other
Power/Other
1. These are “Reserved” pins on the Intel Xeon processor. In
systems utilizing the Intel Xeon processor, the system
designer must terminate these signals to the processor VCC
2. Baseboards treating AA3 and AB3 as Reserved will operate
correctly with a bus clock of 100 MHz.
D21#
D18#
Source Sync Input/Output
Source Sync Input/Output
.
Datasheet
83
Intel® Xeon™ Processor with 512 KB L2 Cache
5.2
Signal Definitions
Table 41. Signal Definitions (Page 1 of 10)
Name
Type
Description
Notes
A[35:3]# (Address) define a 236 byte physical memory address space. In sub-phase
1 of the address phase, these pins transmit the address of a transaction. In sub-
phase 2, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the front side bus. A[35:3]# are
protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and
are latched into the receiving buffers by ADSTB[1:0]#.
A[35:3]#
I/O
4
On the active-to-inactive transition of RESET#, the processors sample a subset of
the A[35:3]# pins to determine their power-on configuration. See Section 7.1.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal cache and before driving a read/
write transaction on the bus. Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1 MByte boundary. Assertion of A20M# is only
3
supported in real mode.
A20M#
I
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[35:3]# pins. All bus agents observe the ADS# activation to begin
parity checking, protocol checking, address decode, internal snoop, or deferred
reply ID match operations associated with the new transaction. This signal must
connect the appropriate pins on all front side bus agents.
ADS#
I/O
I/O
4
4
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling
edge.
ADSTB[1:0]#
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,
A[35:3]#, and the transaction type on the REQ[4:0]# pins. A correct parity signal is
high if an even number of covered signals are low and low if an odd number of
covered signals are low. This allows parity to be high when all the covered signals
are high. AP[1:0]# should connect the appropriate pins of all front side bus agents.
The following table defines the coverage model of these signals.
AP[1:0]#
I/O
4
Request Signals
Subphase 1
Subphase 2
A[35:24]#
A[23:3]#
AP0#
AP1#
AP1#
AP1#
AP0#
AP0#
REQ[4:0]#
The differential pair BCLK (Bus Clock) determines the bus frequency. All processor
front side bus agents must receive these signals to drive their outputs and latch
their inputs.
4
BCLK[1:0]
I
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing the falling edge of BCLK1.
84
Datasheet
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 41. Signal Definitions (Page 2 of 10)
Name
Type
Description
Notes
BINIT# (Bus Initialization) may be observed and driven by all processor front side
bus agents and if used, must connect the appropriate pins of all such agents. If the
BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal
any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration (see Section 7.1)
and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity
and bus request arbitration state machines. The bus agents do not reset their IOQ
and transaction tracking state machines upon observation of BINIT# assertion.
Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for
the front side bus and attempt completion of their bus queue and IOQ entries.
BINIT#
I/O
4
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling architecture
of the system.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all processor front side
bus agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
BNR#
I/O
4
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[5:0]#
should connect the appropriate pins of all front side bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a
processor output used by debug tools to determine processor debug readiness.
BPM[5:0]#
I/O
3
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is
used by debug tools to request debug operation of the processors.
BPM[5:4]# must be bussed to all bus agents.
These signals do not have on-die termination and must be terminated at the
end agent. See the appropriate platform design guidelines for additional
information.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
front side bus. It must connect the appropriate pins of all processor front side bus
agents. Observing BPRI# active (as asserted by the priority agent) causes all other
agents to stop issuing new requests, unless such requests are part of an ongoing
locked operation. The priority agent keeps BPRI# asserted until all of its requests
are completed, then releases the bus by deasserting BPRI#.
BPRI#
I
4
Datasheet
85
Intel® Xeon™ Processor with 512 KB L2 Cache
Table 41. Signal Definitions (Page 3 of 10)
Name
Type
Description
Notes
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual processor
pins. BR2# and BR3# must not be utilized in a dual processor platform design. The
table below gives the rotating interconnect between the processor and bus signals
for dual processor systems.
BR[1:0]# Signals Rotating Interconnect, dual processor system
Bus Signal Agent 0 Pins Agent 1 Pins
BREQ0#
BREQ1#
BR0#
BR1#
BR1#
BR0#
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its agent
ID. All agents then configure their pins to match the appropriate bus signal protoco
as shown below.
BR0#
BR[1:3]#1
I/O
I
1,4
BR[1:0]# Signal Agent IDs
BR[1:0]# Signals Rotating
Agent ID
Interconnect, dual processor system
BR0#
BR1#
0
1
During power-on configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition
of RESET#. The pin which the agent samples asserted determines it’s agent ID.
These signals do not have on-die termination and must be terminated at the
end agent. See the appropriate platform design guidelines for additional
information.
These output signals are used to select the front side bus frequency. A BSEL[1:0] =
“00” will select a 100 MHz bus clock frequency. The frequency is determined by the
processor(s), chipset, and frequency synthesizer capabilities. All front side bus
agents must operate at the same frequency. Individual processors will only operate
at their specified front side bus (FSB) frequency.
BSEL[1:0]
COMP[1:0]
O
On baseboards which support operation only at 100 MHz bus clocks these signals
can be ignored. On baseboards employing the use of these signals, a 1 KΩ pull-up
resistor be used.
See Table 2 “Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]” on
page 17 for output values.
COMP[1:0] must be terminated to VSS on the baseboard using precision resistors.
These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate
platform design guidelines and Table 13 for implementation details.
I
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Table 41. Signal Definitions (Page 4 of 10)
Name
Type
Description
Notes
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor front side bus agents, and must connect the appropriate
pins on all such agents. The data driver asserts DRDY# to indicate a valid data
transfer.
D[63:0]# are quad-pumped signals, and will thus be driven four times in a common
clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and
DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP#
and one DSTBN#. The following table shows the grouping of data signals to strobes
and DBI#.
D[63:0]#
I/O
4
DSTBN/
DSTBP
Data Group
DBI#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# pins determine the polarity of the data signals. Each group
of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active,
the corresponding data group is inverted and therefore sampled active high.
DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals.
The DBI[3:0]# signals are activated when the data on the data bus is inverted. The
bus agent will invert the data bus signals if more than half the bits, within a 16-bit
group, change logic level in the next cycle.
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI[3:0]#
I/O
4
DBI0#
DBI1#
DBI2#
DBI3#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the
processor front side bus to indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted. This signal must connect the appropriate pins
on all processor front side bus agents.
DBSY#
I/O
4
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor front side bus agents.
DEFER#
DP[3:0]#
DRDY#
I
4
4
4
DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are
driven by the agent responsible for driving D[63:0]#, and must connect the
appropriate pins of all processor front side bus agents.
I/O
I/O
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor front side bus agents.
DSTBN[3:0]#
DSTBP[3:0]#
I/O
I/O
Data strobe used to latch in D[63:0]#.
Data strobe used to latch in D[63:0]#.
4
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Table 41. Signal Definitions (Page 5 of 10)
Name
Type
Description
Notes
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and
its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/
PBE# indicates a floating-point error and will be asserted when the processor
detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/
PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included
for compatibility with systems using MS-DOS*-type floating-point error reporting.
When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the
processor has a pending break event waiting for service. The assertion of FERR#/
PBE# indicates that the processor should be returned to the Normal state. For
additional information on the pending break event functionality, including the
identification of support of the feature and enable/disable information, refer to
volume 3 of the Intel Architecture Software Developer's Manual and the Intel
Processor Identification and the CPUID Instruction application note.
FERR#/PBE#
O
3
This signal does not have on-die termination and must be terminated at the
end agent. See the appropriate Platform Design Guideline for additional
information.
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set at 2/3Vcc. GTLREF is used by the AGTL+ receivers to determine if a
signal is a logical 0 or a logical 1.
GTLREF
I
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any front side bus agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting HIT#
and HITM# together.
HIT#
I/O
I/O
4
Since multiple agents may deliver snoop results at the same time, HIT# and HITM#
are wire-OR signals which must connect the appropriate pins of all processor front
side bus agents. In order to avoid wire-OR glitches associated with simultaneous
edge transitions driven by multiple drivers, HIT# and HITM# are activated on
specific clock edges and sampled on specific clock edges.
HITM#
IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the
processor front side bus. This transaction may optionally be converted to an
external error signal (e.g., NMI) by system core logic. The processor will keep
IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
IERR#
IGNNE#
INIT#
O
3
3
3
This signal does not have on-die termination and must be terminated at the
end agent. See the appropriate Platform Design Guideline for additional
information.
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
I
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside all processors
without affecting their internal caches or floating-point registers. Each processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate pins
of all processor front side bus agents.
I
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
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Table 41. Signal Definitions (Page 6 of 10)
Name
Type
Description
Notes
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side
bus agents. When the APIC functionality is disabled, the LINT0 signal becomes
INTR,
a maskable interrupt request signal, and LINT1 becomes NMI, a
nonmaskable interrupt. INTR and NMI are backward compatible with the signals of
those names on the Pentium processor. Both signals are asynchronous.
3
LINT[1:0]
I
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of all processor front side bus agents. For a
locked sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
LOCK#
I/O
4
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
front side bus, it will wait until it observes LOCK# deasserted. This enables
symmetric agents to retain ownership of the processor front side bus throughout the
bus locked operation and ensure the atomicity of lock.
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor front side bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
•
•
•
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
MCERR#
I/O
•
Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the IA-32 Software
Developer’s Manual, Volume 3: System Programming Guide.
Since multiple agents may drive this signal at the same time, MCERR# is a wire-OR
signal which must connect the appropriate pins of all processor front side bus
agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, MCERR# is activated on specific clock edges
and sampled on specific clock edges.
ODTEN (On-die termination enable) should be connected to VCC to enable on-die
termination for end bus agents. For middle bus agents, pull this signal down via a
resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die
termination will be active, regardless of other states of the bus.
ODTEN
I
PROCHOT# (processor hot) indicates that the processor Thermal Control Circuit
(TCC) has been activated. Under most conditions, PROCHOT# will go active when
the processor’s thermal sensor detects that the processor has reached its
maximum safe operating temperature. See Section 7.3 for more details.
PROCHOT#
O
These signals do not have on-die termination and must be terminated at the
end agent. See the appropriate Platform Design Guideline for additional
information.
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Intel® Xeon™ Processor with 512 KB L2 Cache
Table 41. Signal Definitions (Page 7 of 10)
Name
Type
Description
Notes
PWRGOOD (Power Good) is an input. The processor requires this signal to be a
clean indication that all processor clocks and power supplies are stable and within
their specifications. “Clean” implies that the signal will remain low (capable of
sinking leakage current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then transition
monotonically to a high state. Figure 13 illustrates the relationship of PWRGOOD to
the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and
power must again be stable before a subsequent rising edge of PWRGOOD. It
must also meet the minimum pulse width specification in Table 16, and be followed
by a 1 mS RESET# pulse.
PWRGOOD
I
3
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor
front side bus agents. They are asserted by the current bus owner to define the
currently active transaction type. These signals are source synchronous to
ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking
of these signals.
REQ[4:0]#
I/O
4
Asserting the RESET# signal resets all processors to known states and invalidates
their internal caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCC and BCLK
have reached their proper specifications. On observing active RESET#, all front
side bus agents will deassert their outputs within two clocks. RESET# must not be
kept asserted for more than 10ms.
RESET#
I
4
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
Section 7.1.
This signal does not have on-die termination and must be terminated at the
end agent. See the appropriate Platform Design Guideline for additional
information.
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor front side bus agents.
RS[2:0]#
RSP#
I
I
4
4
RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect to the appropriate pins of all
processor front side bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate
that the processor is present.
SKTOCC#
SLP#
O
I
SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the
Sleep state. During Sleep state, the processor stops providing internal clock signals
to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in
this state will not recognize snoops or interrupts. The processor will recognize only
assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK
input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop-Grant state, restarting its internal clock signals to the bus and
processor core units.
3
SM_ALERT# is an asynchronous interrupt line associated with the SMBus Thermal
Sensor device. It is an open-drain output and the processor includes a 10 KΩ pull-
up resistor to SM_VCC for this signal. For more information on the usage of the
SM_ALERT# pin, see Section 7.4.5.
SM_ALERT#
O
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Table 41. Signal Definitions (Page 8 of 10)
Name
Type
Description
Notes
The SM_CLK (SMBus Clock) signal is an input clock to the system management
logic which is required for operation of the system management features of the
processor. This clock is driven by the SMBus controller and is asynchronous to
other clocks in the processor. The processor includes a 10 KΩ pull-up resistor to
SM_VCC for this signal.
SM_CLK
I/O
The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal
provides the single-bit mechanism for transferring data between SMBus
devices.The processor includes a 10 KΩ pull-up resistor to SM_VCC for this signal.
SM_DAT
I/O
The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in
conjunction with the upper address bits in order to maintain unique addresses on
the SMBus in a system with multiple processors. To set an SM_EP_A line high, a
pull-up resistor should be used that is no larger than 1 KΩ. The processor includes
a 10 KΩ pull-down resistor to VSS for each of these signals. For more information
on the usage of these pins, see Section 7.4.8.
SM_EP_A[2:0]
I
The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus
in conjunction with the upper address bits in order to maintain unique addresses on
the SMBus in a system with multiple processors.
SM_TS_A[1:0]
I
The device’s addressing, as implemented, includes a Hi-Z state for both address
pins. The use of the Hi-Z state is achieved by leaving the input floating
(unconnected). For more information on the usage of these pins, see Section 7.4.8.
Provides power to the SMBus components on the processor, as well as to the
processor VID logic. The baseboard MUST provide SM_Vcc to the processor. See
Figure 19 “Example 3.3 VDC/SM_VCC Sequencing” on page 44 for further details.
SM_VCC
SM_WP
I
I
WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch
EEPROM is write-protected when this input is pulled high to SM_VCC.The
processor includes a 10 KΩ pull-down resistor to VSS for this signal.
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, processors save the current state
and enter System Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the SMM handler.
SMI#
I
I
3
3
If SMI# is asserted during the deassertion of RESET# the processor will tri-state its
outputs.
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the front
side bus and APIC units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
STPCLK#
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
TCK
TDI
I
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
TDO
O
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Table 41. Signal Definitions (Page 9 of 10)
Name
Type
Description
Notes
All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor
which matches the trace impedance within a range of ±10 ohms. TESTHI[3:0] and
TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if
desired. However, utilization of boundary scan test will not be functional if these
pins are connected together. TESTHI4 must always be pulled up independently
from the other TESTHI pins. For optimum noise margin, all pull-up resistor values
used for TESTHI[6:0] pins should have a resistance value within ±20 percent of the
impedance of the baseboard transmission line traces. For example, if the trace
impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used. The
TESTHI[6:0] termination recommendations provided in the Intel® XeonTM
processor datasheet are still suitable for the Intel® XeonTM processor with 512 KB
L2 cache. However, Intel recommends new designs or designs undergoing design
updates follow the trace impedance matching termination guidelines given in this
section.
TESTHI[6:0]
I
Activation of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond which permanent silicon damage may
occur. Measurement of the temperature is accomplished through an internal
thermal sensor which is configured to trip at approximately 135 °C. To properly
protect the processor, power must be removed upon THERMTRIP# becoming
active. See Figure 16 and Table 20 for the appropriate power down sequence and
timing requirement. In parallel, the processor will attempt to reduce its temperature
by shutting off internal clocks and stopping all program execution. Once activated,
THERMTRIP# remains latched and the processor will be stopped until RESET# is
asserted. A RESET# pulse will reset the processor and execution will begin at the
boot vector. If the temperature has not dropped below the trip level, the processor
will assert THERMTRIP# and return to the shutdown state. The processor releases
THERMTRIP# when RESET# is activated even if the processor is still too hot.
THERMTRIP#
O
2
This signal do not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guidelines for additional
information.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TMS
I
This signal does not have on-die termination and must be terminated at the
end agent.See the appropriate platform design guidelines for additional
information.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins
of all front side bus agents.
TRDY#
TRST#
I
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset. See the appropriate Platform Design Guideline for
additional information.
VCCA provides isolated power for the analog portion of the internal PLL’s. Use a
discrete RLC filter to provide clean power. Use the filter defined in Section 2.5 to
provide clean power to the PLL. The tolerance and total ESR for the filter is
important. Refer to the appropriate platform design guidelines for complete
implementation details.
VCCA
I
I
VCCIOPLL provides isolated power for digital portion of the internal PLL’s. Follow the
guidelines for VCCA (Section 2.5), and refer to the appropriate platform design
guidelines for complete implementation details.
VCCIOPLL
The Vccsense and Vsssense pins are the points for which processor minimum and
maximum voltage requirements are specified. Uniprocessor designs may utilize
these pins for voltage sensing for the processor's voltage regulator. However, multi-
processor designs must not connect these pins to sense logic, but rather utilize
VCCSENSE
VSSSENSE
O
them for power delivery validation.
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Table 41. Signal Definitions (Page 10 of 10)
Name
Type
Description
Notes
VID[4:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages (VCC). Unlike previous processor generations, these pins are
driven by processor logic. Hence the voltage supply for these pins (SM_VCC) must
be valid before the VRM supplying Vcc to the processor is enabled. Conversely, the
VRM output must be disabled prior to the voltage supply for these pins becomes
invalid. The VID pins are needed to support processor voltage specification
variations. See Table 3 for definitions of these pins. The power supply must supply
the voltage that is requested by these pins, or disable itself.
VID[4:0]
O
VSSA provides an isolated, internal ground for internal PLL’s. Do not connect
directly to ground. This pin is to be connected to VCCA and VCCIOPLL through a
discrete filter circuit.
VSSA
I
NOTES:
1. Intel Xeon processors only support BR0# and BR1#. However, the Intel Xeon processors must terminate BR2# and BR3# to the
processor VCC.
2. For this pin on Intel® Xeon™ processors, the maximum number of symmetric agents is one. Maximum number of Central
Agents is zero.
3. For this pin on Intel® Xeon™ processors, the maximum number of symmetric agents is two. Maximum number of Central
Agents is zero.
4. For this pin on Intel® Xeon™ processors, the maximum number of symmetric agents is two. Maximum number of Central
Agents is one.
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6.0
Thermal Specifications
This chapter provides the thermal specifications necessary for designing a thermal solution for the
Intel® Xeon™ processor with 512 KB L2 cache. Thermal solutions should include heatsinks that
attach to the integrated heat spreader (IHS). The IHS provides a common interface intended to be
compatible with many heatsink designs. Thermal specifications are based on the temperature of the
IHS top, referred to as the case temperature, or TCASE. Thermal solutions should be designed to
maintain the processor within TCASE specifications. For information on performing TCASE
measurements, refer to the Intel® Xeon™ Processor Thermal Design Guidelines. See Figure 37 for
an exploded view of the processor package and thermal solution assembly.
Note: The processor is either shipped alone or with a heatsink (boxed processor only). All other
components shown in Figure 37 must be purchased separately.
Figure 37. Processor with Thermal and Mechanical Components - Exploded View
Heat sink clip
Heat sink
EMI ground
frame
Retention
mechanism
603-pin
socket
Note: This is a graphical representation. For specifications, see each component’s respective
documentation listed in Section 1.3.
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Intel® Xeon™ Processor with 512 KB L2 Cache
6.1
Thermal Specifications
Table 42 specifies the thermal design power dissipation envelope for the Intel® Xeon™ processor
with 512 KB L2 cache. The processor power listed in Table 42 is described in thermal design
power. Analysis indicates that real applications are unlikely to cause the processor to consume the
maximum possible power consumption. Intel recommends that system thermal designs utilize the
Thermal Design Power indicated in Table 42. Thermal Design Power recommendations are chosen
through characterization of server and workstation applications on the processor.
The Thermal Monitor feature is intended to protect the processor from overheating on any high
power code that exceeds the recommendations in this table. For more details on the Thermal
Monitor feature, refer to Section 7.3. In all cases, the Thermal Monitor feature must be enabled for
the processor to be operating within specification. Table 42 also lists the minimum and maximum
processor TCASE temperature specifications. A thermal solution should be designed to ensure the
temperature of the processor never exceeds these specifications.
Table 42. Processor Thermal Design Power
Thermal Design
Minimum TCASE Maximum TCASE
1
Core Frequency
Power
(W)
Notes
(°C)
(°C)
1.80 GHz
2 GHz
55
58
61
65
71
5
5
5
5
5
69
70
75
74
74
2, 3
2, 3
2, 3
2, 3
2, 3
2.20 GHz
2.40 GHz
2.60 GHz
2.80 GHz
3 GHz
74
85
5
5
75
73
2, 3
2, 3
NOTE:
1. Intel recommends that thermal solutions be designed utilizing the Thermal Design Power values. Refer to the
Intel® Xeon™ Processor Thermal Design Guidelines.
2. TDP values are specified at the point on Vcc_max loadline corresponding to Icc_TDP.
3. Systems must be designed to ensure that the processor is not subjected to any static Vcc and Icc
combination wherein Vcc exceeds Vcc_max at specified Icc. Please refer to the loadline specifications in
Chapter 2.0.
Figure 38. Processor Thermal Design Power vs Electrical Projections for VID = 1.500V
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Figure 39. Processor Thermal Design Power vs Electrical Projections for VID = 1.525V
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Intel® Xeon™ Processor with 512 KB L2 Cache
6.2
Measurements for Thermal Specifications
6.2.1
Processor Case Temperature Measurement
The minimum and maximum case temperatures (TCASE) for processors are specified in Table 42 of
the previous section. These temperature specifications are meant to ensure correct and reliable
operation of the processor. Figure 40 illustrates the thermal measurement point for TCASE. This
point is at the geometric center of the integrated heat spreader (IHS).
Figure 40. Thermal Measurement Point for Processor TCASE
Note: Figure is not to scale, and is for reference only
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7.0
Features
7.1
Power-On Configuration Options
The Intel® Xeon™ processor with 512 KB L2 cache has several configuration options that are
determined by the state of specific processor pins at the active-to-inactive transition of the
processor RESET# signal. These configuration options cannot be changed except by another reset.
Both power on and software induced resets reconfigure the processor(s).
Table 43. Power-On Configuration Option Pins
1
Configuration Option
Pin
Notes
Output tri state
SMI#
INIT#
Execute BIST (Built-In Self Test)
In Order Queue de-pipelining (set IOQ depth to 1)
Disable MCERR# observation
Disable BINIT# observation
APIC cluster ID (0-3)
A7#
A9#
A10#
A[12:11]#
A15#
2
3
Disable bus parking
Disable Hyper-Threading Technology
Symmetric agent arbitration ID
A31#
BR[3:0]#
NOTES:
1. Asserting this signal during active-to-inactive edge of RESET# will selects the corresponding option.
2. The Intel® Xeon™ processor with 512 KB L2 cache does not support this feature, therefore platforms
utilizing this processor should not use these configuration pins.
3. Intel Xeon processor with 512 KB L2 cache utilize only BR0# and BR1# signals. 2-way platforms must not
utilize BR2# and BR3# signals.
7.2
Clock Control and Low Power States
The processor allows the use of AutoHALT, Stop-Grant and Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See Figure 41 for a visual representation of the processor low power states.
Due to the inability of processors to recognize bus transactions during the Sleep state,
multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the
other processor in the Normal or Stop-Grant state.
7.2.1
Normal State—State 1
This is the normal operating state for the processor.
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7.2.2
AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#,
LINT[1:0] (NMI, INTR), or an interrupt delivered over the front side bus. RESET# will cause the
processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
Figure 41. Stop Clock State Machine
HALT Instruction and
HALT Bus Cycle Generated
2. Auto HALT Power Down State
BCLK running
INIT#, BINIT#, INTR, NMI,
SMI#, RESET#
.
1. Normal State
Normal execution
Snoops and interrupts allowed
STPCLK#
De-asserted
STPCLK#
Asserted
Snoop
Event
Snoop
Event
Occurs
Serviced
4. HALT/Grant Snoop State
BCLK running
3. Stop Grant State
BCLK running
Snoop Event Occurs
Snoop Event Serviced
Service snoops to caches
Snoops and interrupts allowed
SLP#
Asserted
SLP#
De-asserted
5. Sleep State
BCLK running
No snoops or interrupts
allowed
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7.2.3
Stop-Grant State—State 3
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once
the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop
Grant state. Both logical processors of the Intel® Xeon™ processor with 512 KB L2 cache must be
in the Stop Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven
(allowing the level to return to VCC) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the front side bus should be driven to the inactive state.
BINIT# will be recognized while the processor is in Stop-Grant state. If STPCLK# is still asserted
at the completion of the BINIT# bus initialization, the processor will remain in Stop-Grant mode. If
the STPCLK# is not asserted at the completion of the BINIT# bus initialization, the processor will
return to Normal state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the sleep state, STPCLK# should
only be deasserted one or more bus clocks after the deassertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
front side bus (see Section 7.2.4). A transition to the Sleep state (see Section 7.2.5) will occur with
the assertion of the SLP# signal.
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal state. Only one occurrence
of each event will be recognized upon return to the Normal state.
7.2.4
7.2.5
HALT/Grant Snoop State—State 4
The processor will respond to snoop transactions on the front side bus while in Stop-Grant state or
in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant
Snoop state. The processor will stay in this state until the snoop on the front side bus has been
serviced (whether by the processor or another agent on the front side bus). After the snoop is
serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as
appropriate.
Sleep State—State 5
The Sleep state is a very low power state in which each processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be
entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing
the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT
states.
Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will
cause unpredictable behavior.
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In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the front side bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and
STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous front side bus
event occurs. The SLP# pin should only be asserted when the processor (and all logical processors
within the physical processor) is in the Stop-Grant state. SLP# assertions while the processors are
not in the Stop-Grant state is out of specification and may result in illegal operation.
7.2.6
Bus Response During Low Power States
While in AutoHALT Power Down and Stop-Grant states, the processor will process a front side bus
snoop.
When the processor is in Sleep state, the processor will not process interrupts or snoop
transactions.
7.3
Thermal Monitor
Thermal Monitor is a feature of the processor that allows system designers to lower the cost of
thermal solutions, without compromising system integrity or reliability. By using a factory-tuned,
precision on-die temperature sensor, and a fast acting thermal control circuit (TCC), the processor,
without the aid of any additional software or hardware, can control the processors’ die temperature
within factory specifications under typical real-world operating conditions. Thermal Monitor thus
allows the processor and system thermal solutions to be designed much closer to the power
envelopes of real applications, instead of being designed to the much higher maximum processor
power envelopes.
Thermal Monitor controls the processor temperature by modulating (starting and stopping) the
internal processor core clocks. The processor clocks are modulated when the thermal control
circuit (TCC) is activated. Thermal Monitor uses two modes to activate the TCC: Automatic mode
and On-Demand mode. Automatic mode must be enabled via BIOS, which is required for the
processor to operate within specifications. Once automatic mode is enabled, the TCC will
activate only when the internal die temperature is very near the temperature limits of the processor.
When the TCC is enabled, and a high temperature situation exists (i.e. TCC is active), the clocks
will be modulated by maintaining a duty cycle within a range of 30% - 50%. Clocks will not be off
or on more than 3.0 ms when the TCC is active. Cycle times are processor speed dependent and
will decrease as processor core frequencies increase. A small amount of hysteresis has been
included to prevent rapid active/inactive transitions of the TCC when the processor temperature is
near the trip point. Once the temperature has returned to a non-critical level, and the hysteresis
timer has expired, modulation ceases and the TCC goes inactive. Processor performance will be
decreased by ~50% when the TCC is active (assuming a duty cycle that varies from 30%-50%),
however, with a properly designed and characterized thermal solution the TCC most likely will
only be activated briefly during the most power intensive applications while at maximum chassis
ambient temperature.
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For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic
mode does not require any additional hardware, software drivers or interrupt handling routines.
The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor
Control Register is written to a “1” the TCC will be activated immediately, independent of the
processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the
clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control
Register. In automatic mode, the duty cycle is fixed anywhere within a range of 30% to 50%;
however in On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to
87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used at the same time
Automatic mode is enabled, however, if TCC is enabled via On-Demand mode at the same time
automatic mode is enabled AND a high temperature condition exists, the fixed duty cycle of the
automatic mode will override the duty cycle selected by the On-Demand mode.
An external signal, PROCHOT# (processor hot) is asserted at any time the TCC is active (either in
Automatic or On-Demand mode). Bus snooping and interrupt latching are also active while the
TCC is active. The temperature at which the thermal control circuit activates is not user
configurable and is not software visible. In an MP system, Thermal Monitor must be configured
identically for each processor within the system.
Besides the thermal sensor and thermal control circuit, the Thermal Monitor feature also includes
one ACPI register, one performance counter register, three model specific registers (MSR), and one
I/O pin (PROCHOT#). All are available to monitor and control the state of the Thermal Monitor
feature. Thermal Monitor can be configured to generate an interrupt upon the assertion or de-
assertion of PROCHOT# (i.e. upon the activation/deactivation of TCC). Refer to Volume 3 of the
IA32 Intel Architecture Software Developer’s for specific register and programming details.
If automatic mode is disabled the processor will be operating out of specification and cannot be
guaranteed to provide reliable results. Regardless of enabling of the automatic or On-Demand
modes, in the event of a catastrophic cooling failure, the processor will automatically shut down
when the silicon has reached a temperature of approximately 135 °C. At this point the front side
bus signal THERMTRIP# will go active and stay active until the processor has cooled down and
RESET# has been initiated. THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles.If THERMTRIP# is asserted, processor core voltage (VCC) must
be removed within the timeframe defined in Figure 16.
7.3.1
Thermal Diode
The processor incorporates an on-die thermal diode. A thermal sensor located on the processor may
be used to monitor the die temperature of the processor for thermal management/long term die
temperature change purposes. This thermal diode is separate from the Thermal Monitor’s thermal
sensor and cannot be used to predict the behavior of the Thermal Monitor. See Section 7.4.4 for
details.
7.4
System Management Bus (SMBus) Interface
The processor includes an SMBus interface which allows access to a memory component with two
sections (referred to as the Processor Information ROM and the Scratch EEPROM) and a thermal
sensor on the substrate. The SMBus thermal sensor may be used to read the thermal diode
mentioned in Section 7.3.1. These devices and their features are described below. See Chapter 4.0
for the physical location of these devices.
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Note: The SMBus thermal sensor and its associated thermal diode are not related to, and are completely
independent of, the precision on-die temperature sensor and thermal control circuit (TCC) of the
Thermal Monitor feature discussed in Section 7.3.
The processor SMBus implementation uses the clock and data signals of the V1.1 System
Management Bus Specification. It does not implement the SMBSUS# signal. Layout and routing
guidelines are available in the appropriate platform design guidelines document.
For platforms which do not implement any of the SMBus features found on the processor, all of the
SMBus connections to the socket pins, except SM_VCC, may be left unconnected (SM_ALERT#,
SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], SM_WP). SM_VCC provides power to the
VID generation logic in addition to supplying the SMBus and must be supplied with 3.3 volt power
to assure correct setting of the processor core voltage (VCC).
Figure 42. Logical Schematic of SMBus Circuitry
SM_VCC
SM_TS_A0
SM_TS_A1
VCC
VCC
A0
A1
SM_EP_A0
SM_EP_A1
SM_EP_A2
CLK
A0
A1
CLK
Processor
Information
ROM
and
Scratch
DATA
DATA
Thermal
Sensor
A2
STDBY#
ALERT#
WP
SM_WP
EEPROM
(1 Kbit each)
VSS
VSS
SM_CLK
SM_DAT
SM_ALERT#
NOTE: Actual implementation may vary. For use in general understanding of the architecture. All SMBus pull-up
and pull-down resistors are 10K ohms and located on the processor.
7.4.1
Processor Information ROM (PIROM)
The lower half (128 bytes) of the SMBus memory component is an electrically programmed read-
only memory with information about the processor. This information is permanently write-
protected. Table 44 shows the data fields and formats provided in the Processor Information ROM
(PIROM).
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Table 44. Processor Information ROM Format (Page 1 of 2)
# of
Bits
Offset/Section
Function
Notes
Header:
00h
01 - 02h
03h
8
16
8
Data Format Revision
EEPROM Size
Two 4-bit hex digits
Size in bytes (MSB first)
Processor Data Address
Byte pointer, 00h if not present
Processor Core Data
Address
04h
8
Byte pointer, 00h if not present
05h
06h
07h
8
8
8
L3 Cache Data Address
Package Data Address
Part Number Data Address
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Thermal Reference Data
Address
08h
8
Byte pointer, 00h if not present
09h
0Ah
8
8
Feature Data Address
Other Data Address
Reserved
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Reserved
0Bh
16
8
0Dh
Checksum
1 byte checksum
Processor Data:
0E - 13h
48
S-spec Number
Six 8-bit ASCII characters
6
2
Reserved
Reserved (most significant bits)
14h
Sample/Production
00b=Sample only, 01-11b=Production
15h
Processor Core Data:
16 - 17h
8
Checksum
1 byte checksum
2
4
Processor Core Type
Processor Core Family
Processor Core Model
Processor Core Stepping
Reserved
From CPUID
From CPUID
4
From CPUID
4
From CPUID
2
Reserved
18 - 19h
1A - 1Bh
16
16
Reserved
Reserved
Front Side Bus Speed
16-bit binary number (in MHz)
2
6
Multiprocessor Support
Reserved
00b=UP, 01b=DP, 10b=RSVD, 11b=MP
Reserved
1Ch
1D - 1Eh
1F - 20h
21 - 22h
23h
16
16
16
8
Maximum Core Frequency
Processor VID (Voltage ID)
Core Voltage, Minimum
16-bit binary number (in MHz)
Voltage requested by VID outputs in mV
Minimum processor DC Vcc spec in mV
Maximum case temperature spec in °C
1 byte checksum
T
CASE Maximum
24h
8
Checksum
Cache Data:
25 - 26h
27-28h
16
16
Reserved
Reserved
L2 Cache Size
16-bit binary number (in KB)
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Table 44. Processor Information ROM Format (Page 2 of 2)
# of
Bits
Offset/Section
Function
Notes
29 - 2Ah
16
48
8
L3 Cache Size
16-bit binary number (in KB)
Reserved
2B - 30h
31h
Reserved
Checksum
1 byte checksum
Package Data:
32 - 35h
32
8
Package Revision
Reserved
Four 8-bit ASCII characters
Reserved
36h
37h
8
Checksum
1 byte checksum
Part Number Data:
38 - 3Eh
56
Processor Part Number
Reserved
Seven 8-bit ASCII characters
Reserved
3F - 4Ch
112
Processor Electronic
Signature
4D - 54h
64
64-bit identification number
55 - 6Eh
208
8
Reserved
Reserved
6Fh
Thermal Ref. Data:
70h
Checksum
1 byte checksum
8
16
8
Thermal Reference Byte
Reserved
See Section 7.4.4 for details
Reserved
71 - 72h
73h
Checksum
1 byte checksum
Feature Data:
Processor Core Feature
Flags
74 - 77h
32
8
From CPUID function 1, EDX contents
[7] = Reserved
[6] = Serial Signature
[5] = Electronic Signature Present 1
[4] = Thermal Sense Device Present
[3] = Thermal Reference Byte Present
[2] = OEM EEPROM Present
[1] = Core VID Present
78h
Processor Feature Flags
[0] = L3 Cache Present
Additional Processor
Feature Flags
79-7Bh
24
Reserved
7Ch
7Dh
8
8
Reserved
Reserved
Checksum
1 byte checksum
Other Data:
7E - 7Fh
16
Reserved
Reserved
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7.4.2
7.4.3
Scratch EEPROM
Also available in the memory component on the processor SMBus is an EEPROM which may be
used for other data at the system or processor vendor’s discretion. The data in this EEPROM, once
programmed, can be write-protected by asserting the active-high SM_WP signal. This signal has a
weak pull-down (10 kW) to allow the EEPROM to be programmed in systems with no
implementation of this signal. The Scratch EEPROM resides in the upper half of the memory
component (addresses 80 - FFh). The lower half comprises the Processor Information ROM
(address 00 - 7Fh), which is permanently write protected by Intel.
PIROM and Scratch EEPROM Supported SMBus Transactions
The Processor Information ROM (PIR) responds to two SMBus packet types: Read Byte and Write
Byte. However, since the PIR is write-protected, it will acknowledge a Write Byte command but
ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte commands. Table 45
diagrams the Read Byte command. Table 46 diagrams the Write Byte command. Following a write
cycle to the scratch ROM, software must allow a minimum of 10ms before accessing either ROM
of the processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents a read bit,
‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’ represents a negative
acknowledge (NACK). The shaded bits are transmitted by the Processor Information ROM or
Scratch EEPROM, and the bits that aren’t shaded are transmitted by the SMBus host controller. In
the tables the data addresses indicate 8 bits.The SMBus host controller should transmit 8 bits with
the most significant bit indicating which section of the EEPROM is to be addressed: the Processor
Information ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
Table 45. Read Byte SMBus Packet
Slave
Address
Command
Code
Slave
Address
Rea
d
S
Write
A
A
S
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Table 46. Write Byte SMBus Packet
Slave
Address
S
Write
A
Command Code
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1
7.4.4
SMBus Thermal Sensor
The processor’s SMBus thermal sensor provides a means of acquiring thermal data from the
processor. The thermal sensor is composed of control logic, SMBus interface logic, a precision
analog-to-digital converter, and a precision current source. The sensor drives a small current
through the p-n junction of a thermal diode located on the processor core. The forward bias voltage
generated across the thermal diode is sensed and the precision A/D converter derives a single byte
of thermal reference data, or a “thermal byte reading.” The nominal precision of the least
significant bit of a thermal byte is 1 °C.
The processor incorporates the SMBus thermal sensor and thermal reference byte onto the
processor package as was previously done on Intel® Xeon™ processor family. Upper and lower
thermal reference thresholds can be individually programmed for the SMBus thermal sensor.
Comparator circuits sample the register where the single byte of thermal data (thermal byte
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reading) is stored. These circuits compare the single byte result against programmable threshold
bytes. If enabled, the alert signal on the processor SMBus (SM_ALERT#) will be asserted when
the sensor detects that either threshold is reached or crossed. Analysis of SMBus thermal sensor
data may be useful in detecting changes in the system environment that may require attention.
During manufacturing, the thermal reference byte (TRB) is programmed into the Processor
Information ROM. The thermal reference byte represents the approximate thermal byte reading
that is obtained when the processor is operating at its maximum specified TCASE. The TRB is
derived for each individual processor during Intel’s manufacturing process.
The processor SMBus thermal sensor and thermal reference byte may be used to monitor long term
temperature trends, but can not be used to manage the short term temperature of the processor or
predict the activation of the thermal control circuit. As mentioned earlier, the processors high
thermal ramp rates make this infeasible. Refer to the Intel® XeonTM Processor Family Thermal
Design Guidelines for more details.
The SMBus thermal sensor feature in the processor cannot be used to measure TCASE. The TCASE
specification in Chapter 6.0 must be met regardless of the reading of the processor's thermal sensor
in order to ensure adequate cooling for the processor. The SMBus thermal sensor feature is only
available while VCC and SM_VCC are at valid levels and the processor is not in a low-power state.
7.4.5
Thermal Sensor Supported SMBus Transactions
The thermal sensor responds to five of the SMBus packet types: Write Byte, Read Byte, Send Byte,
Receive Byte, and Alert Response Address (ARA). The Send Byte packet is used for sending one-
shot commands only. The Receive Byte packet accesses the register commanded by the last Read
Byte packet and can be used to continuously read from a register. If a Receive Byte packet was
preceded by a Write Byte or send Byte packet more recently than a Read Byte packet, then the
behavior is undefined. Table 47 through Table 50 diagram the five packet types. In these figures,
‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘Ack’ represents an acknowledge, and
‘///’ represents a negative acknowledge (NACK). The shaded bits are transmitted by the thermal
sensor, and the bits that aren’t shaded are transmitted by the SMBus host controller. Table 51 shows
the encoding of the command byte.
Table 47. Write Byte SMBus Packet
Slave
Address
Comman
d Code
S
Write
Ack
Ack
Data
Ack
P
1
7-bits
1
1
8-bits
1
8-bits
1
1
Table 48. Read Byte SMBus Packet
Slave
Addres
s
Slave
Addres
s
Comman
d Code
Rea
d
S
Write
Ack
Ack
S
Ack
Data
///
P
8-
bits
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
1
1
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Table 49. Send Byte SMBus PacketReceive Byte SMBus Packet
S
1
S
1
Slave Address
Read
Ack
Command Code
Ack
1
P
1
P
1
7-bits
1
1
8-bits
Slave Address
7-bits
Read
1
Ack
1
Data
///
8-bits
1
Table 50. ARA SMBus Packet
S
ARA
Read
Ack
Address
///
P
1
0001 100
1
1
Device Address1
1
1
NOTE:
1. This is an 8-bit field. The device which sent the alert will respond to the ARA Packet with its address in the seven most signifi-
cant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See Section 7.4.8 for details on the Thermal Sensor
Device addressing.
Table 51. SMBus Thermal Sensor Command Byte Bit Assignments
Register
Command
Reset State
Function
RESERVED
TRR
00h
01h
02h
03h
04h
05h
06h
RESERVED
0000 0000
N/A
Reserved for future use
Read processor core thermal diode
Read status byte (flags, busy signal)
Read configuration byte
RS
RC
00XX XXXX
0000 0010
RESERVED
RESERVED
RCR
Read conversion rate byte
Reserved for future use
RESERVED
RESERVED
Reserved for future use
Read processor core thermal diode THIGH
limit
RRHL
RRLL
07h
08h
0111 1111
1100 1001
Read processor core thermal diode TLOW
limit
WC
09h
0Ah
0Bh
0Ch
N/A
Write configuration byte
Write conversion rate byte
Reserved for future use
Reserved for future use
WCR
N/A
RESERVED
RESERVED
RESERVED
RESERVED
Write processor core thermal diode THIGH
limit
WRHL
WRLL
0Dh
0Eh
N/A
N/A
Write processor core thermal diode TLOW
limit
OSHT
0Fh
N/A
N/A
One shot command (use send byte packet)
Reserved for future use
RESERVED
10h – FFh
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All of the commands in Table 51 are for reading or writing registers in the SMBus thermal sensor,
except the one-shot command (OSHT) register. The one-shot command forces the immediate start
of a new conversion cycle. If a conversion is in progress when the one-shot command is received,
then the command is ignored. If the thermal sensor is in stand-by mode when the one-shot
command is received, a conversion is performed and the sensor returns to stand-by mode. The one-
shot command is not supported when the thermal sensor is in auto-convert mode.
Note: Writing to a read-command register or reading from a write-command register will produce invalid
results.
The default command after reset is to a reserved value (00h). After reset, “Receive Byte” SMBus
packets will return invalid data until another command is sent to the thermal sensor.
7.4.6
SMBus Thermal Sensor Registers
Thermal Reference Registers
7.4.6.1
Once the SMBus thermal sensor reads the processor thermal diode, it performs an analog to digital
conversion and stores the result in the Thermal Reference Register (TRR). The supported range is
+127 to 0 decimal and is expressed as an eight-bit number representing temperature in degrees
Celsius. This eight-bit value consists of seven data bits and a sign bit (MSB) as shown in Table 52.
The values shown are also used to program the Thermal Limit Registers.
The values of these registers should be treated as saturating values. Values above 127 are
represented as 127 decimal, while values of zero and below may be represented as 0 to -127
decimal. If the thermal sensor returns a value with the sign bit set (1) and the data is 000_0000
through 111_1110, the temperature should be interpreted as 0 ºC.
Table 52. Thermal Reference Register Values
Temperature
(°C)
Register Value
(binary)
+127
+126
+100
+50
+25
+1
0 111 1111
0 111 1110
0 110 0100
0 011 0010
0 001 1001
0 000 0001
0 000 0000
0
7.4.6.2
Thermal Limit Registers
The SMBus thermal sensor has four Thermal Limit Registers: RRHL is used to read the high limit;
RRLL is read for the low limit; WRHL is used to write the high limit; and the WRLL to write the
low limit. These registers allow the user to define high and low limits for the processor core
thermal diode reading. The encoding for these registers is the same as for the Thermal Reference
Register shown in Table 52. If the processor thermal diode reading equals or exceeds one of these
limits, then the alarm bit (RHIGH or RLOW) in the Thermal Sensor Status Register is triggered.
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7.4.6.3
Status Register
The Status Register shown in Table 53 indicates which (if any) thermal value thresholds for the
processor core thermal diode have been exceeded. It also indicates if a conversion is in progress or
if an open circuit has been detected in the processor core thermal diode connection. Once set, alarm
bits stay set until they are cleared by a Status Register read. A successful read to the Status Register
will clear any alarm bits that may have been set, unless the alarm condition persists. If the
SM_ALERT# signal is enabled via the Thermal Sensor Configuration Register and a thermal diode
threshold is exceeded, an alert will be sent to the platform via the SM_ALERT# signal.
This register is read by accessing the RS Command Register.
Table 53. SMBus Thermal Sensor Status Register
Bit
Name
Reset State
Function
If set, indicates that the device’s analog to digital converter is
busy.
7 (MSB)
BUSY
N/A
6
5
RESERVED
RESERVED
RESERVED
RESERVED
Reserved for future use
Reserved for future use
If set, indicates the processor core thermal diode high
temperature alarm has activated.
4
3
2
RHIGH
RLOW
OPEN
0
0
0
If set, indicates the processor core thermal diode low
temperature alarm has activated.
If set, indicates an open fault in the connection to the
processor core diode.
1
RESERVED
RESERVED
RESERVED
RESERVED
Reserved for future use.
Reserved for future use.
0 (LSB)
7.4.6.4
Configuration Register
The Configuration Register controls the operating mode (stand-by vs. auto-convert) of the SMBus
thermal sensor. Table 54 shows the format of the Configuration Register. If the RUN/STOP bit is
set (high) then the thermal sensor immediately stops converting and enters stand-by mode. The
thermal sensor will still perform analog to digital conversions in stand-by mode when it receives a
one-shot command. If the RUN/STOP bit is clear (low) then the thermal sensor enters auto-
conversion mode.
This register is accessed by using the thermal sensor Command Register: The RC command
register is used for read commands and the WC command register is used for write commands. See
Table 51.
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Table 54. SMBus Thermal Sensor Configuration Register
Bit
Name
Reset State
Function
Mask SM_ALERT# bit. Clear bit to allow interrupts via
SM_ALERT# and allow the thermal sensor to respond to the
ARA command when an alarm is active. Set the bit to disable
interrupt mode. The bit is not used to clear the state of the
SM_ALERT# output. An ARA command may not be recognized
if the mask is enabled.
7 (MSB)
MASK
0
Stand-by mode control bit. If set, the device immediately stops
converting, and enters stand-by mode. If cleared, the device
converts in either one-shot mode or automatically updates on a
timed basis.
6
RUN/STOP
RESERVED
0
5:0
RESERVED Reserved for future use.
7.4.6.5
Conversion Rate Registers
The contents of the Conversion Rate Registers determine the nominal rate at which analog to
digital conversions happen when the SMBus thermal sensor is in auto-convert mode. There are two
Conversion Rate Registers, RCR for reading the conversion rate value and WCR for writing the
value. Table 55 shows the mapping between Conversion Rate Register values and the conversion
rate. As indicated in Table 51, the Conversion Rate Register is set to its default state of 02h
(0.25 Hz nominally) when the thermal sensor is powered up. There is a ±30% error tolerance
between the conversion rate indicated in the conversion rate register and the actual conversion rate.
Table 55. SMBus Thermal Sensor Conversion Rate Registers
Register Value
Conversion Rate (Hz)
00h
01h
0.0625
0.125
02h
0.25
03h
0.5
04h
1.0
05h
2.0
06h
4.0
8.0
07h
08h to FFh
Reserved for future use
7.4.7
SMBus Thermal Sensor Alert Interrupt
The SMBus thermal sensor located on the processor includes the ability to interrupt the SMBus
when a fault condition exists. The fault conditions consist of: 1) a processor thermal diode value
measurement that exceeds a user-defined high or low threshold programmed into the Command
Register or 2) disconnection of the processor thermal diode from the thermal sensor. The interrupt
can be enabled and disabled via the thermal sensor Configuration Register and is delivered to the
baseboard via the SM_ALERT# open drain output. Once latched, the SM_ALERT# should only be
cleared by reading the Alert Response byte from the Alert Response Address of the thermal sensor.
The Alert Response Address is a special slave address shown in Table 50. The SM_ALERT# will
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be cleared once the SMBus master device first reads the status register then reads the slave ARA
unless the fault condition persists. Reading the Status Register alone or setting the mask bit within
the Configuration Register does not clear the interrupt.
7.4.8
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of the form
“1010XXXZb”. The “XXX” bits are defined by pullups and pulldowns on the system baseboard.
These address pins are pulled down weakly (10 KΩ) on the processor substrate to ensure that the
memory components are in a known state in systems which do not support the SMBus, or only
support a partial implementation. The “Z” bit is the read/write bit for the serial bus transaction.
The thermal sensor internally decodes one of three upper address patterns from the bus of the form
“0011XXXZb”, “1001XXXZb”, or “0101XXXZb”. The device’s addressing, as implemented, uses
the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state. Therefore, the thermal sensor supports
nine unique addresses. To set either pin for the Hi-Z state, the pin must be left floating. As before,
the “Z” bit is the read/write bit for the serial transaction.
Note that addresses of the form “0000XXXXb” are Reserved and should not be generated by an
SMBus master. The thermal sensor samples and latches the SM_TS_A[1:0] signals at power-up
and at the starting point of every conversion. System designers should ensure that these signals are
at valid input levels before the thermal sensor powers up. This should be done by pulling the pins to
SM_VCC or VSS via a 1 KΩ or smaller resistor, or leaving the pins floating to achieve the Hi-Z
state. If the designer desires to drive the SM_TS_A[1:0] pins with logic, the designer must ensure
that the pins are at input levels of 3.3V or 0V before SM_VCC begins to ramp. The system designer
must also ensure that their particular implementation does not add excessive capacitance to the
address inputs. Excess capacitance at the address inputs may cause address recognition problems.
Refer to the appropriate platform design guidelines document and the System Management Bus
Specification.
Figure 42 on page 104 shows a logical diagram of the pin connections. Table 56 and Table 57
describe the address pin connections and how they affect the addressing of the devices.
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Table 56. Thermal Sensor SMBus Addressing
Upper
Address (Hex)
Device Select
8-bit Address Word on Serial Bus
b[7:0]
Address1
SM_TS_A1
SM_TS_A0
0
Z2
1
0
0
0
0011000Xb
0011001Xb
0011010Xb
3Xh
5Xh
9Xh
0011
0101
1001
0
Z2
1
Z2
Z2
Z2
0101001Xb
0101010Xb
0101011Xb
0
Z2
1
1
1
1
1001100Xb
1001101Xb
1001110Xb
NOTES:
1. Upper address bits are decoded in conjunction with the select pins.
2. A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
Note: System management software must be aware of the processor dependent addresses for the thermal
sensor.
Table 57. Memory Device SMBus Addressing
Address
(Hex)
Upper
Address
Device Select
R/W
bit 0
1
SM_EP_A2
bit 3
SM_EP_A1
bit 2
SM_EP_A0
bit 1
bits 7-4
A0h/A1h
A2h/A3h
A4h/A5h
A6h/A7h
A8h/A9h
AAh/ABh
ACh/ADh
AEh/AFh
1010
1010
1010
1010
1010
1010
1010
1010
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
NOTES:
1. . This addressing scheme will support up to 8 processors on a single SMBus.
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8.0
Boxed Processor Specifications
8.1
Introduction
The Intel® Xeon™ processor with 512 KB L2 cache is also offered as an Intel boxed processor.
Intel boxed processors are intended for system integrators who build systems from components
available through distribution channels. The boxed processor is supplied with an unattached
passive heatsink. It also contains an optional active duct solution, called Processor Wind Tunnel
(PWT), to provide adequate airflow across the heatsink. If the chassis or baseboard used contains
an alternate cooling solution that has been thermally validated, the PWT may be discarded. This
chapter documents baseboard and platform requirements for the cooling solution that is supplied
with the boxed processor. This chapter is particularly important for OEM's that manufacture
baseboards and chassis for integrators. Figure 43 and Figure 44 show a mechanical representation
of a boxed processor heatsink.
Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These
dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system
designer's responsibility to consider their proprietary cooling solution when designing to the
required keep-out zone on their system platform and chassis.
Figure 43. Mechanical Representation of the Boxed Processor Passive Heatsink for 3
GHz processors
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Figure 44. Mechanical Representation of the Boxed Processor Passive Heatsink for 2
- 2.80 GHz processors
8.2
Mechanical Specifications
This section documents the mechanical specifications of the boxed processor passive heatsink and
the PWT.
Proper clearance is required around the heatsink to ensure proper installation of the processor and
unimpeded airflow for proper cooling.
8.2.1
Heatsink Dimensions
The boxed processor is shipped with an unattached passive heatsink. Clearance is required around
the heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and
dimensions for the boxed Intel® Xeon™ processor with 512KB L2 cache assembled heatsink are
shown in Figure 47 (Multiple Views). The airflow requirements for the boxed processor heatsink
must also be taken into consideration when designing new baseboards and chassis. The airflow
requirements are detailed in the Thermal Specifications, Section 8.4.
8.2.2
Heatsink Weight
The boxed processor heatsink weighs no more than 450 grams. See Chapter 4.0 and Chapter 6.0 of
this document along with the Intel® XeonTM Processor Family Thermal Design Guidelines for
details on the processor weight and heatsink requirements.
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8.2.3
Retention Mechanism and Heatsink Supports
The boxed processor requires processor retention solution to secure the processor, the baseboard,
and the chassis. The retention solution contains one retention mechanisms and two retention clips
per processor. The boxed processor ships with retention mechanism, cooling solution retention
clips, and direct chassis attach screws. Baseboards and chassis designed for use by system
integrators should include holes that are in proper alignment with each other to support the boxed
processor. Refer to the Server System Infrastructure Specification (SSI-EEB) at http://
www.ssiforum.org for details on the hole locations. Please refer to the “Boxed integration notes” at
http://support.intel.com/support/processors/xeon for retention mechanism installation instructions.
Please reference Figure 45 for the dimmensions of the retention mechanism that ships with the
boxed processor. Please reference Figure 46 for a representation of the retention mechanism clip.
Retention mechanism clips must interface with the boxed processor retention mechanism area
shown in Detail A in Figure 45.
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Figure 45. Retention Mechanism
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Figure 46. Boxed Processor Clip
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Figure 47. Multiple View Space Requirements for the Boxed Processor
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8.2.4
Processor Wind Tunnel
The boxed processor ships with an active duct cooling solution called the Processor Wind Tunnel,
or PWT. This is an optional cooling solution that is designed to meet the thermal requirements of a
diverse combination of baseboards and chassis. It ships with the processor in order to reduce the
burden on the chassis manufacture to provide adequate airflow across the processor heatsink.
Manufacturers may elect to use their own cooling solution.
Note: Although Intel will be testing a select number of baseboard and chassis combinations for thermal
compliance, this is in no way a comprehensive test. It is ultimately the system integrator’s
responsibility to test that their solution meets all of the requirements specified in this document.
The PWT is meant to assist in processor cooling, but additional cooling techniques may be required
in order to ensure that the entire system meets the thermal requirements.
See Figure 49 and Figure 50 for the Processor Wind Tunnel dimensions.
8.2.5
8.2.6
Fan
The Processor Wind Tunnel includes a 25mm fan for use with processors <= 2.8 GHz, or a 38mm
fan for use with processors running at 3 GHz. The 38mm fan provides the high performance
required to meet the demanding thermal requirements of processors running at 3 GHz. The 38mm
fan provides local fan speed control. There is a temperature diode on the fan that measures the inlet
temperature to the fan and adjusts the speed accordingly. The benefit is that system manufacturers
can pass acoustical requirements while still being able to pass thermal requirements at maximum
ambient temperature
Fan Power Supply
The Processor Wind Tunnel includes a fan, which requires a constant +12V power supply. A fan
power cable is shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinouts are shown in Figure 48 and the fan cable
connector requirements are detailed in Table 58. Platforms must provide a matched power header
to support the boxed processor. Table 59 contains specifications for the input and output signals at
the fan heatsink connector. The fan heatsink outputs a SENSE signal, an open-collector output, that
pulses at a rate of two pulses per fan revolution. A baseboard pull-up resistor provides VOH to
match the baseboard-mounted fan speed monitor requirements, if applicable. Use of the SENSE
signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.
The power header on the baseboard must be positioned to allow the fan heatsink power cable to
reach it. The power header identification and location should be documented in the platform
documentation, or on the baseboard itself. The baseboard power header should be positioned
within 7 inches from the centre of the processor socket
Figure 48. Fan Connector Electrical Pin Sequence
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.
Table 58. Fan Cable Connector Requirements
Item
Specification
−
−
−
Fan connector must be a straight square pin, 3-pin terminal
housing with polarizing ribs and friction locking ramp.
Match with a straight pin, friction lock header on the
mainboard.
Connector Type
Manufacturer and part number or equivalent:
†
o
o
AMP : Fan connector: 643815-3, header: 640456-3
†
†
Walden / Molex : Fan connector: 22-01-3037,
header: 22-23-2031
−
−
−
Pin 1: Ground; black wire.
Pin 2: Power, +12 V; yellow wire.
Pin 3: Signal, Open collector tachometer output signal
requirement: 2 pulses per revolution; green wire.
Pin Out
(See Figure
Above)
The fan cable connector must reach a mating mainboard
connector at any point within a radius of 110 mm (4.33”)
measured from the central datum planes of the enabled
assembly (datum planes A, B & C on Drawing AXXXXX).
Fan power cable must be routed in such a way to prevent it from
contacting the fan impellor and it must be positioned in a
consistent location from unit to unit.
Fan cable length
(Drawing
747887):
Fan cable
routing
Table 59. Fan Power and Signal Specifications
Description
Min
Typ
Max
Unit
Notes
+12V: 12 Vot Fan Power Supply
IC: Fan Current Draw
6.0
12.0
13.2
V
1.5,400
A,mA
Pulses per fan
revolution
SENSE Frequency
2
1
NOTE:
1. Baseboard should pull this pin up to VCC with a resistor.
2. 1.5A is required for 3 GHz and 400 mA is required for frequencies 1.80 GHz and 2.80 GHz.
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Figure 49. Processor Wind Tunnel General Dimensions
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Figure 50. Processor Wind Tunnel Detailed Dimensions
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8.3
1U Rack Mount Server Solution
The 1U solution contains a passive heatsink and a foam pad, in addition to the retention solution
included with the other options. Because of the small form factor, the 1U heatsink is not as efficient
at dissipating heat as the general-purpose heatsink. In order to ensure maximum thermal efficiency,
the foam pad must be attached to the top of the 1U heatsink, blocking airflow between the heatsink
and the chassis cover. This will force air through the heatsink fins instead of allowing it to bypass
over the top. See Figure 51 and Figure 52 for more detail on installation.
Figure 51. Exploded View of the 1U Thermal Solution
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Figure 52. Assembled View of the 1U Thermal Solution
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8.4
Thermal Specifications
This section describes the cooling requirements of the heatsink solution utilized by the boxed
processor.
8.4.1
Boxed Processor Cooling Requirements
The boxed processor will be directly cooled with a passive heatsink. For the passive heatsink to
effectively cool the boxed processor, it is critical that sufficient, unimpeded, cool air flow over the
heatsink of every processor in the system. Meeting the processor's temperature specification is a
function of the thermal design of the entire system, and ultimately the responsibility of the system
integrator. The processor temperature specification is found in Chapter 6.0. It is important that
system integrators perform thermal tests to verify that the boxed processor is kept below its
maximum temperature specification in a specific baseboard and chassis.
At an absolute minimum, the boxed processor heatsink will require 500 Linear Feet per Minute
(LFM) of cool air flowing over the heatsink. The airflow must be directed from the outside of the
chassis directly over the processor heatsinks in a direction passing from one retention mechanism
to the other. It also should flow from the front to the back of the chassis. Directing air over the
passive heatsink of the boxed Product Name processor can be done with auxiliary chassis fans, fan
ducts, or other techniques.
It is also recommended that the ambient air temperature outside of the chassis be kept at or below
35 °C. The air passing directly over the processor heatsink should not be preheated by other system
components (such as another processor), and should be kept at or below 45 °C. Again, meeting the
processor's temperature specification is the responsibility of the system integrator. The processor
temperature specification is found in Chapter 6.0.
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9.0
Debug Tools Specifications
The Debug Port design information has been moved. This includes all information necessary to
develop a Debug Port on this platform, including electrical specifications, mechanical
requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700
Debug Port Design Guide for the design of your platform.
9.1
Logic Analyzer Interface (LAI)
Intel® is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for
use in debugging systems. Tektronix* and Agilent* should be contacted to get specific information
about their logic analyzer interfaces. The following information is general in nature. Specific
information must be obtained from the logic analyzer vendor.
Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture
front side bus signals. There are two sets of considerations to keep in mind when designing a
system that can make use of an LAI: mechanical and electrical.
9.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI pins plug into the
socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI
egresses the system to allow an electrical connection between the processor and a logic analyzer.
The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable
egress restrictions, should be obtained from the logic analyzer vendor. System designers must
make sure that the keepout volume remains unobstructed inside the system. Note that it is possible
that the keepout volume reserved for the LAI may differ from the space normally occupied by the
processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as
part of the LAI.
9.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the front side bus; therefore, it is critical to
obtain electrical load models from each of the logic analyzers to be able to run system level
simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for
electrical specifications and load models for the LAI solution they provide.
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