RN80532KE072512_技术文档

Intel^®Xeon^™Processor with 533 MHz

Front Side Bus at 2 GHz to 3.06 GHz

Product Features

• Available at 2, 2.40, 2.66, 2.80, and 3.06 GHz

• 512 KB Advanced Transfer L2 Cache (on-die,

full speed Level 2 cache) with 8-way

• Dual processing server/workstation support

associativity and Error Correcting Code (ECC)

• Binary compatible with applications running on

previous members of Intel’s IA32

microprocessor line

• Enables system support of up to 64 GB of

physical memory

• Intel^®NetBurst™ micro-architecture

• Hyper-Threading Technology

• Streaming SIMD Extensions 2 (SSE2)

— 144 new instructions for double-precision

floating point operations, media/video

streaming, and secure transactions

— Hardware support for multithreaded

applications

• Enhanced floating point and multimedia unit for

enhanced video, audio, encryption, and 3D

performance

• Power Management capabilities

— System Management mode

— Multiple low-power states

• Advanced System Management Features

— Thermal Monitor

• 533 MHz Front Side Bus

— Bandwidth up to 4.3 GB/second

• Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor core

frequency

• Hyper Pipelined Technology

• Advance Dynamic Execution

— Very deep out-of-order execution

— Enhanced branch prediction

— Machine Check Architecture (MCA)

• Level 1 Execution Trace Cache stores 12 K

micro-ops and removes decoder latency from

main execution loops

— Includes 8 KB Level 1 data cache

The Intel^®Xeon™ Processor with 533 MHz Front Side Bus is designed for high-performance

dual-processor workstation and server applications. Based on the Intel^®NetBurst™ micro-

architecture and the new Hyper-Threading Technology, it is binary compatible with previous

Intel Architecture (IA-32) processors. The Intel Xeon processor with 533 MHz Front Side Bus is

scalable to two processors in a multiprocessor system providing exceptional performance for

applications running on advanced operating systems such as Windows XP*, Windows* 2000,

Linux*, and UNIX*.

The Intel Xeon processor with 533 MHz Front

Side Bus delivers compute power at unparalleled

value and flexibility for powerful workstations,

internet infrastructure, and departmental server

applications. The Intel^®NetBurst™ micro-

architecture and Hyper-Threading Technology

deliver outstanding performance and headroom

for peak internet server workloads, resulting in

faster response times, support for more users, and

improved scalability.

Document Number: 252135-003

March 2003

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

*Other names and brands may be claimed as the property of others.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel^®Xeon™ processor may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.MPEG is an international standard for video compression/

decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities,

including Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademark or registered trademarks of Intel Corporation or its subsidiaries in the

United States and other countries.

2

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Contents

1.0

Introduction.........................................................................................................................7

1.1

Terminology...........................................................................................................8

1.1.1 Processor Packaging Terminology...........................................................8

State of Data .........................................................................................................9

References..........................................................................................................10

1.2

1.3

2.0

Electrical Specifications....................................................................................................11

2.1

2.2

2.3

Front Side Bus and GTLREF ..............................................................................11

Power and Ground Pins ......................................................................................11

Decoupling Guidelines ........................................................................................11

2.3.1 VCC Decoupling.....................................................................................12

2.3.2 Front Side Bus AGTL+ Decoupling........................................................12

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking................................12

2.4.1 Bus Clock ...............................................................................................13

PLL Filter.............................................................................................................13

2.5.1 Mixing Processors..................................................................................15

Voltage Identification..........................................................................................15

2.6.1 Mixing Processors of Different Voltages ................................................16

Reserved Or Unused Pins...................................................................................17

Front Side Bus Signal Groups.............................................................................17

Asynchronous GTL+ Signals...............................................................................19

Maximum Ratings................................................................................................19

Processor DC Specifications...............................................................................19

AGTL+ Front Side Bus Specifications.................................................................26

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

3.0

Mechanical Specifications................................................................................................29

3.1

3.2

3.3

3.4

3.5

3.6

3.7

Mechanical Specifications...................................................................................30

Processor Package Load Specifications.............................................................35

Insertion Specifications .......................................................................................36

Mass Specifications.............................................................................................36

Materials..............................................................................................................36

Markings..............................................................................................................37

Pin-Out Diagram..................................................................................................38

4.0

Pin Listing and Signal Definitions.....................................................................................41

4.1

4.2

Processor Pin Assignments ................................................................................41

4.1.1 Pin Listing by Pin Name .........................................................................41

4.1.2 Pin Listing by Pin Number......................................................................50

Signal Definitions.................................................................................................60

5.0

6.0

Thermal Specifications.....................................................................................................69

5.1

5.2

Thermal Specifications........................................................................................70

Measurements for Thermal Specifications.........................................................72

5.2.1 Processor Case Temperature Measurement .........................................72

Features ...........................................................................................................................73

6.1

6.2

Power-On Configuration Options ........................................................................73

Clock Control and Low Power States..................................................................73

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

3

6.2.1 Normal State—State 1 ...........................................................................73

6.2.2 AutoHALT Powerdown State—State 2 ..................................................74

6.2.3 Stop-Grant State—State 3 .....................................................................74

6.2.4 HALT/Grant Snoop State—State 4 ........................................................75

6.2.5 Sleep State—State 5..............................................................................75

6.2.6 Bus Response During Low Power States ..............................................76

Thermal Monitor..................................................................................................76

6.3.1 Thermal Diode........................................................................................77

6.3

7.0

Boxed Processor Specifications.......................................................................................79

7.1

7.2

Introduction .........................................................................................................79

Mechanical Specifications...................................................................................80

7.2.1 Boxed Processor Heatsink Dimensions .................................................80

7.2.2 Boxed Processor Heatsink Weight.........................................................80

7.2.3 Boxed Processor Retention Mechanism and Heatsink Supports...........80

Boxed Processor Requirements .........................................................................84

7.3.1 Intel® Xeon™ Processor with 533 MHz Front Side Bus........................84

7.3.2 1U Rack Mount Server Solution.............................................................88

Thermal Specifications........................................................................................90

7.4.1 Boxed Processor Cooling Requirements ...............................................90

7.3

7.4

8.0

Debug Tools Specifications..............................................................................................91

8.1

Logic Analyzer Interface (LAI).............................................................................91

8.1.1 Mechanical Considerations ....................................................................91

8.1.2 Electrical Considerations........................................................................91

Figures

1

2

3

Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................14

Phase Lock Loop (PLL) Filter Requirements ......................................................14

Intel® Xeon™ processor with 533 MHz Front Side Bus Voltage-

Current Projections (VID 1.5V)............................................................................22

4

Intel Xeon processor with 533 MHz Front Side Bus Voltage-Current

Projections (VID 1.525V).....................................................................................23

Electrical Test Circuit ..........................................................................................27

THERMTRIP# to VCC Timing.............................................................................27

FC-mPGA2 Processor Package Assembly Drawing...........................................29

FC-mPGA Processor Package Top View: Component Placement Detail...........30

Intel® Xeon™ Processor with 533 MHz Front Side Bus in the

5

6

7

8

9

FC-mPGA2 Package Drawing ............................................................................31

FC-mPGA2 Processor Package Top View: Component Height Keep-in............32

FC-mPGA2 Processor Package Cross Section View: Pin Side

10

11

Component Keep-in ............................................................................................33

FC-mPGA2 Processor Package: Pin Detail........................................................34

IHS Flatness and Tilt Drawing.............................................................................35

Processor Top-Side Markings.............................................................................37

Processor Bottom-Side Markings........................................................................37

Processor Pin Out Diagram: Top View ...............................................................38

Processor Pin Out Diagram: Bottom View ..........................................................39

Processor with Thermal and Mechanical Components - Exploded View............69

Processor Thermal Design Power vs Electrical Projections for VID = 1.500V... 70

12

13

14

15

16

17

18

19

4

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

20

21

22

23

24

25

26

27

28

29

30

31

Processor Thermal Design Power vs Electrical Projections for VID = 1.525V....71

Thermal Measurement Point for Processor TCASE............................................72

Stop Clock State Machine...................................................................................74

Mechanical Representation of the Boxed Processor Passive Heatsink..............79

Boxed Processor Retention Mechanism and Clip...............................................81

Boxed Processor Retention Mechanism that Ships with the Processor..............82

Multiple View Space Requirements for the Boxed Processor.............................83

Fan Connector Electrical Pin Sequence.............................................................85

Processor Wind Tunnel General Dimensions .....................................................86

Processor Wind Tunnel Detailed Dimensions.....................................................87

Exploded View of the 1U Thermal Solution.........................................................88

Assembled View of the 1U Thermal Solution......................................................89

Tables

1

2

3

4

5

6

7

8

Front Side Bus-to-Core Frequency Ratio............................................................13

Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]....................13

Voltage Identification Definition...........................................................................16

Front Side Bus Signal Groups.............................................................................18

Processor Absolute Maximum Ratings ...............................................................19

Voltage and Current Specifications.....................................................................21

Front Side Bus Differential BCLK Specifications.................................................23

AGTL+ Signal Group DC Specifications .............................................................24

TAP and PWRGOOD Signal Group DC Specifications.......................................24

Asynchronous GTL+ Signal Group DC Specifications ........................................25

BSEL[1:0] and VID[4:0] DC Specifications..........................................................25

AGTL+ Bus Voltage Definitions...........................................................................26

Miscellaneous Signals + Specifications ..............................................................27

Dimensions for the Intel® Xeon™ Processor with 533 MHz Front

9

10

11

12

13

14

Side Bus in the FC-mPGA2 Package..................................................................32

Package Dynamic and Static Load Specifications ..............................................35

Processor Mass...................................................................................................36

Processor Material Properties.............................................................................36

Pin Listing by Pin Name ......................................................................................41

Pin Listing by Pin Number...................................................................................50

Signal Definitions.................................................................................................60

Processor Thermal Design Power.......................................................................70

Power-On Configuration Option Pins ..................................................................73

Thermal Diode Parameters .................................................................................77

Thermal Diode Interface......................................................................................78

Fan Cable Connector Requirements...................................................................85

Fan Power and Signal Specifications..................................................................85

15

16

17

38

39

41

42

43

44

45

46

47

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

5

Revision History

Revision

Date of Release

Description

No.

November 2002

-001

Initial Release

Added 3.06 GHz information.

Edited definitions with current terminology.

Added two TDP loadline figures in chapter 6.

Edited figures 18 and 19.

Added notes to signal definition tables for symmetric agents.

Edited Chapter 8.0 Boxed Processor Specifications.

February 2003

March 2003

-002

-003

Deleted Chapter 3 and Removed Section 2.13, 2.14

Added Table 13

6

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

1.0

Introduction

The Intel^®Xeon™ Processor with 533 MHz Front Side Bus is based on the Intel^®NetBurst™

micro-architecture, which operates at significantly higher clock speeds and delivers performance

levels that are significantly higher than previous generations of IA-32 processors. While based on

the Intel NetBurst micro-architecture, it maintains the tradition of compatibility with IA-32

software.

The Intel NetBurst micro-architecture features begin with innovative techniques that enhance

processor execution such as Hyper Pipelined Technology, a Rapid Execution Engine, Advanced

Dynamic Execution, enhanced Floating Point and Multimedia unit, and Streaming SIMD

Extensions 2 (SSE2). The Hyper Pipelined Technology doubles the pipeline depth in the processor,

allowing the processor to reach much higher core frequencies. The Rapid Execution Engine allows

the two integer ALUs in the processor to run at twice the core frequency, which allows many

integer instructions to execute in one half of the internal core clock period. The Advanced Dynamic

Execution improves speculative execution and branch prediction internal to the processor. The

floating point and multi-media units have been improved by making the registers 128 bits wide and

adding a separate register for data movement. Finally, SSE2 adds 144 new instructions for double-

precision floating point, SIMD integer, and memory management for improvements in video/

multimedia processing, secure transactions, and visual internet applications.

Also part of the Intel NetBurst micro-architecture, the front side bus and caches on the Intel Xeon

processor with 533 MHz Front Side Bus provide tremendous throughput for server and workstation

workloads. The 533 MHz Front Side Bus provides a high-bandwidth pipeline to the system

memory and I/O. It is a quad-pumped bus running off a 133 MHz Front Side Bus clock making

4.3 Gigabytes per second (4,300 Megabytes per second) data transfer rates possible. The Execution

Trace Cache is a level 1 cache that stores approximately twelve thousand decoded micro-

operations, which removes the decoder latency from the main execution path and increases

performance. The Advanced Transfer Cache is a 512 KB on-die level 2 cache running at the speed

of the processor core providing increased bandwidth over previous micro-architectures.

In addition to the Intel NetBurst micro-architecture, the Intel Xeon processor with 533 MHz Front

Side Bus includes a groundbreaking new technology called Hyper-Threading technology, which

enables multi-threaded software to execute tasks in parallel within the processor resulting in a more

efficient, simultaneous use of processor resources. Server applications can realize increased

performance from Hyper-Threading technology today, while workstation applications are expected

to benefit from Hyper-Threading technology in the future through software and processor

evolution. The combination of Intel NetBurst micro-architecture and Hyper-Threading technology

delivers outstanding performance, throughput, and headroom for peak software workloads

resulting in faster response times and improved scalability.

The Intel Xeon processor with 533 MHz Front Side Bus is intended for high performance worksta-

tion and server systems with up to two processors on a single bus. The processor supports both uni-

and dual-processor designs. The Intel Xeon with 533 MHz Front Side Bus processors do not incor-

porate system managment devices (PIROM, OEM Scratchpad EEPROM, and thermal sensor), but

offer direct access to the pins of an on-die thermal diode. These output pins can interface with a

thermal sensor device that is placed on the baseboard. The Intel Xeon processor with 533 MHz

Front Side Bus is packaged in a 604-pin flip chip micro-PGA2 (FC-mPGA2) package, and utilizes

a surface mount ZIF socket with 604 pins.

The FC-mPGA2 package contains an extra pin (located at location AE30) compared to the INT-

mPGA package. This additional pin serves as a keying mechanism to prevent the FC-mPGA2

package from being installed in the 603-pin socket since processors in the FC-mPGA2 package are

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

7

only supported in the 604-pin socket. Since the additional contact for pin AE30 is electrically inert,

the 604-pin socket will not have a solder ball at this location.

Mechanical components used for attaching thermal solutions to the baseboard should have a high

degree of commonality with the thermal solution components enabled for the Intel Xeon processor

Heatsinks and retention mechanisms have been designed with manufacturability as a high priority.

Hence, mechanical assembly can be completed from the top of the baseboard.

The Intel Xeon processor with 533 MHz Front Side Bus uses a scalable front side bus protocol

referred to as the “Front Side Bus” in this document. The processor front side bus utilizes a split-

transaction, deferred reply protocol similar to that introduced by the Pentium^®Pro processor Front

Side Bus, but is not compatible with the Pentium Pro processor front side bus. The Intel Xeon

processor with 533 MHz Front Side Bus is compatible with the Intel Xeon processor Front Side

Bus. The front side bus uses Source-Synchronous Transfer (SST) of address and data to improve

performance, and transfers data four times per bus clock (4X data transfer rate). Along with the 4X

data bus, the address bus can deliver addresses two times per bus clock and is referred to as a

‘double-clocked’ or 2X address bus. In addition, the Request Phase completes in one clock cycle.

Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 4.3

Gigabytes per second. Finally, the front side bus also introduces transactions that are used to

deliver interrupts.

Signals on the front side bus use Assisted GTL+ (AGTL+) level voltages which are fully described

in the appropriate platform design guide (refer to Section 1.3).

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted

state when driven to a low level. For example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where

the name does not imply an active state but describes part of a binary sequence (such as address or

data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a

hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

Front Side Bus (FSB): The electrical interface that connects the processor to the chipset. Also

referred to as the processor system bus or the system bus. All memory and I/O transactions as well

as interrupt messages pass between the processor and chipset over the FSB.

1.1.1

Processor Packaging Terminology

Commonly used terms are explained here for clarification:

• 604-pin socket - The 604-pin socket contains an additional contact to accept the additional

keying pin on the Intel Xeon processor in the FC-mPGA2 packages at pin location AE30. The

604-pin socket will also accept processors with the INT-mPGA package. Since the additional

contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this

location. Therefore, the additional keying pin will not require a baseboard via nor a surface-

mount pad. See the mPGA604 Socket Design Guidelines for details regarding this socket.

• Central Agent - The central agent is the host bridge to the processor and is typically known as

the chipset.

8

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

• Flip Chip Ball Grid Array (FC-BGA) - Microprocessor packaging using “flip chip” design,

where the processor is attached to the substrate face-down for better signal integrity, more

efficient heat removal and lower inductance.

• FC-mPGA2 - Packaging technology with the processor die mounted directly to a micro-Pin

Grid Array substrate with an integrated heat spreader (IHS).

• Front Side Bus - Front Side Bus (FSB) is the electrical interface that connects the processor to

the chipset. Also referred to as the processor system bus or the system bus. All memory and

I/O transactions as well as interrupt messages pass between the processor and chipset over the

FSB.

• Intel^®Xeon™ processor with 512 KB L2 cache - The entire processor in its INT-mPGA

package, including processor core in its FC-BGA package, integrated heat spreader (IHS), and

interposer.

• Intel^®Xeon™ processor with 533 MHz Front Side Bus - The entire processor in its FC-

mPGA2 package, including processor core in its FC-BGA package, integrated heat spreader

(IHS), and interposer.

• Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal

solution to the processor.

• Interposer - The structure on which the processor core package and I/O pins are mounted.

• OEM - Original Equipment Manufacturer.

• Processor core - The processor’s execution engine. All AC timing and signal integrity

specifications are to the pads of the processor core.

• Retention mechanism - The support components that are mounted through the baseboard to

the chassis to provide mechanical retention for the processor and heatsink assembly.

• Symmetric Agent - A symmetric agent is a processor which shares the same I/O subsystem

and memory array, and runs the same operating system as another processor in a system.

Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems.

Intel^®Xeon™ (DP - Dual Processor) processors should only be used in SMP systems which

have two or fewer symmetric agents.

1.2

State of Data

The data contained in this document is subject to change. It is the best information that Intel is able

to provide at the publication date of this document.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

9

1.3

References

The reader of this specification should also be familiar with material and concepts presented in the

following documents:.

Document

Intel Order Number¹

AP-485, Intel® Processor Identification and the CPUID Instruction

241618

IA-32 Intel ® Architecture Software Developer's Manual

• Volume I: Basic Architecture

245470

245471

245472

• Volume II: Instruction Set Reference

• Volume III: System Programming Guide

Intel ® Xeon^TMProcessor with 512-KB L2 Cache and Intel^®E7505 Chipset

Platform Design Guide

http://developer.intel.com

Intel® Xeon™ Processor Thermal Design Guidelines

603 -Pin Socket Design Guidelines

298348

249672

11299

mPGA604 Socket Design Guidelines

Intel® Xeon™ Processor Specification Update

CK00 Clock Synthesizer/Driver Design Guidelines

VRM 9.0 DC-DC Converter Design Guidelines

VRM 9.1 DC-DC Converter Design Guidelines

249678

249206

249205

298646

Dual Intel® Xeon^TMProcessor Voltage Regulator Down (VRD) Design

Guidelines

298644

249679

ITP700 Debug Port Design Guide

Intel® Xeon™ Processor with 533 MHz Front Side Bus System Compatibility

Guidelines

Intel® Xeon™ Processor with 533 MHz Front Side Bus Signal Integrity

Models

http://developer.intel.com

Intel® Xeon™ Processor with 533 MHz Front Side Bus Mechanical Models in

ProE* Format

IIntel® Xeon™ Processor with 533 MHz Front Side Bus Mechanical Models

in IGES* Format

Intel® Xeon™ Processor with 512-KB L2 Cache Front Side Bus Thermal

Models (FloTherm* and ICEPAK* format)

Intel® Xeon™ Processor with 533 MHz Front Side Bus Core Boundary Scan

Descriptor Language (BSDL) Model

http://developer.intel.com

Wired for Management 2.0 Design Guide

Boxed Integration Notes

http://support.intel.com/

support/processors/xeon

NOTES:

1. Contact your Intel representative for the latest revision of documents without order numbers.

10

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

2.0

Electrical Specifications

2.1

Front Side Bus and GTLREF

Most Intel^®Xeon™ Processor with 533MHz Front Side Bus signals use Assisted Gunning

Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved

noise margins and reduced ringing through low voltage swings and controlled edge rates. The

processor termination voltage level is V_CC, the operating voltage of the processor core. The use of a

termination voltage that is determined by the processor core allows better voltage scaling on the

processor front side bus. Because of the speed improvements to data and address busses, signal

integrity and platform design methods become more critical than with previous processor families.

Front side bus design guidelines are detailed in the appropriate platform design guide (refer to

Section 1.3).

The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to

determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See

Table 12 for GTLREF specifications). Termination resistors are provided on the processor silicon

and are terminated to its core voltage (V_CC). The on-die termination resistors are a selectable

feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination

can be enabled to control reflections on the transmission line. For middle bus agents, on-die

termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating

the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to Section 2.12 for

details on ODTEN resistor termination requirements.

Note: Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard.

See Table 4 for details regarding these signals.

The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+

signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the

front side bus, including trace lengths, is highly recommended when designing a system. Please

refer to http://developer.intel.com to obtain the Intel^®Xeon™ Processor with 533 MHZ Front Side

Bus Signal Integrity Models.

2.2

2.3

Power and Ground Pins

For clean on-chip power distribution, the Intel Xeon processor with 533 MHz Front Side Bus has

190 V_CC(power) and 189 V_SS(ground) inputs. All V_CCpins must be connected to the system power

plane, while all V_SSpins must be connected to the system ground plane. The processor V_CCpins

must be supplied the voltage determined by the processor VID (Voltage ID) pins.

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large average current swings between low and full power states. This may cause

voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.

Larger bulk storage (C_BULK), such as electrolytic capacitors, supply current during longer lasting

changes in current demand by the component, such as coming out of an idle condition. Similarly,

they act as a storage well for current when entering an idle condition from a running condition.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

11

Care must be taken in the baseboard design to ensure that the voltage provided to the processor

remains within the specifications listed in Table 6. Failure to do so can result in timing violations or

reduced lifetime of the component. For further information and guidelines, refer to the appropriate

platform design guidelines.

2.3.1

V_CCDecoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and the baseboard designer must ensure a low interconnect resistance from the regulator (or VRM

pins) to the 604-pin socket. Bulk decoupling may be provided on the voltage regulation module

(VRM) to meet help meet the large current swing requirements. The remaining decoupling is

provided on the baseboard. The power delivery path must be capable of delivering enough current

while maintaining the required tolerances (defined in Table 6). For further information regarding

power delivery, decoupling, and layout guidelines, refer to the appropriate platform design

guidelines.

2.3.2

Front Side Bus AGTL+ Decoupling

The Intel^®Xeon™ processor with 533MHz Front Side Bus integrates signal termination on the die

as well as part of the required high frequency decoupling capacitance on the processor package.

However, additional high frequency capacitance must be added to the baseboard to properly

decouple the return currents from the front side bus. Bulk decoupling must also be provided by the

baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate

platform design guidelines.

2.4

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor core frequency is a multiple of the

BCLK[1:0] frequency. The maximum processor bus ratio multiplier will be set during

manufacturing. The default setting will equal the maximum speed for the processor.

The BCLK[1:0] inputs directly control the operating speed of the front side bus interface. The

processor core frequency is configured during reset by using values stored internally during

manufacturing. The stored value sets the highest bus fraction at which the particular processor can

operate.

Clock multiplying within the processor is provided by the internal PLL, which requires a constant

frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC

specifications for the BCLK[1:0] inputs are provided in Table 7 and Table 13, respectively. These

specifications must be met while also meeting signal integrity requirements as outlined in Chapter

3.0. The processor utilizes a differential clock. Details regarding BCLK[1:0] driver specifications

are provided in the CK408 Clock Synthesizer/Driver Design Guidelines.^.Table 1 contains the sup-

ported bus fraction ratios and their corresponding core frequencies.

12

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Intel® Xeon™ Processor with 533 MHz Front Side Bus

Table 1. Front Side Bus-to-Core Frequency Ratio

Front Side Bus-to-Core

Frequency Ratio

Core Frequency

1/15

1/18

1/20

1/21

1/23

2 GHz

2.40 GHz

2.66 GHz

2.80 GHz

3.06 GHz

2.4.1

Bus Clock

The front side bus frequency is set to the maximum supported by the individual processor.

BSEL[1:0] are outputs used to select the front side bus frequency. Table 2 defines the possible

combinations of the signals and the frequency associated with each combination. The frequency is

determined by the processor(s), chipset, and clock synthesizer. All front side bus agents must

operate at the same frequency. Individual processors will only operate at their specified front side

bus clock frequency, (100 MHz for present generation processors).

The Intel® Xeon ^TMprocessor with a 533 MHz Front Side Bus is designed to run on a baseboard

with a 133 MHz bus clock.. On these baseboards, BSEL[0:1] are considered ‘reserved’ at the

processor socket. .

Table 2. Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]

BSEL1

BSEL0

Bus Clock Frequency

L

H

L

100 MHz

133 MHz

Reserved

H

2.5

PLL Filter

V_CCAand V_CCIOPLLare power sources required by the processor PLL clock generator. This

requirement is identical to that of the Intel Xeon processor with 512-KB L2 cache. Since these

PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is

detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e.

maximum frequency). To prevent this degradation, these supplies must be low pass filtered from

V_CC. A typical filter topology is shown in Figure 1.

The AC low-pass requirements, with input at V_CCand output measured across the capacitor (C_Aor

C

_IOin Figure 1), is as follows:

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

Datasheet

13

The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter

refer to the appropriate platform design guidelines.

Figure 1. Typical V_CCIOPLL, V_CCAand V_SSAPower Distribution

Trace < 0.02 Ω

Processor interposer "pin"

VCC

L1/L2

R-Socket

R-Trace

VCCA

PLL

C

Baseboard via that connects

filter to VCC plane

Socket pin

Processor

VSSA

C

R-Socket

VCCIOPLL

L1/L2

Figure 2. Phase Lock Loop (PLL) Filter Requirements

0.2 dB

0 dB

-0.5 dB

forbidden

zone

-28 dB

forbidden

zone

-34 dB

fpeak

fcore

DC

passband

1 Hz

1 MHz

66 MHz

high frequency

band

14

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

NOTES:

1. Diagram not to scale.

2. No specifications for frequencies beyond f_core(core frequency).

3. f_peak, if existent, should be less than 0.05 MHz.

2.5.1

Mixing Processors

Intel only supports those processor combinations operating with the same front side bus frequency,

core frequency, VID settings, and cache sizes. Not all operating systems can support multiple

processors with mixed frequencies. Intel does not support or validate operation of processors with

different cache sizes. Mixing processors of different steppings but the same model (as per CPUID

instruction) is supported, and is outlined in the Intel® Xeon™ Processor Specification Update.

Additional details are provided in AP-485, the Intel Processor Identification and the CPUID

Instruction application note.

The Intel Xeon processor with 533 MHz Front Side Bus does not sample the pins IGNNE#,

LINT[0]/INTR, LINT[1]/NMI, and A20M# to establish the core to front side bus ratio. Rather, the

processor runs at its tested frequency at initial power-on. If the processor needs to run at a lower

core frequency, as must be done when a higher speed processor is added to a system that contains a

lower frequency processor, the system BIOS is able to effect the change in the core to front side bus

ratio.

2.6

Voltage Identification

The VID specification for the processor is defined in this datasheet, and is supported by power

TM

delivery solutions designed according to the Dual Intel® Xeon

Processor Voltage Regulator

Down (VRD) Design Guidelines, VRM 9.0 DC-DC Converter Design Guidelines, and VRM 9.1

DC-DC Converter Design Guidelines. The minimum voltage is provided in Table 6, and varies

with processor frequency. This allows processors running at a higher frequency to have a relaxed

minimum voltage specification. The specifications have been set such that one voltage regulator

design can work with all supported processor frequencies.

Note that the VID pins will drive valid and correct logic levels when the Intel^®Xeon™ processor

with 533 MHz Front Side Bus is provided with a valid voltage applied to the SM_V_CCpins.

VID_V_CCmust be correct and stable prior to enabling the output of the VRM that supplies

V_CC. Similarly, the output of the VRM must be disabled before VID_V_CCbecomes invalid.

Refer to Figure 17 for details.

The processor uses five voltage identification pins, VID[4:0], to support automatic selection of

processor voltages. Table 3 specifies the voltage level corresponding to the state of VID[4:0]. A ‘1’

in this table refers to a high voltage and a ‘0’ refers to low voltage level. If the processor socket is

empty (VID[4:0] = 11111), or the VRD or VRM cannot supply the voltage that is requested, it must

disable its voltage output. For further details, see the Dual Intel® Xeon^TMProcessor Voltage

Regulator Down (VRD) Design Guidelines, or VRM 9.0 DC-DC Converter Design Guidelines or

the VRM 9.1 DC-DC Converter Design Guidelines.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

15

Table 3. Voltage Identification Definition

Processor Pins

VID4

VID3

VID2

VID1

VID0

V_{CC_VID}(V)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VRM output off

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

2.6.1

Mixing Processors of Different Voltages

Mixing processors operating with different VID settings (voltages) is not supported and will not be

validated by Intel.

16

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

2.7

Reserved Or Unused Pins

All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to

V_CC, V_SS, or to any other signal (including one another) can result in component malfunction or

incompatibility with future processors. See Chapter 5.0 for a pin listing of the processor and for the

location of all Reserved pins.

For reliable operation, unused inputs or bidirectional signals should always be connected to an

appropriate signal level. In a system-level design, on-die termination has been included on the

processor to allow signal termination to be accomplished by the processor silicon. Most unused

AGTL+ inputs should be left as no connects, as AGTL+ termination is provided on the processor

silicon. However, see Table 4 for details on AGTL+ signals that do not include on-die termination.

Unused active high inputs should be connected through a resistor to ground (V_SS). Unused outputs

can be left unconnected, however this may interfere with some TAP functions, complicate debug

probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional

signals to power or ground. When tying any signal to power or ground, a resistor will also allow for

system testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same value

for the on-die termination resistors (R_TT). See Table 12.

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die

termination. Inputs and all used outputs must be terminated on the baseboard. Unused outputs may

be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated

may interfere with some TAP functions, complicate debug probing, and prevent boundary scan

testing. Signal termination for these signal types is discussed in the ITP700 Debug Port Design

Guide.

All TESTHI[6:0] pins should be individually connected to V_CCvia a pull-up resistor which

matches the trace impedance within ±10 Ω. TESTHI[3:0] and TESTHI[6:5] may all be tied

together and pulled up to V_CCwith a single resistor if desired. However, utilization of boundary

scan test will not be functional if these pins are connected together. TESTHI4 must always be

pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-up

resistor values used for TESTHI[6:0] pins should have a resistance value within 20 percent of the

impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 Ω,

then a pull-up resistor value between 40 and 60 Ω should be used. The TESTHI[6:0] termination

recommendations provided in the Intel® Xeon^TMProcessor Datasheet are also suitable for the

Intel^®Xeon™ processor with 533 MHz Front Side Bus. However, Intel recommends new designs

or designs undergoing design updates follow the trace impedance matching termination guidelines

outlined in this section.

2.8

Front Side Bus Signal Groups

In order to simplify the following discussion, the front side bus signals have been combined into

groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as

a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as

well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+

output group as well as the AGTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of

timing parameters. One set is for common clock signals whose timings are specified with respect to

rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source

synchronous signals which are relative to their respective strobe lines (data and address) as well as

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

17

rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can

become active at any time during the clock cycle. Table 4 identifies which signals are common

clock, source synchronous and asynchronous.

Table 4. Front Side Bus Signal Groups

Signal Group

Type

Signals ¹

BPRI#, BR[3:1]#^3,4, DEFER#, RESET#⁴,

RS[2:0]#, RSP#, TRDY#

AGTL+ Common Clock Input

Synchronous to BCLK[1:0]

ADS#, AP[1:0]#, BINIT#⁷, BNR#⁷,

AGTL+ Common Clock I/O

Synchronous to BCLK[1:0]

BPM[5:0]#², BR0#², DBSY#, DP[3:0]#,

DRDY#, HIT#⁷, HITM#⁷, LOCK#, MCERR#⁷

Signals

Associated Strobe

REQ[4:0]#,A[16:3]#⁶

A[35:17]#⁵

ADSTB0#

ADSTB1#

AGTL+ Source Synchronous

I/O

Synchronous to assoc.

strobe

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

AGTL+ Strobes

Synchronous to BCLK[1:0]

Asynchronous

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

A20M#⁵, IGNNE#⁵, INIT#⁶, LINT0/INTR⁵,

LINT1/NMI⁵, SLP#, STPCLK#

Asynchronous GTL+ Input ⁴

Asynchronous GTL+ Output ⁴Asynchronous

FERR#, IERR#, THERMTRIP#, PROCHOT#

Front Side Bus Clock

TAP Input ²

Clock

BCLK1, BCLK0

TCK, TDI, TMS, TRST#

TDO

Synchronous to TCK

TAP Output ²

BSEL[1:0], COMP[1:0], GTLREF, ODTEN,

Reserved, SKTOCC#, TESTHI[6:0],VID[4:0],

V

Power/Other

_CC, VID_V_CC⁸, V_CCA, V_CCIOPLL, V_SSA, V_SS

,

V_CCSENSE, V_SSSENSE,PWRGOOD

NOTES:

1. Refer to Section 5.2 for signal descriptions.

2. These signal groups are not terminated by the processor. Refer the ITP700 Debug Port Design Guide and

corresponding Design Guide for termination requirements and further details.

3. The Intel^®Xeon™ processor with 533MHz Front Side Bus utilizes only BR0# and BR1#. BR2# and BR3# are

not driven by the processor but must be terminated to V_CC. For additional details regarding the BR[3:0]#

signals, see Section 5.2 and Section 7.1 and the appropriate Platform Design Guidelines.

4. These signals do not have on-die termination. Refer to corresponding Platform Design Guidelines for

termination requirements.

5. Note that Reset initialization function of these pins is now a software function on the Intel^®Xeon™

processor with 533MHz Front Side Bus.

6. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration

options. See Section 7.1 for details.

7. These signals may be driven simultaneously by multiple agents (wired-or).

8. VID_Vcc is required for correct VID logic operation of the Intel^®Xeon™ processor with 533 MHz Front Side

Bus. Refer to Figure 17 for details.

18

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

2.9

Asynchronous GTL+ Signals

The Intel^®Xeon™ Processor with 533 MHz Front Side Bus does not utilize CMOS voltage levels

on any signals that connect to the processor silicon. As a result, legacy input signals such as

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SLP#, and STPCLK# utilize GTL+ input

buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals IERR#, THERMTRIP# and

PROCHOT# utilize GTL+ output buffers. All of these asynchronous GTL+ signals follow the same

DC requirements as AGTL+ signals, however the outputs are not driven high (during the logical 0-

to-1 transition) by the processor (the major difference between GTL+ and AGTL+). Asynchronous

GTL+ signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all

of the asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for

the processor to recognize them. See Table 10 for the DC specifications for the asynchronous

GTL+ signal groups.

2.10

Maximum Ratings

Table 5 lists the processor’s maximum environmental stress ratings. Functional operation at the

absolute maximum and minimum is neither implied nor guaranteed. The processor should not

receive a clock while subjected to these conditions. Functional operating parameters are listed in

the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.

Furthermore, although the processor contains protective circuitry to resist damage from static

electric discharge, one should always take precautions to avoid high static voltages or electric

fields.

Table 5. Processor Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

T_STORAGE

Processor storage temperature

-40

85

°C

2

Any processor supply voltage with

respect to V^SS

V_CC

-0.3

-0.1

1.75

V

1

AGTL+ buffer DC input voltage with

respect to V^SS

V_inAGTL+

Async GTL+ buffer DC input voltage

with respect to Vss

V_inGTL+

I_VID

1.75

5

V

Max VID pin current

mA

1. This rating applies to any pin of the processor.

2. Contact Intel for storage requirements in excess of one year.

2.11

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads) unless

noted otherwise. See Section 5.1 for the processor pin listings and Section 5.2 for the signal

definitions. The voltage and current specifications for all versions of the processor are detailed in

Table 6. For platform planning refer to Figure 3. Notice that the graphs include Thermal Design

Power (TDP) associated with the maximum current levels. The DC specifications for the AGTL+

signals are listed in Table 8.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

19

Table 6 through Table 11 list the processor DC specifications and are valid only while meeting

specifications for case temperature (T_CASEas specified in Chapter 6.0), clock frequency, and input

voltages. Care should be taken to read all notes associated with each parameter.

20

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Table 6. Voltage and Current Specifications

Symbol

Parameter

Core Freq

Min

Typ

Max

VID

Unit

Notes¹

2 GHz

1.353

1.344

1.334

1.331

1.352

1.461

1.456

1.452

1.450

1.467

1.5

V

2, 3, 4, 5,11, 12

2.40 GHz

2.66 GHz

2.80 GHz

3.06 GHz

V_CCfor Intel Xeon

processor with 533

MHz Front Side Bus

Refer to

Figure 3

V_CC

1.5

1.525

SMBus supply

voltage

SM_V_CC

All freq.

3.135

3.30

3.465

V

8

2 GHz

45.4

51.4

57.1

59.1

69.1

A

4, 5

2.40 GHz

2.66 GHz

2.80 GHz

3.06 GHz

I_CCfor Intel Xeon

processor with 533

MHz Front Side Bus

I_CC

I_CCfor PLL power

pins

I_{CC_PLL}

All freq

60

mA

9

I_{CC_GTLREF}

I_CCfor GTLREF pins

I_CCStop-Grant/Sleep

I_CCTCC active

All freq

15

25

µA

A

10

6

I

_SGnt/I_SLP

I_TCC

18.6

A

7

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processors.

2. These voltages are targets only. A variable voltage source should exist on systems in the event that a

different voltage is required. See Section 2.6 and Table 3 for more information.

3. The voltage specification requirements are measured across vias on the platform for the V_{CC_SENSE}and

V_{SS_SENSE}pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe

capacitance, and 1 milliohm minimum impedance. The maximum length of ground wire on the probe should

be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

4. The processor should not be subjected to any static Vcc level that exceeds the voltage vs current load-line for

any given current loading (as shown in figure 3 for VID=1.500V and figure 4 for VID=1.525V). Moreover, Vcc

should never exceed Vcc_VID. Failure to adhere to this specification can shorten the processor lifetime.

5. Vcc_max and Vcc_min are defined at a load of Icc_max. Icc_max is defined at Vcc_max

6. The current specified is also for AutoHALT State.

7. The maximum instantaneous current the processor will draw while the thermal control circuit is active as

indicated by the assertion of PROCHOT#.

8. VID_V_CCis required for correct operation of the processor VID logic. Refer to Figure 17 for details.

9. This specification applies to the PLL power pins VCCA and VCCIOPLL. See Section 2.5 for details. This

parameter is based on design characterization and is not tested

10.This specification applies to each GTLREF pin.

11.The loadlines specify voltage limits at the die measured at V_{CC_SENSE}and V_{SS_SENSE}pins. Voltage

regulation feedback for voltage regulator circuits must be taken from processor V_CCand V_SSpins.

12.Adherence to this loadline specification is required to ensure reliable processor operation.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

21

Figure 3. Intel® Xeon™ processor with 533 MHz Front Side Bus Voltage-Current

Projections (VID 1.5V)

1.51

1.50

1.49

1.48

1.47

1.46

1.45

1.44

0

10

20

30

40

50

60

70

Processor Current (A)

22

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 4. Intel Xeon processor with 533 MHz Front Side Bus Voltage-Current

Projections (VID 1.525V)

Table 7. Front Side Bus Differential BCLK Specifications

Notes

Symbol

Parameter

Min

Typ

Max

Unit Figure

1

Input Low

Voltage

V_L

V_H

-.150

0.660

0.250

0.000

0.710

N/A

V

7

Input High

Voltage

0.850

0.550

Absolute

Crossing Point

V_CROSS(abs)

7, 7

2,8

2,3,8,9

2,10

0.250 +

0.550 +

Relative

Crossing Point

V_CROSS(rel)

N/A

V

7, 7

0.5(V_Havg- 0.710)

Range of

Crossing Points

∆V_CROSS

N/A

0.140

V_OV

V_US

Overshoot

Undershoot

N/A

-0.300

N/A

V_H+ 0.3

N/A

V

7

6

4

5

V_RBM

V_TM

Ringback Margin

Threshold Margin

0.200

N/A

V_cross- 0.100

V_cross+ 0.100

NOTES:.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

23

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the

falling edge of BCLK1.

3. V_Havgis the statistical average of the V_Hmeasured by the oscilloscope.

4. Overshoot is defined as the absolute value of the maximum voltage.

5. Undershoot is defined as the absolute value of the minimum voltage.

6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback

and the maximum Falling Edge Ringback.

7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential

receiver switches. It includes input threshold hysteresis.

8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

9. V_Havgcan be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.

10.∆V_CROSSis defined as the total variation of all crossing voltages as defined in note 2.

Table 8. AGTL+ Signal Group DC Specifications

Notes

Symbol

Parameter

Min

Max

Unit

1,7

V_IH

V_IL

Input High Voltage

Input Low Voltage

Output High Voltage

1.10 * GTLREF

V_CC

0.90 * GTLREF

V_CC

V

2, 4, 6

3, 6

0.0

V_OH

N/A

4, 6

V^CC/

(0.50 * R_{TT_min}+ R_{ON_min}

)

I_OL

Output Low Current

N/A

mA

6

= 50

100

500

11

I_HI

Pin Leakage High

Pin Leakage Low

N/A

7

µA

Ω

9

8

I_LO

R_ON

Buffer On Resistance

5, 7

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.

2. V_IHis defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

3. V_ILis defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.

4. V_IHand V_ONmay experience excursions above V_CC. However, input signal drivers must comply with the

signal quality specifications in Chapter 3.0.

5. Refer to the Intel^®Xeon™ Processor with 533 MHz Front Side Bus Signal Integrity Models for I/V

characteristics.

6. The V_CCreferred to in these specifications refers to instantaneous V_CC

.

7. V_{OL_MAX}of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with R_TTenabled.

8. Leakage to V_CCwith pin held at 300 mV.

9. Leakage to V_SSwith pin held at V_CC

.

Table 9. TAP and PWRGOOD Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes ^{1, 2}

V_HYS

TAP Input Hysteresis

200

300

8

TAP input low to high

threshold voltage

V_T+

V_T-

0.5 * (V_CC+ V_{HYS_MIN}

)

0.5 * (V_CC+ V_{HYS_MAX}

)

5

TAP input high to low

threshold voltage

0.5 * (V_CC- V_{HYS_MAX}

N/A

0.5 * (V_CC- V_{HYS_MIN})

V_OH

I_OL

I_HI

Output High Voltage

Output Low Current

Pin Leakage High

Pin Leakage Low

V_CC

40

V

3, 5

6, 7

10

mA

µA

N/A

100

500

I_LO

9

24

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

R_ON

Buffer On Resistance

8.75

13.75

Ω

4

NOTES:.

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.

2. All outputs are open drain

3. TAP signal group must meet the system signal quality specification in Chapter 3.0.

4. Refer to the Intel^®Xeon™ Processor with 533 MHz Front Side Bus Signal Integrity Models for I/V

characteristics.

5. The V_CCreferred to in these specifications refers to instantaneous V_CC

.

6. The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

7. V_{OL_MAX}of 0.300V is guaranteed when driving a test load.

8. V_HYSrepresents the amount of hysteresis, nominally centered about 0.5*V_CC, for all TAP inputs.

9. Leakage to V_CCwith Pin held at 300 mV.

10.Leakage to V_SSwith pin held at V_CC

.

Table 10. Asynchronous GTL+ Signal Group DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes^{1, 7}

V_IH

V_IL

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Current

Pin Leakage High

Pin Leakage Low

1.10 * GTLREF

V_CC

V

3, 5, 7

4, 6

2, 5, 7

8,9

0.0

0.90 * GTLREF

V_OH

I_OL

N/A

VCC

50

V

mA

µA

Ω

I_HI

N/A

7

100

500

11

I_LO

10

R_ON

Buffer On Resistance

6

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.

2. All outputs are open drain

3. V_IHis defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high

value.

4. V_ILis defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.

5. V_IHand V_OHmay experience excursions above V_CC. However, input signal drivers must comply with the

signal quality specifications in Chapter 3.0.

6. Refer to the Intel^®Xeon™Processor with 533 MHz Front Side Bus Signal Integrity Models for I/V

characteristics.

7. The V_CCreferred to in these specifications refers to instantaneous V_CC

.

8. The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load.

9. V_{OL_MAX}of 0.450 V is guaranteed when driving into a test load as indicated in Figure 5, with R_TTenabled.

10. Leakage to V_CCwith Pin held at 300 mV.

11.Leakage to V_SSwith pin held at V_CC

.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.

2. These parameters are based on design characterization and are not tested.

Table 11. BSEL[1:0] and VID[4:0] DC Specifications

Symbol

Parameter

Min

Max

Unit

Notes¹

Buffer On

Resistance

Ron (BSEL)

9.2

14.3

Ω

2

Ron

(VID)

Buffer On

Resistance

7.8

12.8

100

Ω

2

3

I_HI

Pin Leakage Hi

N/A

µA

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

25

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. These parameters are not tested and are based on design simulations.

3. Leakage to Vss with pin held at 2.50V.

2.12

AGTL+ Front Side Bus Specifications

Routing topologies are dependent on the number of processors supported and the chipset used in

the design. Please refer to the appropriate platform design guidelines. In most cases, termination

resistors are not required as these are integrated into the processor. See Table 4 for details on which

AGTL+ signals do not include on-die termination.The termination resistors are enabled or disabled

through the ODTEN pin. To enable termination, this pin should be pulled up to V_CCthrough a

resistor and to disable termination, this pin should be pulled down to V_SSthrough a resistor. For

optimum noise margin, all pull-up and pull-down resistor values used for the ODTEN pin should

have a resistance value within 20 percent of the impedance of the baseboard transmission line

traces. For example, if the trace impedance is 50 Ω, then a value between 40 and 60 Ω should be

used. The processor’s on-die termination must be enabled for the end agent only. Please refer to

Table 12 for termination resistor values. For more details on platform design see the appropriate

platform design guidelines.

Valid high and low levels are determined by the input buffers via comparing with a reference

voltage called GTLREF.

Table 12 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be

generated on the baseboard using high precision voltage divider circuits. It is important that the

baseboard impedance is held to the specified tolerance, and that the intrinsic trace capacitance for

the AGTL+ signal group traces is known and well-controlled. For more details on platform design

see the appropriate platform design guidelines.

Table 12. AGTL+ Bus Voltage Definitions

Symbol

Parameter

Min

Typ

Max

Units Notes ¹

GTLREF

Bus Reference Voltage

2/3 * V_CC- 2% 2/3 * V_CC2/3 * V_CC+ 2%

V

Ω

2, 3, 6

2, 3, 6,

4

GTLREF

New Design

Bus Reference Voltage

Termination Resistance

0.63*VCC - 2% 0.63*VCC

0.63*VCC + 2%

46

R_TT

36

45

41

50

Termination Resistance

55

Ω

4, 9

5, 8

New

Design

COMP[1:0] COMP Resistance

COMP[1:0]

New

42.77

49.55

43.2

50

43.63

50.45

COMP Resistance

5, 8, 9

Design

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The tolerances for this specification have been stated generically to enable system designer to calculate the

minimum values across the range of V_CC

.

3. GTLREF is generated from V_CCon the baseboard by a voltage divider of 1 percent resistors. Refer to the

appropriate platform design guidelines for implementation details.

4. R_TTis the on-die termination resistance measured from V_CCto 1/3 V_CCat the AGTL+ output driver. Refer to

the Intel^®Xeon™ Processor with 533MHz Front Side Bus Signal Integrity Models for I/V characteristics.

5. COMP resistors are pull downs to V_SSprovided on the baseboard with 1% tolerance. See the appropriate

platform design guidelines for implementation details.

6. The V_CCreferred to in these specifications refers to instantaneous V_CC

.

7. The COMP resistance value varies by platform. Refer to the appropriate platform design guideline for the

recommended COMP resistance value.

26

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

8. The values for R_TTand COMP noted as ‘New Designs’ apply to designs that are optimized for the Intel^®

Xeon™ processor with 533MHz Front Side Bus. Refer to the appropriate platform design guideline for the

recommended COMP resistance value.

9. This specification applies to the Intel® Xeon™processor with 533MHz Front Side Bus when implemented in

platforms that do not include forward compatibility with future processors.

Table 13. Miscellaneous Signals + Specifications

T# Parameter

Min

Max

Unit

Figure

Notes

T39: THERMTRIP# to Vcc Removal

0.5

S

6

Figure 5. Electrical Test Circuit

Vtt

Rload = 50 ohms

Zo = 50 ohms, d=420mils, So=169ps/in

L = 2.4nH

C = 1.2pF

AC Timings

specified at pad.

Figure 6. THERMTRIP# to V_CCTiming

THERMTRIP# Power Down Sequence

T39

THERMTRIP#

Vcc

T39 < 0.5 seconds

Note: THERMTRIP# is undefined when RESET is active

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

27

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28

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

3.0

Mechanical Specifications

The Intel® Xeon™ Processor with 533 MHz Front Side Bus uses the Flip Chip Micro-Pin Grid

Array (FC-mPGA) package containing the processor die covered by an integrated heat spreader

(IHS) Mechanical specifications for the processor are given in this section. See Section 1.1 for

terminology definitions. Figure 7 provides a basic assembly drawing and includes the components

which make up the entire processor. Package dimensions are provided in Table 14.

The Intel® Xeon™ processor with 533 MHz Front Side Bus utilizes a surface mount 604-pin zero-

insertion force (ZIF) socket for installation into the baseboard. See the 604-Pin Socket Design

Guidelines for further details on the processor socket.

For Figure 9 through Figure 13, the following notes apply:

1. Unless otherwise specified, the following drawings are dimensioned in millimeters.

2. All dimensions are not tested, but are guaranteed by design characterization.

3. Figures and drawings labelled as “Reference Dimensions” are provided for informational

purposes only. Reference Dimensions are extracted from the mechanical design database and

are nominal dimensions with no tolerance information applied. Reference Dimensions are

NOT checked as part of the processor manufacturing process. Unless noted as such,

dimensions in parentheses without tolerances are Reference Dimensions.

4. Drawings are not to scale.

Figure 7.

FC-mPGA2 Processor Package Assembly Drawing

2

1

3

Note: applies to Intel Xeon processor in the FC-mPGA2 package.

1. Integrated Heat Spreader (IHS)

2. Processor die

3. FC-mPGA2 package

4. Land side Capacitors

5. Package Pin

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

29

3.1

Mechanical Specifications

Figure 8.

FC-mPGA Processor Package Top View: Component Placement Detail

Pin A1

30

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 9.

Intel® Xeon™ Processor with 533 MHz Front Side Bus in the FC-mPGA2 Package

Drawing

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

31

Table 14. Dimensions for the Intel® Xeon™ Processor with 533 MHz Front Side

Bus in the FC-mPGA2 Package

Symbol

Milimeters

Nominal

42.50

31.00

3.60

Notes

Min

42.40

30.90

3.42

Max

42.60

31.10

3.78

A

B

E

F

1.95

2.03

2.11

G

H

J

K

L

M

N

R

T

18.80

37.85

19.05

38.10

6.35

12.70

15.24

30.48

6.35

1.27

12.70

0.31

19.30

38.35

Nominal Component Keepin

14.99

30.23

15.49

30.73

Nominal Component Keepin

Nominal

P

0.26

0.36

0.25

Pin Diameter

φ

Pin Tp

Figure 10 details the keep-in zone for components mounted to the top side of the processor

interposer. The components include the EEPROM, thermal sensor, resistors and capacitors.

Figure 10.

FC-mPGA2 Processor Package Top View: Component Height Keep-in

1.61

COMPONENT KEEPOUT

CROSS HATCHED AREA

2.27 mm MAX ALLOWABLE

COMPONENT HEIGHT

7.5

15.5

1.61

7.5

15.5

32

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 11 details the keep-in specification for pin-side components. The processor may contain pin

side capacitors mounted to the processor package. These capacitors will be exposed within the

opening of the interposer cavity.

Figure 11.

FC-mPGA2 Processor Package Cross Section View: Pin Side Component Keep-in

IHS

1.5 mm

FC-mPGA2P

Componen

Keepin

12.7 mm

Component Keepin

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

33

Figure 12.

FC-mPGA2 Processor Package: Pin Detail

1. Kovar pin with plating of 0.2 micrometers Au over 2.0 micrometer Ni.

2. 0.254 Diametric true position, pin to pin.

34

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 13 details the flatness and tilt specifications for the IHS of the Intel Xeon processor with

533 MHz Front Side Bus, respectively. Tilt is measured with the reference datum set to the bottom

of the processor interposer.

Figure 13.

IHS Flatness and Tilt Drawing

0.080

3.2

Processor Package Load Specifications

Table 15 provides dynamic and static load specifications for the processor IHS. These mechanical

load limits should not be exceeded during heat sink assembly, mechanical stress testing, or

standard drop and shipping conditions. The heat sink attach solutions must not induce continuous

stress onto the processor with the exception of a uniform load to maintain the heat sink-to-

processor thermal interface. It is not recommended to use any portion of the processor interposer as

a mechanical reference or load bearing surface for thermal solutions.

Table 15. Package Dynamic and Static Load Specifications

Parameter

Max

Unit

Static

50

lbf

1, 2, 3

50 + 1 lb * 50G input * 1.8 (AF)

= 140

Dynamic

lbf

1, 2, 4, 5

NOTES:

1. This specification applies to a uniform compressed load.

2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and

processor interface.

3. These parameters are based on design characterization and not tested.

4. Dynamic loading specifications are defined assuming a maximum duration of 11ms.

5. The heatsink weight is assumed to be one pound. Shock input to the system during shock testing is assumed

to be 50 G’s. AF is the amplification factor.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

35

3.3

3.4

Insertion Specifications

The processor can be inserted and removed 15 times from a 604-pin socket meeting the mPGA604

Socket Design Guidelines document. Note that this specification is based on design

characterization and is not tested.

Mass Specifications

Table 16 specifies the processors mass. This includes all components which make up the entire

processor product.

Table 16. Processor Mass

Processor

Mass (grams)

Intel® Xeon™ Processor with 533 MHz Front Side

Bus

25

3.5

Materials

The processor is assembled from several components. The basic material properties are described

in Table 17.

Table 17. Processor Material Properties

Component

Material

Integrated Heat Spreader

FC-BGA

Nickel plated copper

BT Resin

Interposer

FR4

Interposer pins

Kovar with Gold over nickel

36

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

3.6

Markings

The following section details the processor top-side laser markings. It is provided to aid in the

identification of the processor.

Figure 14.

Processor Top-Side Markings

Dynamic Laser

Mark Area with 2D Matrix

Group A Line1

Group A Line2

2D Matrix encodes ATPO

number and Serial number

Group B Line1

Group B Line2

Pin A1

NOTE:

1. Character size for laser markings is: height 0.050" (1.27mm), width 0.032" (0.81mm).

2. All characters will be in upper case.

Figure 15.

Processor Bottom-Side Markings

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

37

3.7

Pin-Out Diagram

This section provides two view of the processor pin grid. Figure 16 and Figure 17 detail

the coordinates of the processor pins.

Figure 16.

Processor Pin Out Diagram: Top View

COMMON

CLOCK

COMMON

CLOCK

Async /

JTAG

ADDRESS

1

3

5

7

9

11 13 15 17 19 21 23 25

27 29 31

A

B

A

B

C

D

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

M

N

P

R

T

U

V

U

V

W

Y

W

Y

AA

AB

AC

AD

AB

AC

AD

AE

2

4

6

8

10 12 14 16 18 20 22 24 26 28

CLOCKS

DATA

SMBus

= Signal

= Power

= Ground

= SM_VCC

= GTLREF

= Reserved

= Mechanical

38

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 17.

Processor Pin Out Diagram: Bottom View

Async /

JTAG

COMMON

CLOCK

COMMON

CLOCK

ADDRESS

31

29

27

25

23

21

19

17

15

13

11

9

7

5

3

1

A

B

A

B

C

D

E

F

G

H

J

H

J

K

L

K

L

M

N

P

R

M

N

P

R

T

U

V

U

V

W

Y

W

Y

AA

AB

AC

AB

AC

AD

AE

28

26

24

22

20

18

16

14

12

10

8

6

4

2

SMBus

DATA

CLOCKS

= Signal

= Power

= Ground

= SM_VCC

= GTLREF

= Reserved

= Mechanical

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

39

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40

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Intel® Xeon™ Processor with 533MHz Front Side Bus

4.0

Pin Listing and Signal Definitions

4.1

Processor Pin Assignments

Section 2.8 contains the front side bus signal groups in Table 4 for the Intel^®Xeon™ Processor with

533 MHz Front Side Bus. This section provides a sorted pin list in Table 38 and Table 39. Table 38 is

a listing of all processor pins ordered alphabetically by pin name. Table 39 is a listing of all processor

pins ordered by pin number.

4.1.1

Pin Listing by Pin Name

Table 38. Pin Listing by Pin Name

Signal

Buffer Type

Table 38. Pin Listing by Pin Name

Pin Name

Pin No.

Direction

Signal

Buffer Type

Pin Name

Pin No.

Direction

Source Sync

Async GTL+

Common Clk

Source Sync

Common Clk

Sys Bus Clk

Common Clk

A28#

A29#

E13

D12

C11

B7

Input/Output

Input

Source Sync

A3#

A4#

A22

A20

B18

C18

A19

C17

D17

A13

B16

B14

B13

A12

C15

C14

D16

D15

F15

A10

B10

B11

C12

E14

D13

A9

Input/Output

A30#

A31#

A5#

A32#

A6

A6#

A33#

A7

A7#

A34#

C9

A8#

A35#

C8

A9#

A20M#

ADS#

F27

D19

F17

F14

E10

D9

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

Input/Output

Input

ADSTB0#

ADSTB1#

AP0#

AP1#

BCLK0

BCLK1

BINIT#

BNR#

BPM0#

BPM1#

BPM2#

BPM3#

BPM4#

BPM5#

BPRI#

BR0#

Y4

W5

F11

F20

F6

Input

Input/Output

Input

F8

E7

F5

E8

E4

D23

D20

Input/Output

B8

Datasheet

41

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 38. Pin Listing by Pin Name

Signal

Buffer Type

Signal

Buffer Type

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

BR1#

BR2# ¹

BR3# ¹

BSEL0

BSEL1

COMP0

COMP1

D0#

F12

E11

Common Clk

Power/Other

Source Sync

Input

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#

DBSY#

DEFER#

DBI0#

DBI1#

DBI2#

DBI3#

DP0#

AB16

AA16

AC17

AE13

AD18

AB15

AD13

AD14

AD11

AC12

AE10

AC11

AE9

Source Sync

Common Clk

Source Sync

Common Clk

Input/Output

Input

D10

Input

AA3

Output²

AB3

Output²

AD16

E16

Input

Y26

Input/Output

D1#

AA27

Y24

D2#

D3#

AA25

AD27

Y23

D4#

D5#

D6#

AA24

AB26

AB25

AB23

AA22

AA21

AB20

AB22

AB19

AA19

AE26

AC26

AD25

AE25

AC24

AD24

AE23

AC23

AA18

AC20

AC21

AE22

AE20

AD21

AD19

AB17

AD10

AD8

D7#

D8#

AC9

D9#

AA13

AA14

AC14

AB12

AB13

AA11

AA10

AB10

AC8

D10#

D11#

D12#

D13#

D14#

D15#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

D26#

D27#

D28#

D29#

D30#

D31#

AD7

AE7

AC6

AC5

AA8

Y9

AB6

F18

C23

AC27

AD22

AE12

AB9

Input/Output

AC18

42

Datasheet

Intel® Xeon™ Processor with 533MHz Front Side Bus

Tabl1e 38. Pin Listing by Pin Name

Table 38. Pin Listing by Pin Name

Signal

Buffer Type

Signal

Buffer Type

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Common Clk

Source Sync

Async GTL+

Power/Other

Common Clk

Async GTL+

Common Clk

Power/Other

Async GTL+

Source Sync

Reserved

Anode Pin

Cathode Pin

Reserved

Ground

DP1#

DP2#

AE19

AC15

AE17

E18

Y21

Y18

Y15

Y12

Y20

Y17

Y14

Y11

E27

W23

W9

Input/Output

Output

Reserved

THERMDA

THERMDC

Reserved

SMB_PRT

Reserved

RESET#

RS0#

B1

C5

Reserved

Output

DP3#

D25

W3

DRDY#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

FERR#

Y3

Y27

Y28

AC1

AD1

AE4

AE15

AE16

Y8

Output

Reserved

VSS

Reserved

Common Clk

Power/Other

Async GTL+

Reserved

Async GTL+

TAP

Reserved

Input

GTLREF

HIT#

Input

E21

D22

F21

C6

Input

RS1#

Input

F23

F9

Input

RS2#

Input

RSP#

Input

E22

A23

E5

Input/Output

Output

SKTOCC#

SLP#

A3

Output

HITM#

AE6

AD28

AC28

AC29

AA29

AB29

AB28

AA28

Y29

AE28

AE29

AD29

C27

D4

Input

IERR#

NC

IGNNE#

INIT#

C26

D6

Input

NC

Input

NC

LINT0

B24

G23

A17

D7

Input

NC

LINT1

Input

NC

LOCK#

Input/Output

Input

NC

MCERR#

ODTEN

PROCHOT#

PWRGOOD

REQ0#

NC

B5

NC

B25

AB7

B19

B21

C21

C20

B22

A1

Output

NC

Input

NC

Input/Output

Reserved

NC

REQ1#

SMI#

Input

Output

Input

REQ2#

STPCLK#

TCK

REQ3#

E24

C24

E25

W6

TAP

REQ4#

TDI

TAP

Reserved

TDO

A4

Reserved

TESTHI0

TESTHI1

TESTHI2

TESTHI3

Power/Other

A15

A16

A26

Reserved

W7

Reserved

W8

Reserved

Y6

Datasheet

43

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 38. Pin Listing by Pin Name

Signal

Buffer Type

Signal

Buffer Type

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

TESTHI4

TESTHI5

TESTHI6

THERMTRIP#

TMS

AA7

AD5

AE5

F26

A25

E19

F24

A2

Power/Other

Async GTL+

TAP

Input

Output

Input

VCC

E26

E28

E30

F1

Power/Other

F4

Common Clk

TAP

TRDY#

TRST#

VCC

F10

F16

F22

F29

F31

G2

Power/Other

VCC

A8

VCC

A14

A18

A24

A28

A30

B4

VCC

G4

VCC

G6

VCC

G8

VCC

G24

G26

G28

G30

H1

VCC

B6

VCC

B12

B20

B26

B29

B31

C2

VCC

H3

VCC

H5

VCC

H7

VCC

C4

H9

VCC

C10

C16

C22

C28

C30

D1

H23

H25

H27

H29

H31

J2

VCC

D8

J4

VCC

D14

D18

D24

D29

D31

E2

J6

VCC

J8

VCC

J24

J26

J28

J30

K1

VCC

E6

VCC

E12

E20

K3

VCC

K5

44

Datasheet

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 38. Pin Listing by Pin Name

Signal

Buffer Type

Signal

Buffer Type

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

Power/Other

VCC

K7

K9

VCC

P24

P26

P28

P30

R1

K23

K25

K27

K29

K31

L2

R3

R5

R7

L4

R9

L6

R23

R25

R27

R29

R31

T2

L8

L24

L26

L28

L30

M1

T4

M3

T6

M5

T8

M7

T24

T26

T28

T30

U1

M9

M23

M25

M27

M29

M31

N1

U3

U5

U7

N3

U9

N5

U23

U25

U27

U29

U31

V2

N7

N9

N23

N25

N27

N29

N31

P2

V4

V6

V8

P4

V24

V26

V28

P6

P8

Datasheet

45

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 38. Pin Listing by Pin Name

Signal

Buffer Type

Signal

Buffer Type

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

VCC

V30

W1

Power/Other

VCC

VCCA

VCCIOPLL

VCCSENSE

VID0

VID1

VID2

VID3

VID4

VSS

AE18

AE24

AB4

AD4

B27

F3

Power/Other

W25

W27

W29

W31

Y10

Input

Power/Other

Output

Power/Other

E3

Y16

D3

Y2

C3

Y22

B3

Y30

A5

AA1

VSS

A11

A21

A27

A29

A31

B2

AA4

VSS

AA6

VSS

AA12

AA20

AA26

AA31

AB2

VSS

B9

VSS

B15

B17

B23

B28

B30

C1

AB8

VSS

AB14

AB18

AB24

AB30

AC3

AC4

AC10

AC16

AC22

AC31

AD2

AD6

AD12

AD20

AD26

AD30

AE3

VSS

C7

VSS

C13

C19

C25

C29

C31

D2

VSS

D5

VSS

D11

D21

D27

D28

D30

E1

VSS

AE8

VSS

AE14

VSS

E9

46

Datasheet

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 38. Pin Listing by Pin Name

Signal

Buffer Type

Signal

Buffer Type

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

VSS

E15

E17

E23

E29

E31

F2

Power/Other

VSS

K2

K4

Power/Other

K6

K8

K24

K26

K28

K30

L1

F7

F13

F19

F25

F28

F30

G1

L3

L5

L7

L9

G3

L23

L25

L27

L29

L31

M2

M4

M6

M8

M24

M26

M28

M30

N2

G5

G7

G9

G25

G27

G29

G31

H2

H4

H6

H8

H24

H26

H28

H30

J1

N4

N6

N8

J3

N24

N26

N28

N30

P1

J5

J7

J9

J23

J25

J27

J29

J31

P3

P5

P7

P9

Datasheet

47

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 38. Pin Listing by Pin Name

Signal

Buffer Type

Signal

Buffer Type

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

VSS

P23

P25

P27

P29

P31

R2

Power/Other

VSS

V29

V31

Power/Other

W2

W4

W24

W26

W28

W30

Y1

R4

R6

R8

R24

R26

R28

R30

T1

Y5

Y7

Y13

Y19

Y25

T3

Y31

T5

AA2

T7

AA9

T9

AA15

AA17

AA23

AA30

AB1

T23

T25

T27

T29

T31

U2

AB5

AB11

AB21

AB27

AB31

AC2

AC7

AC13

AC19

AC25

AC30

AD3

AD9

AD15

AD17

AD23

AD31

U4

U6

U8

U24

U26

U28

U30

V1

V3

V5

V7

V9

V23

V25

V27

48

Datasheet

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 38. Pin Listing by Pin Name

Signal

Buffer Type

Signal

Buffer Type

Pin Name

Pin No.

Direction

Pin Name

Pin No.

Direction

VSS

VSSA

AE2

AE11

AE21

AE27

AA5

Power/Other

VSSSENSE

D26

Power/Other

Output

1. In systems utilizing the Intel Xeon processor, the system

designer must pull-up these signals to the processor VCC

2. Baseboard treating AA3 and AB3 as Reserved will operate

correctly with a bus clock of 133 MHz.

Input

Datasheet

49

Intel® Xeon™ Processor with 533MHz Front Side Bus

4.1.2

Pin Listing by Pin Number

Table 39. Pin Listing by Pin Number

Signal

Buffer Type

Pin No.

Pin Name

Direction

Signal

Buffer Type

Pin No.

Pin Name

Direction

B2

B3

VSS

VID4

VCC

Power/Other

Output

Input

A1

A2

Reserved

VCC

Reserved

Power/Other

Reserved

B4

B5

OTDEN

VCC

A3

SKTOCC#

Reserved

VSS

Output

B6

A4

Reserved

B7

A31#

A27#

VSS

Source Sync Input/Output

Power/Other

A5

Power/Other

B8

A6

A32#

Source Sync Input/Output

Power/Other

B9

A7

A33#

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

C1

A21#

A22#

VCC

Source Sync Input/Output

Power/Other

A8

VCC

A9

A26#

Source Sync Input/Output

Power/Other

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

B1

A20#

A13#

A12#

VSS

Source Sync Input/Output

Power/Other

VSS

A14#

Source Sync Input/Output

Power/Other

A10#

A11#

VSS

Source Sync Input/Output

Power/Other

VCC

Reserved

LOCK#

VCC

Reserved

A5#

Source Sync Input/Output

Common Clk

Power/Other

Common Clk

Power/Other

Async GTL+

REQ0#

VCC

Input/Output

Common Clk

Power/Other

Input/Output

REQ1#

REQ4#

VSS

Input/Output

A7#

Source Sync Input/Output

Power/Other

A4#

VSS

LINT0

Input

A3#

Source Sync Input/Output

PROCHOT# Power/Other

VCC Power/Other

VCCSENSE Power/Other

Output

Common Clk

Power/Other

TAP

HITM#

VCC

Input/Output

Output

TMS

Input

VSS

VCC

VSS

VCC

VSS

VCC

VID3

Power/Other

Reserved

VSS

Reserved

Power/Other

Reserved

VCC

VSS

VCC

C2

VSS

C3

Output

Reserved

50

Datasheet

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 39. Pin Listing by Pin Number

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

C4

C5

VCC

Reserved

RSP#

VSS

Power/Other

Reserved

D12

D13

D14

D15

D16

D17

D18

A29#

A25#

VCC

A18#

A17#

A9#

Source Sync Input/Output

Power/Other

Reserved

Input

C6

Common Clk

Power/Other

C7

Source Sync Input/Output

Power/Other

C8

A35#

A34#

VCC

Source Sync Input/Output

Power/Other

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

D1

VCC

A30#

A23#

VSS

Source Sync Input/Output

Power/Other

Common

Input/Output

Clk

D19

D20

ADS#

BR0#

Common

Input/Output

Clk

A16#

A15#

VCC

Source Sync Input/Output

Power/Other

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

E1

VSS

RS1#

Power/Other

Common Clk

Power/Other

Reserved

Input

BPRI#

VCC

A8#

Source Sync Input/Output

Power/Other

A6#

Reserved

Output

VSS

VSSSENSE Power/Other

Common Clk

Power/Other

Common Clk

TAP

REQ3#

REQ2#

VCC

Input/Output

VSS

Power/Other

Common Clk

Power/Other

Common Clk

Power/Other

Common Clk

Power/Other

VCC

DEFER#

TDI

Input

VSS

VCC

VSS

Power/Other

Async GTL+

Power/Other

Async GTL+

Power/Other

Async GTL+

Common Clk

Power/Other

Common Clk

Power/Other

VSS

IGNNE#

SMI#

VCC

E2

VCC

E3

VID1

Output

Input/Output

Output

E4

BPM5#

IERR#

VCC

VSS

E5

VCC

E6

VSS

E7

BPM2#

BPM4#

VSS

Input/Output

VCC

E8

D2

VSS

E9

D3

VID2

Output

Input

E10

E11

E12

E13

E14

E15

E16

E17

E18

AP0#

BR2# ¹

VCC

Input/Output

Input

D4

STPCLK#

VSS

D5

D6

INIT#

MCERR#

VCC

Input

A28#

A24#

VSS

Source Sync Input/Output

Power/Other

D7

Input/Output

D8

D9

AP1#

BR3# ¹

VSS

Input/Output

Input

COMP1

VSS

Power/Other

Common Clk

Input

D10

D11

DRDY#

Input/Output

Datasheet

51

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 39. Pin Listing by Pin Number

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

Common Clk

Power/Other

Common Clk

Power/Other

TAP

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

F1

TRDY#

VCC

Input

F27

F28

F29

F30

F31

G1

A20M#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

LINT1

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Async GTL+

Power/Other

Async GTL+

Power/Other

Input

RS0#

HIT#

Input

Input/Output

VSS

TCK

Input

TDO

TAP

Output

G2

VCC

Power/Other

Async GTL+

Power/Other

Common Clk

Power/Other

Common Clk

Power/Other

Common Clk

Power/Other

G3

FERR#

VCC

Output

G4

G5

VSS

G6

VCC

G7

VSS

G8

VCC

G9

F2

VSS

G23

G24

G25

G26

G27

G28

G29

G30

G31

H1

Input

F3

VID0

Output

F4

VCC

F5

BPM3#

BPM0#

VSS

Input/Output

F6

F7

F8

BPM1#

GTLREF

VCC

Input/Output

Input

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

BINIT#

BR1#

VSS

Input/Output

Input

H2

H3

ADSTB1#

A19#

Source Sync Input/Output

Power/Other

H4

H5

VCC

H6

ADSTB0#

DBSY#

VSS

Source Sync Input/Output

H7

Common Clk

Power/Other

Common Clk

Power/Other

TAP

Input/Output

H8

H9

BNR#

RS2#

VCC

Input/Output

Input

H23

H24

H25

H26

H27

H28

H29

GTLREF

TRST#

VSS

Input

Power/Other

THERMTRIP

#

F26

Async GTL+

Output

52

Datasheet

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 39. Pin Listing by Pin Number

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

H30

H31

J1

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Power/Other

L2

L3

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

Power/Other

L4

J2

L5

J3

L6

J4

L7

J5

L8

J6

L9

J7

L23

L24

L25

L26

L27

L28

L29

L30

L31

M1

J8

J9

J23

J24

J25

J26

J27

J28

J29

J30

J31

K1

M2

M3

M4

K2

M5

K3

M6

K4

M7

K5

M8

K6

M9

K7

M23

M24

M25

M26

M27

M28

M29

M30

M31

N1

K8

K9

K23

K24

K25

K26

K27

K28

K29

K30

K31

L1

N2

N3

N4

Datasheet

53

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 39. Pin Listing by Pin Number

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

N5

N6

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

R8

R9

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

Power/Other

N7

R23

R24

R25

R26

R27

R28

R29

R30

R31

T1

N8

N9

N23

N24

N25

N26

N27

N28

N29

N30

N31

P1

T2

T3

T4

P2

T5

P3

T6

P4

T7

P5

T8

P6

T9

P7

T23

T24

T25

T26

T27

T28

T29

T30

T31

U1

P8

P9

P23

P24

P25

P26

P27

P28

P29

P30

P31

R1

U2

U3

U4

R2

U5

R3

U6

R4

U7

R5

U8

R6

U9

R7

U23

54

Datasheet

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 39. Pin Listing by Pin Number

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

U24

U25

U26

U27

U28

U29

U30

U31

V1

VSS

VCC

Power/Other

Reserved

W27

W28

W29

W30

W31

Y1

VCC

VSS

Power/Other

Reserved

VSS

VCC

VSS

VCC

VSS

Y2

VCC

Y3

Reserved

BCLK0

VSS

Reserved

Input

VSS

Y4

Sys Bus Clk

Power/Other

Common Clk

V2

VCC

Y5

V3

VSS

Y6

TESTHI3

VSS

Input

V4

VCC

Y7

V5

VSS

Y8

RESET#

D62#

V6

VCC

Y9

Source Sync Input/Output

Power/Other

V7

VSS

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

Y27

Y28

Y29

Y30

Y31

AA1

AA2

AA3

VCC

V8

VCC

DSTBP3#

DSTBN3#

VSS

Source Sync Input/Output

Power/Other

V9

VSS

V23

V24

V25

V26

V27

V28

V29

V30

V31

W1

W2

W3

W4

W5

W6

W7

W8

W9

W23

W24

W25

W26

VSS

VCC

DSTBP2#

DSTBN2#

VCC

Source Sync Input/Output

Power/Other

VSS

VCC

VSS

DSTBP1#

DSTBN1#

VSS

Source Sync Input/Output

Power/Other

VCC

VSS

VCC

DSTBP0#

DSTBN0#

VCC

Source Sync Input/Output

Power/Other

VSS

VCC

VSS

D5#

Source Sync Input/Output

Power/Other

Reserved

VSS

Reserved

D2#

Power/Other

Sys Bus Clk

Power/Other

VSS

BCLK1

TESTHI0

TESTHI1

TESTHI2

GTLREF

VSS

Input

D0#

Source Sync Input/Output

THERMDA

THERMDC

NC

Anode Pin

Cathode Pin

Reserved

Output

VCC

Power/Other

VSS

VCC

VSS

BSEL0

Output²

Datasheet

55

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 39. Pin Listing by Pin Number

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

AA4

AA5

VCC

VSSA

VCC

TESTHI4

D61#

VSS

Power/Other

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

AB23

AB24

AB25

AB26

AB27

AB28

AB29

AB30

AB31

AC1

D51#

D52#

VCC

D37#

D32#

D31#

VCC

D14#

D12#

VSS

Source Sync Input/Output

Power/Other

Input

AA6

AA7

Source Sync Input/Output

Power/Other

AA8

Source Sync Input/Output

Power/Other

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AA27

AA28

AA29

AA30

AA31

AB1

D54#

D53#

VCC

D48#

D49#

VSS

Source Sync Input/Output

Power/Other

Source Sync Input/Output

Power/Other

Source Sync Input/Output

Power/Other

D13#

D9#

Source Sync Input/Output

Power/Other

D33#

VSS

Source Sync Input/Output

Power/Other

VCC

D8#

Source Sync Input/Output

Power/Other

D24#

D15#

VCC

D11#

D10#

VSS

Source Sync Input/Output

Power/Other

D7#

VSS

NC

Reserved

Source Sync Input/Output

Power/Other

NC

Reserved

VCC

VSS

Power/Other

D6#

Source Sync Input/Output

Power/Other

Reserved

VSS

Reserved

D3#

AC2

Power/Other

VCC

D1#

AC3

VCC

D60#

D59#

VSS

Source Sync Input/Output

Reserved

AC4

NC

AC5

Source Sync Input/Output

Power/Other

NC

Reserved

AC6

VSS

Power/Other

AC7

VCC

VSS

Power/Other

AC8

D56#

D47#

VCC

D43#

D41#

VSS

Source Sync Input/Output

Power/Other

AC9

AB2

VCC

BSEL1

VCCA

VSS

Power/Other

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AB3

Power/Other

Source Sync

Output²

Input

Source Sync Input/Output

Power/Other

AB4

AB5

AB6

D63#

D50#

DP2#

VCC

D34#

DP0#

VSS

Source Sync Input/Output

Common Clk

AB7

PWRGOOD Power/Other

Input

Input/Output

AB8

VCC

DBI3#

D55#

VSS

Power/Other

AB9

Source Sync Input/Output

Power/Other

Source Sync Input/Output

Common Clk

AB10

AB11

Input/Output

Power/Other

56

Datasheet

Intel® Xeon™ Processor with 533MHz Front Side Bus

Table 39. Pin Listing by Pin Number

Signal

Buffer Type

Signal

Buffer Type

Pin No.

Pin Name

Direction

Pin No.

Pin Name

Direction

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AC27

AC28

AC29

AC30

AC31

AD1

D25#

D26#

VCC

Source Sync Input/Output

Power/Other

AD27

AD28

AD29

AD30

AD31

AE2

D4#

NC

Source Sync Input/Output

Reserved

NC

Reserved

D23#

D20#

VSS

Source Sync Input/Output

Power/Other

VCC

Power/Other

VSS

D17#

DBI0#

NC

Source Sync Input/Output

Reserved

AE3

VCC

AE4

SMD_PRT

TESTHI6

SLP#

D58#

VCC

Ground

Output

Input

AE5

Power/Other

Async GTL+

NC

Reserved

AE6

Input

VSS

Power/Other

AE7

Source Sync Input/Output

Power/Other

VCC

Power/Other

AE8

Reserved

VCC

Reserved

AE9

D44#

D42#

VSS

Source Sync Input/Output

Power/Other

AD2

Power/Other

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

AE26

AE27

AE28

AE29

AD3

VSS

AD4

VCCIOPLL

TESTHI5

VCC

Input

DBI2#

D35#

VCC

Source Sync Input/Output

Power/Other

AD5

AD6

AD7

D57#

D46#

VSS

Source Sync Input/Output

Power/Other

Reserved

DP3#

VCC

Reserved

AD8

Common Clk

Power/Other

Common Clk

AD9

Input/Output

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

D45#

D40#

VCC

Source Sync Input/Output

Power/Other

DP1#

D28#

VSS

Input/Output

Source Sync Input/Output

Power/Other

D38#

D39#

VSS

Source Sync Input/Output

Power/Other

D27#

D22#

VCC

Source Sync Input/Output

Power/Other

COMP0

VSS

Power/Other

Input

D19#

D16#

VSS

Source Sync Input/Output

Power/Other

D36#

D30#

VCC

Source Sync Input/Output

Power/Other

VID_V_CC

Power/Other

D29#

DBI1#

VSS

Source Sync Input/Output

Power/Other

Mechanical

Key

AE30

D21#

D18#

VCC

Source Sync Input/Output

Power/Other

1. In systems utilizing the Intel Xeon processor, the system

designer must pull-up these signals to the processor VCC.

2. Baseboards treating AA3 and AB3 as Reserved will operate

correctly with a bus clock of 133 MHz.

Datasheet

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Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

59

4.2

Signal Definitions

Table 41. Signal Definitions (Sheet 1 of 9)

Name

Type

Description

Notes

A[35:3]# (Address) define a 2³⁶byte physical memory address space. In sub-phase

1 of the address phase, these pins transmit the address of a transaction. In sub-

phase 2, these pins transmit transaction type information. These signals must

connect the appropriate pins of all agents on the front side bus. A[35:3]# are

protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and

are latched into the receiving buffers by ADSTB[1:0]#.

A[35:3]#

I/O

4

On the active-to-inactive transition of RESET#, the processors sample a subset of

the A[35:3]# pins to determine their power-on configuration. See Section 6.1.

If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit

20 (A20#) before looking up a line in any internal cache and before driving a read/

write transaction on the bus. Asserting A20M# emulates the 8086 processor’s

address wrap-around at the 1 MByte boundary. Assertion of A20M# is only

supported in real mode.

A20M#

I

3

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[35:3]# pins. All bus agents observe the ADS# activation to begin

parity checking, protocol checking, address decode, internal snoop, or deferred

reply ID match operations associated with the new transaction. This signal must

connect the appropriate pins on all front side bus agents.

ADS#

I/O

4

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling

edge.

ADSTB[1:0]#

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,

A[35:3]#, and the transaction type on the REQ[4:0]# pins. A correct parity signal is

high if an even number of covered signals are low and low if an odd number of

covered signals are low. This allows parity to be high when all the covered signals

are high. AP[1:0]# should connect the appropriate pins of all front side bus agents.

The following table defines the coverage model of these signals.

AP[1:0]#

I/O

4

Request Signals

Subphase 1

Subphase 2

A[35:24]#

A[23:3]#

AP0#

AP1#

AP0#

REQ[4:0]#

The differential pair BCLK (Bus Clock) determines the bus frequency. All processor

front side bus agents must receive these signals to drive their outputs and latch

their inputs.

BCLK[1:0]

I

4

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing the falling edge of BCLK1.

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Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Table 41. Signal Definitions (Sheet 2 of 9)

Name

Type

Description

Notes

BINIT# (Bus Initialization) may be observed and driven by all processor front side

bus agents and if used, must connect the appropriate pins of all such agents. If the

BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal

any bus condition that prevents reliable future information.

If BINIT# observation is enabled during power-on configuration (see Section 6.1)

and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity

and bus request arbitration state machines. The bus agents do not reset their IOQ

and transaction tracking state machines upon observation of BINIT# assertion.

Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for

the front side bus and attempt completion of their bus queue and IOQ entries.

BINIT#

I/O

4

If BINIT# observation is disabled during power-on configuration, a central agent

may handle an assertion of BINIT# as appropriate to the error handling architecture

of the system.

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is

unable to accept new bus transactions. During a bus stall, the current bus owner

cannot issue any new transactions.

Since multiple agents might need to request a bus stall at the same time, BNR# is a

wire-OR signal which must connect the appropriate pins of all processor front side

bus agents. In order to avoid wire-OR glitches associated with simultaneous edge

transitions driven by multiple drivers, BNR# is activated on specific clock edges and

sampled on specific clock edges.

BNR#

I/O

4

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.

They are outputs from the processor which indicate the status of breakpoints and

programmable counters used for monitoring processor performance. BPM[5:0]#

should connect the appropriate pins of all front side bus agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a

processor output used by debug tools to determine processor debug readiness.

BPM[5:0]#

I/O

3

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is

used by debug tools to request debug operation of the processors.

BPM[5:4]# must be bussed to all bus agents.

These signals do not have on-die termination and must be terminated at the

end agent. See the appropriate platform design guidelines for additional

information.

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor

front side bus. It must connect the appropriate pins of all processor front side bus

agents. Observing BPRI# active (as asserted by the priority agent) causes all other

agents to stop issuing new requests, unless such requests are part of an ongoing

locked operation. The priority agent keeps BPRI# asserted until all of its requests

are completed, then releases the bus by deasserting BPRI#.

BPRI#

I

4

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

61

Table 41. Signal Definitions (Sheet 3 of 9)

Name

Type

Description

Notes

BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The

BREQ[3:0]# signals are interconnected in a rotating manner to individual processor

pins. BR2# and BR3# must not be utilized in a dual processor platform design. The

table below gives the rotating interconnect between the processor and bus signals

for dual processor systems.

BR[1:0]# Signals Rotating Interconnect, dual processor system

Bus Signal Agent 0 Pins Agent 1 Pins

BREQ0#

BREQ1#

BR0#

BR1#

BR0#

During power-up configuration, the central agent must assert the BR0# bus signal.

All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of

RESET#. The pin on which the agent samples an active level determines its agent

ID. All agents then configure their pins to match the appropriate bus signal protoco

as shown below.

BR0#

BR[1:3]#¹

I/O

I

1,4

BR[1:0]# Signal Agent IDs

BR[1:0]# Signals Rotating

Agent ID

Interconnect, dual processor system

BR0#

BR1#

0

1

During power-on configuration, the central agent must assert the BR0# bus signal.

All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition

of RESET#. The pin which the agent samples asserted determines it’s agent ID.

These signals do not have on-die termination and must be terminated at the

end agent. See the appropriate platform design guidelines for additional

information.

These output signals are used to select the front side bus frequency. A BSEL[1:0] =

“00” will select a 100 MHz bus clock frequency. The frequency is determined by the

processor(s), chipset, and frequency synthesizer capabilities. All front side bus

agents must operate at the same frequency. Individual processors will only operate

at their specified front side bus (FSB) frequency.

BSEL[1:0]

O

On baseboards which support operation only at 100 MHz bus clocks these signals

can be ignored. On baseboards employing the use of these signals, a 1 KΩ pull-up

resistor be used.

See Table 2 “Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]” on

page 13 for output values.

COMP[1:0] must be terminated to V_SSon the baseboard using precision resistors.

These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate

platform design guidelines and Table 12 for implementation details.

COMP[1:0]

I

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Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Table 41. Signal Definitions (Sheet 4 of 9)

Name

Type

Description

Notes

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the processor front side bus agents, and must connect the appropriate

pins on all such agents. The data driver asserts DRDY# to indicate a valid data

transfer.

D[63:0]# are quad-pumped signals, and will thus be driven four times in a common

clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and

DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP#

and one DSTBN#. The following table shows the grouping of data signals to strobes

and DBI#.

D[63:0]#

I/O

4

DSTBN/

DSTBP

Data Group

DBI#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DBI# pins determine the polarity of the data signals. Each group

of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active,

the corresponding data group is inverted and therefore sampled active high.

DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals.

The DBI[3:0]# signals are activated when the data on the data bus is inverted. The

bus agent will invert the data bus signals if more than half the bits, within a 16-bit

group, change logic level in the next cycle.

DBI[3:0] Assignment To Data Bus

Bus Signal

Data Bus Signals

DBI[3:0]#

I/O

4

DBI0#

DBI1#

DBI2#

DBI3#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the

processor front side bus to indicate that the data bus is in use. The data bus is

released after DBSY# is deasserted. This signal must connect the appropriate pins

on all processor front side bus agents.

DBSY#

I/O

4

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the responsibility

of the addressed memory or I/O agent. This signal must connect the appropriate

pins of all processor front side bus agents.

DEFER#

DP[3:0]#

DRDY#

I

4

DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are

driven by the agent responsible for driving D[63:0]#, and must connect the

appropriate pins of all processor front side bus agents.

I/O

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

indicating valid data on the data bus. In a multi-common clock data transfer, DRDY#

may be deasserted to insert idle clocks. This signal must connect the appropriate

pins of all processor front side bus agents.

DSTBN[3:0]#

DSTBP[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

4

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

63

Table 41. Signal Definitions (Sheet 5 of 9)

Name

Type

Description

Notes

FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and

its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/

PBE# indicates a floating-point error and will be asserted when the processor

detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/

PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included

for compatibility with systems using MS-DOS*-type floating-point error reporting.

When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the

processor has a pending break event waiting for service. The assertion of FERR#/

PBE# indicates that the processor should be returned to the Normal state. For

additional information on the pending break event functionality, including the

identification of support of the feature and enable/disable information, refer to

volume 3 of the Intel Architecture Software Developer’s Manual and the Intel

Processor Identification and the CPUID Instruction application note.

FERR#/PBE#

O

3

This signal does not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

GTLREF determines the signal reference level for AGTL+ input pins. GTLREF

should be set at 2/3Vcc. GTLREF is used by the AGTL+ receivers to determine if a

signal is a logical 0 or a logical 1.

GTLREF

I

HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

results. Any front side bus agent may assert both HIT# and HITM# together to

indicate that it requires a snoop stall, which can be continued by reasserting HIT#

and HITM# together.

HIT#

I/O

4

Since multiple agents may deliver snoop results at the same time, HIT# and HITM#

are wire-OR signals which must connect the appropriate pins of all processor front

side bus agents. In order to avoid wire-OR glitches associated with simultaneous

edge transitions driven by multiple drivers, HIT# and HITM# are activated on

specific clock edges and sampled on specific clock edges.

HITM#

IERR# (Internal Error) is asserted by a processor as the result of an internal error.

Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the

processor front side bus. This transaction may optionally be converted to an

external error signal (e.g., NMI) by system core logic. The processor will keep

IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.

IERR#

IGNNE#

INIT#

O

3

This signal does not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. If

IGNNE# is deasserted, the processor generates an exception on a noncontrol

floating-point instruction if a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

I

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an I/O write instruction, it must be valid along with the TRDY# assertion of

the corresponding I/O write bus transaction.

INIT# (Initialization), when asserted, resets integer registers inside all processors

without affecting their internal caches or floating-point registers. Each processor

then begins execution at the power-on Reset vector configured during power-on

configuration. The processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal and must connect the appropriate pins

of all processor front side bus agents.

I

If INIT# is sampled active on the active to inactive transition of RESET#, then the

processor executes its Built-in Self-Test (BIST).

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Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Table 41. Signal Definitions (Sheet 6 of 9)

Name

Type

Description

Notes

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side

bus agents. When the APIC functionality is disabled, the LINT0 signal becomes

INTR,

a maskable interrupt request signal, and LINT1 becomes NMI, a

nonmaskable interrupt. INTR and NMI are backward compatible with the signals of

those names on the Pentium processor. Both signals are asynchronous.

LINT[1:0]

I

3

Both of these signals must be software configured via BIOS programming of the

APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC

is enabled by default after Reset, operation of these pins as LINT[1:0] is the default

configuration.

LOCK# indicates to the system that a transaction must occur atomically. This signal

must connect the appropriate pins of all processor front side bus agents. For a

locked sequence of transactions, LOCK# is asserted from the beginning of the first

transaction to the end of the last transaction.

LOCK#

I/O

4

When the priority agent asserts BPRI# to arbitrate for ownership of the processor

front side bus, it will wait until it observes LOCK# deasserted. This enables

symmetric agents to retain ownership of the processor front side bus throughout the

bus locked operation and ensure the atomicity of lock.

Mechanical

Key

Inert

Mechanical Key to prevent compatibility with 603-pin socket.

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error

without a bus protocol violation. It may be driven by all processor front side bus

agents.

MCERR# assertion conditions are configurable at a system level. Assertion options

are defined by the following options:

•

Enabled or disabled.

Asserted, if configured, for internal errors along with IERR#.

Asserted, if configured, by the request initiator of a bus transaction after it

observes an error.

MCERR#

I/O

•

Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the IA-32 Software

Developer’s Manual, Volume 3: System Programming Guide.

Since multiple agents may drive this signal at the same time, MCERR# is a wire-OR

signal which must connect the appropriate pins of all processor front side bus

agents. In order to avoid wire-OR glitches associated with simultaneous edge

transitions driven by multiple drivers, MCERR# is activated on specific clock edges

and sampled on specific clock edges.

ODTEN (On-die termination enable) should be connected to V_CCto enable on-die

termination for end bus agents. For middle bus agents, pull this signal down via a

resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die

termination will be active, regardless of other states of the bus.

ODTEN

I

PROCHOT# (processor hot) indicates that the processor Thermal Control Circuit

(TCC) has been activated. Under most conditions, PROCHOT# will go active when

the processor’s thermal sensor detects that the processor has reached its

maximum safe operating temperature. See Section 6.3 for more details.

PROCHOT#

O

These signals do not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

65

Table 41. Signal Definitions (Sheet 7 of 9)

Name

Type

Description

Notes

PWRGOOD (Power Good) is an input. The processor requires this signal to be a

clean indication that all processor clocks and power supplies are stable and within

their specifications. “Clean” implies that the signal will remain low (capable of

sinking leakage current), without glitches, from the time that the power supplies are

turned on until they come within specification. The signal must then transition

monotonically to a high state. Figure 6 illustrates the relationship of PWRGOOD to

the RESET# signal. PWRGOOD can be driven inactive at any time, but clocks and

power must again be stable before a subsequent rising edge of PWRGOOD. It

must also meet the minimum pulse width specification in Table 13, and be followed

by a 1 mS RESET# pulse.

PWRGOOD

I

3

The PWRGOOD signal must be supplied to the processor; it is used to protect

internal circuits against voltage sequencing issues. It should be driven high

throughout boundary scan operation.

REQ[4:0]# (Request Command) must connect the appropriate pins of all processor

front side bus agents. They are asserted by the current bus owner to define the

currently active transaction type. These signals are source synchronous to

ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking

of these signals.

REQ[4:0]#

I/O

4

Asserting the RESET# signal resets all processors to known states and invalidates

their internal caches without writing back any of their contents. For a power-on

Reset, RESET# must stay active for at least one millisecond after V^CCand BCLK

have reached their proper specifications. On observing active RESET#, all front

side bus agents will deassert their outputs within two clocks. RESET# must not be

kept asserted for more than 10ms.

RESET#

I

4

A number of bus signals are sampled at the active-to-inactive transition of RESET#

for power-on configuration. These configuration options are described in the

Section 6.1.

This signal does not have on-die termination and must be terminated at the

end agent. See the appropriate Platform Design Guideline for additional

information.

RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins of all processor front side bus agents.

RS[2:0]#

RSP#

I

4

RSP# (Response Parity) is driven by the response agent (the agent responsible for

completion of the current transaction) during assertion of RS[2:0]#, the signals for

which RSP# provides parity protection. It must connect to the appropriate pins of all

processor front side bus agents.

A correct parity signal is high if an even number of covered signals are low and low

if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also

high, since this indicates it is not being driven by any agent guaranteeing correct

parity.

SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate

that the processor is present.

SKTOCC#

SLP#

O

I

SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the

Sleep state. During Sleep state, the processor stops providing internal clock signals

to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in

this state will not recognize snoops or interrupts. The processor will recognize only

assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK

input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state

and returns to Stop-Grant state, restarting its internal clock signals to the bus and

processor core units.

3

Pin is grounded on processor packages that do not contain SMBUS components

(PIROM, Scratch EEPROM, and thermal sensor). It is floating on processor

packages that contain the SMBus components.

SMB_PRT

I

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Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Table 41. Signal Definitions (Sheet 8 of 9)

Name

Type

Description

Notes

SMI# (System Management Interrupt) is asserted asynchronously by system logic.

On accepting a System Management Interrupt, processors save the current state

and enter System Management Mode (SMM). An SMI Acknowledge transaction is

issued, and the processor begins program execution from the SMM handler.

If SMI# is asserted during the deassertion of RESET# the processor will tri-state its

SMI#

I

3

outputs.

STPCLK# (Stop Clock), when asserted, causes processors to enter a low power

Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and

stops providing internal clock signals to all processor core units except the front

side bus and APIC units. The processor continues to snoop bus transactions and

service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the

processor restarts its internal clock to all units and resumes execution. The

assertion of STPCLK# has no effect on the bus clock; STPCLK# is an

asynchronous input.

STPCLK#

I

3

TCK (Test Clock) provides the clock input for the processor Test Bus (also known

as the Test Access Port).

TCK

TDI

I

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides

the serial output needed for JTAG specification support.

TDO

O

All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor

which matches the trace impedance within a range of ±10 ohms. TESTHI[3:0] and

TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if

desired. However, utilization of boundary scan test will not be functional if these

pins are connected together. TESTHI4 must always be pulled up independently

from the other TESTHI pins. For optimum noise margin, all pull-up resistor values

used for TESTHI[6:0] pins should have a resistance value within ±20 percent of the

impedance of the baseboard transmission line traces. For example, if the trace

impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used. The

TESTHI[6:0] termination recommendations provided in the Intel® Xeon^TM

processor datasheet are still suitable for the Intel® Xeon^TMprocessor with 533 MHz

Front Side Bus. However, Intel recommends new designs or designs undergoing

design updates follow the trace impedance matching termination guidelines given

in this section.

TESTHI[6:0]

I

Activation of THERMTRIP# (Thermal Trip) indicates the processor junction

temperature has reached a level beyond which permanent silicon damage may

occur. Measurement of the temperature is accomplished through an internal

thermal sensor which is configured to trip at approximately 135 °C. To properly

protect the processor, power must be removed upon THERMTRIP# becoming

active. See Figure 6 for the appropriate power down sequence and timing

requirement. In parallel, the processor will attempt to reduce its temperature by

shutting off internal clocks and stopping all program execution. Once activated,

THERMTRIP# remains latched and the processor will be stopped until RESET# is

asserted. A RESET# pulse will reset the processor and execution will begin at the

boot vector. If the temperature has not dropped below the trip level, the processor

will assert THERMTRIP# and return to the shutdown state. The processor releases

THERMTRIP# when RESET# is activated even if the processor is still too hot.

THERMTRIP#

O

2

This signal do not have on-die termination and must be terminated at the end

agent. See the appropriate platform design guidelines for additional

information.

THERMDA

THERMDC

O

Thermal Diode Anode.

Thermal Diode Cathode.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

67

Table 41. Signal Definitions (Sheet 9 of 9)

Name

Type

Description

Notes

TMS (Test Mode Select) is a JTAG specification support signal used by debug

tools.

TMS

I

This signal does not have on-die termination and must be terminated at the

end agent.See the appropriate platform design guidelines for additional

information.

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive

a write or implicit writeback data transfer. TRDY# must connect the appropriate pins

of all front side bus agents.

TRDY#

TRST#

I

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven

low during power on Reset. See the appropriate Platform Design Guideline for

additional information.

VCCA provides isolated power for the analog portion of the internal PLL’s. Use a

discrete RLC filter to provide clean power. Use the filter defined in Section 2.5 to

provide clean power to the PLL. The tolerance and total ESR for the filter is

important. Refer to the appropriate platform design guidelines for complete

implementation details.

V_CCA

I

V_CCIOPLLprovides isolated power for digital portion of the internal PLL’s. Follow the

V_CCIOPLL

guidelines for V_CCA(Section 2.5), and refer to the appropriate platform design

guidelines for complete implementation details.

The Vccsense and Vsssense pins are the points for which processor minimum and

maximum voltage requirements are specified. Uniprocessor designs may utilize

these pins for voltage sensing for the processor's voltage regulator. However, multi-

processor designs must not connect these pins to sense logic, but rather utilize

V_CCSENSE

V_SSSENSE

O

them for power delivery validation.

VID[4:0] (Voltage ID) pins can be used to support automatic selection of power

supply voltages (V_CC). Unlike previous processor generations, these pins are

driven by processor logic. Hence the voltage supply for these pins (SM_V_CC) must

be valid before the VRM supplying Vcc to the processor is enabled. Conversely, the

VRM output must be disabled prior to the voltage supply for these pins becomes

invalid. The VID pins are needed to support processor voltage specification

variations. See Table 3 for definitions of these pins. The power supply must supply

the voltage that is requested by these pins, or disable itself.

VID[4:0]

O

VID_VCC .

V_SSA

I

Voltage for VID and BSEL logic

V_SSAprovides an isolated, internal ground for internal PLL’s. Do not connect

directly to ground. This pin is to be connected to V_CCAand V_CCIOPLLthrough a

discrete filter circuit.

NOTES:

1. Intel Xeon processors only support BR0# and BR1#. However, the Intel Xeon processors must terminate BR2# and BR3# to the

processor V_CC.

2. For this pin on Intel^®Xeon™ processors, the maximum number of symmetric agents is one. Maximum number of Central

Agents is zero.

3. For this pin on Intel^®Xeon™ processors, the maximum number of symmetric agents is two. Maximum number of Central

Agents is zero.

4. For this pin on Intel^®Xeon™ processors, the maximum number of symmetric agents is two. Maximum number of Central

Agents is one.

68

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

5.0

Thermal Specifications

This chapter provides the thermal specifications necessary for designing a thermal solution for the

Intel^®Xeon™ Processor with 533 MHz Front Side Bus. Thermal solutions should include

heatsinks that attach to the integrated heat spreader (IHS). The IHS provides a common interface

intended to be compatible with many heatsink designs. Thermal specifications are based on the

temperature of the IHS top, referred to as the case temperature, or T_CASE. Thermal solutions should

be designed to maintain the processor within T_CASEspecifications. For information on performing

T

_CASEmeasurements, refer to the Intel® Xeon™ Processor Thermal Design Guidelines. See Figure

18 for an exploded view of the processor package and thermal solution assembly.

Note: The processor is either shipped alone or with a heatsink (boxed processor only). All other

components shown in Figure 18 must be purchased separately.

Figure 18. Processor with Thermal and Mechanical Components - Exploded View

604 Pin

Note: This is a graphical representation. For specifications, see each component’s respective

documentation listed in Section 1.3.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

69

5.1

Thermal Specifications

Table 42 specifies the thermal design power dissipation envelope for the Intel^®Xeon™ processor

with 533 MHz Front Side Bus. The processor power listed in Table 42 is described in thermal

design power. Analysis indicates that real applications are unlikely to cause the processor to

consume the maximum possible power consumption. Intel recommends that system thermal

designs utilize the Thermal Design Power indicated in Table 42. Thermal Design Power

recommendations are chosen through characterization of server and workstation applications on

the processor.

The Thermal Monitor feature is intended to protect the processor from overheating on any high

power code that exceeds the recommendations in this table. For more details on the Thermal

Monitor feature, refer to Section 6.3. In all cases, the Thermal Monitor feature must be enabled for

the processor to be operating within specification. Table 42 also lists the minimum and maximum

processor T_CASEtemperature specifications. A thermal solution should be designed to ensure the

temperature of the processor never exceeds these specifications.

Table 42. Processor Thermal Design Power

Thermal Design

Maximum Power Minimum T^CASEMaximum T^CASE

Core Frequency

Power¹

(W)

Notes

(W)

(°C)

2 GHz

58

65

72

74

85

66

75

5

70

74

75

73

2,3

2.40 GHz

2.66 GHz

2.80 GHz

3.06 GHz

83

86

101

NOTE:

1. Intel recommends that thermal solutions be designed utilizing the Thermal Design Power values. Refer to the

Intel® Xeon™ Processor Thermal Design Guidelines.

2. TDP values are specified at the point on Vcc_max loadline corresponding to Icc_TDP.

3. Systems must be designed to ensure that the processor is not subjected to any static Vcc and Icc

combination wherein Vcc exceeds Vcc_max at specified Icc. Please refer to the loadline specifications in

Chapter 2.0.

Figure 19. Processor Thermal Design Power vs Electrical Projections for VID = 1.500V

70

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 20. Processor Thermal Design Power vs Electrical Projections for VID = 1.525V

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

71

5.2

Measurements for Thermal Specifications

5.2.1

Processor Case Temperature Measurement

The minimum and maximum case temperatures (T_CASE) for processors are specified in Table 42 of

the previous section. These temperature specifications are meant to ensure correct and reliable

operation of the processor. Figure 21 illustrates the thermal measurement point for T_CASE. This

point is at the geometric center of the integrated heat spreader (IHS).

Figure 21. Thermal Measurement Point for Processor T_CASE

Note: Figure is not to scale, and is for reference only

72

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

6.0

Features

6.1

Power-On Configuration Options

The Intel^®Xeon™ Processor with 533 MHz Front Side Bus has several configuration options that

are determined by the state of specific processor pins at the active-to-inactive transition of the

processor RESET# signal. These configuration options cannot be changed except by another reset.

Both power on and software induced resets reconfigure the processor(s).

Table 43. Power-On Configuration Option Pins

Configuration Option

Pin¹

Notes

Output tri state

SMI#

INIT#

Execute BIST (Built-In Self Test)

In Order Queue de-pipelining (set IOQ depth to 1)

Disable MCERR# observation

Disable BINIT# observation

APIC cluster ID (0-3)

A7#

A9#

A10#

A[12:11]#

A15#

2

3

Disable bus parking

Disable Hyper-Threading Technology

Symmetric agent arbitration ID

A31#

BR[3:0]#

NOTES:

1. Asserting this signal during active-to-inactive edge of RESET# will selects the corresponding option.

2. The Intel® Xeon™ processor with 533 MHz Front Side Bus does not support this feature, therefore platforms

utilizing this processor should not use these configuration pins.

3. Intel Xeon processor with 533 MHz Front Side Bus utilize only BR0# and BR1# signals. 2-way platforms must

not utilize BR2# and BR3# signals.

6.2

Clock Control and Low Power States

The processor allows the use of AutoHALT, Stop-Grant and Sleep states to reduce power

consumption by stopping the clock to internal sections of the processor, depending on each

particular state. See Figure 22 for a visual representation of the processor low power states.

Due to the inability of processors to recognize bus transactions during the Sleep state,

multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the

other processor in the Normal or Stop-Grant state.

6.2.1

Normal State—State 1

This is the normal operating state for the processor.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

73

6.2.2

AutoHALT Powerdown State—State 2

AutoHALT is a low power state entered when the processor executes the HALT instruction. The

processor will transition to the Normal state upon the occurrence of BINIT#, INIT#, LINT[1:0]

(NMI, INTR), or an interrupt delivered over the front side bus. RESET# will cause the processor to

immediately initialize itself.

The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.

When the system deasserts the STPCLK# interrupt, the processor will return execution to the

HALT state.

Figure 22. Stop Clock State Machine

HALT Instruction and

HALT Bus Cycle Generated

2. Auto HALT Power Down

State

INIT#, BINIT#, INTR, NMI,

RESET#

1. Normal State

.

BCLK running

Normal execution

Snoops and interrupts allowed

STPCLK#

De-asserted

STPCLK#

Asserted

Snoop

Event

Snoop

Event

Occurs

Serviced

4. HALT/Grant Snoop State

BCLK running

3. Stop Grant State

BCLK running

Snoop Event Occurs

Snoop Event Serviced

Service snoops to caches

Snoops and interrupts allowed

SLP#

Asserted

De-asserted

5. Sleep State

BCLK running

No snoops or interrupts

allowed

6.2.3

Stop-Grant State—State 3

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks

after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once

the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop

Grant state. Both logical processors of the Intel^®Xeon™ processor with 533 MHz Front Side Bus

must be in the Stop Grant state before the deassertion of STPCLK#.

74

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Since the AGTL+ signal pins receive power from the front side bus, these pins should not be driven

(allowing the level to return to V^CC) for minimum power drawn by the termination resistors in this

state. In addition, all other input pins on the front side bus should be driven to the inactive state.

BINIT# will be recognized while the processor is in Stop-Grant state. If STPCLK# is still asserted

at the completion of the BINIT# bus initialization, the processor will remain in Stop-Grant mode. If

the STPCLK# is not asserted at the completion of the BINIT# bus initialization, the processor will

return to Normal state.

RESET# will cause the processor to immediately initialize itself, but the processor will stay in

Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the

STPCLK# signal. When re-entering the Stop-Grant state from the sleep state, STPCLK# should

only be deasserted one or more bus clocks after the deassertion of SLP#.

A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the

front side bus (see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) will occur with

the assertion of the SLP# signal.

While in the Stop-Grant state, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and

only serviced when the processor returns to the Normal state. Only one occurrence of each event

will be recognized upon return to the Normal state.

6.2.4

6.2.5

HALT/Grant Snoop State—State 4

The processor will respond to snoop transactions on the front side bus while in Stop-Grant state or

in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant

Snoop state. The processor will stay in this state until the snoop on the front side bus has been

serviced (whether by the processor or another agent on the front side bus). After the snoop is

serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as

appropriate.

Sleep State—State 5

The Sleep state is a very low power state in which each processor maintains its context, maintains

the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be

entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing

the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT

states.

Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will

cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching

interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)

are allowed on the front side bus while the processor is in Sleep state. Any transition on an input

signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in

the RESET# pin specification, then the processor will reset itself, ignoring the transition through

Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and

STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the

processor correctly executes the reset sequence.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

75

Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous front side bus

event occurs. The SLP# pin should only be asserted when the processor (and all logical processors

within the physical processor) is in the Stop-Grant state. SLP# assertions while the processors are

not in the Stop-Grant state is out of specification and may result in illegal operation.

6.2.6

Bus Response During Low Power States

While in AutoHALT Power Down and Stop-Grant states, the processor will process a front side bus

snoop.

When the processor is in Sleep state, the processor will not process interrupts or snoop

transactions.

6.3

Thermal Monitor

Thermal Monitor is a feature of the processor that allows system designers to lower the cost of

thermal solutions, without compromising system integrity or reliability. By using a factory-tuned,

precision on-die temperature sensor, and a fast acting thermal control circuit (TCC), the processor,

without the aid of any additional software or hardware, can control the processors’ die temperature

within factory specifications under typical real-world operating conditions. Thermal Monitor thus

allows the processor and system thermal solutions to be designed much closer to the power

envelopes of real applications, instead of being designed to the much higher maximum processor

power envelopes.

Thermal Monitor controls the processor temperature by modulating (starting and stopping) the

internal processor core clocks. The processor clocks are modulated when the thermal control

circuit (TCC) is activated. Thermal Monitor uses two modes to activate the TCC: Automatic mode

and On-Demand mode. Automatic mode must be enabled via BIOS, which is required for the

processor to operate within specifications. Once automatic mode is enabled, the TCC will

activate only when the internal die temperature is very near the temperature limits of the processor.

When the TCC is enabled, and a high temperature situation exists (i.e. TCC is active), the clocks

will be modulated by maintaining a duty cycle within a range of 30% - 50%. Clocks will not be off

or on more than 3.0 ms when the TCC is active. Cycle times are processor speed dependent and

will decrease as processor core frequencies increase. A small amount of hysteresis has been

included to prevent rapid active/inactive transitions of the TCC when the processor temperature is

near the trip point. Once the temperature has returned to a non-critical level, and the hysteresis

timer has expired, modulation ceases and the TCC goes inactive. Processor performance will be

decreased by ~50% when the TCC is active (assuming a duty cycle that varies from 30%-50%),

however, with a properly designed and characterized thermal solution the TCC most likely will

only be activated briefly during the most power intensive applications while at maximum chassis

ambient temperature.

For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic

mode does not require any additional hardware, software drivers or interrupt handling routines.

The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor

Control Register is written to a “1” the TCC will be activated immediately, independent of the

processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the

clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control

Register. In automatic mode, the duty cycle is fixed anywhere within a range of 30% to 50%;

however in On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to

87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used at the same time

76

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Automatic mode is enabled, however, if TCC is enabled via On-Demand mode at the same time

automatic mode is enabled AND a high temperature condition exists, the fixed duty cycle of the

automatic mode will override the duty cycle selected by the On-Demand mode.

An external signal, PROCHOT# (processor hot) is asserted at any time the TCC is active (either in

Automatic or On-Demand mode). Bus snooping and interrupt latching are also active while the

TCC is active. The temperature at which the thermal control circuit activates is not user

configurable and is not software visible. In an MP system, Thermal Monitor must be configured

identically for each processor within the system.

Besides the thermal sensor and thermal control circuit, the Thermal Monitor feature also includes

one ACPI register, one performance counter register, three model specific registers (MSR), and one

I/O pin (PROCHOT#). All are available to monitor and control the state of the Thermal Monitor

feature. Thermal Monitor can be configured to generate an interrupt upon the assertion or de-

assertion of PROCHOT# (i.e. upon the activation/deactivation of TCC). Refer to Volume 3 of the

IA32 Intel Architecture Software Developer’s for specific register and programming details.

If automatic mode is disabled the processor will be operating out of specification and cannot be

guaranteed to provide reliable results. Regardless of enabling of the automatic or On-Demand

modes, in the event of a catastrophic cooling failure, the processor will automatically shut down

when the silicon has reached a temperature of approximately 135 °C. At this point the front side

bus signal THERMTRIP# will go active and stay active until the processor has cooled down and

RESET# has been initiated. THERMTRIP# activation is independent of processor activity and

does not generate any bus cycles.If THERMTRIP# is asserted, processor core voltage (V_CC) must

be removed within the timeframe defined in Figure 6.

6.3.1

Thermal Diode

The processor incorporates an on-die thermal diode. A thermal sensor located on the baseboard

may be used to monitor the die temperature of the processor for thermal management/long term die

temperature change purposes. Table 44 and Table 45 provide the diode parameter and interface

specifications.This thermal diode is separate from the Thermal Monitor’s thermal sensor and

cannot be used to predict the behavior of the Thermal Monitor.

Table 44. Thermal Diode Parameters

Symbol Parameter

Min

Typ

Max

Unit

Notes

Forward Bias

Current

I_FW

n

5

300

uA

1

Diode Ideality

Factor

1.0011

1.0021

3.64

1.0030

2,3,4

2,3,5

Series

Resistance

R_T

W

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.

2. Characterized at 75°C.

3. Not 100% tested. Specified by design characterization.

4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode

equation:

I_FW=I_s*(e^(qVD/nkT)-1)

Where I_S= saturation current, q = electronic charge, V_D= voltage across the diode, k = Boltzmann Constant,

and T = absolute temperature (Kelvin).

5. The series resistance, R_T, is provided to allow for a more accurate measurement of the diode junction

temperature. R_Tas defined includes the pins of the processor but does not include any socket resistance or

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

77

board trace resistance between the socket and the external remote diode thermal sensor. R_Tcan be used by

remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.

Another application is that a temperature offset can be manually calculated and programmed into an offset

register in the remote diode thermal sensors as exemplified by the equation: T_error= [R_T*(N-1)*I_FWmin]/[(nk/

q)*ln N]

Where T_error= sensor temperature error, N = sensor current ration, k = Boltzmann Constant, q = electronic

charge.

Table 45. Thermal Diode Interface

Pin Name

Pin Number

Pin Description

THERMDA

THERMDC

Y27

Y28

diode anode

diode cathode

78

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

7.0

Boxed Processor Specifications

7.1

Introduction

The Intel® Xeon™ Processor with 533 MHz Front Side Bus is also offered as an Intel boxed

processor. Intel boxed processors are intended for system integrators who build systems from

components available through distribution channels. The boxed processor is supplied with an

unattached passive heatsink. It will also contain an optional active duct solution, called Processor

Wind Tunnel (PWT), to provide adequate airflow across the heatsink. If the chassis or baseboard

used contains an alternate cooling solution that has been thermally validated, the PWT may be

discarded. This chapter documents baseboard and platform requirements for the cooling solution

that is supplied with the boxed processor. This chapter is particularly important for OEM's that

manufacture baseboards and chassis for integrators. Figure 23 shows a mechanical representation

of a boxed processor heatsink.

Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These

dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system

designer's responsibility to consider their proprietary cooling solution when designing to the

required keep-out zone on their system platform and chassis.

Figure 23. Mechanical Representation of the Boxed Processor Passive Heatsink

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

79

7.2

Mechanical Specifications

This section documents the mechanical specifications of the boxed processor passive heatsink and

the PWT.

Proper clearance is required around the heatsink to ensure proper installation of the processor and

unimpeded airflow for proper cooling.

7.2.1

Boxed Processor Heatsink Dimensions

The boxed processor is shipped with an unattached passive heatsink. Clearance is required around

the heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and

dimensions for the boxed processor with assembled heatsink are shown in Figure 26 (Multiple

Views). The airflow requirements for the boxed processor heatsink must also be taken into

consideration when designing new baseboards and chassis. The airflow requirements are detailed

in the Thermal Specifications, Section 7.4.

7.2.2

7.2.3

Boxed Processor Heatsink Weight

The boxed processor heatsink weighs no more than 450 grams. See Chapter 3.0 and Chapter 5.0 of

this document along with the Intel^®Xeon^TMProcessor Family Thermal Design Guidelines for

details on the processor weight and heatsink requirements.

Boxed Processor Retention Mechanism and Heatsink Supports

The boxed processor requires processor retention solution to secure the processor, the baseboard,

and the chassis. The retention solution contains one retention mechanisms and two retention clips

per processor. The boxed processor ships with retention mechanism, cooling solution retention

clips, and direct chassis attach screws.Baseboards and chassis designed for use by system integra-

tors should include holes that are in proper alignment with each other to support the boxed proces-

sor. Refer to the Server System Infrastructure Specification (SSI-EEB) at http://www.ssiforum.org

for details on the hole locations. Please refer to the “Boxed integration notes” at http://sup-

port.intel.com/support/processors/xeon for retention mechanism installation instructions. Retention

mechanism clips must interface with the boxed processor heatsink area shown in Detail A in Figure

26.

The retention mechanism that ships with the boxed processor is different than the reference solu-

tion from Intel. Please refer to Figure 24 below, which contains the dimensions for the reference

solution. Please refer to Figure 25 for the retention mechanism that ships with the boxed processor.

80

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 24. Boxed Processor Retention Mechanism and Clip

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

81

Figure 25. Boxed Processor Retention Mechanism that Ships with the Processor

82

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 26. Multiple View Space Requirements for the Boxed Processor

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

83

7.3

Boxed Processor Requirements

7.3.1

Intel® Xeon™ Processor with 533 MHz Front Side Bus

Processor Wind Tunnel

7.3.1.1

The boxed processor ships with an active duct cooling solution called the Processor Wind Tunnel,

or PWT. This is an optional cooling solution that is designed to meet the thermal requirements of a

diverse combination of baseboards and chassis. It ships with the processor in order to reduce the

burden on the chassis manufacturer to provide adequate airflow across the processor heatsink.

Manufacturers may elect to use their own cooling solution.

Note: Although Intel will be testing a select number of baseboard and chassis combinations for thermal

compliance, this is in no way a comprehensive test. It is ultimately the system integrator’s

responsibility to test that their solution meets all of the requirements specified in this document.

The PWT is meant to assist in processor cooling, but additional cooling techniques may be required

in order to ensure that the entire system meets the thermal requirements.

See Figure 28 and Figure 29 for the Processor Wind Tunnel dimensions.

7.3.1.2

Fan Power Supply

The Processor Wind Tunnel includes a fan, which requires a constant +12V power supply. A fan

power cable is shipped with the boxed processor to draw power from a power header on the

baseboard. The power cable connector and pinouts are shown in Figure 27 and the fan cable

connector requirements are detailed in Table 46. Platforms must provide a matched power header

to support the boxed processor. Table 47 contains specifications for the input and output signals at

the fan heatsink connector. The fan heatsink outputs a SENSE signal, an open-collector output, that

pulses at a rate of two pulses per fan revolution. A baseboard pull-up resistor provides V_OHto

match the baseboard-mounted fan speed monitor requirements, if applicable. Use of the SENSE

signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.

The power header on the baseboard must be positioned to allow the fan heatsink power cable to

reach it. The power header identification and location should be documented in the platform

documentation, or on the baseboard itself. The baseboard power header should be positioned

within 7 inches from the centre of the processor socket.

84

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 27. Fan Connector Electrical Pin Sequence

Table 46. Fan Cable Connector Requirements

Item

Specification

−

Fan connector must be a straight square pin, 3-pin terminal

housing with polarizing ribs and friction locking ramp.

Match with a straight pin, friction lock header on the

mainboard.

Connector Type

Manufacturer and part number or equivalent:

†

o

AMP : Fan connector: 643815-3, header: 640456-3

†

Walden / Molex : Fan connector: 22-01-3037,

header: 22-23-2031

−

Pin 1: Ground; black wire.

Pin 2: Power, +12 V; yellow wire.

Pin 3: Signal, Open collector tachometer output signal

requirement: 2 pulses per revolution; green wire.

Pin Out

(See Figure

Above)

The fan cable connector must reach a mating mainboard

connector at any point within a radius of 110 mm (4.33”)

measured from the central datum planes of the enabled

assembly (datum planes A, B & C on Drawing AXXXXX).

Fan power cable must be routed in such a way to prevent it from

contacting the fan impellor and it must be positioned in a

consistent location from unit to unit.

Fan cable length

(Drawing

747887):

Fan cable

routing

Table 47. Fan Power and Signal Specifications

Description

Min

Typ

Max

Unit

Notes

+12V: 12 Vot Fan Power Supply

IC: Fan Current Draw

6.0

12.0

13.2

1.5

V

A

Pulses per fan

revolution

SENSE Frequency

2

1

1. Baseboard should pull this pin up to V_CCwith a resistor.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

85

Figure 28. Processor Wind Tunnel General Dimensions

86

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 29. Processor Wind Tunnel Detailed Dimensions

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

87

7.3.1.3

Fan

The Processor Wind Tunnel includes a 25mm fan for use with processors <= 2.8 GHz, or a 38mm

fan for use with processors running at 3 GHz and above. The 38mm fan provides the high

performance required to meet the demanding thermal requirements of processors running at 3 GHz

and above. The 38mm fan provides local fan speed control. There is a temperature diode on the fan

that measures the inlet temperature to the fan and adjusts the speed accordingly. The benefit is that

system manufacturers can pass acoustical requirements while still being able to pass thermal

requirements at maximum ambient temperature.

7.3.2

1U Rack Mount Server Solution

The 1U solution contains a passive heatsink and a foam pad, in addition to the retention solution

included with the other options. Because of the small form factor, the 1U heatsink is not as efficient

at dissipating heat as the general-purpose heatsink. In order to ensure maximum thermal efficiency,

the foam pad must be attached to the top of the 1U heatsink, blocking airflow between the heatsink

and the chassis cover. This will force air through the heatsink fins instead of allowing it to bypass

over the top. See Figure 30 and Figure 31 for more detail on installation.

Figure 30. Exploded View of the 1U Thermal Solution

88

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

Figure 31. Assembled View of the 1U Thermal Solution

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

89

7.4

Thermal Specifications

This section describes the cooling requirements of the heatsink solution utilized by the boxed

processor.

7.4.1

Boxed Processor Cooling Requirements

The boxed processor will be directly cooled with a passive heatsink. For the passive heatsink to

effectively cool the boxed processor, it is critical that sufficient, unimpeded, cool air flow over the

heatsink of every processor in the system. Meeting the processor’s temperature specification is a

function of the thermal design of the entire system, and ultimately the responsibility of the system

integrator. The processor temperature specification is found in Chapter 5.0. It is important that

system integrators perform thermal tests to verify that the boxed processor is kept below its

maximum temperature specification in a specific baseboard and chassis.

At an absolute minimum, the boxed processor heatsink will require 500 Linear Feet per Minute

(LFM) of cool air flowing over the heatsink. The airflow must be directed from the outside of the

chassis directly over the processor heatsinks in a direction passing from one retention mechanism

to the other. It also should flow from the front to the back of the chassis. Directing air over the

passive heatsink of the boxed Intel® Xeon™ Processor with 533 MHz Front Side Bus can be done

with auxiliary chassis fans, fan ducts, or other techniques.

It is also recommended that the ambient air temperature outside of the chassis be kept at or below

35 °C. The air passing directly over the processor heatsink should not be preheated by other system

components (such as another processor), and should be kept at or below 45 °C. Again, meeting the

processor's temperature specification is the responsibility of the system integrator. The processor

temperature specification is found in Chapter 5.0.

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Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

8.0

Debug Tools Specifications

The Debug Port design information has been moved. This includes all information necessary to

develop a Debug Port on this platform, including electrical specifications, mechanical

requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700

Debug Port Design Guide for the design of your platform.

8.1

Logic Analyzer Interface (LAI)

Intel® is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for

use in debugging systems. Tektronix* and Agilent* should be contacted to get specific information

about their logic analyzer interfaces. The following information is general in nature. Specific

information must be obtained from the logic analyzer vendor.

Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture

front side bus signals. There are two sets of considerations to keep in mind when designing a

system that can make use of an LAI: mechanical and electrical.

8.1.1

Mechanical Considerations

The LAI is installed between the processor socket and the processor. The LAI pins plug into the

socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI

egresses the system to allow an electrical connection between the processor and a logic analyzer.

The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable

egress restrictions, should be obtained from the logic analyzer vendor. System designers must

make sure that the keepout volume remains unobstructed inside the system. Note that it is possible

that the keepout volume reserved for the LAI may differ from the space normally occupied by the

processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as

part of the LAI.

8.1.2

Electrical Considerations

The LAI will also affect the electrical performance of the front side bus; therefore, it is critical to

obtain electrical load models from each of the logic analyzers to be able to run system level

simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for

electrical specifications and load models for the LAI solution they provide.

Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz

91

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Intel® Xeon™ Processor with 533 MHz Front Side Bus at 2 GHz to 3.06 GHz


型号：	RN80532KE072512
厂家：	INTEL
描述：	RISC Microprocessor, 32-Bit, 2800MHz, CMOS, CPGA604, 外围集成电路
文件：	总92页 (文件大小：1719K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RN80532KE072512 [INTEL]

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