RN80532KC0601M [INTEL]
Microprocessor, 32-Bit, 2500MHz, CMOS, CPGA603, INTERPOSER, MICRO, PGA-603;
| 型号： | RN80532KC0601M |
| 厂家： | 
INTEL |
| 描述： | Microprocessor, 32-Bit, 2500MHz, CMOS, CPGA603, INTERPOSER, MICRO, PGA-603 时钟 外围集成电路 |
| 文件： | 总132页 (文件大小：2316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® Xeon™ Processor MP with up to 2MB L3 Cache (on the 0.13 Micron Process)
Datasheet
Product Features
■ Available at 1.50, 1.90, 2, 2.50, and
■ 512-KB Advanced Transfer L2 Cache (on-
die, full speed Level 2 cache) with 8-way
associativity and Error Correcting Code
(ECC)
■ 1-MB or 2-MB L3 Cache (on-die, full
speed Level 3 cache) with 8-way
associativity and Error Correcting Code
(ECC)
2.80 GHz
■ Multi-processing server support
■ Binary compatible with applications
running on previous members of the Intel®
IA32 microprocessor line
■ Intel® NetBurst™ microarchitecture
■ Hyper-Threading Technology
■ Enables system support of up to 64 GB of
— Hardware support for multi-threaded
physical memory
applications
■ Streaming SIMD Extensions 2 (SSE2)
■ 400 MHz System bus
— 144 new instructions for double-precision
floating point operations, media/video
streaming, and secure transactions
— Bandwidth up to 3.2 GB/second
■ Rapid Execution Engine: Arithmetic Logic
Units (ALUs) run at twice the processor
core frequency
■ Enhanced floating point and multimedia
unit for enhanced video, audio, encryption,
and 3D performance
■ Hyper-Pipelined Technology
■ Power Management capabilities
— System Management mode
— Multiple low-power states
■ Advance Dynamic Execution
— Very deep out-of-order execution
— Enhanced branch prediction
■ Advanced System Management Features
— System Management Bus
■ Level 1 Execution Trace Cache stores 12 K
micro-ops and removes decoder latency
from main execution loops
— Processor Information ROM (PIROM)
— OEM Scratch EEPROM
— Includes 8- KB Level 1 data cache
— Thermal Monitor
— Machine Check Architecture (MCA)
The Intel® Xeon™ processor MP with up to 2-MB L3 cache on the 0.13 micron process is designed for high-
performance multi-processor server applications. Based on the Intel® NetBurst™ microarchitecture and the new
Hyper-Threading Technology, it is binary compatible with previous Intel Architecture (IA-32) processors. The Intel
Xeon processor MP with up to 2-MB L3 cache is scalable to four processors in a multiprocessor system providing
exceptional performance for applications running on advanced operating systems such as Microsoft Windows* XP
and Windows* 2000 operating systems, Linux*, and UNIX*. The Intel Xeon processor MP with up to 2 MB L3
cache delivers compute power at unparalleled value and flexibility for internet infrastructure and departmental
server applications. The Intel NetBurst microarchitecture and Hyper-Threading Technology deliver outstanding
performance and headroom for peak internet server workloads, resulting in faster response times, support for more
users, and improved scalability.
Document Number 251931-002
June 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL
ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO
SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel® Xeon™ processor MP with up to 2-MB L3 Cache may contain design defects or errors known as errata which may
cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed
by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including
Philips Electronics N.V. and North American Philips Corporation.
Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries.
* Other names and brands may be claimed as the property of others.
Copyright © 2002-2003 Intel Corporation
ii
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Contents
1
Introduction ............................................................................................................................. 1-1
1.1
Terminology .................................................................................................................... 1-3
1.1.1 Processor Packaging Terminology.................................................................... 1-3
References ....................................................................................................................... 1-4
1.2
2
Electrical Specifications ...................................................................................................... 2-1
2.1
2.2
2.3
System Bus and GTLREF ............................................................................................... 2-1
Power and Ground Pins................................................................................................... 2-1
Decoupling Guidelines.................................................................................................... 2-1
2.3.1
2.3.2
VCC Decoupling............................................................................................... 2-2
System Bus AGTL+ Decoupling...................................................................... 2-2
2.4
2.5
2.6
System Bus Clock (BCLK[1:0]) and Processor Clocking .............................................. 2-2
2.4.1 Bus Clock......................................................................................................... 2-3
PLL Filter ........................................................................................................................ 2-4
2.5.1 Mixing Processors............................................................................................. 2-5
Voltage Identification..................................................................................................... 2-6
2.6.1 Mixing Processors of Different Voltages.......................................................... 2-7
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
Reserved or Unused Pins................................................................................................. 2-8
System Bus Signal Groups.............................................................................................. 2-8
Asynchronous GTL+ Signals .......................................................................................... 2-9
Maximum Ratings ......................................................................................................... 2-10
Processor DC Specifications ......................................................................................... 2-10
AGTL+ System Bus Specifications .............................................................................. 2-16
System Bus AC Specifications...................................................................................... 2-17
Processor AC Timing Waveforms................................................................................. 2-22
3
System Bus Signal Quality Specifications.................................................................... 3-1
3.1
System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines 3-
1
3.2
3.3
System Bus Signal Quality Specifications and Measurement Guidelines ...................... 3-2
System Bus Signal Quality Specifications and Measurement Guidelines ...................... 3-5
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
Overshoot/Undershoot Guidelines.................................................................... 3-5
Overshoot/Undershoot Magnitude.................................................................... 3-6
Overshoot/Undershoot Pulse Duration ............................................................. 3-6
Activity Factor .................................................................................................. 3-6
Reading Overshoot/Undershoot Specification Tables ...................................... 3-7
Determining if a System Meets the Overshoot/Undershoot Specifications...... 3-7
4
Mechanical Specifications .................................................................................................. 4-1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Mechanical Specifications............................................................................................... 4-3
Package Load Specifications........................................................................................... 4-8
Insertion Specifications ................................................................................................... 4-8
Mass Specifications......................................................................................................... 4-8
Materials.......................................................................................................................... 4-9
Markings.......................................................................................................................... 4-9
Pinout Diagram.............................................................................................................. 4-10
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
iii
5
6
Thermal Specifications ........................................................................................................5-1
5.1
5.2
Thermal Specifications.................................................................................................... 5-3
Measurements for Thermal Specifications......................................................................5-5
5.2.1
Processor Case Temperature Measurement ...................................................... 5-5
Features...................................................................................................................................... 6-1
6.1
6.2
Power-On Configuration Options.................................................................................... 6-1
Clock Control and Low Power States.............................................................................. 6-1
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
Normal State—State 1.......................................................................................6-1
AutoHALT Powerdown State—State 2............................................................ 6-1
Stop-Grant State—State 3.................................................................................6-2
HALT/Grant Snoop State—State 4................................................................... 6-3
Sleep State—State 5.......................................................................................... 6-3
Bus Response during Low Power States........................................................... 6-4
6.3
6.4
Thermal Monitor.............................................................................................................. 6-4
6.3.1 Thermal Diode................................................................................................... 6-4
System Management Bus (SMBus) Interface ................................................................. 6-5
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Processor Information ROM (PIROM)............................................................. 6-6
Scratch EEPROM.............................................................................................. 6-8
PIROM and Scratch EEPROM Supported SMBus Transactions ..................... 6-8
SMBus Thermal Sensor .................................................................................... 6-8
Thermal Sensor Supported SMBus Transactions.............................................. 6-9
SMBus Thermal Sensor Registers................................................................... 6-11
6.4.6.1 Thermal Reference Registers............................................................ 6-11
6.4.6.2 Thermal Limit Registers................................................................... 6-11
6.4.6.3 Status Register .................................................................................. 6-11
6.4.6.4 Configuration Register...................................................................... 6-12
6.4.6.5 Conversion Rate Registers................................................................ 6-13
SMBus Thermal Sensor Alert Interrupt .......................................................... 6-13
SMBus Device Addressing ............................................................................. 6-13
6.4.7
6.4.8
7
Boxed Processor Specifications........................................................................................ 7-1
7.1
7.2
Introduction ..................................................................................................................... 7-1
Mechanical Specifications............................................................................................... 7-2
7.2.1
7.2.2
7.2.3
Boxed Processor Heatsink Dimensions............................................................. 7-2
Boxed Processor Heatsink Weight.................................................................... 7-2
Boxed Processor Retention Mechanism and Heatsink Supports ...................... 7-2
7.3
7.4
Boxed Processor Requirements.......................................................................................7-5
7.3.1
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor....................
........................................................................................................................... 7-5
Thermal Specifications.................................................................................................... 7-5
7.4.1 Boxed Processor Cooling Requirements........................................................... 7-5
8
9
Debug Tools Specifications......................................................................................... 8-1
8.1 Logic Analyzer Interface (LAI).......................................................................................8-1
8.1.1
8.1.2
Mechanical Considerations ............................................................................... 8-1
Electrical Considerations................................................................................... 8-1
Pin Listing and Signal Definitions ........................................................................... 9-1
9.1
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Pin Assignments . 9-1
9.1.1 Pin Listing by Pin Number.............................................................................. 9-10
9.2
Signal Definitions..........................................................................................................9-19
iv
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Figures
1
2
3
Typical VCCIOPLL, VCCA and VSSA Power Distribution.......................................... 2-4
Phase Lock Loop (PLL) Filter Requirements ................................................................. 2-5
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Voltage-Current Pro-
jections........................................................................................................................... 2-12
Electrical Test Circuit.................................................................................................... 2-22
TCK Clock Waveform .................................................................................................. 2-23
Differential Clock Waveform........................................................................................ 2-23
Differential Clock Crosspoint Specification ................................................................. 2-24
System Bus Common Clock Valid Delay Timing Waveform ...................................... 2-24
System Bus Source Synchronous 2X (Address) Timing Waveform............................. 2-25
System Bus Source Synchronous 4X (Data) Timing Waveform.................................. 2-26
System Bus Reset and Configuration Timing Waveform............................................. 2-27
Power-On Reset and Configuration Timing Waveform................................................ 2-27
TAP Valid Delay Timing Waveform ............................................................................ 2-28
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform..................
....................................................................................................................................... 2-28
THERMTRIP# to Vcc Timing...................................................................................... 2-28
SMBus Timing Waveform ............................................................................................ 2-29
SMBus Valid Delay Timing Waveform........................................................................ 2-29
Example 3.3 Volt/SM_VCC Sequencing...................................................................... 2-30
FERR#/PBE# Valid Delay Timing ............................................................................... 2-31
BCLK[1:0] Signal Integrity Waveform........................................................................... 3-2
Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous
GTL+ Buffers.................................................................................................................. 3-3
High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous
GTL+ Buffers.................................................................................................................. 3-3
Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers
3-4
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers
3-5
25
26
Maximum Acceptable Overshoot/Undershoot Waveform............................................ 3-10
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™ Pro-
cessor with 512-KB L2 Cache in INT-mPGA Package - Assembly Drawing (Including
Socket)............................................................................................................................. 4-2
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Package Top View
Component Placement Detail.......................................................................................... 4-3
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Package Drawing 4-3
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Top View - Compo-
nent Keep-In.................................................................................................................... 4-5
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™ Pro-
cessor with 512-KB L2 Cache in INT-mPGA Package - Cross Section View - Pin Side
Component Keep-In ........................................................................................................ 4-5
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™ Pro-
cessor with 512-KB L2 Cache in INT-mPGA Package - Processor Pin Details............. 4-6
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Package IHS Flatness
and Tilt Drawing.............................................................................................................. 4-7
Intel® Xeon™ Processor MP on the 0.13 Micron Process INT-mPGA Package IHS Flat-
ness and Tilt Drawing...................................................................................................... 4-7
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Top-Side Markings
27
28
29
30
31
32
33
34
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
v
(Package Example).......................................................................................................... 4-9
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Bottom-Side Markings
(Package Example)........................................................................................................ 4-10
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™ Pro-
cessor with 512-KB L2 Cache in INT-mPGA Package - Pinout Diagram - Top View 4-11
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™ Pro-
cessor with 512-KB L2 Cache in INT-mPGA Package - Pinout Diagram - Bottom View..
4-12
35
36
37
38
39
Thermal and Mechanical Components - Exploded View................................................ 5-1
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Thermal Design Power
vs. Electrical Projections ................................................................................................. 5-4
Thermal Measurement Point for Processor TCASE........................................................ 5-5
Stop Clock State Machine ............................................................................................... 6-2
Logical Schematic of SMBus Circuitry........................................................................... 6-5
Mechanical Representation of the Boxed Intel® Xeon™ Processor MP on the 0.13 Micron
Process Processor Passive Heatsink ................................................................................ 7-1
Boxed Processor Clip ...................................................................................................... 7-3
Boxed Processor Retention Mechanism.......................................................................... 7-3
Multiple View Space Requirements for Boxed Processors............................................. 7-4
40
41
42
43
44
45
46
Tables
1
Feature Table for Intel® Xeon™ Processor MP on the 0.13 Micron Process......................
......................................................................................................................................... 1-2
Core Frequency to System Bus Multiplier Configuration...............................................2-3
System Bus Clock Frequency Select Truth Table for BSEL[1:0]................................... 2-3
Voltage Identification Definition..................................................................................... 2-7
System Bus Signal Groups .............................................................................................. 2-9
Processor Absolute Maximum Ratings ......................................................................... 2-10
Voltage and Current Specifications...............................................................................2-11
System Bus Differential BCLK DC Specifications....................................................... 2-13
AGTL+ Signal Group DC Specifications...................................................................... 2-14
PWRGOOD and TAP Signal Group DC Specifications............................................... 2-14
Asynchronous GTL+ Signal Group DC Specifications ................................................ 2-15
SMBus Signal Group DC Specifications....................................................................... 2-15
BSEL[1:0] and VID[4:0] DC Specifications................................................................. 2-15
AGTL+ Bus Voltage Definitions .................................................................................. 2-17
System Bus Differential Clock AC Specifications....................................................... 2-18
System Bus Common Clock AC Specifications............................................................ 2-18
System Bus Source Synchronous AC Specifications.................................................... 2-19
Miscellaneous Signals AC Specifications ..................................................................... 2-20
System Bus AC Specifications (Reset Conditions)....................................................... 2-20
TAP Signal Group AC Specifications........................................................................... 2-21
SMBus Signal Group AC Specifications....................................................................... 2-21
BCLK Signal Quality Specifications............................................................................... 3-1
Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers........................ 3-2
Ringback Specifications for PWRGOOD Input and TAP Buffers.................................. 3-3
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Source Synchronous
AGTL+ Signal Group (Data) Overshoot/Undershoot Tolerance .........................................
......................................................................................................................................... 3-8
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
vi
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
26
27
28
29
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Common Clock
AGTL+ Signal Group Overshoot/Undershoot Tolerance ............................................... 3-8
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Common Clock
AGTL+ Signal Group Overshoot/Undershoot Tolerance ............................................... 3-9
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Asynchronous GTL+
and TAP Signal Groups Overshoot/Undershoot Tolerance ............................................ 3-9
Dimensions for the Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor
Package............................................................................................................................ 4-4
Package Dynamic and Static Load Specifications .......................................................... 4-8
Processor Mass ................................................................................................................ 4-8
Processor Material Properties.......................................................................................... 4-9
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Thermal Design Power
5-3
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Power-On Configuration Option Pins ............................................................................. 6-1
Processor Information ROM Format............................................................................... 6-6
Read Byte SMBus Packet................................................................................................ 6-8
Write Byte SMBus Packet............................................................................................... 6-8
Write Byte SMBus Packet............................................................................................... 6-9
Read Byte SMBus Packet................................................................................................ 6-9
Send Byte SMBus Packet.............................................................................................. 6-10
Receive Byte SMBus Packet......................................................................................... 6-10
ARA SMBus Packet...................................................................................................... 6-10
SMBus Thermal Sensor Command Byte Bit Assignments........................................... 6-10
Thermal Reference Register Values.............................................................................. 6-11
SMBus Thermal Sensor Status Register........................................................................ 6-12
SMBus Thermal Sensor Configuration Register........................................................... 6-12
SMBus Thermal Sensor Conversion Rate Registers..................................................... 6-13
Thermal Sensor SMBus Addressing on the Intel® Xeon™ Processor MP on the 0.13 Mi-
cron Process Processor .................................................................................................. 6-15
Memory Device SMBus Addressing on the Intel® Xeon™ Processor MP on the 0.13 Mi-
cron Process Processor .................................................................................................. 6-15
Pin Listing by Pin Name for the INT-mPGA Package.................................................... 9-1
Pin Listing by Pin Number for the INT-mPGA Package.............................................. 9-10
Signal Definitions.......................................................................................................... 9-19
49
50
51
52
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
vii
§
viii
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Revision History
Revision
Description
Date
-001
-002
Initial public release
November 2002
June 2003
Added 2.80 GHz 2-MB L3 cache specifications
Added 2.50 GHz 1-MB L3 cache specifications
Added 2 GHz 1-MB L3 cache specifications
Updated Sections 5.1, 5.2.1, and 6.3
§
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
ix
x
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Introduction
Introduction
1
The Intel® Xeon™ processor MP with up to 2-MB L3 cache on the 0.13 micron process is based on
the Intel® NetBurstTM microarchitecture, which operates at significantly higher clock speeds and
delivers performance levels that are significantly higher than previous generations of IA-32
processors. While based on the Intel NetBurst microarchitecture, it maintains the tradition of
compatibility with IA-32 software. The Intel NetBurst microarchitecture features include Hyper
Pipelined Technology, a Rapid Execution Engine, a 400 MHz system bus, and an Execution Trace
Cache. The Hyper Pipelined Technology doubles the pipeline depth in the processor, allowing the
processor to reach much higher core frequencies. The Rapid Execution Engine allows the two
integer ALUs in the processor to run at twice the core frequency, which allows many integer
instructions to execute in one half of the internal core clock period. The 400 MHz system bus is a
quad-pumped bus running off a 100 MHz system bus clock making 3.2 GB/sec data transfer rates
possible. The Execution Trace Cache is a L1 cache that stores approximately twelve thousand
decoded micro-operations, which removes the decoder from the main execution path and increases
performance.
Improved features within the Intel NetBurst microarchitecture include Advanced Dynamic
Execution, Advanced Transfer Cache, enhanced floating point and multi-media unit, and
Streaming SIMD Extensions 2 (SSE2). The Advanced Dynamic Execution improves speculative
execution and branch prediction internal to the processor. The Advanced Transfer Cache is a
512-KB, on-die L2 cache with increased bandwidth over previous microarchitectures. The floating
point and multi-media units have been improved by making the registers 128 bits wide and adding
a separate register for data movement. Finally, SSE2 adds 144 new instructions for double-
precision floating point, SIMD integer, and memory management.
In addition, the Intel Xeon processor MP with up to 2-MB L3 cache includes Hyper-Threading
Technology. This new technology delivers two logical processors that can execute different tasks
simultaneously using shared hardware resources. As a result, multi-threaded applications will
execute on more than one thread per physical processor. This will increasing the performance of
system applications.
The Intel Xeon processors MP with up to 2-MB L3 Cache are intended for high performance server
systems with up to four processors on one bus. The processor is designed for 1-4 way (and beyond)
designs.
The Intel Xeon processor MP with up to 2-MB L3 cache is available with 1 MB or 2 MB of
integrated level 3 (L3) cache. All versions of this processor will include manageability features and
are based upon the Intel NetBurst microarchitecture. Components of the manageability features
include an OEM EEPROM and Processor Information ROM which are accessed through a SMBus
interface and contain information relevant to the particular processor and system in which it is
installed. In addition, enhancements have been made to the Machine Check Architecture.
The Intel Xeon processor MP with 400 MHz system bus support will be offered only in the
Interposer Micro-Pin Grid Array (INT-mPGA) package. These output pins can interface with a
thermal sensor device that is placed on the baseboard. The 603-pin socket will accommodate the
Intel Xeon processor in the INT-mPGA package. The different processor features are summarized
in Table 1.
The Intel Xeon processor MP on the 0.13 micron process processor in INT-mPGA package utilize
a surface mount ZIF socket with 603 pins. This INT-mPGA package will include the processor die,
and a pinned FR4 interposer. This package includes an integrated heat spreader (IHS).
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
1-1
Introduction
As a note of reference, the Intel® Xeon™ processor with 512-KB L2 cache on the 0.13 micron
process in the FC-mPGA2 package contains an extra pin (located at location AE30) compared to
the INT-mPGA package. This additional pin serves as a keying mechanism to prevent the FC-
mPGA2 package from being installed in the 603-pin socket since processors in the FC-mPGA2
package are only supported in the 604-pin socket. Since the additional contact for pin AE30 is
electrically inert, the 604-pin socket will not have a solder ball at this location.
Mechanical components used for attaching thermal solutions to the baseboard should have a high
degree of commonality with the thermal solution components enabled for the Intel Xeon processor.
Enabled heatsinks and retention mechanisms have been designed with manufacturability as a high
priority. Hence, mechanical assembly can be completed from the top of the baseboard.
Table 1. Feature Table for Intel® Xeon™ Processor MP on the 0.13 Micron Process
Intel®
Xeon™
processor
MP with
up to 2-
MB L3
INT-
mPGA
1MB, 2
MB
1 - 4
512 KB
400 MHz
Yes
Yes
Yes
603-pin
(603 pins)
cache
The Intel Xeon processor MP on the 0.13 micron process uses a scalable system bus protocol
referred to as the “system bus” in this document. This processor system bus utilizes a split-
transaction, deferred reply protocol similar to that of the P6 processor family system bus, but is not
compatible with the P6 processor family system bus. This processor system bus is compatible with
the Intel Xeon processor system bus. The system bus uses Source-Synchronous Transfer (SST) of
address and data to improve performance. Whereas the P6 processor family transfers data once per
bus clock, the Intel Xeon processor MP on the 0.13 micron process processor transfers data four
times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a ‘double-clocked’ or 2X
address bus. In addition, the Request Phase completes in one clock cycle. Working together, the 4X
data bus and 2X address bus provide a data bus bandwidth of up to 3.2 GB/second (3200 MB/sec)
with a 400 MHz system bus. Finally, the system bus also introduces transactions that are used to
deliver interrupts.
Signals on the system bus use Assisted GTL+ (AGTL+) level voltages which are fully described in
the appropriate platform design guide (refer to Section 1.2).
1-2
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Introduction
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“System bus” refers to the interface between the processor, system core logic (the chipset
components), and other bus agents. The system bus is a multiprocessing interface to processors,
memory, and I/O. For this document, “system bus” is used as the generic term for the “Intel®
Xeon™ processor MP with up to 2-MB L3 cache processor system bus”.
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
• 603-Pin Socket - The connector which mates the Intel Xeon processor MP with up to 2-MB
L3 Cache in INT-mPGA package to the baseboard. The 603-pin socket is a surface mount
technology (SMT), zero insertion force (ZIF) socket utilizing solder ball attachment to the
platform. See the 603-Pin Socket Design Guidelines for details regarding this socket.
• 604-Pin Socket - The 604-pin socket contains an additional contact to accept the additional
keying pin on the Intel Xeon processor in the FC-mPGA2 packages at pin location AE30. The
604-pin socket will also accept processors with the INT-mPGA package. Since the additional
contact for pin AE30 is electrically inert, the 604-pin socket will not have a solder ball at this
location. Therefore, the additional keying pin will not require a baseboard via nor a surface-
mount pad.
• Flip Chip Ball Grid Array (FCBGA) - Microprocessor packaging using “flip chip” design,
where the processor is attached to the substrate face-down for better signal integrity, more
efficient heat removal and lower inductance.
• FC-mPGA2 - Packaging technology with the processor die mounted directly to a micro-Pin
Grid Array substrate with an integrated heat spreader (IHS).
• Integrated Heat Spreader (IHS) - The surface used to attach a heatsink or other thermal
solution to the Intel Xeon processor MP with up to 2-MB L3 cache processor. The IHS will
come in two sizes for the Intel Xeon processor MP with up to 2-MB L3 cache processor, see
Section 4 for specific details.
• Interposer - The structure on which the processor core package and I/O pins are mounted.
• INT-mPGA - Packaging technology with the processor die on a Flip Chip Ball Grid Array
(FC-BGA) core mounted to a pinned interposer with an integrated heat spreader (IHS).
• OEM - Original Equipment Manufacturer.
• Processor core - The processor’s execution engine. All AC timing and signal integrity
specifications are to the pads of the processor core.
• Processor Information ROM (PIROM) - A memory device located on the Intel Xeon
processor MP with up to 2-MB L3 cache processor and the Intel Xeon processor in INT-
mPGA package, accessible via the SMBus which contains information regarding the
processor’s features. This device is shared with a scratch EEPROM. The PIROM is
programmed during the manufacturing and is write-protected. See Section 6.4 for details on
the PIROM.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
1-3
Introduction
• Retention mechanism - The support components that are mounted through the baseboard to
the chassis to provide mechanical retention for the processor and heatsink assembly.
• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory) - A
memory device located on the Intel Xeon processor MP with up to 2-MB L3 cache processor
and the Intel Xeon processor in INT-mPGA package, addressable via the SMBus which can be
used by the OEM to store information (e.g., information for system management, etc). See
Section 6.4 for details on the Scratch EEPROM.
• SMBus - System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the system. It is based on
the principals of the operation of the I2C two-wire serial bus from Philips Semiconductor.
1.2
References
Material and concepts available in the following documents may be beneficial when reading this
document.
Document
Number/Location
®
AP-485, Intel Processor Identification and the CPUID Instruction
241618
®
IA-32 Intel Architecture Software Developer's Manual
1. Volume I: Basic Architecture
245470
245471
245472
2. Volume II: Instruction Set Reference
3. Volume III: System Programming Guide
CK00 Clock Synthesizer/Driver Design Guidelines
VRM 9.1 DC-DC Converter Design Guidelines
249206
298646
®
Intel Xeon™ Processor Multiprocessor Platform Design Guide
250397
®
Intel Xeon™ Processor (MP) Thermal Design Guidelines
298650
603 -Pin Socket Design Guidelines
249672
®
Intel Xeon™ Processor MP Family Enabled Components ProE* Files
http://developer.intel.com
http://developer.intel.com
®
Intel Xeon™ Processor MP Family Enabled Components IGES Files
®
Intel Xeon™ Processor MP with 512-KB L2 Cache Core Boundary Scan
Descriptor Language (BSDL) Model (V1.1) and Cell Descriptor File (V1.0)
http://developer.intel.com
ITP 700 Debug Port Design Guide
249679
System Management Bus Specification, rev 1.1
Wired for Management 2.0 Design Guide
www.sbs-forum.org/smbus
http://developer.intel.com
NOTES:.
1. Available electronically on the Intel Developer public website http://developer.intel.com
2. Available electronically on the www.sbs-forum.org/smbus.
§
1-4
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Electrical Specifications
2
2.1
System Bus and GTLREF
Most Xeon processor family system bus signals use Assisted Gunning Transceiver Logic (AGTL+)
signaling technology. This signaling technology provides improved noise margins and reduced
ringing through low voltage swings and controlled edge rates. The termination voltage level for the
Xeon processor family AGTL+ signals is VCC, the operating voltage of the processor core. This is
the same as the previous Intel Xeon processor MP processor. VTT (termination voltage level for the
I/O buffers) is identical to VCC on the Intel Xeon processor family. The use of a termination voltage
that is determined by the processor core allows better voltage scaling on the system bus for the
Intel Xeon processor MP on the 0.13 micron process. Because of the speed improvements to data
and address busses, signal integrity and platform design methods become more critical than with
previous processor families. Design guidelines for the Intel Xeon processor MP on the 0.13 micron
process system bus are detailed in the appropriate platform design guide (refer to Section 1.2).
The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard (See
Table 14 for GTLREF specifications). Termination resistors are provided on the processor silicon
and are terminated to its core voltage (VCC). The on-die termination resistors are a selectable
feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination
can be enabled to control reflections on the transmission line. For middle bus agents, on-die
termination must be disabled. Intel chipsets will also provide on-die termination, thus eliminating
the need to terminate the bus on the baseboard for most AGTL+ signals. Refer to Section 2.12 for
details on ODTEN resistor termination requirements.
Note: Some AGTL+ signals do not include on-die termination and must be terminated on the baseboard.
See Table 5 for details regarding these signals.
The AGTL+ signals depend on incident wave switching. Therefore timing calculations for AGTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the
system bus, including trace lengths, is highly recommended when designing a system. The Intel®
Xeon™ Processor MP on the 0.13 Micron Process Processor Signal Integrity and Package Models
are available through your Intel representative.
2.2
2.3
Power and Ground Pins
For clean on-chip power distribution, Intel Xeon processor MP on the 0.13 micron process
processor has 190 VCC (power) and 189 VSS (ground) inputs. All power pins must be connected to
the system power plane, while all VSS pins must be connected to the system ground plane. The
processor VCC pins must be supplied the voltage determined by the processor VID (Voltage ID)
pins.
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the Intel Xeon processor MP
on the 0.13 micron process processor is capable of generating large average current swings
between low and full power states. This may cause voltages on power planes to sag below their
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-1
Electrical Specifications
minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as
electrolytic capacitors, supply current during longer lasting changes in current demand by the
component, such as coming out of an idle condition. Similarly, they act as a storage well for current
when entering an idle condition from a running condition. Care must be taken in the baseboard
design to ensure that the voltage provided to the processor remains within the specifications listed
in Table 7. Failure to do so can result in timing violations or reduced lifetime of the component. For
further information and guidelines, refer to the appropriate platform design guidelines.
2.3.1
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and the baseboard designer must assure a low interconnect resistance from the regulator (or VRM
pins) to the 603-pin socket. Bulk decoupling may be provided on the voltage regulation module
(VRM) to meet, in part, the need to handle large current swings. The remaining decoupling is
provided on the baseboard. The power delivery path must be capable of delivering enough current
while maintaining the required tolerances (defined in Table 7). For further information regarding
power delivery, decoupling, and layout guidelines, refer to the appropriate platform design
guidelines.
2.3.2
System Bus AGTL+ Decoupling
The Intel Xeon processor MP on the 0.13 micron process integrates signal termination on the die as
well as part of the required high frequency decoupling capacitance on the processor package.
However, additional high frequency capacitance must be added to the baseboard to properly
decouple the return currents from the system bus. Bulk decoupling must also be provided by the
baseboard for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate
platform design guidelines.
2.4
System Bus Clock (BCLK[1:0]) and Processor
Clocking
BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the
processor. As in previous generation processors, the Intel Xeon processor MP on the 0.13 micron
process processor core frequency is a multiple of the BCLK[1:0] frequency. The Intel Xeon
processor MP on the 0.13 micron process processor bus ratio multiplier will be set during
manufacturing. The default setting will equal the maximum speed for the processor. It will be
possible to override this setting using software. This will permit operation at speeds lower than the
processor’s tested frequency.
The BCLK[1:0] inputs directly control the operating speed of the system bus interface. The
processor core frequency is configured during Reset by using values stored internally during
manufacturing. The stored value sets the highest bus fraction at which the particular processor can
operate. If lower speeds are desired, the appropriate ratio can be set with software using
MSR_EBC_FREQ_GOAL to produce a lower operating speed. For details of operation at core
frequencies lower than the maximum rated processor speed.
Clock multiplying within the processor is provided by the internal PLL, which requires a constant
frequency BCLK[1:0] input with exceptions for spread spectrum clocking. Processor DC and AC
specifications for the BCLK[1:0] inputs are provided in Table 8 and Table 13, respectively. These
specifications must be met while also meeting signal integrity requirements as outlined in
Section 3. The Intel Xeon processor MP on the 0.13 micron process processor utilizes a differential
2-2
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
clock. Details regarding BCLK[1:0] driver specifications are provided in the CK00 Clock
Synthesizer/Driver Design Guidelines. Table 2 contains Intel Xeon processor MP on the 0.13
micron process processor bus fraction ratios and their corresponding core frequencies.
Table 2. Core Frequency to System Bus Multiplier Configuration
Core Frequency to System Bus
Multiplier Configuration
1,2,3
Core Frequency 100 MHz BCLK
Notes
1/12
1/13
1/14
1/15
1/16
1/17
1/18
1/19
1/20
1/25
1/28
1.20 GHz
1.30 GHz
1.40 GHz
1.50 GHz
1.60 GHz
1.70 GHz
1.80 GHz
1.90 GHz
2 GHz
2.5 GHz
2.8 GHz
NOTES:
1. Individual processors operate only at or below the frequency marked on the package.
2. Listed frequencies are not necessarily committed production frequencies.
3. Platforms should support a 400 MHz system bus.
2.4.1
Bus Clock
The system bus frequency is set to the maximum supported by the individual processor. BSEL[1:0]
are outputs used to select the system bus frequency. Table 3 defines the possible combinations of
the signals and the frequency associated with each combination. The frequency is determined by
the processor(s), chipset, and clock synthesizer. All system bus agents must operate at the same
frequency. Individual processors will only operate at their specified system bus clock frequency.
The Intel Xeon processor with a 400 MHz system bus is designed to run on a baseboard with a
100 MHz bus clock. On these baseboards, BSEL[1:0] are both considered ‘reserved’ at the
processor socket. No change is required for operation with Intel Xeon processor MP on the 0.13
micron process processors. Operation will default to 100 MHz.
See the appropriate platform design guide for further details.
Table 3. System Bus Clock Frequency Select Truth Table for BSEL[1:0]
BSEL1
BSEL0
Bus Clock Frequency
0
0
1
1
0
1
0
1
100 MHz
Reserved
Reserved
Reserved
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-3
Electrical Specifications
2.5
PLL Filter
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Intel Xeon
processor MP on the 0.13 micron process processor. This requirement is identical to that used on
the Intel Xeon processors. Since these PLLs are analog in nature, they require quiet power supplies
for minimum jitter. Jitter is detrimental to the system; it degrades external I/O timings as well as
internal core timings (i.e. maximum frequency). To prevent this degradation, these supplies must
be low pass filtered from VCC. A typical filter topology is shown in Figure 1.
The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or
CIO in Figure 1), is as follows:
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz (see DC drop in next set of requirements)
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter
refer to the appropriate platform design guidelines.
Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution
Trace < 0.02 Ω
Processor interposer "pin"
VCCA
VCC
L1/L2
R-Socket
R-Socket
R-Trace
R-Trace
PLL
C
Baseboard via that connects
filter to VCC plane
Socket pin
Processor
VSSA
C
R-Socket
VCCIOPLL
L1/L2
2-4
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Figure 2. Phase Lock Loop (PLL) Filter Requirements
0.2 dB
0 dB
-0.5 dB
forbidden
zone
-28 dB
forbidden
zone
-34 dB
DC
passband
1 Hz
fpeak
1 MHz
66 MHz
fcore
high frequency
band
NOTES:
1. Diagram not to scale.
2. No specifications for frequencies beyond f
(core frequency).
core
3. f
, if existent, should be less than 0.05 MHz.
peak
2.5.1
Mixing Processors
Intel only supports multi-processor combinations that operate with the same system bus frequency,
core frequency, VID settings, and cache sizes. Mixing processors operating at different internal
clock frequencies is not supported and will not be validated by Intel. Not all operating systems can
support multiple processors with mixed frequencies. Intel does not support or validate operation of
processors with different cache sizes. Mixing processors of different steppings but the same model
(as per CPUID instruction) is supported. Details on CPUID are provided in the Intel Processor
Identification and the CPUID Instruction application note.
Unlike previous Intel Xeon processors, the Intel Xeon processor with 512-KB L2 cache and the
Low Voltage Intel Xeon processor do not sample the pins IGNNE, LINT0, LINT1, and A20M# to
establish the core to system bus ratio. Rather, the processor runs at its tested frequency at initial
power-on. If the processor needs to run at a lower core frequency, as must be done when a higher
speed processor is added to a system that contains a lower frequency processor, the system BIOS
writes a value in the MSR_EBC_FREQ_GOAL (Ratio Configuration Register), and asserts a
system reset to effect the change in the core to system bus ratio. On previous platforms, the second
reset has not been required, so the impact of this second reset needs to be comprehended by the
system designer.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-5
Electrical Specifications
2.6
Voltage Identification
The VID specification for the Intel Xeon processor MP on the 0.13 micron process processor is
supported by the VRM 9.1 DC-DC Converter Design Guidelines. The minimum voltage is
provided in Table 7, and changes with processor frequency. This allows processors running at a
higher frequency to have a relaxed minimum voltage specification. The specifications have been
set such that one voltage regulator design can work with all supported processor frequencies.
Note that the VID pins will drive valid and correct logic levels when the Intel Xeon processor MP
on the 0.13 micron process processor is provided with a valid voltage applied to the SM_VCC pins.
SM_VCC must be correct and stable prior to enabling the output of the VRM that supplies
VCC. Similarly, the output of the VRM must be disabled before SM_VCC becomes invalid.
Refer to Figure 18 for details.
The Intel Xeon processor MP on the 0.13 micron process processor uses five voltage identification
pins, VID[4:0], to support automatic selection of processor voltages. Table 4 specifies the voltage
level corresponding to the state of VID[4:0]. A ‘1’ in this table refers to a high voltage and a ‘0’
refers to low voltage level. If the processor socket is empty (VID[4:0] = 11111), or the VRM cannot
supply the voltage that is requested, this VRM must disable itself. See the VRM 9.1 DC-DC
Converter Design Guidelines.
2-6
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Table 4. Voltage Identification Definition
Processor Pins
VID4
VID3
VID2
VID1
VID0
VCC_VID (V)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VRM output off
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
2.6.1
Mixing Processors of Different Voltages
Mixing processors operating with different VID settings (voltages) is not supported and will not be
validated by Intel.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-7
Electrical Specifications
2.7
Reserved or Unused Pins
All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to
VCC, VSS, or to any other signal (including each other) can result in component malfunction or
incompatibility with future processors. See Section 9 for a pin listing of the processor and for the
location of all Reserved pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. In a system level design, on-die termination has been included on the Intel Xeon
processor MP on the 0.13 micron process processor to allow signals to be terminated within the
processor silicon. Most unused AGTL+ inputs should be left as no connects, as AGTL+ termination
is provided on the processor silicon. However, see Table 4 for details on AGTL+ signals that do not
include on-die termination. Unused active high inputs should be connected through a resistor to
ground (VSS). Unused outputs can be left unconnected, however this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used
when tying bidirectional signals to power or ground. When tying any signal to power or ground, a
resistor will also allow for system testability. For unused AGTL+ input or I/O signals, use pull-up
resistors of the same value for the on-die termination resistors (RTT). See Table 14.
TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die
termination. Inputs and all used outputs must be terminated on the baseboard. Unused outputs may
be terminated on the baseboard or left unconnected. Note that leaving unused outputs unterminated
may interfere with some TAP functions, complicate debug probing, and prevent boundary scan
testing.
All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor which
matches the trace impedance within a range of ± 10 Ω. TESTHI[3:0] and TESTHI[6:5] may all be
tied together and pulled up to VCC with a single resistor if desired. However, utilization of boundary
scan test will not be functional if these pins are connected together. TESTHI4 must always be
pulled up independently from the other TESTHI pins. For optimum noise margin, all pull-up
resistor values used for TESTHI[6:0] pins should have a resistance value within ± 20% of the
impedance of the baseboard transmission line traces. For example, if the trace impedance is 50 Ω,
then a value between 40 Ω and 60 Ω should be used. The TESTHI[6:0] termination
recommendations provided in the Intel® Xeon™ Processor MP Datasheet are still suitable for the
Intel Xeon processor MP on the 0.13 micron process processor. However, Intel recommends new
designs or designs undergoing design updates follow the trace impedance matching termination
guidelines given in this section.
2.8
System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as
a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+
output group as well as the AGTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of
timing parameters. One set is for common clock signals whose timings are specified with respect to
rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source
synchronous signals which are relative to their respective strobe lines (data and address) as well as
the rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can
become active at any time during the clock cycle. Table 5 identifies which signals are common
clock, source synchronous and asynchronous.
2-8
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Table 5. System Bus Signal Groups
1
Signal Group
Type
Signals
3
3
BPRI#, BR[3:1]# , DEFER#, RESET# ,
RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock Input
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
Synchronous to BCLK[1:0]
6
6
ADS#, AP[1:0]#, BINIT# , BNR# ,
2
2
BPM[5:0]# , BR0# , DBSY#, DP[3:0]#,
DRDY#, HIT# , HITM# , LOCK#, MCERR#
6
6
6
Signals
Associated Strobe
REQ[4:0]#,A[16:3]#5
A[35:17]#4
ADSTB0#
ADSTB1#
AGTL+ Source Synchronous
I/O
Synchronous to assoc.
strobe
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
AGTL+ Strobes
Synchronous to BCLK[1:0]
Asynchronous
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
4
4
5
4
A20M# , IGNNE# , INIT# , LINT0/INTR ,
3
Asynchronous GTL+ Input
4
5
LINT1/NMI , SMI# , SLP#, STPCLK#
3
Asynchronous GTL+ Output
System Bus Clock
Asynchronous
Clock
FERR#, IERR#, THERMTRIP#, PROCHOT#
BCLK1, BCLK0
TCK, TDI, TMS, TRST#
TDO
2
TAP Input
Synchronous to TCK
Synchronous to TCK
2
TAP Output
SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT,
SM_CLK, SM_ALERT#, SM_WP
7
SMBus Interface
Synchronous to SM_CLK
BSEL[1:0], COMP[1:0], GTLREF, ODTEN,
PWRGOOD, Reserved, SKTOCC#,
Power/Other
Power/Other
8
TESTHI[6:0],VID[4:0], V , SM_VCC , V
,
CC
CCA
V
, V
, , V
,
V
, V
CCIOPLL
SSA
SS
CCSENSE SSSENSE
NOTES:
1. Refer to Section 9.2 for signal descriptions.
2. These signal groups are not terminated by the processor.
3. These signals do not have on-die termination. Refer to corresponding platform design guidelines for
termination requirements.
4. Note that Reset initialization function of these pins is now a software function on the Intel Xeon
processor MP on the 0.13 micron process processor.
5. The value of these pins during the active-to-inactive edge of RESET# to determine processor configuration
options. See Section 6.1 for details.
6. These signals may be driven simultaneously by multiple agents (wired-or).
7. These signals are not terminated by the processor’s on-die termination. However, some signals in this group
include termination on the processor interposer. See Section 6.4 for details.
8. SM_Vcc is required for correct operation of the Intel Xeon processor MP on the 0.13 micron process
processors VID logic. Refer to Figure 18 for details.
2.9
Asynchronous GTL+ Signals
The Intel Xeon processor MP on the 0.13 micron process processor does not utilize CMOS voltage
levels on any signals that connect to the processor silicon. As a result, legacy input signals such as
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-9
Electrical Specifications
input buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals IERR#, THERMTRIP#
and PROCHOT# utilize GTL+ output buffers. All of these asynchronous GTL+ signals follow the
same DC requirements as AGTL+ signals, however the outputs are not driven high (during the
logical 0-to-1 transition) by the processor (the major difference between GTL+ and AGTL+).
Asynchronous GTL+ signals do not have setup or hold time specifications in relation to
BCLK[1:0]. However, all of the asynchronous GTL+ signals are required to be asserted for at least
two BCLKs in order for the processor to recognize them. See Table 11 and Table 18 for the DC
and AC specifications for the asynchronous GTL+ signal groups.
SMBus signals are derived from components mounted on the processor interposer along with the
processor silicon. The required SM_VCC for these signals is 3.3 V. See Section 6.4 for further
details.
2.10
Maximum Ratings
Table 6 lists the processor’s maximum environmental stress ratings. Functional operation at the
absolute maximum and minimum is neither implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating parameters are listed in
the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.
Furthermore, although the processor contains protective circuitry to resist damage from static
electric discharge, one should always take precautions to avoid high static voltages or electric
fields.
Table 6. Processor Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
T
Processor storage temperature
–40
85
°C
2
STORAGE
Any processor supply voltage with
respect to VSS
V
V
V
V
–0.3
–0.1
-0.1
-0.3
1.75
1.75
1.75
V
V
V
1
CC
AGTL+ buffer DC input voltage with
respect to VSS
inAGTL+
inGTL+
inSMBus
Async GTL+ buffer DC input voltage
with respect to Vss
SMBus buffer DC input voltage with
respect to Vss
6.0
5
V
I
Max VID pin current
mA
VID
NOTES:
1. This rating applies to any pin of the processor.
2. Contact Intel for storage requirements in excess of one year.
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless
noted otherwise. See for the Intel Xeon processor MP on the 0.13 micron process processor pin
listings and Section 9.2 for the signal definitions. The voltage and current specifications for all
versions of the processor are detailed in Table 6. For platform planning refer to Figure 3. Notice
that the graphs include Thermal Design Power (TDP) associated with the maximum current levels.
The DC specifications for the AGTL+ signals are listed in Table 9.
2-10
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
The system bus clock signal group and the SMBus interface signal group are detailed in Table 8
and Table 12, respectively. The DC specifications for these signal groups are listed in Table 12.
Table 7 through Table 11 list the DC specifications for the Intel Xeon processor MP on the
0.13 micron process processor and are valid only while meeting specifications for case temperature
(TCASE as specified inSection 5), clock frequency, and input voltages. Care should be taken to read
all notes associated with each parameter. )
Table 7. Voltage and Current Specifications
1
Symbol
Parameter
Core Freq
Min
Typ
Max
VID
Unit
Notes
VCC for processor
core with 2-MB L3
cache
2 GHz
1.333
1.314
1.449
1.441
Refer to
Figure 3
VCC
1.475
V
2, 3, 4,11,12
2.80 GHz
1.50 GHz
1.90 GHz
2 GHz
1.345
1.336
1.333
1.327
1.453
1.450
1.449
1.432
VCC for processor
core with 1-MB L3
cache
2, 3, 4,11,12
2, 3, 4,11,12
Refer to
Figure 3
VCC
1.475
V
2.50 GHz
SMBus supply
voltage
SM_VCC
ICC
All frequencies
3.135
3.30
3.465
V
A
8
ICC for processor
core with 2-MB L3
cache
2 GHz
44.8
57.5
4, 5
2.80 GHz
1.50 GHz
1.90 GHz
2 GHz
37.2
43.1
44.8
51.9
ICC for processor
core with 1-MB L3
Cache
4, 5
4, 5
ICC
A
2.50 GHz
ICC for PLL power
pins
I
All frequencies
All frequencies
60
mA
mA
9
8
CC_PLL
Icc for SMBus power
supply
ICC_SMBus
100.0
122.5
ICC_GTLREF
I
for GTLREF pins
All frequencies
All frequencies
15
25
uA
A
10
6
CC
ISGnt/I
ICC Stop-Grant
SLP
ICC Stop-Grant for
ISGnt/I
All frequencies
All frequencies
10.1
18.6
A
A
6
7
SLP
Low Voltage Intel
Xeon processor
I
I
TCC active
CC
TCC
NOTES:
1. Unless otherwise noted, all specifications in this table are based on the latest silicon measurements available
at the time of publication.
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.6 and Table 4 for more information.
3. The voltage specification requirements are measured across vias on the platform for the VCC_SENSE and
VSS_SENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 mohm minimum impedance. The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
4. Refer to Figure 3 as appropriate for the particular Intel Xeon processor MP on the 0.13 micron process
processor of interest. The processor should not be subjected to any static V level that exceeds the
CC
V
associated with any particular current. Moreover, Vcc should never exceed VCC_VID. Failure to
CC_MAX
adhere to this specification can shorten the processor lifetime.
5. Maximum current is defined at VCC_max
.
6. The current specified is also for AutoHALT State.
7. The maximum instantaneous current the processor will draw while the thermal control circuit is active as
indicated by the assertion of PROCHOT#.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-11
Electrical Specifications
8. SM_Vcc/VID_Vcc is required for correct operation of the Intel Xeon processor MP on the 0.13 micron
process processor VID and BSEL logic. Refer to Figure 18 for details.
9. This specification applies to the PLL power pins VCCA and VCCIOPLL. See Section 2.4.1 for details. This
parameter is based on design characterization and is not tested
10.This specification applies to each GTLREF pin.
11.The loadlines specify voltage limits at the die measured at V _sense and Vss_sense pins. Voltage
CC
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins.
12.Adherence to this loadline specification as shown in Figure 3 is required to ensure reliable processor
operations.
Figure 3. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Voltage-Current
Projections
1.480
1.475
1.470
1.465
1.460
1.455
1.450
1.445
1.440
1.435
1.430
0
10
20
30
40
50
60
70
Processor Current (A)
2-12
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Table 8. System Bus Differential BCLK DC Specifications
Notes
Symbol
Parameter
Min
Typ
Max
Unit Figure
1
Input Low
Voltage
V
-0.150
0.660
0.000
0.710
N/A
N/A
V
V
V
6
6
L
Input High
Voltage
V
0.850
H
V
V
Absolute
Crossing Point
CROSS(
abs)
0.250
0.550
6, 7
2,8
0.250 +
0.550 +
Relative
Crossing Point
CROSS(
rel)
N/A
N/A
V
V
6, 7
6, 7
2,3,8,9
0.5(V
- 0.710)
0.5(V
- 0.710)
Havg
Havg
Range of
Crossing Points
∆V
N/A
0.140
2,10
CROS
S
V
Overshoot
Undershoot
N/A
N/A
N/A
N/A
N/A
V
+ 0.3
H
V
V
V
V
6
6
6
6
4
5
6
7
OV
US
V
-0.300
0.200
N/A
N/A
+ 0.100
V
Ringback Margin
Threshold Margin
RBM
VTM
V
- 0.100
V
CROSS
CROSS
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
falling edge of BCLK1.
3. V
is the statistical average of the V measured by the oscilloscope.
Havg
H
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
7. Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
8. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
9. V
can be measured directly using “Vtop” on Agilent scopes and “High” on Tektronix scopes.
Havg
10.∆V
is defined as the total variation of all crossing voltages as defined in note 2.
CROSS
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-13
Electrical Specifications
Table 9. AGTL+ Signal Group DC Specifications
Notes
Symbol
Parameter
Min
Max
Unit
1,8
VIH
VIL
VOH
IOL
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Current
Pin Leakage High
Pin Leakage Low
1.10 * GTLREF
V
V
V
2, 4, 5
CC
0.0
N/A
N/A
N/A
N/A
7
0.90 * GTLREF
3, 5
4, 5
5
V
V
CC
50
mA
µA
µA
Ω
IHI
100
500
11
8
ILO
7
RON
Buffer On Resistance
6
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
3. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal
quality specifications in Section 3.
5. The VCC referred to in these specifications refers to instantaneous VCC
.
6. V of 0.450 V is guaranteed when driving into a test load as indicated in Figure 4, with Rtt enabled.
OL_MAX
7. Leakage to Vcc with Pin held at 300 mV.
8. Leakage to Vss with pin held at Vcc.
Table 10. PWRGOOD and TAP Signal Group DC Specifications
1,2
Symbol
Parameter
Min
Max
Unit
Notes
V
Input Hysteresis
200
300
mV
7
HYS
Input Low to High
Threshold Voltage
V
1/2*(V + V
)
)
1/2*(V + V )
HYS_MAX
V
V
4
4
T+
T-
cc
HYS_MIN
cc
Input High to Low
Threshold Voltage
V
1/2*(V - V
1/2*(V - V
)
HYS_MIN
cc
HYS_MAX
cc
VOH
IOL
Output High Voltage
Output Low Current
Pin Leakage High
Pin Leakage Low
N/A
VCC
40
V
mA
µA
µA
Ω
3,4
5,6
9
IHI
N/A
N/A
8.75
100
500
ILO
8
RON
Buffer On Resistance
13.75
NOTES:.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All outputs are open drain
3. TAP signal group must meet the system signal quality specification in Section 3.
4. The Vcc referred to in these specifications refers to instantaneous Vcc.
5. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
6. V
7. V
of 0.300 V is guaranteed when driving a test load.
represents the amount of hysteresis, nominally centered about 1/2 Vcc, for all TAP inputs.
OL_MAX
HYS
8. Leakage to Vcc with Pin held at 300 mV.
9. Leakage to Vss with pin held at Vcc.
2-14
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Table 11. Asynchronous GTL+ Signal Group DC Specifications
Notes
Symbol
Parameter
Min
Max
Unit
1, 6
VIH
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Current
Pin Leakage High
Pin Leakage Low
1.10 * GTLREF
VCC
V
V
3, 5, 6
4
V
0.0
0.90 * GTLREF
IL
VOH
IOL
N/A
VCC
50
V
2, 5, 6
7, 8
10
mA
µA
µA
Ω
IHI
N/A
N/A
7
100
500
11
ILO
9
RON
Buffer On Resistance
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All outputs are open drain
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
5. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal
quality specifications in Section 3.
6. The VCC referred to in these specifications refers to instantaneous VCC
.
7. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
8. V
of 0.450 V is guaranteed when driving into a test load as indicated in Figure 4, with Rtt enabled.
OL_MAX
9. Leakage to Vcc with Pin held at 300 mV.
10. Leakage to Vss with pin held at Vcc.
Table 12. SMBus Signal Group DC Specifications
1, 2, 3
Symbol
Parameter
Min
Max
Unit
Notes
VIL
Input Low Voltage
Input High Voltage
-0.30
0.30 * SM_V
3.465
0.400
3.0
V
V
CC
VIH
VOL
IOL
ILI
0.70 * SM_V
CC
Output Low Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
SMBus Pin Capacitance
0
V
N/A
N/A
N/A
mA
µA
µA
pF
± 10
ILO
± 10
C
15.0
4
SMB
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All DC specifications for the SMBus signal group are measured at the processor pins.
4. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine
maximum rise and fall times for SMBus signals.
Table 13. BSEL[1:0] and VID[4:0] DC Specifications
1
Symbol
Parameter
Min
Max
Unit
Notes
Buffer On
Resistance
Ron (BSEL)
9.2
14.3
Ω
2
Ron
(VID)
Buffer On
Resistance
7.8
12.8
100
Ω
2
3
I
Pin Leakage Hi
N/A
µA
HI
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-15
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50 V.
2.12
AGTL+ System Bus Specifications
Routing topologies are dependent on the number of processors supported and the chipset used in
the design. Please refer to the appropriate platform design guidelines. In most cases, termination
resistors are not required as these are integrated into the processor. See Table 5 for details on which
AGTL+ signals do not include on-die termination. The termination resistors are enabled or disabled
through the ODTEN pin. To enable termination, this pin should be pulled up to VCC through a
resistor and to disable termination, this pin should be pulled down to VSS through a resistor. For
optimum noise margin, all pull-up and pull-down resistor values used for the ODTEN pin should
have a resistance value within ± 20% of the impedance of the baseboard transmission line traces.
For example, if the trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.
The processor's on-die termination must be enabled for the end agent only. Please refer to Table 12
for termination resistor values. For more details on platform design see the appropriate platform
design guidelines.
Valid high and low levels are determined by the input buffers via comparing with a reference
voltage called GTLREF.
Table 12 lists the GTLREF specifications. The AGTL+ reference voltage (GTLREF) should be
generated on the baseboard using high precision voltage divider circuits. It is important that the
baseboard impedance is held to the specified tolerance, and that the intrinsic trace capacitance for
the AGTL+ signal group traces is known and well-controlled. For more details on platform design
see the appropriate platform design guidelines.
2-16
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Table 14. AGTL+ Bus Voltage Definitions
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
GTLREF
Bus Reference Voltage
2/3 VCC - 2%
2/3 VCC
2/3 VCC + 2%
V
2, 3, 6
GTLREF
New Design
Bus Reference Voltage
Termination Resistance
Termination Resistance
0.63*VCC - 2% 0.63*VCC 0.63*VCC + 2%
V
2, 3, 6
4
R
36
45
41
50
46
55
Ω
Ω
Ω
Ω
TT
R
TT
New Design
4, 8
COMP[1:0] COMP Resistance
42.77
49.55
43.2
50
43.63
50.45
5, 7
COMP[1:0]
COMP Resistance
New Design
5, 7, 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The tolerances for this specification have been stated generically to enable system designer to calculate the
minimum values across the range of V
.
CC
3. GTLREF is generated from V on the baseboard by a voltage divider of 1% resistors. Refer to the
CC
appropriate platform design guidelines for implementation details.
4. R is the on-die termination resistance measured from V to 1/3 V at the AGTL+ output driver.
TT
CC
CC
5. COMP resistors are pull downs to VSS provided on the baseboard with 1% tolerance. See the appropriate
platform design guidelines for implementation details.
6. The V referred to in these specifications refers to instantaneous V
.
CC
CC
7. COMP value may vary with chipset.
8. The values for R and COMP noted as ‘New Designs’ apply to designs that will not support Intel Xeon
TT
processor MP (previously code named Foster MP). These designs are optimized for the Intel Xeon processor
MP on the 0.13 micron process processor.
2.13
System Bus AC Specifications
The processor system bus timings specified in this section are defined at the processor core (pads).
See Section 9 for the Intel Xeon processor MP on the 0.13 micron process processor pin listing and
signal definitions.
Table 15 through Table 20 list the AC specifications associated with the processor system bus.
Specific parameters for a 400 MHz system bus are listed in these tables.
All AGTL+ timings are referenced to GTLREF for both ‘0’ and ‘1’ logic levels unless otherwise
specified.
AGTL+ layout guidelines are also available in the appropriate platform design guidelines.
Note: Care should be taken to read all notes associated with a particular timing parameter
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-17
Electrical Specifications
Table 15. System Bus Differential Clock AC Specifications
1
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
System Bus Clock Frequency (400 MHz)
T1: BCLK[1:0] Period (400 MHz)
T2: BCLK[1:0] Period Stability
100.0
10.20
150
MHz
ns
2
3
10.00
N/A
6
ps
4, 5
T3: T BCLK[1:0] Pulse High Time (400 MHz)
3.94
3.94
175
5
5
6.12
6.12
700
ns
6
6
6
6
PH
T4: T BCLK[1:0] Pulse Low Time (400 MHz)
ns
PL
T5: BCLK[1:0] Rise Time
T6: BCLK[1:0] Fall Time
ps
6
6
175
700
ps
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. The Intel Xeon processor MP on the 0.13 micron process processor core clock frequency is derived from
BCLK. The bus clock to processor core clock ratio is determined during initialization as described in Section
2.4. Table 2 shows the supported ratios for the Intel Xeon processor MP on the 0.13 micron process
processor.
3. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2).
4. For the clock jitter specification, refer to either the CK00 Clock Synthesizer/Driver Design Guidelines or the
CK408 Clock Synthesizer/Driver Design Guidelines or the CK408B Clock Synthesizer/Driver Design
Guidelines.
5. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
6. Slew rate is measured between the 35% and 65% points of the clock swing (V and V ).
L
H
.
Table 16. System Bus Common Clock AC Specifications
1,2,3
T# Parameter
Min
Max
Unit
Figure Notes
T10: Common Clock Output Valid Delay
T11: Common Clock Input Setup Time
T12: Common Clock Input Hold Time
T13: RESET# Pulse Width
0.12
0.65
0.40
1.00
1.27
N/A
ns
ns
ns
ms
8
8
4
5
5
N/A
8
10.00
11
6, 7, 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
4. Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF
at 2/3 VCC ± 2%.
5. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of
0.3 V/ ns to 4.0V/ns.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. This should be measured after VCC and BCLK[1:0] become stable.
8. Maximum specification applies only while PWRGOOD is asserted.
2-18
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
.
Table 17. System Bus Source Synchronous AC Specifications
1,2,3,4
T# Parameter
Min
Max
Unit
Figure Notes
T20: Source Sync. Output Valid Delay (first data/
address only)
0.20
1.30
ns
ns
ns
ns
ns
9, 10
10
10
9
5
T21: T
Source Sync. Data Output Valid Before
VBD
0.85
0.85
1.88
1.88
5, 8
5, 8
5, 8
5, 9
Data Strobe (400 MHz)
T22: T Source Sync. Data Output Valid After
VAD
Data Strobe (400 MHz)
T23: T Source Sync. Address Output Valid
VBA
Before Address Strobe (400 MHz)
T24: T Source Sync. Address Output Valid After
VAA
9
Address Strobe (400 MHz)
T25: T
T26: T
Source Sync. Input Setup Time
0.21
0.21
ns
ns
9, 10
9, 10
6
6
SUSS
Source Sync. Input Hold Time
HSS
T27: T
BCLK
Source Sync. Input Setup Time to
SUCC
0.65
ns
9, 10
9
7
10, 14
11, 12, 14
13
T28: T
Address Strobe
First Address Strobe to Second
FASS
1/2
n/4
BCLKs
BCLKs
T29: T : First Data Strobe to Subsequent
Strobes
FDSS
10
T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay
(400 MHz)
8.80
2.27
10.20
4.23
ns
ns
10
9
T31: Address Strobe Output Valid Delay (400 MHz)
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source
synchronous data signals are referenced to the falling edge of their associated data strobe. Source
synchronous address signals are referenced to the rising and falling edge of their associated address strobe.
All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core.
4. Unless otherwise noted, these specifications apply to both data and address timings.
5. Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF
at 2/3 VCC ± 2%.
6. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of
0.3 V/ns to 4.0 V/ns.
7. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each
respective strobe.
8. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the
appropriate platform design guidelines for more information on the definitions and use of these specifications.
9. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the
appropriate platform design guidelines for more information on the definitions and use of these specifications.
10.The rising edge of ADSTB# must come approximately 1/2 BCLK period after the falling edge of ADSTB#.
11.For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.
12.The second data strobe (falling edge of DSTBn#) must come approximately 1/4 BCLK period after the first
falling edge of DSTBp#. The third data strobe (falling edge of DSTBp#) must come approximately 2/4 BCLK
period after the first falling edge of DSTBp#. The last data strobe (falling edge of DSTBn#) must come
approximately 3/4 BCLK period after the first falling edge of DSTBp#.
13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.
14.This specification reflects a typical value, not a minimum or maximum.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-19
Electrical Specifications
.
Table 18. Miscellaneous Signals AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
T35: Async GTL+ input pulse width
T36: PWRGOOD to RESET# de-assertion time
T37: PWRGOOD inactive pulse width
T38: PROCHOT# pulse width
2
1
N/A
10
BCLKs
ms
1, 2, 3, 4
1, 2, 3, 4
12
12
14
18
10
500
N/A
BCLKs
µs
1, 2, 3, 4, 5
1, 2, 3, 4, 6
T39: THERMTRIP# to Vcc Removal
0.5
5
s
T40: FERR# Valid Delay from STPCLK#
deassertion
0
BCLKs
19
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing
Voltage (V
). All Asynchronous GTL+ signal timings are referenced at GTLREF. PWRGOOD is
CROSS
referenced to the BCLK0 rising edge at 0.5*VCC.
3. These signals may be driven asynchronously.
4. Refer to Section 6.2 for additional timing requirements for entering and leaving low power states.
5. Refer to the PWRGOOD signal definition in Section 9.2 for more detail information on behavior of the signal.
6. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the
assertion of PROCHOT# for the processor to complete current instruction execution.
Table 19. System Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Reset Configuration Signals (A[31:3]#,
BR[3:0]#, INIT#, SMI#) Setup Time
4
BCLKs
11
1
T46: Reset Configuration Signals (A[31:3]#,
BR[3:0]#, INIT#, SMI#) Hold Time
2
20
BCLKs
11
2
NOTES:
1. Before the de-assertion of RESET#
2. After the clock that de-asserts RESET#
.
2-20
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Table 20. TAP Signal Group AC Specifications
Notes
1,2,3,9
T# Parameter
Min
Max
Unit
Figure
T55: TCK Period
60.0
ns
ns
ns
ns
ns
ns
ns
ns
5
5
T56: TCK Rise Time
9.5
9.5
8.5
8.5
4
4
T57: TCK Fall Time
5
T58: TMS, TDI Rise Time
T59: TMS, TDI Fall Time
T61: TDI, TMS Setup Time
T62: TDI, TMS Hold Time
T63: TDO Clock to Output Delay
T64: TRST# Assert Time
5
4
5
4
0
13
13
13
14
5, 7
5,7
6
3.0
0.5
2.0
3.5
T
8
TCK
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5 * Vcc at the processor pins. All TAP
signal timings (TMS, TDI, etc) are referenced at the 0.5 * Vcc processor pins.
4. Rise and fall times are measured from the 20% to 80% points of the signal swing.
5. Referenced to the rising edge of TCK.
6. Referenced to the falling edge of TCK.
7. Specification for a minimum swing defined between TAP 20% to 80%. This assumes a minimum edge rate of
0.5 V/ns
8. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
9. It is recommended that TMS be asserted while TRST# is being deasserted.
.
Table 21. SMBus Signal Group AC Specifications
1,2,3
T# Parameter
T70: SM_CLK Frequency
Min
Max
Unit
Figure
Notes
10
10
100
100
N/A
N/A
1.0
KHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
T71: SM_CLK Period
T72: SM_CLK High Time
4.0
4.7
0.02
0.02
0.1
250
300
4.7
4.0
4.7
4.0
16
16
16
16
17
16
16
16
16
16
16
T73: SM_CLK Low Time
T74: SMBus Rise Time
5
5
T75: SMBus Fall Time
0.3
T76: SMBus Output Valid Delay
T77: SMBus Input Setup Time
T78: SMBus Input Hold Time
T79: Bus Free Time
4.5
N/A
N/A
N/A
N/A
N/A
N/A
4, 6
T80: Hold Time after Repeated Start Condition
T81: Repeated Start Condition Setup Time
T82: Stop Condition Setup Time
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All AC timings for the SMBus signals are referenced at V
pins. Refer to Figure 16.
or V
and measured at the processor
IL_MAX
IH_MIN
4. Minimum time allowed between request cycles.
5. Rise time is measured from (V
- 0.15 V) to (V
+ 0.15 V). Fall time is measured from (0.9 *
IH_MIN
IL_MAX
SM_VCC) to (V
- 0.15V). DC parameters are specified in Table 12.
IL_MAX
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-21
Electrical Specifications
6. Following a write transaction, an internal device write cycle time of 10ms must be allowed before starting the
next transaction.
2.14
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 14 through
Table 21.
Note: For Figure 4 through Figure 19, the following apply:
1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage
(VCROSS) of the BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal
timings are referenced at GTLREF at the processor core (pads).
2. All source synchronous AC timings for AGTL+ signals are referenced to their associated
strobe (address or data) at GTLREF. Source synchronous data signals are referenced to the
falling edge of their associated data strobe. Source synchronous address signals are referenced
to the rising and falling edge of their associated address strobe. All source synchronous
AGTL+ signal timings are referenced at GTLREF at the processor core (pads).
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All
AGTL+ strobe signal timings are referenced at GTLREF at the processor core (pads).
4. All AC Timing for the TAP signals are referenced to the TCK signal at 0.5 * Vcc at the
processor pins. All TAP signal timings (TMS, TDI, etc) are referenced at the 0.5 * Vcc at the
processor core (pads).
5. All AC timings for the SMBus signals are referenced to the SM_CLK signal at 0.5 * SM_VCC
at the processor pins. All SMBus signal timings (SM_DAT, SM_ALERT#, etc) are referenced
at VIL_MAX or VIL_MIN at the processor pins.
Figure 4. Electrical Test Circuit
Vtt
Vtt
Rload = 50 ohms
Zo = 50 ohms, d=420mils, So=169ps/in
L = 2.4nH
C = 1.2pF
AC Timings
specified at pad.
2-22
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Figure 5. TCK Clock Waveform
tr
*V2
*V3
CLK
*V1
tf
tp
Tr = T56, T58 (Rise Time)
Tf = T57, T59 (Fall Time)
T p = T55 (Period)
V1, V2: For rise and fall times, TCK is measured between 20% to 80%points on the waveform
V3:
TCK is referenced to 0.5 * Vcc
Figure 6. Differential Clock Waveform
Tph
Overshoot
VH
BCLK1
Rising Edge
Ringback
Crossing
Voltage
Crossing
Voltage
Ringback
Margin
Threshold
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
Tpl
Tp
Tp = T1 (BCLK[1:0] period)
T2 = BCLK[1:0] Period stability (not shown)
Tph =T3 (BCLK[1:0] pulse high time)
Tpl = T4 (BCLK[1:0] pulse low time)
T5 = BCLK[1:0] rise time through the threshold region
T6 = BCLK[1:0] fall time through the threshold region
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-23
Electrical Specifications
Figure 7. Differential Clock Crosspoint Specification
Crosspoint Specification
650
600
550
500
450
400
350
300
250
200
550 mV
550 + 0.5 (VHavg - 710)
250 + 0.5 (VHavg - 710)
250 mV
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
Vhavg (mV)
Figure 8. System Bus Common Clock Valid Delay Timing Waveform
T0
T1
T2
BCLK1
BCLK0
TP
Common Clock
Signal (@ driver)
valid
valid
TQ
TR
Common Clock
Signal (@ receiver)
valid
TP = T10: Common Clock Output Valid Delay
TQ = T11: Common Clock Input Setup
TR = T12: Common Clock Input Hold Time
2-24
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Figure 9. System Bus Source Synchronous 2X (Address) Timing Waveform
T1
T2
1/4
1/2
3/4
BCLK BCLK BCLK
BCLK1
BCLK0
TP
ADSTB# (@ driver)
A# (@ driver)
TR
TH
TJ
TH
TJ
valid
valid
TS
ADSTB# (@ receiver)
A# (@ receiver)
TK
valid
valid
TN
TM
TH = T23: Source Sync. Address Output Valid Before Address Strobe
TJ = T24: Source Sync. Address Output Valid After Address Strobe
TK = T27: Source Sync. Input Setup to BCLK
TM = T26: Source Sync. Input Hold Time
TN = T25: Source Sync. Input Setup Time
TP = T28: First Address Strobe to Second Address Strobe
TS = T20: Source Sync. Output Valid Delay
TR = T31: Address Strobe Output Valid Delay
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-25
Electrical Specifications
Figure 10. System Bus Source Synchronous 4X (Data) Timing Waveform
T0
T1
T2
1/4
1/2
3/4
BCLK BCLK BCLK
BCLK1
BCLK0
DSTBp# (@ driver)
DSTBn# (@ driver)
TH
TD
TA TB TA
D# (@ driver)
TJ
DSTBp# (@ receiver)
DSTBn# (@ receiver)
D# (@ receiver)
TC
TE TG TE TG
TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe
TB = T22: Source Sync. Data Output Valid Delay After Data Strobe
TC = T27: Source Sync. Setup Time to BCLK
TD = T30: Source Sync. Data Strobe 'N' (DSTBN#) Output Valid Delay
TE = T25: Source Sync. Input Setup Time
TG = T26: Source Sync. Input Hold Time
TH = T29: First Data Strobe to Subsequent Strobes
TJ = T20: Source Sync. Data Output Valid Delay
2-26
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Figure 11. System Bus Reset and Configuration Timing Waveform
T
u
T
t
RESET#
T
v
T
x
Configuration
Safe
Valid
Valid
(A[31:3]#, BR0#,
SMI#, INIT#)
Tw
Configuration
(A[31:3]#, BR0#,
SMI#, INIT#)
T
v
=
=
T13 (RESET# Pluse Width)
T
T45 (Reset Configuration Signals (A[14:5]#, BR0#, SMI#, INIT#) Setup Time)
w
T
T46 (Reset Configuration signals (A[14:5]#, BR0#, SMI#, INIT#) Hold Time)
x
=
Figure 12. Power-On Reset and Configuration Timing Waveform
BLCK
VCC
PWRGOOD
T
a
T
b
RESET#
Ta = T37 (PWRGOOD Inactive Pluse Width)
Tb = T36 (PWRGOOD to RESET# de-assertion time)
NOTES:
1. The function of configuration signals (A20M#, IGNNE#, LINT[1:0]) are illustrated for legacy designs only.
Setting the bus ratio for Intel Xeon processor MP on the 0.13 micron process processor is software
controlled.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-27
Electrical Specifications
Figure 13. TAP Valid Delay Timing Waveform
V
TCK
Ts
Th
Tx
Signal
V Valid
Tx = T63 (TDO Clock to Output Delay)
Ts = T61 (TDI, TMS Setup Time)
Th = T62 (TDI, TMS Hold Time)
V = 0.5 *Vcc
Figure 14. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform
V
T
q
T64 (TRST# Pulse Width), V = 0.5 * Vcc
T38 (PROCHOT# Pulse Width), V=GTLREF
T
=
q
Figure 15. THERMTRIP# to Vcc Timing
T39
THERMTRIP#
Vcc
T39 < 0.5 seconds
NOTE: THERMTRIP# is undefined when RESET is active.
2-28
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Figure 16. SMBus Timing Waveform
t
t
F
t
HD;STA
R
t
LOW
Clk
t
t
t
t
t
HIGH
SU;STO
t
HD;STA
SU;STA
HD;DAT
SU;DAT
Data
t
BUF
S
S
P
P
STOP
START
START
STOP
t
t
t
t
t
t
t
t
t
=
=
=
=
T80
T78
T79
T77
= T73
=T81
=T82
LOW
HD;STA
HD;DAT
BUF
SU;STA
SU;STD
t
HIGH = T72
R
F
=
T74
= T75
SU;DAT
Figure 17. SMBus Valid Delay Timing Waveform
SM_CLK
TAA
DATA VALID
SM_DAT
DATA OUTPUT
TAA = T76
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-29
Electrical Specifications
Figure 18. Example 3.3 Volt/SM_VCC Sequencing
Power UP
T0=95% 3.3 volt level
3.3 VDC/SM_VCC
OUTEN
> T0 + 100 ms
PWR_OK /
VID[4:0]
T0 + 1 mS
T0 + 1 mS
BSEL[1:0]
VRM PWRGD
> 10 ms
Processor
PWRGOOD
Processor
RESET#
1 ms<T36<10 ms
VID[4:0]
PWRGD
VRM
PWRGOOD
OUTEN
CPU
PWR_OK
SM_VCC
Power
Supply
3.3 VDC
95% 3.3 volt level
Power Down
3.3 VDC/SM_VCC
PWROK
Power Down Warning > 1 ms
2-30
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Electrical Specifications
Figure 19. FERR#/PBE# Valid Delay Timing
BCLK
system bus
STPCLK#
SG
Ack
Ta
FERR#/
FERR# undefined
PBE#
undefined FERR#
PBE#
Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion)
Note: FERR#/PBE# is undefined from STPCLK# assertion until the stop grant acknowledge is driven on the processor system
bus. FERR#/PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions the PBE#
signal is driven. FERR# is driven at all other times.
§
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
2-31
Electrical Specifications
2-32
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
System Bus Signal Quality Specifications
System Bus Signal Quality
Specifications
3
Source synchronous data transfer requires the clean reception of data signals and their associated
strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage
swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be
tolerated since these phenomena may inadvertently advance receiver state machines. Excessive
signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can
cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and
undershoot can degrade timing due to the build up of inter-symbol interference (ISI) effects. For
these reasons, it is crucial that the designer assure acceptable signal quality across all systematic
variations encountered in volume manufacturing.
This section documents signal quality metrics used to derive topology and routing guidelines
through simulation and all specifications are specified at the processor core (pad measurements).
Specifications for signal quality are for measurements at the processor core only and are only
observable through simulation. The same is true for all system bus AC timing specifications in
Section 2.13.
3.1
System Bus Clock (BCLK) Signal Quality
Specifications and Measurement Guidelines
Table 22 describes the signal quality specifications at the processor pads for the processor system
bus clock (BCLK) signals. Figure 20 describes the signal quality waveform for the system bus
clock at the processor pads.
Table 22. BCLK Signal Quality Specifications
1
Parameter
BCLK[1:0] Overshoot
Min
Max
0.30
0.30
N/A
Unit
V
Figure
20
Notes
N/A
N/A
0.20
N/A
BCLK[1:0] Undershoot
V
20
BCLK[1:0] Ringback Margin
BCLK[1:0] Threshold Region
V
20
0.10
V
20
2
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
3-1
System Bus Signal Quality Specifications
Figure 20. BCLK[1:0] Signal Integrity Waveform
Overshoot
VH
BCLK1
Rising Edge
Ringback
Crossing
Voltage
Crossing
Voltage
Ringback
Margin
Threshold
Region
Falling Edge
Ringback,
BCLK0
VL
Undershoot
3.2
System Bus Signal Quality Specifications and
Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the appropriate platform design guidelines.
Table 23 provides the signal quality specifications for all processor signals for use in simulating
signal quality at the processor pads.
Intel Xeon processor MP on the 0.13 micron process processor maximum allowable overshoot and
undershoot specifications for a given duration of time are detailed in Table 25 through Table 28.
Figure 21 shows the system bus ringback tolerance for low-to-high transitions and Figure 22 shows
ringback tolerance for high-to-low transitions.
Table 23. Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers
Maximum Ringback
(with Input Diodes Present)
Signal Group
Transition
Unit
Figure
Notes
AGTL+, Asynch GTL+
AGTL+, Asynch GTL+
L → H
H → L
GTLREF + 0.100*GTLREF
GTLREF - 0.100*GTLREF
V
V
21
22
1, 2, 3, 4, 5, 6
1, 2, 3, 4, 5, 6
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all Intel Xeon processor MP on the 0.13 micron
process processor frequencies and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0 V/ns at the receiver.
4. All values specified by design characterization.
5. Please see Section 3.1 for maximum allowable overshoot.
6. Intel recommends simulations not exceed a ringback value of GTLREF ± 0.100*GTLREF to allow margin for
other sources of system noise.
3-2
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
System Bus Signal Quality Specifications
Table 24. Ringback Specifications for PWRGOOD Input and TAP Buffers
Maximum Ringback
(with Input Diodes
Present)
Signal
Group
Transition
Threshold
Unit
Figure
Notes
TAP and
PWRGOOD
L → H
H → L
VT+(max) TO VT-(max)
VT-(min) TO VT+(min)
VT+(max)
VT-(min)
V
V
23
24
1, 2, 3, 4, 5
1, 2, 3, 4, 5
TAP and
PWRGOOD
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all Intel Xeon processor MP on the 0.13 micron
process processor frequencies and cache sizes
3. Specifications are for the edge rate of 0.3 - 4.0 V/ns.
4. All values specified by design characterization.
5. Please see Section 3.1 for maximum allowable overshoot.
Figure 21. Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and
Asynchronous GTL+ Buffers
VCC
Noise Margin
+10%
GTLREF
-10%
VSS
Figure 22. High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and
Asynchronous GTL+ Buffers
VCC
+10%
GTLREF
-10%
Noise Margin
VSS
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
3-3
System Bus Signal Quality Specifications
Figure 23. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers
Vcc
Threshold Region to switch
receiver to a logic 1.
Vt+ (max)
Vt+ (min)
0.5 * Vcc
Vt- (max)
Allowable Ringback
Vss
3-4
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
System Bus Signal Quality Specifications
Figure 24. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers
Vcc
Allowable Ringback
Vt+ (min)
0.5 * Vcc
Vt- (max)
Vt- (min)
Threshold Region to switch
receiver to a logic 0.
Vss
3.3
System Bus Signal Quality Specifications and
Measurement Guidelines
3.3.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS. The
overshoot/undershoot specifications limit transitions beyond VCC or VSS due to the fast signal edge
rates. The processor can be damaged by single and/or repeated overshoot or undershoot events on
any input, output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great
enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the
magnitude, the pulse direction, and the activity factor (AF). Permanent damage to the processor is
the likely result of excessive overshoot/undershoot.
When performing simulations to determine impact of overshoot and undershoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modelled within Intel I/O buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the Intel Xeon processor MP on the 0.13 micron process processor
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
3-5
System Bus Signal Quality Specifications
system bus, care must be taken to ensure that ESD models do not clamp extreme voltage levels.
Intel I/O buffer models also contain I/O capacitance characterization. Therefore, removing the ESD
diodes from an I/O buffer model will impact results and may yield excessive overshoot/undershoot.
3.3.2
Overshoot/Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference
level. For the Intel Xeon processor MP on the 0.13 micron process processor both are referenced to
VSS. It is important to note that overshoot and undershoot conditions are separate and their impact
must be determined independently.
Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed
in Table 25 through Table 28. These specifications must not be violated at any time regardless of
bus activity or system state. Within these specifications are threshold levels that define different
allowed pulse duration. Provided that the magnitude of the overshoot/undershoot is within the
absolute maximum specifications, the pulse magnitude, duration and activity factor must all be
used to determine if the overshoot/undershoot pulse is within specifications.
3.3.3
3.3.4
Overshoot/Undershoot Pulse Duration
Pulse duration describes the total time an overshoot/undershoot event exceeds VID. The total time
could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot
pulses within a single overshoot/undershoot event may need to be measured to determine the total
pulse duration.
Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot
pulse duration.
Activity Factor
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of any common clock signal is every other clock, an
AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock
cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs
one time in every 200 clock cycles.
For source synchronous signals (address, data, and associated strobes), the activity factor is in
reference to the strobe edge. The highest frequency of assertion of any source synchronous signal is
every active edge of its associated strobe. So, an AF = 1 indicates that the specific overshoot (or
undershoot) waveform occurs every strobe cycle.
The specifications provided in Table 25 through Table 28 show the maximum pulse duration
allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is
independent of all others, meaning that the pulse duration reflects the existence of overshoot/
undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just
meets the pulse duration for a specific magnitude where the AF < 1, means that there can be no
other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event
occurs at all times and no other events can occur).
3-6
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
System Bus Signal Quality Specifications
NOTES:
1. Activity factor for common clock AGTL+ signals is referenced to BCLK[1:0] frequency.
2. Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#.
3. Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]#and DSTBN[3:0]#.
3.3.5
Reading Overshoot/Undershoot Specification Tables
The overshoot/undershoot specification for the Intel Xeon processor MP on the 0.13 micron
process processor is not a simple single value. Instead, many factors are needed to determine the
over/undershoot specification. In addition to the magnitude of the overshoot, the following
parameters must be considered: the width of the overshoot and the activity factor (AF). To
determine the allowed overshoot for a particular overshoot event, the following must be done:
1. Determine the signal group that particular signal falls into. For AGTL+ signals operating in
the 4X source synchronous domain, use Table 25. For AGTL+ signals operating in the 2X
source synchronous domain, use Table 26. If the signal is an AGTL+ signal operating in the
common clock domain, use Table 27. Finally, all other signals reside in the 33 MHz domain
(asynchronous GTL+, TAP, etc.) and are referenced in Table 28.
2. Determine the magnitude of the overshoot or the undershoot (relative to VSS).
3. Determine the activity factor (how often does this overshoot occur).
4. Next, from the appropriate specification table, determine the maximum pulse duration (in
nanoseconds) allowed.
5. Compare the specified maximum pulse duration to the signal being measured. If the pulse
duration measured is less than the pulse duration shown in the table, then the signal meets the
specifications.
Undershoot events must be analyzed separately from overshoot events as they are mutually
exclusive.
3.3.6
Determining if a System Meets the Overshoot/Undershoot
Specifications
The overshoot/undershoot specifications listed in the following tables specify the allowable
overshoot/undershoot for a single overshoot/undershoot event. However most systems will have
multiple overshoot and/or undershoot events for a given transition, with each having their own set
of parameters (duration, AF and magnitude). While each overshoot on its own may meet the
overshoot specification, when you add the total impact of all overshoot events, the system may fail
(see Figure 25). A guideline to ensure a system passes the overshoot and undershoot specifications
is shown below.
1. Ensure no signal ever exceeds VCC or -0.25V or
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot
specifications in the following tables or
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse
duration for each magnitude and compare the results against the AF = 1 specifications. If all of
these worst case overshoot or undershoot events meet the specifications (measured time <
specifications) in the table (where AF=1), then the system passes.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
3-7
System Bus Signal Quality Specifications
The following notes apply to Table 25 through Table 28.
NOTES:
1. Absolute Maximum Overshoot magnitude of 1.8V must never be exceeded.
2. Absolute Maximum Overshoot is measured referenced to VSS, Pulse Duration of overshoot is measured
relative to VCC
.
3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS
4. Ringback below VCC cannot be subtracted from overshoots/undershoots.
5. Lesser undershoot does not allocate longer or larger overshoot.
6. OEMs are strongly encouraged to follow Intel layout guidelines.
7. All values specified by design characterization.
.
8. Refer to Table 5 for signal group definitions.
Table 25. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Source
Synchronous AGTL+ Signal Group (Data) Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse Duration
(ns)
Pulse Duration
(ns)
Pulse Duration
(ns)
AF = 1
AF = 0.1
AF = 0.01
1.80
1.75
1.70
1.65
1.60
1.55
1.50
- 0.347
- 0.297
- 0.247
- 0.197
- 0.147
- 0.097
- 0.047
0.04
0.12
0.36
1.05
3.09
5.00
5.00
0.46
1.37
5.00
5.00
5.00
5.00
5.00
4.70
5.00
5.00
5.00
5.00
5.00
5.00
NOTES:
1. These specifications are measured at the processor pad.
2. Assumes a BCLK period of 10 ns.
3. AF is referenced to associated source synchronous strobes
Table 26. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Common Clock
AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse Duration
(ns)
Pulse Duration
(ns)
Pulse Duration
(ns)
AF = 1
AF = 0.1
AF = 0.01
1.80
1.75
1.70
1.65
1.60
1.55
1.50
- 0.347
- 0.297
- 0.247
- 0.197
- 0.147
- 0.097
- 0.047
0.08
0.25
0.86
2.53
8.67
10.00
10.00
10.00
10.00
10.00
10.00
0.73
7.34
2.11
10.00
10.00
10.00
10.00
6.19
10.00
10.00
NOTES:
1. These specifications are measured at the processor pad.
2. Assumes a BCLK period of 10 ns.
3. AF is referenced to associated source synchronous strobes.
.
3-8
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
System Bus Signal Quality Specifications
Table 27. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Common Clock
AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse Duration
(ns)
Pulse Duration
(ns)
Pulse Duration
(ns)
AF = 1
AF = 0.1
AF = 0.01
1.80
1.75
1.70
1.65
1.60
1.55
1.50
- 0.347
- 0.297
- 0.247
- 0.197
- 0.147
- 0.097
- 0.047
0.17
0.50
1.73
5.06
17.34
20.00
20.00
20.00
20.00
20.00
20.00
1.46
14.69
20.00
20.00
20.00
20.00
4.23
12.39
20.00
20.00
NOTES:
1. These specifications are measured at the processor pad.
2. BCLK period is 10 ns.
3. WIRED OR signals on Intel Xeon processor MP on the 0.13 micron process processor can tolerate up to 1 V
of overshoot/undershoot.
4. AF is referenced to BCLK[1:0].
Table 28. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Asynchronous
GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance
Absolute
Maximum
Overshoot
(V)
Absolute
Maximum
Undershoot
(V)
Pulse Duration
(ns)
Pulse Duration
(ns)
Pulse Duration
(ns)
AF = 1
AF = 0.1
AF = 0.01
1.80
1.75
1.70
1.65
1.60
1.55
1.50
- 0.347
- 0.297
- 0.247
- 0.197
- 0.147
- 0.097
- 0.047
0.52
1.51
5.20
52.03
60.00
60.00
60.00
60.00
60.00
60.00
15.19
44.90
60.00
60.00
60.00
60.00
4.40
12.71
37.19
60.00
60.00
NOTES:
1. These specifications are measured at the processor pad.
2. These signals are assumed in a 33 MHz time domain.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
3-9
System Bus Signal Quality Specifications
Figure 25. Maximum Acceptable Overshoot/Undershoot Waveform
Maximum
Absolute
Overshoot
Time-dependent
Overshoot
VMAX
VCC
GTLREF
VOL
VSS
VMIN
Time-dependent
Undershoot
Maximum
Absolute
Undershoot
§
3-10
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Mechanical Specifications
Mechanical Specifications
4
The Intel Xeon processor MP on the 0.13 micron process processor uses a Micro-Pin Grid Array
(INT-mPGA) packaging technology. The Intel Xeon processor with 512-KB of L2 cache uses the
INT-mPGA package for 400 MHz system bus processors and the Flip Chip Micro-Pin Grid Array
(FC-mPGA2) package for 533 MHz system bus processors. In addition, the Low Voltage Intel
Xeon processor uses the Flip Chip Micro-Pin Grid Array (FC-mPGA2) package for 400 MHz
system bus processors. Both packages include an integrated heat spreader (IHS). The Intel Xeon
processor MP on the 0.13 micron process and the Intel Xeon processor in INT-mPGA package
include the processor die, and a pinned FR4 interposer. The Intel Xeon processor in the FC-
mPGA2 package contains the processor die but no interposer, PIROM or scratch EEPROM.
Mechanical specifications for the processor are given in this section. See Section 1.1 for
terminology definitions. Figure 26 and Figure 27 provide a basic processor assembly drawing and
includes the components which make up the entire processor. The Intel Xeon processor MP on the
0.13 micron process processor and the Intel Xeon processor in INT-mPGA package also includes
several SMBus components on the package interposer, an EEPROM, and a thermal sensor.
Table 29 provides dimensions for the package shown in Figure 28. These dimensions describe a
high thermal performance package for use on the Intel Xeon processor MP on the 0.13 micron
process processor. A thermal performance benefit is expected from the use of an IHS with an
increase in thickness from 1.5 mm to 3.0 mm. This results in a change from the Intel Xeon
processor package configuration.
The Intel Xeon processor MP on the 0.13 micron process processor and the Intel Xeon processor in
INT-mPGA utilize a surface mount 603-pin zero-insertion force (ZIF) socket for installation into
the baseboard. Please refer to the 603- Pin Socket Design Guidelines for further details on the
processor socket. The Intel Xeon processor in the FC-mPGA2 package utilizes a surface mount
604-pin zero-insertion force (ZIF) socket for installation into the baseboard. The 604-pin socket is
required to accommodate the solder fillet on the FC-mPGA2 package pins. Please refer to the 604-
Pin Socket Design Guidelines for further details on the processor socket. Note that Intel Xeon
processor in INT-mPGA package can utilize the 604-pin socket.
Note: For Figure 26 through Figure 37, the following notes apply:
1. Unless otherwise specified, the following drawing dimensions are expressed in millimeters.
2. Currently, all mechanical specifications are preliminary and subject to change.
3. Figures and drawings labelled as “Reference Dimensions” are provided for informational
purposes only. Reference Dimensions are extracted from the mechanical design database and
are nominal dimensions with no tolerance information applied. Reference Dimensions are
NOT checked as part of the processor manufacturing process. Unless noted as such,
dimensions in parentheses without tolerances are Reference Dimensions.
4. The Intel Xeon processor MP on the 0.13 micron process processor will utilize a 42.5 mm
INT-mPGA package and for the purpose of this section will be referred to as the “Xeon MP
package.” The Intel Xeon processor will use a 35 mm INT-mPGA or 31 mm for the FC-
mPGA2 package. The differences between these packages include the package dimensions
and the IHS dimensions. Thermal solutions should be designed to support both packages and
their associated IHS sizes. See the Intel® Xeon™ Processor (MP) Thermal Design Guidelines
for additional details on thermal solution design.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
4-1
Mechanical Specifications
Figure 26. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel®
Xeon™ Processor with 512-KB L2 Cache in INT-mPGA Package - Assembly
Drawing (Including Socket)
1
2
5
6
3
4
7
8
9
Note: This drawing is not to scale and is for reference only. The assembly applies to both Intel Xeon
processor MP on the 0.13 micron process processor and Intel Xeon processor in the INT-mPGA
package. The 603-pin socket is supplied as a reference only.
1. Integrated Heat Spreader (IHS)
2. Thermal Interface Material (TIM) between processor die and IHS
3. Processor die
4. Flip Chip interconnect
5. FCBGA (Flip Chip Ball Grid Array) package
6. FCBGA solder joints
7. Processor interposer
8. 603-pin socket
9. 603-pin socket solder joints
4-2
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Mechanical Specifications
4.1
Mechanical Specifications
Figure 27. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Package Top
View Component Placement Detail
Pin A1
CPU
Figure 28. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Package
Drawing
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
4-3
Mechanical Specifications
Table 29. Dimensions for the Intel® Xeon™ Processor MP on the 0.13 Micron Process
Processor Package
Millimeters
Symbol
Notes
Min
Nominal
53.34
Max
A
B
C
D
E
F
53.19
42.45
38.40
3.47
53.49
42.64
38.95
4.15
42.50
38.50
3.81
Includes placement tolerance
Includes placement tolerance
6.05
6.50
6.95
1.95
2.03
2.11
G
H
J
19.05
38.10
7.32
Nominal
Nominal
7.19
7.44
K
L
14.38
14.63
13.97
30.48
6.05
14.88
Nominal
Nominal
M
N
5.92
0.28
6.17
0.36
φP
R
0.31
Pin Diameter
Nominal
1.27
T
14.38
14.63
14.88
0.26
Pin Tp
Figure 29 details the keep-in zone for components mounted to the top side of the processor
interposer for the Intel Xeon processor MP on the 0.13 micron process processor and Intel Xeon
processor in INT-mPGA package. The components include the EEPROM, thermal sensor, resistors
and capacitors.
4-4
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Mechanical Specifications
Figure 29. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Top View -
Component Keep-In
Figure 30 details the keep in specification for pin-side components. The Intel Xeon processor MP
on the 0.13 micron process processor may contain pin side capacitors mounted to the processor
INT-mPGA package. The capacitors will be exposed within the opening of the interposer cavity.
This keep-out specification applies to the Intel Xeon processor MP on the 0.13 micron process
processor and the Intel Xeon processor in INT-mPGA package.
Figure 30. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel®
Xeon™ Processor with 512-KB L2 Cache in INT-mPGA Package - Cross Section
View - Pin Side Component Keep-In
IHS
FCBGA
Interposer
1.270mm
Component
Keepin
13.411mm
Component Keepin
Socket must allow clearance
for pin shoulders and mate
flush with this surface
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
4-5
Mechanical Specifications
Figure 31. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel®
Xeon™ Processor with 512-KB L2 Cache in INT-mPGA Package - Processor Pin
Details
NOTES:
1. Kovar pin with plating of 0.2 micrometers Au over 2.0 micrometer Ni.
2. 0.254 Diametric true position, pin to pin.
Figure 32 and Figure 33 detail the flatness and tilt specifications for the IHS of the Intel Xeon
processor MP on the 0.13 micron process processor and Intel Xeon processor. Tilt is measured with
the reference datum set to the bottom of the processor interposer.
4-6
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Mechanical Specifications
Figure 32. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Package IHS
Flatness and Tilt Drawing
Figure 33. Intel® Xeon™ Processor MP on the 0.13 Micron Process INT-mPGA Package IHS
Flatness and Tilt Drawing
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
4-7
Mechanical Specifications
4.2
Package Load Specifications
Table 30 provides dynamic and static load specifications for the Intel Xeon processor MP on the
0.13 micron process processor IHS. These mechanical load limits should not be exceeded during
heat sink assembly, mechanical stress testing, or standard drop and shipping conditions. The heat
sink attach solutions must not induce continuous stress onto the processor with the exception of a
uniform load to maintain the heat sink-to-processor thermal interface. It is not recommended to use
any portion of the processor interposer as a mechanical reference or load bearing surface for
thermal solutions.
Table 30. Package Dynamic and Static Load Specifications
Parameter
Max
Unit
Notes
Static
50
lbf
lbf
1, 2, 3
Dynamic
50 + 1 lb * 50G input * 1.8 (AF)
1, 2, 4,5
NOTES:
1. This specification applies to a uniform compressed load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface.
3. These parameters are based on design characterization and not tested.
4. Dynamic loading specifications are defined assuming a maximum duration of 11 ms.
5. 1 lb is Heatsink weight. 50 G is shock input to the system during shock testing. AF is the amplification factor.
This is equivalent to 140 lbs.
4.3
4.4
Insertion Specifications
The Intel Xeon processor MP on the 0.13 micron process processor can be inserted and removed 15
times from a 603/604-pin socket meeting the 603-Pin Socket Design Guidelines document.
Mass Specifications
Table 31 specifies the processors mass. This includes all components which make up the entire
processor product.
Table 31. Processor Mass
Processor
Mass (grams)
Intel® Xeon™ processor MP on the 0.13 micron process processor
with 1-MB L3 cache
57
Intel® Xeon™ processor MP on the 0.13 micron process processor
with 2-MB L3 cache
57
4-8
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Mechanical Specifications
4.5
Materials
The Intel Xeon processor MP on the 0.13 micron process processor is assembled from several
components. The basic material properties are described in Table 32.
Table 32. Processor Material Properties
Component
Material
Notes
Integrated Heat Spreader
INT-mPGA & FC-mPGA2 package
Interposer
Nickel plated copper
BT Resin
FR4
Interposer pins (INT-mPGA2)
FC-mPGA2 package pins
Kovar with Gold over nickel
Cu Alloy 194
4.6
Markings
Figure 34 shows the topside markings while Figure 35 shows the bottom side markings on the
processor. These diagrams are to aid in the identification of the Intel Xeon processor MP on the
0.13 micron process processor.
Figure 34. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Top-Side
Markings (Package Example)
Dynamic Laser
Mark Area with 2D Matrix
Group A Line1
Group A Line2
2D Matrix encodes ATPO
number and Serial number
Pin A1
NOTES:
1. Character size for laser marking is: height 0.050 inch (1.27mm), width 0.032 inch (0.81mm)
2. All characters will be in upper case.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
4-9
Mechanical Specifications
Figure 35. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Bottom-Side
Markings (Package Example)
Engr (QDF)
Sample Mark
Prod(SSPEC)
Sample Mark
Description
Legal mark
Group A Line 1 Intel Confidential {Intel Brand}
Group A Line 2 i(m) '02
i(m) '02
Group B Line 1 XXXXXXXX
Croup B Line 2 YYYY
XXXXXXXX
YYYY
ATPO mark
Serial number mark
Group C Line 1 80532KC2.0G2M 2000/2M/400/1/475V Product code
Group C Line 2 QXXXCosta Rica S XXXCosta Rica
Group C Line 3 XXXXXXXX-YYYY XXXXXXXX-YYYY
QDF/Sspec, Assy site
FPO-SN mark
Group C Line 1
Group C Line 2
Group C Line 3
*Example shown is a 2.0GHz Intel(R) Xeon(TM) Processor
Pin A1
4.7
Pinout Diagram
This section provides two views of the processor pin grid. Figure 36 and Figure 37 detail the
coordinates of the Intel Xeon processor MP on the 0.13 micron process processor and Intel Xeon
processor in INT-mPGA 603-pins package.
4-10
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Mechanical Specifications
Figure 36. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel®
Xeon™ Processor with 512-KB L2 Cache in INT-mPGA Package - Pinout Diagram -
Top View
COMMON
CLOCK
COMMON
CLOCK
Async /
JTAG
ADDRESS
1
3
5
7
9
11
13
15
17
19
21
23 25
27
29
31
A
B
A
B
C
D
C
D
E
E
F
F
G
H
J
G
H
J
K
L
M
N
P
R
K
L
Intel® Xeon™ Processor MP
on the 0.13 Micron Process
Processor
M
N
P
Top View
R
T
T
U
V
U
V
W
Y
W
Y
AA
AA
AB
AC
AD
AB
AC
AD
AE
AE
2
4
6
8
10
12
14
16
18
20
22
24
26
28
CLOCKS
DATA
SMBus
= Signal
= Power
= Ground
= SM_VCC
= GTLREF
= Reserved
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
4-11
Mechanical Specifications
Figure 37. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel®
Xeon™ Processor with 512-KB L2 Cache in INT-mPGA Package - Pinout Diagram -
Bottom View
Async /
JTAG
COMMON
CLOCK
COMMON
CLOCK
ADDRESS
31
29
27
25 23 21
19 17 15
13 11
9
7
5
3
1
A
B
A
B
C
C
D
D
E
E
F
F
G
G
H
J
H
J
K
L
M
N
P
R
K
L
Intel® Xeon™ Processor MP on the
0.13 Micron Process Processor
Family
M
N
P
Bottom View
R
T
T
U
V
W
U
V
W
Y
Y
AA
AB
AA
AB
AC
AC
AD
AE
AD
AE
28 26 24
22 20
18 16
14 12 10
= SM_VCC
8
6
4
2
SMBus
DATA
CLOCKS
= Signal
= Power
= Ground
= GTLREF
= Reserved
§
4-12
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Thermal Specifications
Thermal Specifications
5
This chapter provides the thermal specifications necessary for designing a thermal solution for the
Intel Xeon processor MP on the 0.13 micron process processor. The IHS provides a common
interface intended to be compatible with many heatsink designs. Thermal specifications are based
on the temperature of the IHS top, referred to as “TCASE”. Thermal solutions should be designed to
maintain the processor within its TCASE specifications. For information on performing Tcase
measurements for thermal solution design and validation, refer to the Intel® Xeon™ Processor
(MP) Thermal Design Guidelines. See Figure 38 for an exploded view of the processor package
and thermal solution assembly. For boxed processor specifications, refer to Section 7.
Note: The processor is either shipped alone or with a heatsink (boxed processor only). All other
components shown in Figure 38 must be purchased separately.
Figure 38. Thermal and Mechanical Components - Exploded View
Heat sink clip
Heat sink
EMI ground
frame
Retention
mechanism
603-pin
socket
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
5-1
Thermal Specifications
NOTE: This is a graphical representation. It is applicable for the 604-pin socket also which is required for the
Intel Xeon processor with 512-KB L2 cache in the FC-mPGA2 package. For specifications, see each
component’s respective documentation listed in Section 1.2.
5-2
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Thermal Specifications
5.1
Thermal Specifications
To assure the optimal operation and long-term reliability of Intel Xeon processor-based systems,
the system/processor thermal solution should be designed such that the processor remains between
the minimum and maximum case temperature (TC) specifications when operating at or below the
Thermal Design Power (TDP) value listed per frequency in Table 33.Thermal solutions not
designed to provide this level of thermal capability may affect the long-term reliability of the
processor and system. For more details on thermal solution design, please refer to the appropriate
processor thermal design guidelines.
The case temperature is defined at the geometric top center of the processor IHS (Integrated Heat
Spreader). Analysis indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that complete thermal
solution designs target the Thermal Design Power (TDP) indicated in Table 33 instead of the
maximum processor power consumption. The Thermal Monitor feature is intended to help protect
the processor in the unlikely event that an application exceeds the TDP recommendation for a
sustained period of time. For more details on the usage of this feature, refer to Section 6.3. To
ensure maximum flexibility for future requirements, systems should be designed to the Flexible
Motherboard Guidelines (FMB), even if a processor with a lower thermal dissipation is currently
planned. In all cases, the Thermal Monitor feature must be enabled for the processor to remain
within specification
.
Table 33. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Thermal Design
Power
Maximum
Processor
Power (W)
ThermalDesign
Minimum
TCASE
(°C)
Maximum
TCASE
2
7
3, 4
Core Frequency
Power
(W)
Note
1
(°C)
Processor with 2-MB
L3 Cache
2 GHz
65
83
57
72
5
5
69
69
2.80 Ghz
Processor 1-MB L3
Cache
1.50 GHz
1.90 GHz
2 GHz
54
63
65
74
48
55
57
66
5
5
5
5
67
68
69
70
2.50 GHz
NOTES:
1. Maximum Processor Power is the maximum thermal power that can be dissipated by the processor through
the integrated heat spreader.
2. Intel recommends that thermal solutions be designed to meet the Thermal Design Power guidelines. Refer to
®
the Intel Xeon™ Processor (MP) Thermal Design Guidelines.
3. TDP values are specified at the point on Vcc_max loadline corresponding to Icc_TDP.
4. Systems must be designed to ensure that the processor is not subjected to any static Vcc and Icc
combination wherein Vcc exceeds Vcc_max at specified Icc. Please refer to the loadline specifications in
Section 2.
5. Values are based on the latest silicon available at the time of publication. Any updates will be provided in a
future revision of this document.
6. Actual specifications for future processor frequencies may be different.
7. TCASE values are based on Intel reference heatsink with psi_ca of 0.33 C/W. Refer to the Intel Xeon™
®
Processor (MP) Thermal Design Guidelines for details.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
5-3
Thermal Specifications
Figure 39. Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Thermal Design
Power vs. Electrical Projections
1.455
1.450
1.445
1.440
1.435
80
70
60
50
40
TDP
VMAX
35
40
45
50
55
60
65
70
Processor MaximumCurrent (A)
5-4
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Thermal Specifications
5.2
Measurements for Thermal Specifications
5.2.1
Processor Case Temperature Measurement
The maximum and minimum case temperature (TC) for the Intel Xeon Processor is specified in
Table 33. This temperature specification is meant to help ensure proper operation of the processor.
Figure 40 illustrates where Intel recommends TC thermal measurements should be made.
Figure 40. Thermal Measurement Point for Processor TCASE
Measure from edge of processor interposer
Measure TCASE at this point
(geometric center of IHS)
26.67 mm [1.05 in]
22.86 mm [0.90 in]
Thermal grease should cover
entire area of IHS
Intel® Xeon™ MP Processor with up to 2-MB L3 Cache
(53.34 mm x 53.34 mm interposer)
NOTE: Figure is not to scale, and is for reference only
§
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
5-5
Thermal Specifications
5-6
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Features
Features
6
6.1
Power-On Configuration Options
Intel Xeon processor MP on the 0.13 micron process processor members have several
configuration options that are determined by the state of specific processor pins at the active-to-
inactive transition of the processor RESET# signal. These configuration options cannot be changed
except by another reset. Both power on and software induced resets reconfigure the processor(s).
Table 34. Power-On Configuration Option Pins
1
Configuration Option
Pin
Notes
Output tri state
SMI#
INIT#
Execute BIST (Built-In Self Test)
In Order Queue de-pipelining (set IOQ depth to 1)
Disable MCERR# observation
Disable BINIT# observation
APIC cluster ID (0-3)
A7#
A9#
A10#
A[12:11]#
A15#
2
3
Disable bus parking
Disable Hyper-Threading Technology
Symmetric agent arbitration ID
A31#
BR[3:0]#
NOTES:
1. Asserting this signal during active-to-inactive edge of RESET# will selects the corresponding option.
6.2
Clock Control and Low Power States
The Intel Xeon processor MP on the 0.13 micron process processor allows the use of AutoHALT,
Stop-Grant and Sleep states to reduce power consumption by stopping the clock to internal sections
of the processor, depending on each particular state. See Figure 41 for a visual representation of the
processor low power states.
Due to the inability of processors to recognize bus transactions during the Sleep state,
multiprocessor Intel Xeon processor MP on the 0.13 micron process processor based systems are
not allowed to simultaneously have one processor in Sleep state and the other processors in Normal
or Stop-Grant state.
6.2.1
6.2.2
Normal State—State 1
This is the normal operating state for the processor.
AutoHALT Powerdown State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#,
LINT[1:0] (NMI, INTR), or an interrupt delivered over the system bus. RESET# will cause the
processor to immediately initialize itself.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
6-1
Features
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
Figure 41. Stop Clock State Machine
HALT Instruction and
HALT Bus Cycle Generated
2. Auto HALT Power Down State
BCLK running
INIT#, BINIT#, INTR, NMI,
SMI#, RESET#
.
1. Normal State
Normal execution
Snoops and interrupts allowed
STPCLK#
De-asserted
STPCLK#
Asserted
Snoop
Event
Snoop
Event
Occurs
Serviced
4. HALT/Grant Snoop State
BCLK running
3. Stop Grant State
BCLK running
Snoop Event Occurs
Snoop Event Serviced
Service snoops to caches
Snoops and interrupts allowed
SLP#
Asserted
SLP#
De-asserted
5. Sleep State
BCLK running
No snoops or interrupts
allowed
6.2.3
Stop-Grant State—State 3
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks
after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once
the STPCLK# pin has been asserted, it may only be deasserted once the processor is in the Stop
Grant state. For the Intel Xeon processor MP on the 0.13 micron process processor, both logical
processors must be in the Stop Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VCC) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
6-2
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Features
BINIT# will be recognized while the processor is in Stop-Grant state. If STPCLK# is still asserted
at the completion of the BINIT# bus initialization, the processor will remain in Stop-Grant mode. If
the STPCLK# is not asserted at the completion of the BINIT# bus initialization, the processor will
return to Normal state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the
STPCLK# signal. When re-entering the Stop-Grant state from the sleep state, STPCLK# should
only be deasserted one or more bus clocks after the deassertion of SLP#.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
system bus (see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal state. Only one occurrence
of each event will be recognized upon return to the Normal state.
6.2.4
6.2.5
HALT/Grant Snoop State—State 4
The processor will respond to snoop transactions on the system bus while in Stop-Grant state or in
AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant
Snoop state. The processor will stay in this state until the snoop on the system bus has been
serviced (whether by the processor or another agent on the system bus). After the snoop is serviced,
the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.
Sleep State—State 5
The Sleep state is a very low power state in which each processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be
entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing
the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT
states.
Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and
STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the reset sequence.
Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous system bus event
occurs. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. For
Intel Xeon processor MP on the 0.13 micron process processors, the SLP# pin may only be
asserted when all logical processors are in the Stop-Grant state. SLP# assertions while the
processors are not in the Stop-Grant state is out of specification and may result in illegal operation.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
6-3
Features
6.2.6
Bus Response during Low Power States
While in AutoHALT Power Down and Stop-Grant states, the processor will process a system bus
snoop.
When the processor is in Sleep state, the processor will not process interrupts or snoop
transactions.
6.3
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the Thermal
Control Circuit (TCC) when the processor silicon reaches its maximum operating temperature. The
TCC reduces processor power consumption by modulating (starting and stopping) the internal
processor core clocks. The Thermal Monitor feature must be enabled for the processor to be
operating within specifications. The temperature at which Thermal Monitor activates the thermal
control circuit is not user configurable and is not software visible. Bus traffic is snooped in the
normal manner, and interrupt requests are latched (and serviced during the time that the clocks are
on) while the TCC is active.
When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e. TCC is
active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle
specific to the processor (typically 30-50%). Clocks often will not be off for more than 3.0
microseconds when the TCC is active. Cycle times are processor speed dependent and will
decrease as processor core frequencies increase. A small amount of hysteresis has been included to
prevent rapid active/inactive transitions of the TCC when the processor temperature is near its
maximum operating temperature. Once the temperature has dropped below the maximum
operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
With a properly designed and characterized thermal solution, it is anticipated that the TCC would
only be activated for very short periods of time when running the most power intensive
applications. The processor performance impact due to these brief periods of TCC activation is
expected to be so minor that it would be immeasurable. An under-designed thermal solution that is
not able to prevent excessive activation of the TCC in the anticipated ambient environment may
cause a noticeable performance loss, and in some cases may result in a TC that exceeds the
specified maximum temperature and may affect the long-term reliability of the processor. In
addition, a thermal solution that is significantly under-designed may not be capable of cooling the
processor even when the TCC is active continuously. Refer to the Intel Xeon Processor Thermal
Design Guidelines for information on designing a thermal solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and
cannot be modified. The Thermal Monitor does not require any additional hardware, software
drivers, or interrupt handling routines.
6.3.1
Thermal Diode
The Intel Xeon processor MP on the 0.13 micron process processor incorporates an on-die thermal
diode. This thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be
used to predict the behavior of the Thermal Monitor. See Section 6.4.4 for details.
6-4
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Features
6.4
System Management Bus (SMBus) Interface
The Intel Xeon processor MP on the 0.13 micron process processor in the INT-mPGA package
includes an SMBus interface which allows access to a memory component with two sections
(referred to as the Processor Information ROM and the Scratch EPROM) and a thermal sensor on
the substrate. The SMBus thermal sensor may be used to read the thermal diode mentioned in
Section 6.3.1. These devices and their features are described below. See Section 4 for the physical
location of these devices.
The SMBus thermal sensor and its associated thermal diode are not related to, and are completely
independent of, the precision on-die temperature sensor and thermal control circuit (TCC) of the
Thermal Monitor feature discussed in Section 6.3.
The processor SMBus implementation uses the clock and data signals of the V1.1 System
Management Bus Specification. It does not implement the SMBSUS# signal. Layout and routing
guidelines are available in the appropriate platform design guidelines document and the SMBus
and I2C Bus Design Guide application note.
For platforms which do not implement any of the SMBus features found on the processor, all of the
SMBus connections, except SM_VCC, to the socket pins may be left unconnected (SM_ALERT#,
SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], SM_WP). SM_VCC provides power to the
VID generation logic in addition to supplying the SMBus and must be supplied with 3.3 volt power
to assure correct setting of the processor core voltage (VCC).
Figure 42. Logical Schematic of SMBus Circuitry
SM_VCC
SM_TS_A0
SM_TS_A1
VCC
VCC
A0
SM_EP_A0
SM_EP_A1
SM_EP_A2
CLK
A0
A1
CLK
Processor
Information
ROM
and
Scratch
DATA
A1
A2
WP
DATA
Thermal
Sensor
STDBY#
ALERT#
SM_WP
EEPROM
(1 Kbit each)
VSS
VSS
SM_CLK
SM_DAT
SM_ALERT#
NOTE: Actual implementation may vary. For use in general understanding of the architecture. All SMBus pull-up
and pull-down resistors are 10KΩ and located on the processor.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
6-5
Features
6.4.1
Processor Information ROM (PIROM)
The lower half (128 bytes) of the SMBus memory component is an electrically programmed read-
only memory with information about the processor. This information is permanently write-
protected. Table 35 shows the data fields and formats provided in the Processor Information ROM
(PIROM).
Table 35. Processor Information ROM Format (Sheet 1 of 2)
# of
Bits
Offset/Section
Function
Notes
Header:
00h
01 - 02h
03h
8
16
8
Data Format Revision
EEPROM Size
Two 4-bit hex digits
Size in bytes (MSB first)
Processor Data Address
Byte pointer, 00h if not present
Processor Core Data
Address
04h
8
Byte pointer, 00h if not present
05h
06h
07h
8
8
8
L3 Cache Data Address
Package Data Address
Part Number Data Address
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Thermal Reference Data
Address
08h
8
Byte pointer, 00h if not present
09h
0Ah
8
8
Feature Data Address
Other Data Address
Reserved
Byte pointer, 00h if not present
Byte pointer, 00h if not present
Reserved
0Bh
16
8
0Dh
Checksum
1 byte checksum
Processor Data:
0E - 13h
48
S-spec/QDF Number
Six 8-bit ASCII characters
6
2
Reserved
Reserved (most significant bits)
14h
Sample/Production
00b=Sample only, 01-11b=Production
15h
Processor Core Data:
16 - 17h
8
Checksum
1 byte checksum
2
4
Processor Core Type
Processor Core Family
Processor Core Model
Processor Core Stepping
Reserved
From CPUID
From CPUID
4
From CPUID
4
From CPUID
2
Reserved
18 - 19h
1A - 1Bh
16
16
Reserved
Reserved
System Bus Speed
16-bit binary number (in MHz)
2
6
Multiprocessor Support
Reserved
00b=UP, 01b=DP, 10b=RSVD, 11b=MP
Reserved
1Ch
1D - 1Eh
1F - 20h
21 - 22h
23h
16
16
16
8
Maximum Core Frequency
Processor VID (Voltage ID)
Core Voltage, Minimum
16-bit binary number (in MHz)
Voltage requested by VID outputs in mV
Minimum processor DC Vcc spec in mV
Maximum case temperature spec in °C
T
Maximum
CASE
6-6
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Features
Table 35. Processor Information ROM Format (Sheet 2 of 2)
# of
Bits
Offset/Section
Function
Checksum
Notes
24h
8
1 byte checksum
Reserved
Cache Data:
25 - 26h
16
16
16
48
8
Reserved
27-28h
L2 Cache Size
L3 Cache Size
Reserved
16-bit binary number (in KB)
16-bit binary number (in KB)
Reserved
29 - 2Ah
2B - 30h
31h
Checksum
1 byte checksum
Package Data:
32 - 35h
32
8
Package Revision
Reserved
Four 8-bit ASCII characters
Reserved
36h
37h
8
Checksum
1 byte checksum
Part Number Data:
38 - 3Eh
56
Processor Part Number
Reserved
Seven 8-bit ASCII characters
Reserved
3F - 4Ch
112
Processor Electronic
Signature
4D - 54h
64
64-bit identification number
55 - 6Eh
208
8
Reserved
Reserved
6Fh
Thermal Ref. Data:
70h
Checksum
1 byte checksum
8
16
8
Thermal Reference Byte
Reserved
See Section 6.4.4 for details
Reserved
71 - 72h
73h
Checksum
1 byte checksum
Feature Data:
Processor Core Feature
Flags
74 - 77h
32
8
From CPUID function 1, EDX contents
[7] = Reserved
[6] = Serial Signature
[5] = Electronic Signature Present
[4] = Thermal Sense Device Present
[3] = Thermal Reference Byte Present
[2] = OEM EEPROM Present
[1] = Core VID Present
78h
Processor Feature Flags
[0] = L3 Cache Present
Additional Processor
Feature Flags
79-7Bh
24
Reserved
7Ch
7Dh
8
8
Reserved
Reserved
Checksum
1 byte checksum
Other Data:
7E - 7Fh
16
Reserved
Reserved
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
6-7
Features
6.4.2
Scratch EEPROM
Also available in the memory component on the Intel Xeon processor MP on the 0.13 micron
process processor in INT-mPGA package, is an EEPROM which may be used for other data at the
system or processor vendor’s discretion. The data in this EEPROM, once programmed, can be
write-protected by asserting the active-high SM_WP signal. This signal has a weak pull-down
(10 kΩ) to allow the EEPROM to be programmed in systems with no implementation of this
signal. The Scratch EEPROM resides in the upper half of the memory component (addresses 80 -
FFh). The lower half comprises the Processor Information ROM (address 00 - 7Fh), which is
permanently write protected by Intel.
6.4.3
PIROM and Scratch EEPROM Supported SMBus
Transactions
The Processor Information ROM (PIR) responds to two SMBus packet types: Read Byte and Write
Byte. However, since the PIR is write-protected, it will acknowledge a Write Byte command but
ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte commands. Table 36
diagrams the Read Byte command. Table 37 diagrams the Write Byte command. Following a write
cycle to the scratch ROM, software must allow a minimum of 10 ms before accessing either ROM
of the processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents a read bit,
‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’ represents a negative
acknowledge (NACK). The shaded bits are transmitted by the Processor Information ROM or
Scratch EEPROM, and the bits that aren’t shaded are transmitted by the SMBus host controller. In
the tables the data addresses indicate 8 bits.The SMBus host controller should transmit 8 bits with
the most significant bit indicating which section of the EEPROM is to be addressed: the Processor
Information ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
Table 36. Read Byte SMBus Packet
Slave
Address
Command
Code
Slave
Address
Rea
d
S
Write
A
A
S
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Table 37. Write Byte SMBus Packet
Slave
Address
S
Write
A
Command Code
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1
6.4.4
SMBus Thermal Sensor
The Intel Xeon processor MP on the 0.13 micron process processor in INT-mPGA package provide
a SMBus thermal sensor as a means of acquiring thermal data from the processor. The thermal
sensor is composed of control logic, SMBus interface logic, a precision analog-to-digital converter,
and a precision current source. The sensor drives a small current through the p-n junction of a
thermal diode located on the processor core. The forward bias voltage generated across the thermal
diode is sensed and the precision A/D converter derives a single byte of thermal reference data, or
a “thermal byte reading.” The nominal precision of the least significant bit of a thermal byte is 1°C.
6-8
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Features
The processor incorporates the SMBus thermal sensor and thermal reference byte onto the
processor package for the Intel Xeon processor MP on the 0.13 micron process processor and Intel
Xeon processor in the INT-mPGA package. Upper and lower thermal reference thresholds can be
individually programmed for the SMBus thermal sensor. Comparator circuits sample the register
where the single byte of thermal data (thermal byte reading) is stored. These circuits compare the
single byte result against programmable threshold bytes. If enabled, the alert signal on the
processor SMBus (SM_ALERT#) will be asserted when the sensor detects that either threshold is
reached or crossed. Analysis of SMBus thermal sensor data may be useful in detecting changes in
the system environment that may require attention.
During manufacturing, the thermal reference byte (TRB) is programmed into the Processor
Information ROM. The thermal reference byte represents the approximate temperature reading
from the thermal diode when the processor is operating at its maximum specified TCASE under
steady state temperature and application conditions. The TRB is derived for the processor through
device characterization and the value varies with processor core frequency, similar to the TCASE
specifications.
The processor SMBus thermal sensor and thermal reference byte may be used to monitor long term
temperature trends, but can not be used to manage the short term temperature of the processor or
predict the activation of the thermal control circuit. As mentioned earlier, the processors high
thermal ramp rates make this infeasible. Refer to the Intel® XeonTM Processor (MP) Thermal
Design Guidelines for more details.
The SMBus thermal sensor feature in the processor cannot be used to measure TCASE. The TCASE
specification in Section 5 must be met regardless of the reading of the processor's thermal sensor in
order to ensure adequate cooling for the entire Intel Xeon processor MP on the 0.13 micron process
processor. The SMBus thermal sensor feature is only available while VCC and SM_VCC are at
valid levels and the processor is not in a low-power state.
6.4.5
Thermal Sensor Supported SMBus Transactions
The thermal sensor responds to five of the SMBus packet types: Write Byte, Read Byte, Send Byte,
Receive Byte, and Alert Response Address (ARA). The Send Byte packet is used for sending one-
shot commands only. The Receive Byte packet accesses the register commanded by the last Read
Byte packet and can be used to continuously read from a register. If a Receive Byte packet was
preceded by a Write Byte or send Byte packet more recently than a Read Byte packet, then the
behavior is undefined. Table 38 through Table 42 diagram the five packet types. In these figures,
‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘Ack’ represents an acknowledge, and
‘///’ represents a negative acknowledge (NACK). The shaded bits are transmitted by the thermal
sensor, and the bits that aren’t shaded are transmitted by the SMBus host controller. Table 43 shows
the encoding of the command byte.
Table 38. Write Byte SMBus Packet
Slave
Address
Command
Code
S
Write
Ack
Ack
Data
Ack
P
1
7-bits
1
1
8-bits
1
8-bits
1
1
Table 39. Read Byte SMBus Packet
Slave
Address
Command
Code
Slave
Address
S
Write Ack
Ack
S
Read Ack
Data
8-bits
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
1
1
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
6-9
Features
Table 40. Send Byte SMBus Packet
Command
Code
S
Slave Address
Read
Ack
Ack
P
1
7-bits
1
1
8-bits
1
1
Table 41. Receive Byte SMBus Packet
S
Slave Address
Read
Ack
Data
///
P
1
7-bits
1
1
8-bits
1
1
Table 42. ARA SMBus Packet
S
ARA
Read
Ack
Address
///
P
1
0001 100
1
1
Device Address1
1
1
NOTE: This is an 8-bit field. The device which sent the alert will respond to the ARA Packet with its address in
the seven most significant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See
Section 6.4.8 for details on the Thermal Sensor Device addressing.
Table 43. SMBus Thermal Sensor Command Byte Bit Assignments
Register
Command
Reset State
Function
Reserved for future use
RESERVED
TRR
00h
01h
RESERVED
0000 0000
N/A
Read processor core thermal diode
Read status byte (flags, busy signal)
Read configuration byte
RS
02h
RC
03h
00XX XXXX
0000 0010
RESERVED
RESERVED
0111 1111
1100 1001
N/A
RCR
04h
Read conversion rate byte
RESERVED
RESERVED
RRHL
05h
Reserved for future use
06h
Reserved for future use
07h
Read processor core thermal diode T
Read processor core thermal diode T
Write configuration byte
limit
limit
HIGH
LOW
RRLL
08h
WC
09h
WCR
0Ah
N/A
Write conversion rate byte
RESERVED
RESERVED
WRHL
0Bh
RESERVED
RESERVED
N/A
Reserved for future use
0Ch
0Dh
0Eh
Reserved for future use
Write processor core thermal diode T
Write processor core thermal diode T
limit
limit
HIGH
LOW
WRLL
N/A
OSHT
0Fh
N/A
One shot command (use send byte packet)
Reserved for future use
RESERVED
10h – FFh
N/A
All of the commands in Table 48 are for reading or writing registers in the SMBus thermal sensor,
except the one-shot command (OSHT) register. The one-shot command forces the immediate start
of a new conversion cycle. If a conversion is in progress when the one-shot command is received,
then the command is ignored. If the thermal sensor is in stand-by mode when the one-shot
command is received, a conversion is performed and the sensor returns to stand-by mode. The one-
shot command is not supported when the thermal sensor is in auto-convert mode.
6-10
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Features
Note: Writing to a read-command register or reading from a write-command register will produce invalid
results.
The default command after reset is to a reserved value (00h). After reset, “Receive Byte” SMBus
packets will return invalid data until another command is sent to the thermal sensor.
6.4.6
SMBus Thermal Sensor Registers
6.4.6.1
Thermal Reference Registers
Once the SMBus thermal sensor reads the processor thermal diode, it performs an analog to digital
conversion and stores the result in the Thermal Reference Register (TRR). The supported range is
+127 to 0 decimal and is expressed as an eight-bit number representing temperature in degrees
Celsius. This eight-bit value consists of seven data bits and a sign bit (MSB) as shown in Table 44.
The values shown are also used to program the Thermal Limit Registers.
The values of these registers should be treated as saturating values. Values above 127 are
represented as 127 decimal, while values of zero and below may be represented as 0 to -127
decimal. If the thermal sensor returns a value with the sign bit set (1) and the data is 000_0000
through 111_1110, the temperature should be interpreted as 0 ºC.
Table 44. Thermal Reference Register Values
Temperature
(°C)
Register Value
(binary)
+127
+126
+100
+50
+25
+1
0 111 1111
0 111 1110
0 110 0100
0 011 0010
0 001 1001
0 000 0001
0 000 0000
0
6.4.6.2
6.4.6.3
Thermal Limit Registers
The SMBus thermal sensor has four Thermal Limit Registers: RRHL is used to read the high limit;
RRLL is read for the low limit; WRHL is used to write the high limit; and the WRLL to write the
low limit. These registers allow the user to define high and low limits for the processor core
thermal diode reading. The encoding for these registers is the same as for the Thermal Reference
Register shown in Table 44. If the processor thermal diode reading equals or exceeds one of these
limits, then the alarm bit (RHIGH or RLOW) in the Thermal Sensor Status Register is triggered.
Status Register
The Status Register shown in Table 45 indicates which (if any) thermal value thresholds for the
processor core thermal diode have been exceeded. It also indicates if a conversion is in progress or
if an open circuit has been detected in the processor core thermal diode connection. Once set, alarm
bits stay set until they are cleared by a Status Register read. A successful read to the Status Register
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
6-11
Features
will clear any alarm bits that may have been set, unless the alarm condition persists. If the
SM_ALERT# signal is enabled via the Thermal Sensor Configuration Register and a thermal diode
threshold is exceeded, an alert will be sent to the platform via the SM_ALERT# signal.
This register is read by accessing the RS Command Register.
Table 45. SMBus Thermal Sensor Status Register
Bit
Name
Reset State
Function
If set, indicates that the device’s analog to digital converter is
busy.
7 (MSB)
BUSY
N/A
6
5
RESERVED
RESERVED
RESERVED
RESERVED
Reserved for future use
Reserved for future use
If set, indicates the processor core thermal diode high
temperature alarm has activated.
4
3
2
RHIGH
RLOW
OPEN
0
0
0
If set, indicates the processor core thermal diode low
temperature alarm has activated.
If set, indicates an open fault in the connection to the
processor core diode.
1
RESERVED
RESERVED
RESERVED
RESERVED
Reserved for future use.
Reserved for future use.
0 (LSB)
6.4.6.4
Configuration Register
The Configuration Register controls the operating mode (stand-by vs. auto-convert) of the SMBus
thermal sensor. Table 46 shows the format of the Configuration Register. If the RUN/STOP bit is
set (high) then the thermal sensor immediately stops converting and enters stand-by mode. The
thermal sensor will still perform analog to digital conversions in stand-by mode when it receives a
one-shot command. If the RUN/STOP bit is clear (low) then the thermal sensor enters auto-
conversion mode.
This register is accessed by using the thermal sensor Command Register: The RC command
register is used for read commands and the WC command register is used for write commands. See
Table 43.
Table 46. SMBus Thermal Sensor Configuration Register
Bit
Name
Reset State
Function
Mask SM_ALERT# bit. Clear bit to allow interrupts via
SM_ALERT# and allow the thermal sensor to respond to the
ARA command when an alarm is active. Set the bit to disable
interrupt mode. The bit is not used to clear the state of the
SM_ALERT# output. An ARA command may not be
recognized if the mask is enabled.
7 (MSB)
MASK
0
Stand-by mode control bit. If set, the device immediately stops
converting, and enters stand-by mode. If cleared, the device
converts in either one-shot mode or automatically updates on
a timed basis.
6
RUN/STOP
RESERVED
0
5:0
RESERVED Reserved for future use.
6-12
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Features
6.4.6.5
Conversion Rate Registers
The contents of the Conversion Rate Registers determine the nominal rate at which analog to
digital conversions happen when the SMBus thermal sensor is in auto-convert mode. There are two
Conversion Rate Registers, RCR for reading the conversion rate value and WCR for writing the
value. Table 47 shows the mapping between Conversion Rate Register values and the conversion
rate. As indicated in Table 43, the Conversion Rate Register is set to its default state of 02h
(0.25 Hz nominally) when the thermal sensor is powered up. There is a ±30% error tolerance
between the conversion rate indicated in the conversion rate register and the actual conversion rate.
Table 47. SMBus Thermal Sensor Conversion Rate Registers
Register Value
Conversion Rate (Hz)
00h
01h
0.0625
0.125
02h
0.25
03h
0.5
04h
1.0
05h
2.0
06h
4.0
8.0
07h
08h to FFh
Reserved for future use
6.4.7
SMBus Thermal Sensor Alert Interrupt
The SMBus thermal sensor located on the processor includes the ability to interrupt the SMBus
when a fault condition exists. The fault conditions consist of: 1) a processor thermal diode value
measurement that exceeds a user-defined high or low threshold programmed into the Command
Register or 2) disconnection of the processor thermal diode from the thermal sensor. The interrupt
can be enabled and disabled via the thermal sensor Configuration Register and is delivered to the
baseboard via the SM_ALERT# open drain output. Once latched, the SM_ALERT# should only be
cleared by reading the Alert Response byte from the Alert Response Address of the thermal sensor.
The Alert Response Address is a special slave address shown in Table 42. The SM_ALERT# will
be cleared once the SMBus master device first reads the status register then reads the slave ARA
unless the fault condition persists. Reading the Status Register alone or setting the mask bit within
the Configuration Register does not clear the interrupt.
6.4.8
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of the form
“1010XXXZb”. The “XXX” bits are defined by pullups and pulldowns on the system baseboard.
These address pins are pulled down weakly (10 kΩ) on the processor substrate to ensure that the
memory components are in a known state in systems which do not support the SMBus, or only
support a partial implementation. The “Z” bit is the read/write bit for the serial bus transaction.
The thermal sensor internally decodes one of three upper address patterns from the bus of the form
“0011XXXZb”, “1001XXXZb”, or “0101XXXZb”. The device’s addressing, as implemented, uses
the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state. Therefore, the thermal sensor supports
nine unique addresses. To set either pin for the Hi-Z state, the pin must be left floating. As before,
the “Z” bit is the read/write bit for the serial transaction.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
6-13
Features
Note that addresses of the form “0000XXXXb” are Reserved and should not be generated by an
SMBus master. The thermal sensor samples and latches the SM_TS_A[1:0] signals at power-up
and at the starting point of every conversion. System designers should ensure that these signals are
at valid VIH, VIL, or floating input levels prior to or while the thermal sensor’s SM_VCC supply
powers up. This should be done by pulling the pins to SM_VCC or VSS via a 1 kΩ or smaller
resistor, or leaving the pins floating to achieve the Hi-Z state. If the designer desires to drive the
SM_TS_A[1:0] pins with logic, the designer must still ensure that the pins are at valid input levels
prior to or while the SM_VCC supply ramps up. The system designer must also ensure that their
particular implementation does not add excessive capacitance to the address inputs. Excess
capacitance at the address inputs may cause address recognition problems. Refer to the appropriate
platform design guidelines document and the SMBus and I2C Bus Design Guide application note.
Figure 42 on page 5 shows a logical diagram of the pin connections. Table 48 and Table 49
describe the address pin connections and how they affect the addressing of the devices.
6-14
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Features
Table 48. Thermal Sensor SMBus Addressing on the Intel® Xeon™ Processor MP on the 0.13
Micron Process Processor
Device Select
8-bit Address Word on Serial Bus
b[7:0]
Address (Hex)
Upper Address1
SM_TS_A1
SM_TS_A0
0
0
0
0
0011000Xb
0011001Xb
0011010Xb
0101001Xb
0101010Xb
0101011Xb
1001100Xb
1001101Xb
1001110Xb
2
3Xh
0011
Z
1
0
2
Z
2
2
5Xh
9Xh
0101
1001
Z
Z
2
1
0
Z
1
1
1
2
Z
1
NOTES:
1. Upper address bits are decoded in conjunction with the select pins.
2. A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
Note: System management software must be aware of the processor dependent addresses for the thermal
sensor.
Table 49. Memory Device SMBus Addressing on the Intel® Xeon™ Processor MP on the 0.13
Micron Process Processor
Upper
Device Select
R/W
bit 0
1
Address
bits 7-4
Address
(Hex)
SM_EP_A2
bit 3
SM_EP_A1
bit 2
SM_EP_A0
bit 1
A0h/A1h
A2h/A3h
A4h/A5h
A6h/A7h
A8h/A9h
AAh/ABh
ACh/ADh
AEh/AFh
1010
1010
1010
1010
1010
1010
1010
1010
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
NOTES:
1. . This addressing scheme will support up to 8 processors on a single SMBus.
§
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
6-15
Features
6-16
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Boxed Processor Specifications
Boxed Processor Specifications
7
7.1
Introduction
The Intel Xeon processor MP on the 0.13 micron process processor is also offered as an Intel boxed
processor. Intel boxed processors are intended for system integrators who build systems from
components available through distribution channels. The current plan for the Intel Xeon processor
MP on the 0.13 micron process boxed processor is to include an unattached passive heatsink. Intel
boxed processors do not include voltage regulation modules (VRMs). Integrators should contact
their baseboard supplier to receive a list of supported module vendors and models.
This chapter documents baseboard and platform requirements for the cooling solution that is
supplied with the boxed processor. This chapter is particularly important for OEM's that
manufacture baseboards and chassis for integrators. Figure 43 shows the a mechanical
representation of the boxed processor heatsink for the Intel Xeon processor MP on the 0.13 micron
process processor.
Note: Drawings in this section reflect only the specifications on the Intel boxed processor product. These
dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system
designer's responsibility to consider their proprietary cooling solution when designing to the
required keep-out zone on their system platform and chassis.
Figure 43. Mechanical Representation of the Boxed Intel® Xeon™ Processor MP on the 0.13
Micron Process Processor Passive Heatsink
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
7-1
Boxed Processor Specifications
7.2
Mechanical Specifications
This section documents the mechanical specifications of the boxed processor passive heatsink.
Proper clearance is required around the heatsink to ensure proper installation of the processor and
unimpeded airflow for proper cooling.
7.2.1
Boxed Processor Heatsink Dimensions
The boxed processor is shipped with an unattached passive heatsink. Clearance is required around
the heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and
dimensions for the boxed Intel Xeon processor with 512KB L2 cache and assembled heatsink are
shown in Figure 44 and Figure 45. The airflow requirements for the boxed processor heatsink must
also be taken into consideration when designing new baseboards and chassis. The airflow
requirements are detailed in the Thermal Specifications, Section 7.4.
Please refer to the Intel® Xeon™ Processor Multiprocessor (MP) Thermal Design Guidelines for
details on the processor clearance requirements.
7.2.2
7.2.3
Boxed Processor Heatsink Weight
The boxed processor heatsink weighs no more than 450 grams. See Section 4 and Section 5 of this
document along with the Intel® Xeon™ Processor Multiprocessor (MP) Thermal Design
Guidelines for details on the processor weight and heatsink requirements.
Boxed Processor Retention Mechanism and Heatsink
Supports
The boxed processor requires a processor retention solution to secure the processor, the baseboard,
and the chassis. The retention solution contains two retention mechanisms and two retention clips
per processor. For the boxed processor, the current plan is to ship with retention mechanisms,
cooling solution retention clips, and direct chassis attach screws. Baseboards and chassis designed
for use by system integrators should include holes that are in proper alignment with each other to
support the boxed processor. Refer to the Server System Infrastructure Specification (SSI-EEB) at
http://www.ssiforum.org for details on the hole locations. Please see the <Boxed integration notes>
at http://support.intel.com/support/processors/xeon/ for retention mechanism installation
instructions. Retention mechanism clips must interface with the boxed processor heatsink area
shown in Detail A in Figure 46.
The retention mechanism that ships with the boxed Intel Xeon processor is different than the
reference solution from Intel. It adds tabs that allow the PWT (processor wind tunnel) to be
attached directly to it. Please reference Figure 45 below, which contains the dimensions for the tabs
that are different. For dimensions of the reference solution, please see the appropriate platform
design guidelines.
7-2
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Boxed Processor Specifications
Figure 44. Boxed Processor Clip
Figure 45. Boxed Processor Retention Mechanism
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
7-3
Boxed Processor Specifications
Figure 46. Multiple View Space Requirements for Boxed Processors
7-4
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Boxed Processor Specifications
7.3
Boxed Processor Requirements
®
7.3.1
Intel Xeon™ Processor MP on the 0.13 Micron Process
Processor
Systems do not need to account for the processor wind tunnel or heat sink fan header in order to
support the Intel boxed processor based on the Intel Xeon processor MP on the 0.13 micron process
processor. If the system has no intention of supporting the boxed Intel Xeon processor with
512-KB L2 cache, these features may be removed. It has not yet been determined if the retention
mechanism for the Intel Xeon processor MP on the 0.13 micron process processor will ship with
the boxed processor or with the baseboards. If the retention mechanism is not included with the
boxed processor, the system integrator or baseboard supplier will have to account for these pieces.
No other special platform or system design considerations are required for integrated boxed Intel
Xeon processor MP on the 0.13 micron process processor.
7.4
Thermal Specifications
This section describes the cooling requirements of the heatsink solution utilized by the boxed
processor.
7.4.1
Boxed Processor Cooling Requirements
The boxed processor will be directly cooled with a passive heatsink. For the passive heatsink to
effectively cool the boxed processor, it is critical that sufficient, unimpeded, cool air flow over the
heatsink of every processor in the system. Meeting the processor's temperature specification is a
function of the thermal design of the entire system, and ultimately the responsibility of the system
integrator. The processor temperature specification is found in Section 5. It is important that system
integrators perform thermal tests to verify that the boxed processor is kept below its maximum
temperature specification in a specific baseboard and chassis.
At an absolute minimum, the boxed processor heatsink will require 500 Linear Feet per Minute
(LFM) of cool air flowing over the heatsink. The airflow must be directed from the outside of the
chassis directly over the processor heatsinks in a direction passing from one retention mechanism
to the other. It also should flow from the front to the back of the chassis. Directing air over the
passive heatsink of the boxed Intel Xeon processor MP on the 0.13 micron process processor can
be done with auxiliary chassis fans, fan ducts, or other techniques.
It is also recommended that the ambient air temperature outside of the chassis be kept at or below
35 °C. The air passing directly over the processor heatsink should not be preheated by other system
components (such as another processor), and should be kept at or below 45 °C. Again, meeting the
processor's temperature specification is the responsibility of the system integrator. The processor
temperature specification is found in Section 5.
§
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
7-5
Boxed Processor Specifications
7-6
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Debug Tools Specifications
Debug Tools Specifications
8
The Debug Port design information has been moved. This includes all information necessary to
develop a Debug Port on this platform, including electrical specifications, mechanical
requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700
Debug Port Design Guide for the design of your platform.
Note: This change is effective for all future processors.
8.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use
in debugging systems. Tektronix and Agilent should be contacted to get specific information about
their logic analyzer interfaces. The following information is general in nature. Specific information
must be obtained from the logic analyzer vendor.
Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture
system bus signals. There are two sets of considerations to keep in mind when designing a system
that can make use of an LAI: mechanical and electrical.
8.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI pins plug into the
socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI
egresses the system to allow an electrical connection between the processor and a logic analyzer.
The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable
egress restrictions, should be obtained from the logic analyzer vendor. System designers must
make sure that the keepout volume remains unobstructed inside the system. Note that it is possible
that the keepout volume reserved for the LAI may differ from the space normally occupied by the
processor heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as
part of the LAI.
8.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the system bus; therefore, it is critical to
obtain electrical load models from each of the logic analyzers to be able to run system level
simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for
electrical specifications and load models for the LAI solution they provide.
§
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
8-1
Debug Tools Specifications
8-2
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Pin Listing and Signal Definitions
Pin Listing and Signal Definitions
9
9.1
Intel® Xeon™ Processor MP on the 0.13 Micron
Process Processor Pin Assignments
Section 2.8 contains the system bus signal groups in Table 5 for the Intel Xeon processor MP on the
0.13 micron process processor. This section provides a sorted pin list in Table 50 and Table 51 for
INT-mPGA package. Table 50 is a listing of all processor pins ordered alphabetically by pin name.
Table 51 is a listing of all processor pins ordered by pin number.
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Signal
Pin Name
Pin No.
Direction
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
A27#
A28#
B8
E13
D12
C11
B7
Source Sync Input/Output
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Async GTL+
Common Clk
Source Sync
Source Sync
Common Clk
Common Clk
Sys Bus Clk
Sys Bus Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
A3#
A4#
A22
A20
B18
C18
A19
C17
D17
A13
B16
B14
B13
A12
C15
C14
D16
D15
F15
A10
B10
B11
C12
E14
D13
A9
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
A29#
A30#
A5#
A31#
A6#
A32#
A6
A7#
A33#
A7
A8#
A34#
C9
A9#
A35#
C8
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A20M#
ADS#
F27
D19
F17
F14
E10
D9
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
ADSTB0#
ADSTB1#
AP0#
AP1#
BCLK0
BCLK1
BINIT#
BNR#
Y4
W5
F11
F20
F6
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
F8
E7
F5
E8
E4
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-1
Pin Listing and Signal Definitions
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
BPRI#
BR0#
BR1#
D23
D20
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DBSY#
DEFER#
DBI0#
DBI1#
DBI2#
AD19
AB17
AB16
AA16
AC17
AE13
AD18
AB15
AD13
AD14
AD11
AC12
AE10
AC11
AE9
Source Sync Input/Output
Source Sync Input/Output
Source Sync Input/Output
Source Sync Input/Output
Input/Output
Input
F12
1
BR2#
E11
Input
1
BR3#
D10
Input
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
2
BSEL0
AA3
Output
2
BSEL1
AB3
Output
COMP0
COMP1
D0#
AD16
E16
Input
Input
Y26
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
D1#
AA27
Y24
D2#
D3#
AA25
AD27
Y23
D4#
D5#
D6#
AA24
AB26
AB25
AB23
AA22
AA21
AB20
AB22
AB19
AA19
AE26
AC26
AD25
AE25
AC24
AD24
AE23
AC23
AA18
AC20
AC21
AE22
AE20
AD21
AD10
AD8
D7#
D8#
AC9
D9#
AA13
AA14
AC14
AB12
AB13
AA11
AA10
AB10
AC8
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
AD7
AE7
Source Sync Input/Output
Source Sync Input/Output
AC6
Source Sync Input/Output
Source Sync Input/Output
AC5
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
AA8
Input/Output
Input/Output
Input/Output
Input/Output
Input
Y9
AB6
F18
C23
AC27
AD22
AE12
Input/Output
Input/Output
Input/Output
9-2
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Pin Listing and Signal Definitions
Table 50. Pin Listing by Pin Na1m4e for the
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
DBI3#
DP0#
AB9
AC18
AE19
AC15
AE17
E18
Y21
Y18
Y15
Y12
Y20
Y17
Y14
Y11
E27
W23
W9
Source Sync Input/Output
Common Clk Input/Output
Common Clk Input/Output
Common Clk Input/Output
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RESET#
RS0#
A15
A16
A26
B1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Common Clk
Common Clk
Common Clk
Common Clk
Common Clk
Power/Other
Async GTL+
SMBus
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Input
DP1#
DP2#
DP3#
Common Clk
Common Clk
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Async GTL+
Async GTL+
Async GTL+
Async GTL+
Async GTL+
Common Clk
Common Clk
Power/Other
Async GTL+
Power/Other
Source Sync
Source Sync
Source Sync
Source Sync
Source Sync
Reserved
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Output
C5
DRDY#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
FERR#
D25
W3
Y3
Y27
Y28
AC1
AD1
AE4
AE15
AE16
Y8
GTLREF
GTLREF
GTLREF
GTLREF
HIT#
Input
Input
E21
D22
F21
Input
F23
F9
Input
RS1#
Input
Input
RS2#
Input
E22
A23
E5
Input/Output
Input/Output
Output
RSP#
C6
Input
HITM#
SKTOCC#
SLP#
A3
Output
IERR#
AE6
AD28
AC28
AC29
AA29
AB29
AB28
AA28
Y29
AE28
AE29
AD29
C27
D4
Input
IGNNE#
INIT#
C26
D6
Input
SM_ALERT#
SM_CLK
SM_DAT
SM_EP_A0
SM_EP_A1
SM_EP_A2
SM_TS1_A0
SM_TS1_A1
SM_VCC
SM_VCC
SM_WP
SMI#
Output
Input
SMBus
Input
LINT0
B24
G23
A17
D7
Input
SMBus
Input/Output
Input
LINT1
Input
SMBus
LOCK#
Input/Output
Input/Output
Input
SMBus
Input
MCERR#
ODTEN
PROCHOT#
PWRGOOD
REQ0#
SMBus
Input
B5
SMBus
Input
B25
AB7
B19
B21
C21
C20
B22
A1
Output
SMBus
Input
Power/Other
Power/Other
SMBus
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Reserved
Reserved
REQ1#
Input
Input
Input
Input
Input
Output
Async GTL+
Async GTL+
TAP
REQ2#
REQ3#
STPCLK#
TCK
REQ4#
E24
C24
E25
TAP
Reserved
Reserved
TDI
Reserved
TAP
A4
TDO
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-3
Pin Listing and Signal Definitions
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
THERMTRIP#
TMS
W6
W7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Async GTL+
TAP
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E2
E6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
W8
E12
E20
E26
E28
E30
F1
Y6
AA7
AD5
AE5
F26
A25
E19
F24
A2
F4
TRDY#
TRST#
VCC
Common Clk
TAP
F10
F16
F22
F29
F31
G2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
A8
VCC
A14
A18
A24
A28
A30
B4
VCC
VCC
G4
VCC
G6
VCC
G8
VCC
G24
G26
G28
G30
H1
VCC
B6
VCC
B12
B20
B26
B29
B31
C2
VCC
VCC
VCC
H3
VCC
H5
VCC
H7
VCC
C4
H9
VCC
C10
C16
C22
C28
C30
D1
H23
H25
H27
H29
H31
J2
VCC
VCC
VCC
VCC
VCC
VCC
D8
J4
VCC
D14
D18
D24
D29
D31
J6
VCC
J8
VCC
J24
J26
J28
VCC
VCC
9-4
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Pin Listing and Signal Definitions
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J30
K1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
N31
P2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
K3
P4
K5
P6
K7
P8
K9
P24
P26
P28
P30
R1
K23
K25
K27
K29
K31
L2
R3
R5
L4
R7
L6
R9
L8
R23
R25
R27
R29
R31
T2
L24
L26
L28
L30
M1
M3
M5
M7
M9
M23
M25
M27
M29
M31
N1
T4
T6
T8
T24
T26
T28
T30
U1
U3
U5
N3
U7
N5
U9
N7
U23
U25
U27
U29
U31
V2
N9
N23
N25
N27
N29
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-5
Pin Listing and Signal Definitions
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V4
V6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VCCIOPLL
VCCSENSE
VID0
VID1
VID2
VID3
VID4
VSS
AD20
AD26
AD30
AE3
AE8
AE14
AE18
AE24
AB4
AD4
B27
F3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
V8
V24
V26
V28
V30
W1
W25
W27
W29
W31
Y10
Input
Input
Output
Output
Output
Output
Output
Output
E3
Y16
D3
Y2
C3
Y22
B3
Y30
A5
AA1
AA4
AA6
AA12
AA20
AA26
AA31
AB2
AB8
AB14
AB18
AB24
AB30
AC3
AC4
AC10
AC16
AC22
AC31
AD2
AD6
AD12
VSS
A11
A21
A27
A29
A31
B2
VSS
VSS
VSS
VSS
VSS
VSS
B9
VSS
B15
B17
B23
B28
B30
C1
VSS
VSS
VSS
VSS
VSS
VSS
C7
VSS
C13
C19
C25
C29
C31
D2
VSS
VSS
VSS
VSS
VSS
VSS
D5
VSS
D11
9-6
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Pin Listing and Signal Definitions
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D21
D27
D28
D30
E1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J7
J9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J23
J25
J27
J29
J31
K2
E9
E15
E17
E23
E29
E31
F2
K4
K6
K8
K24
K26
K28
K30
L1
F7
F13
F19
F25
F28
F30
G1
L3
L5
L7
G3
L9
G5
L23
L25
L27
L29
L31
M2
M4
M6
M8
M24
M26
M28
M30
N2
G7
G9
G25
G27
G29
G31
H2
H4
H6
H8
H24
H26
H28
H30
J1
N4
N6
J3
N8
J5
N24
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-7
Pin Listing and Signal Definitions
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N26
N28
N30
P1
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V1
V3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
V5
V7
P3
V9
P5
V23
V25
V27
V29
V31
W2
P7
P9
P23
P25
P27
P29
P31
R2
W4
W24
W26
W28
W30
Y1
R4
R6
R8
R24
R26
R28
R30
T1
Y5
Y7
Y13
Y19
Y25
Y31
AA2
AA9
AA15
AA17
AA23
AA30
AB1
AB5
AB11
AB21
AB27
AB31
AC2
AC7
AC13
AC19
T3
T5
T7
T9
T23
T25
T27
T29
T31
U2
U4
U6
U8
U24
U26
U28
U30
9-8
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Pin Listing and Signal Definitions
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Table 50. Pin Listing by Pin Name for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin Name
Pin No.
Direction
Pin Name
Pin No.
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AC25
AC30
AD3
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
AE11
AE21
AE27
AA5
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
AD9
VSSA
Input
AD15
AD17
AD23
AD31
AE2
VSSSENSE
D26
Output
NOTES:
1. In systems utilizing the Intel Xeon processor, the system
designer must pull-up these signals to the processor VCC.
2. Baseboard treating AA3 and AB3 as Reserved will operate
correctly with a bus clock of 100 MHz.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-9
Pin Listing and Signal Definitions
9.1.1
Pin Listing by Pin Number
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Signal
Buffer Type
Pin No.
Pin Name
Direction
Signal
Pin Name
Pin No.
Direction
B1
B2
Reserved
VSS
Reserved
Reserved
Buffer Type
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
A1
A2
Reserved
VCC
Reserved
Power/Other
Power/Other
Reserved
Reserved
B3
VID4
Output
Input
B4
VCC
A3
SKTOCC#
Reserved
VSS
Output
B5
OTDEN
VCC
A4
Reserved
B6
A5
Power/Other
B7
A31#
A27#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A6
A32#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
B8
A7
A33#
B9
A8
VCC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
C1
A21#
A22#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A9
A26#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A20#
VSS
A13#
A12#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A14#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A10#
VCC
A11#
VSS
Source Sync Input/Output
Power/Other
Reserved
Reserved
LOCK#
VCC
Reserved
Reserved
Reserved
Reserved
A5#
Source Sync Input/Output
Common Clk
Power/Other
Input/Output
REQ0#
VCC
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Async GTL+
Input/Output
A7#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
REQ1#
REQ4#
VSS
Input/Output
Input/Output
A4#
VSS
A3#
Source Sync Input/Output
LINT0
Input
Common Clk
Power/Other
TAP
HITM#
VCC
Input/Output
PROCHOT# Power/Other
VCC Power/Other
VCCSENSE Power/Other
Output
TMS
Input
Output
Reserved
VSS
Reserved
Reserved
VSS
VCC
VSS
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VSS
VCC
VSS
9-10
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Pin Listing and Signal Definitions
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
1
C2
C3
VCC
VID3
Power/Other
Power/Other
Power/Other
Reserved
D10
D11
D12
D13
D14
D15
D16
D17
D18
BR3#
Common Clk
Input
Output
VSS
A29#
A25#
VCC
A18#
A17#
A9#
Power/Other
C4
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
C5
Reserved
RSP#
VSS
Reserved
Input
C6
Common Clk
Power/Other
C7
Source Sync Input/Output
Source Sync Input/Output
Source Sync Input/Output
Power/Other
C8
A35#
A34#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
D1
VCC
A30#
A23#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Common
Input/Output
Clk
D19
D20
ADS#
BR0#
Common
Input/Output
Clk
A16#
A15#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
E1
VSS
RS1#
Power/Other
Common Clk
Common Clk
Power/Other
Reserved
Input
Input
BPRI#
VCC
A8#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
A6#
Reserved
Reserved
Output
VSS
VSSSENSE Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
TAP
REQ3#
REQ2#
VCC
Input/Output
Input/Output
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
VCC
DEFER#
TDI
Input
Input
Input
Input
Input
VSS
VCC
VSS
Power/Other
Async GTL+
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Async GTL+
Power/Other
Async GTL+
Common Clk
Power/Other
Common Clk
VSS
IGNNE#
SMI#
VCC
E2
VCC
E3
VID1
BPM5#
IERR#
VCC
Output
Input/Output
Output
E4
VSS
E5
VCC
E6
VSS
E7
BPM2#
BPM4#
VSS
Input/Output
Input/Output
VCC
E8
D2
VSS
E9
D3
VID2
Output
Input
E10
E11
E12
E13
E14
E15
AP0#
Input/Output
Input
D4
STPCLK#
VSS
1
BR2#
D5
VCC
A28#
A24#
VSS
D6
INIT#
MCERR#
VCC
Input
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D7
Input/Output
D8
D9
AP1#
Input/Output
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-11
Pin Listing and Signal Definitions
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
F1
COMP1
VSS
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
TAP
Input
F24
F25
TRST#
VSS
TAP
Input
Power/Other
DRDY#
TRDY#
VCC
Input/Output
Input
THERMTRIP
#
F26
Async GTL+
Output
Input
F27
F28
F29
F30
F31
G1
A20M#
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
LINT1
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
RS0#
HIT#
Input
Input/Output
VSS
TCK
Input
TDO
TAP
Output
G2
VCC
Power/Other
Async GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
Common Clk
Power/Other
Power/Other
Common Clk
Common Clk
Power/Other
G3
FERR#
VCC
Output
G4
G5
VSS
G6
VCC
G7
VSS
G8
VCC
G9
F2
VSS
G23
G24
G25
G26
G27
G28
G29
G30
G31
H1
Input
F3
VID0
Output
F4
VCC
F5
BPM3#
BPM0#
VSS
Input/Output
Input/Output
F6
F7
F8
BPM1#
GTLREF
VCC
Input/Output
Input
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
BINIT#
BR1#
VSS
Input/Output
Input
H2
H3
ADSTB1#
A19#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
H4
H5
VCC
H6
ADSTB0#
DBSY#
VSS
Source Sync Input/Output
H7
Common Clk
Power/Other
Common Clk
Common Clk
Power/Other
Power/Other
Input/Output
H8
H9
BNR#
RS2#
VCC
Input/Output
Input
H23
H24
H25
GTLREF
Input
9-12
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Pin Listing and Signal Definitions
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
H26
H27
H28
H29
H30
H31
J1
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
K29
K30
K31
L1
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
L2
L3
L4
J2
L5
J3
L6
J4
L7
J5
L8
J6
L9
J7
L23
L24
L25
L26
L27
L28
L29
L30
L31
M1
J8
J9
J23
J24
J25
J26
J27
J28
J29
J30
J31
K1
M2
M3
M4
K2
M5
K3
M6
K4
M7
K5
M8
K6
M9
K7
M23
M24
M25
M26
M27
M28
M29
M30
M31
K8
K9
K23
K24
K25
K26
K27
K28
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-13
Pin Listing and Signal Definitions
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
N1
N2
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
R4
R5
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
N3
R6
N4
R7
N5
R8
N6
R9
N7
R23
R24
R25
R26
R27
R28
R29
R30
R31
T1
N8
N9
N23
N24
N25
N26
N27
N28
N29
N30
N31
P1
T2
T3
T4
P2
T5
P3
T6
P4
T7
P5
T8
P6
T9
P7
T23
T24
T25
T26
T27
T28
T29
T30
T31
U1
P8
P9
P23
P24
P25
P26
P27
P28
P29
P30
P31
R1
U2
U3
U4
R2
U5
R3
U6
9-14
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Pin Listing and Signal Definitions
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
U7
U8
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
W23
W24
W25
W26
W27
W28
W29
W30
W31
Y1
GTLREF
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
Input
U9
VCC
VCC
U23
U24
U25
U26
U27
U28
U29
U30
U31
V1
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
Y2
VCC
VCC
Y3
Reserved
BCLK0
VSS
Reserved
Input
VSS
Y4
Sys Bus Clk
Power/Other
Power/Other
Power/Other
Common Clk
V2
VCC
Y5
V3
VSS
Y6
TESTHI3
VSS
Input
V4
VCC
Y7
V5
VSS
Y8
RESET#
D62#
Input
V6
VCC
Y9
Source Sync Input/Output
Power/Other
V7
VSS
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
VCC
V8
VCC
DSTBP3#
DSTBN3#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
V9
VSS
V23
V24
V25
V26
V27
V28
V29
V30
V31
W1
W2
W3
W4
W5
W6
W7
W8
W9
VSS
VCC
DSTBP2#
DSTBN2#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
VCC
VSS
DSTBP1#
DSTBN1#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VCC
VSS
VCC
DSTBP0#
DSTBN0#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
VCC
VSS
D5#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Reserved
VSS
Reserved
D2#
Power/Other
Sys Bus Clk
Power/Other
Power/Other
Power/Other
Power/Other
VSS
BCLK1
TESTHI0
TESTHI1
TESTHI2
GTLREF
Input
Input
Input
Input
Input
D0#
Source Sync Input/Output
Reserved
Reserved
SM_TS1_A1
VCC
Reserved
Reserved
SMBus
Reserved
Reserved
Input
Power/Other
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-15
Pin Listing and Signal Definitions
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
Y31
AA1
AA2
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AB8
AB9
VCC
DBI3#
D55#
VSS
Power/Other
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB31
AC1
2
AA3
BSEL0
VCC
Output
Input
AA4
AA5
D51#
D52#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSSA
VCC
AA6
AA7
TESTHI4
D61#
VSS
Input
D37#
D32#
D31#
VCC
Source Sync Input/Output
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AA8
Source Sync Input/Output
Power/Other
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AA31
AB1
D54#
D53#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D14#
D12#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D48#
D49#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D13#
D9#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D33#
VSS
Source Sync Input/Output
Power/Other
VCC
D8#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D24#
D15#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D7#
VSS
SM_EP_A2
SM_EP_A1
VCC
SMBus
Input
Input
D11#
D10#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
SMBus
Power/Other
Power/Other
Reserved
VSS
D6#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Reserved
VSS
Reserved
D3#
AC2
Power/Other
Power/Other
Power/Other
VCC
AC3
VCC
D1#
Source Sync Input/Output
AC4
VCC
SM_TS1_A0
SM_EP_A0
VSS
SMBus
Input
Input
AC5
D60#
D59#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
SMBus
AC6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Sync
AC7
VCC
AC8
D56#
D47#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
AC9
AB2
VCC
AC10
AC11
AC12
AC13
AC14
AC15
2
AB3
BSEL1
VCCA
VSS
Output
Input
D43#
D41#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AB4
AB5
AB6
AB7
D63#
D50#
DP2#
Source Sync Input/Output
PWRGOOD Power/Other
Input
Common Clk
Input/Output
9-16
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Pin Listing and Signal Definitions
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Table 51. Pin Listing by Pin Number for the
INT-mPGA Package
Signal
Buffer Type
Signal
Buffer Type
Pin No.
Pin Name
Direction
Pin No.
Pin Name
Direction
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AC30
AC31
AD1
VCC
D34#
DP0#
VSS
Power/Other
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AE2
D21#
D18#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Source Sync Input/Output
Common Clk
Input/Output
VCC
Power/Other
D4#
Source Sync Input/Output
D25#
D26#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
SM_ALERT#
SM_WP
VCC
SMBus
Output
Input
SMBus
Power/Other
Power/Other
Power/Other
Power/Other
Reserved
D23#
D20#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
VSS
AE3
VCC
D17#
DBI0#
SM_CLK
SM_DAT
VSS
Source Sync Input/Output
Source Sync Input/Output
AE4
Reserved
TESTHI6
SLP#
Reserved
Input
AE5
Power/Other
Async GTL+
SMBus
Input
AE6
Input
SMBus
Output
AE7
D58#
Source Sync Input/Output
Power/Other
Power/Other
Power/Other
Reserved
AE8
VCC
VCC
AE9
D44#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
Reserved
VCC
Reserved
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
D42#
AD2
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
AD3
VSS
DBI2#
D35#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AD4
VCCIOPLL
TESTHI5
VCC
Input
Input
AD5
VCC
AD6
Reserved
Reserved
DP3#
Reserved
Reserved
Reserved
Reserved
AD7
D57#
D46#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
AD8
Common Clk
Power/Other
Common Clk
Input/Output
AD9
VCC
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
D45#
D40#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
DP1#
Input/Output
D28#
Source Sync Input/Output
Power/Other
VSS
D38#
D39#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D27#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D22#
VCC
COMP0
VSS
Power/Other
Power/Other
Input
D19#
Source Sync Input/Output
Source Sync Input/Output
Power/Other
D16#
D36#
D30#
VCC
Source Sync Input/Output
Source Sync Input/Output
Power/Other
VSS
SM_VCC
SM_VCC
Power/Other
Power/Other
D29#
DBI1#
VSS
Source Sync Input/Output
Source Sync Input/Output
Power/Other
1. In systems utilizing the Intel Xeon processor, the system
designer must pull-up these signals to the processor VCC.
2. Baseboards treating AA3 and AB3 as Reserved will operate
correctly with a bus clock of 100 MHz.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-17
Pin Listing and Signal Definitions
§
9-18
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9.2
Signal Definitions
Table 52. Signal Definitions (Sheet 1 of 9)
Name
Type
Description
36
A[35:3]# (Address) define a 2 byte physical memory address space. In sub-phase
1 of the address phase, these pins transmit the address of a transaction. In sub-
phase 2, these pins transmit transaction type information. These signals must
®
connect the appropriate pins of all agents on the Intel Xeon™ processor MP on
the 0.13 micron process processor system bus. A[35:3]# are protected by parity
signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the
receiving buffers by ADSTB[1:0]#.
A[35:3]#
I/O
On the active-to-inactive transition of RESET#, the processors sample a subset of
the A[35:3]# pins to determine their power-on configuration. See Section 6.1.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal cache and before driving a read/
write transaction on the bus. Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported
in real mode.
A20M#
I
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[35:3]# pins. All bus agents observe the ADS# activation to begin
parity checking, protocol checking, address decode, internal snoop, or deferred
reply ID match operations associated with the new transaction. This signal must
connect the appropriate pins on all Intel Xeon processor MP on the 0.13 micron
process processor System Bus agents.
ADS#
I/O
I/O
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling
edge.
ADSTB[1:0]#
AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,
A[35:3]#, and the transaction type on the REQ[4:0]# pins. A correct parity signal is
high if an even number of covered signals are low and low if an odd number of
covered signals are low. This allows parity to be high when all the covered signals
are high. AP[1:0]# should connect the appropriate pins of all Intel Xeon processor
MP on the 0.13 micron process processor system bus agents. The following table
defines the coverage model of these signals.
AP[1:0]#
I/O
Request Signals
Subphase 1
Subphase 2
A[35:24]#
A[23:3]#
AP0#
AP1#
AP1#
AP1#
AP0#
AP0#
REQ[4:0]#
The differential pair BCLK (Bus Clock) determines the bus frequency. All processor
system bus agents must receive these signals to drive their outputs and latch their
inputs.
BCLK[1:0]
I
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing the falling edge of BCLK1.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-19
Table 52. Signal Definitions (Sheet 2 of 9)
Name
Type
Description
BINIT# (Bus Initialization) may be observed and driven by all processor system bus
agents and if used, must connect the appropriate pins of all such agents. If the
BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal
any bus condition that prevents reliable future information.
If BINIT# observation is enabled during power-on configuration (see Section 6.1)
and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity
and bus request arbitration state machines. The bus agents do not reset their IOQ
and transaction tracking state machines upon observation of BINIT# assertion.
Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for
the system bus and attempt completion of their bus queue and IOQ entries.
BINIT#
I/O
If BINIT# observation is disabled during power-on configuration, a central agent
may handle an assertion of BINIT# as appropriate to the error handling architecture
of the system.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all processor system
bus agents. In order to avoid wire-OR glitches associated with simultaneous edge
transitions driven by multiple drivers, BNR# is activated on specific clock edges and
sampled on specific clock edges.
BNR#
I/O
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[5:0]#
should connect the appropriate pins of all Intel Xeon processor MP on the 0.13
micron process processor system bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a
processor output used by debug tools to determine processor debug readiness.
BPM[5:0]#
I/O
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is
used by debug tools to request debug operation of the processors.
BPM[5:4]# must be bussed to all bus agents.
These signals do not have on-die termination and must be terminated at the
end agent. See the ITP Debug Port Design Guide for more information.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
system bus. It must connect the appropriate pins of all processor system bus
agents. Observing BPRI# active (as asserted by the priority agent) causes all other
agents to stop issuing new requests, unless such requests are part of an ongoing
locked operation. The priority agent keeps BPRI# asserted until all of its requests
are completed, then releases the bus by deasserting BPRI#.
BPRI#
I
9-20
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Table 52. Signal Definitions (Sheet 3 of 9)
Name
Type
Description
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual processor
pins. The tables below give the rotating interconnect between the processor and
bus signals for 2-way and 4-way systems.
BR[3:0]# Signals Rotating Interconnect, 4-way system (MP processors only)
Bus Signal Agent 0 Pins Agent 1 Pins Agent 2 pins Agent 3 pins
BREQ0#
BREQ1#
BREQ2#
BREQ3#
BR0#
BR1#
BR2#
BR3#
BR3#
BR0#
BR1#
BR2#
BR2#
BR3#
BR0#
BR1#
BR1#
BR2#
BR3#
BR0#
BR0#
BR[1:3]#
I/O
I
BR[1:0]# Signals Rotating Interconnect, 2-way system
Bus Signal Agent 0 Pins Agent 1 Pins
1
BREQ0#
BREQ1#
BR0#
BR1#
BR1#
BR0#
BR2# and BR3# must not be utilized in 2-way platform designs.
During power-on configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[3:0]# pins on the active-to-inactive transition
of RESET#. The pin which the agent samples asserted determines it’s agent ID.
These signals do not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
BSEL[1:0] (Bus Select) output signals are used to select the system bus frequency.
A BSEL[1:0] = “00” will select a 100 MHz bus clock frequency. The frequency is
determined by the processor(s), chipset, and frequency synthesizer capabilities. All
system bus agents must operate at the same frequency. The Intel Xeon processor
MP on the 0.13 micron process processor currently operates at 100 MHz system
bus frequencies. Individual processors will only operate at their specified front side
bus (FSB) frequency.
BSEL[1:0]
O
On baseboards which support operation only at 100 MHz bus clocks these signals
can be ignored.
See the appropriate platform design guide for implementation examples.
See Table 3, “System Bus Clock Frequency Select Truth Table for BSEL[1:0]” on
page 3 for output values.
COMP[1:0] must be terminated to V on the baseboard using precision resistors.
SS
COMP[1:0]
I
These inputs configure the AGTL+ drivers of the processor. Refer to the appropriate
platform design guidelines and Table 14 for implementation details.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-21
Table 52. Signal Definitions (Sheet 4 of 9)
Name
Type
Description
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor system bus agents, and must connect the appropriate pins
on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals, and will thus be driven four times in a common
clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and
DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP#
and one DSTBN#. The following table shows the grouping of data signals to strobes
and DBI#.
DSTBN/
DSTBP
D[63:0]#
I/O
Data Group
DBI#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DBI# pins determine the polarity of the data signals. Each group
of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active,
the corresponding data group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of
the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data
bus is inverted. The bus agent will invert the data bus signals if more than half the
bits, within a 16-bit group, change logic level in the next cycle.
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI[3:0]#
I/O
DBI0#
DBI1#
DBI2#
DBI3#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the
processor system bus to indicate that the data bus is in use. The data bus is
released after DBSY# is deasserted. This signal must connect the appropriate pins
on all processor system bus agents.
DBSY#
I/O
DEFER# (Defer) is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.
DEFER#
DP[3:0]#
DRDY#
I
DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They are
driven by the agent responsible for driving D[63:0]#, and must connect the
appropriate pins of all processor system bus agents.
I/O
I/O
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
DSTBN[3:0]#
DSTBP[3:0]#
I/O
I/O
Data strobe used to latch in D[63:0]#.
Data strobe used to latch in D[63:0]#.
9-22
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Table 52. Signal Definitions (Sheet 5 of 9)
Name
Type
Description
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and
its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/
PBE# indicates a floating-point error and will be asserted when the processor
detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/
PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included
for compatibility with systems using MS-DOS*-type floating-point error reporting.
When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the
processor has a pending break event waiting for service. The assertion of FERR#/
PBE# indicates that the processor should be returned to the Normal state. When
FERR#/PBE# is asserted, indicating a break event, it will remain asserted until
STPCLK# is deasserted. For additional information on the pending break event
functionality, including the identification of support of the feature and enable/disable
information, refer to volume 3 of the Intel Architecture Software Developer's Manual
and the Intel Processor Identification and the CPUID Instruction application note.
FERR#/PBE#
O
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF
should be set to either 2/3Vcc or 0.63*Vcc (future processors). GTLREF is used by
the AGTL+ receivers to determine if a signal is a logical 0 or a logical 1.
GTLREF
I
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation
results. Any system bus agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be continued by reasserting HIT#
and HITM# together.
HIT#
I/O
I/O
Since multiple agents may deliver snoop results at the same time, HIT# and HITM#
are wire-OR signals which must connect the appropriate pins of all processor
system bus agents. In order to avoid wire-OR glitches associated with simultaneous
edge transitions driven by multiple drivers, HIT# and HITM# are activated on
specific clock edges and sampled on specific clock edges.
HITM#
IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the
processor system bus. This transaction may optionally be converted to an external
error signal (e.g., NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#.
IERR#
O
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE#
I
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside all processors
without affecting their internal caches or floating-point registers. Each processor
then begins execution at the power-on Reset vector configured during power-on
configuration. The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the appropriate pins
of all processor system bus agents.
INIT#
I
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-23
Table 52. Signal Definitions (Sheet 6 of 9)
Name
Type
Description
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all system
bus agents. When the APIC functionality is disabled, the LINT0 signal becomes
INTR,
a maskable interrupt request signal, and LINT1 becomes NMI, a
nonmaskable interrupt. INTR and NMI are backward compatible with the signals of
those names on the Pentium processor. Both signals are asynchronous.
LINT[1:0]
I
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of all processor system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction to the end of the last transaction.
LOCK#
I/O
When the priority agent asserts BPRI# to arbitrate for ownership of the processor
system bus, it will wait until it observes LOCK# deasserted. This enables symmetric
agents to retain ownership of the processor system bus throughout the bus locked
operation and ensure the atomicity of lock.
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
without a bus protocol violation. It may be driven by all processor system bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion options
are defined by the following options:
•
•
•
Enabled or disabled.
Asserted, if configured, for internal errors along with IERR#.
Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
MCERR#
I/O
•
Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the IA-32 Software
Developer’s Manual, Volume 3: System Programming Guide.
Since multiple agents may drive this signal at the same time, MCERR# is a wire-OR
signal which must connect the appropriate pins of all processor system bus agents.
In order to avoid wire-OR glitches associated with simultaneous edge transitions
driven by multiple drivers, MCERR# is activated on specific clock edges and
sampled on specific clock edges.
ODTEN (On-die termination enable) should be connected to V
to enable on-die
CC
termination for end bus agents. For middle bus agents, pull this signal down via a
resistor to ground to disable on-die termination. Whenever ODTEN is high, on-die
termination will be active, regardless of other states of the bus.
ODTEN
I
The assertion of PROCHOT# (processor hot) indicates that the processor die
temperature has reached its thermal limit. See Section 6.3 for more details.
PROCHOT#
O
These signals do not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
PWRGOOD (Power Good) is an input. The processor requires this signal to be a
clean indication that all Intel Xeon processor MP on the 0.13 micron process
processor clocks and power supplies are stable and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage current),
without glitches, from the time that the power supplies are turned on until they come
within specification. The signal must then transition monotonically to a high state.
Figure 12 illustrates the relationship of PWRGOOD to the RESET# signal.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. It must also meet the
minimum pulse width specification in Table 18, and be followed by a 1 ms RESET#
pulse.
PWRGOOD
I
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
9-24
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Table 52. Signal Definitions (Sheet 7 of 9)
Name
Type
Description
REQ[4:0]# (Request Command) must connect the appropriate pins of all processor
system bus agents. They are asserted by the current bus owner to define the
currently active transaction type. These signals are source synchronous to
ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking
of these signals.
REQ[4:0]#
I/O
Asserting the RESET# signal resets all processors to known states and invalidates
their internal caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least one millisecond after VCC and BCLK
have reached their proper specifications. On observing active RESET#, all system
bus agents will deassert their outputs within two clocks. RESET# must not be kept
asserted for more than 10ms.
RESET#
I
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
Section 6.1.
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RS[2:0]#
RSP#
I
I
RSP# (Response Parity) is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#, the signals for
which RSP# provides parity protection. It must connect to the appropriate pins of all
processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low
if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also
high, since this indicates it is not being driven by any agent guaranteeing correct
parity.
SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate
that the processor is present.
SKTOCC#
SLP#
O
I
SLP# (Sleep), when asserted in Stop-Grant state, causes processors to enter the
Sleep state. During Sleep state, the processor stops providing internal clock signals
to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in
this state will not recognize snoops or interrupts. The processor will recognize only
assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK
input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state
and returns to Stop-Grant state, restarting its internal clock signals to the bus and
processor core units.
SMB_PRT (SMBus Present) pin is grounded on processor packages (FC-mPGA2)
that do not contain SMBus components (PIROM, Scratch EEPROM, and thermal
sensor). It is floating on processor packages (INT-mPGA) that do contain the
SMBus components.
SMB_PRT
O
O
SM_ALERT# (SMBus Alert) is an asynchronous interrupt line associated with the
SMBus Thermal Sensor device. It is an open-drain output and the processor
SM_ALERT#
includes a 10kΩ pull-up resistor to SM_V for this signal. It is only available on the
CC
Intel Xeon processor in INT-mPGA package. For more information on the usage of
the SM_ALERT# pin, see Section 6.4.5.
The SM_CLK (SMBus Clock) signal is an input clock to the system management
logic which is required for operation of the system management features of the Intel
Xeon processor MP on the 0.13 micron process processor. This clock is driven by
the SMBus controller and is asynchronous to other clocks in the processor.The
SM_CLK
SM_DAT
I/O
I/O
processor includes a 10 kΩ pull-up resistor to SM_V
for this signal. It is only
available on the Intel Xeon processor in INT-mPGA package.
CC
The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal
provides the single-bit mechanism for transferring data between SMBus
devices.The processor includes a 10 kΩ pull-up resistor to SM_V for this signal.
CC
It is only available on the Intel Xeon processor in INT-mPGA package.
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-25
Table 52. Signal Definitions (Sheet 8 of 9)
Name
Type
Description
The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in
conjunction with the upper address bits in order to maintain unique addresses on
the SMBus in a system with multiple processors. To set an SM_EP_A line high, a
pull-up resistor should be used that is no larger than 1kΩ. The processor includes a
SM_EP_A[2:0]
I
10kΩ pull-down resistor to V for each of these signals. It is only available on the
SS
Intel Xeon processor in INT-mPGA package.
For more information on the usage of these pins, see Section 6.4.8.
The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus
in conjunction with the upper address bits in order to maintain unique addresses on
the SMBus in a system with multiple processors.
The device’s addressing, as implemented, includes a Hi-Z state for both address
pins. The use of the Hi-Z state is achieved by leaving the input floating
(unconnected). It is only available on the Intel Xeon processor in INT-mPGA
package.
SM_TS_A[1:0]
I
For more information on the usage of these pins, see Section 6.4.8.
Provides power to the SMBus components which are only available on the Intel
Xeon processor in INT-mPGA package. Additionally provides power for the VID and
BSEL logic. Intel Xeon processor MP on the 0.13 micron processprocessor
baseboards MUST provide SM_Vcc. See Figure for further details.
SM_V
I
I
CC
WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch
EEPROM is write-protected when this input is pulled high to SM_V .The
CC
SM_WP
SMI#
processor includes a 10k pull-down resistor to V for this signal. It is only available
SS
on the Intel Xeon processor in INT-mPGA package.
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, processors save the current state
and enter System Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the SMM handler.
I
I
If SMI# is asserted during the deassertion of RESET# the processor will tri-state its
outputs. It is only available on the Intel Xeon processor in INT-mPGA package.
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the system
bus and APIC units. The processor continues to snoop bus transactions and
service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
STPCLK#
TCK (Test Clock) provides the clock input for the processor Test Bus (also known
as the Test Access Port).
TCK
TDI
I
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
TDO
O
All TESTHI[6:0] pins should be individually connected to VCC via a pull-up resistor
which matches the trace impedance within a range of ± 10 Ω. TESTHI[3:0] and
TESTHI[6:5] may all be tied together and pulled up to VCC with a single resistor if
desired. However, utilization of boundary scan test will not be functional if these
pins are connected together. TESTHI4 must always be pulled up independently
from the other TESTHI pins. For optimum noise margin, all pull-up resistor values
used for TESTHI[6:0] pins should have a resistance value within ± 20% of the
impedance of the baseboard transmission line traces. For example, if the trace
impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.
TESTHI[6:0]
I
9-26
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Table 52. Signal Definitions (Sheet 9 of 9)
Name
Type
Description
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level where permanent silicon damage may occur.
Measurement of the temperature is accomplished through an internal thermal
sensor which is configured to trip at approximately 135°C. Upon assertion of
THERMTRIP#, the processor will shut off its internal clocks (thus halting program
execution) in an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (Vcc) must be removed following the assertion of
THERMTRIP#. See Figure 15 and Table 18 for the appropriate power down
sequence and timing requirements.
THERMTRIP#
O
Once activated, THERMTRIP# remains latched until RESET# is asserted. While
the assertion of the RESET# signal will de-assert THERMTRIP#, if the processor’s
junction temperature remains at or above the trip level, THERMTRIP# will again be
asserted.
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TMS
I
This signal does not have on-die termination and must be terminated at the end
agent. See the appropriate platform design guideline for additional information.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive
a write or implicit writeback data transfer. TRDY# must connect the appropriate pins
of all system bus agents.
TRDY#
TRST#
I
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset. See the appropriate platform design guideline for
additional information.
VCCA provides isolated power for the analog portion of the internal PLL’s. Use a
discrete RLC filter to provide clean power. Use the filter defined in Section 2.5 to
provide clean power to the PLL. The tolerance and total ESR for the filter is
important. Refer to the appropriate platform design guidelines for complete
implementation details.
V
V
I
I
CCA
V
provides isolated power for digital portion of the internal PLL’s. Follow the
CCIOPLL
guidelines for V
(Section 2.5). Refer to the appropriate platform design
CCIOPLL
CCA
guidelines for complete implementation details.
The Vccsense and Vsssense pins are the points for which processor minimum and
maximum voltage requirements are specified. Uniprocessor designs may utilize
these pins for voltage sensing for the processor's voltage regulator. However, multi-
processor designs must not connect these pins to sense logic, but rather utilize
V
V
CCSENSE
O
SSSENSE
them for power delivery validation.
VID[4:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages (V ). Unlike previous generations of processors, these are logic
CC
signals and are driven by the Intel Xeon processor MP on the 0.13 micron process
processor. Hence the voltage supply for these pins (SM_Vcc) must be valid before
the VRM supplying Vcc to the processor is enabled (see Figure ). Conversely, the
VRM output must be disabled prior to the voltage supply for these pins becomes
invalid. The VID pins are needed to support processor voltage specification
variations. See Table 4 for definitions of these pins. The power supply must supply
the voltage that is requested by these pins, or disable itself.
VID[4:0]
O
V
provides an isolated, internal ground for internal PLL’s. Do not connect
SSA
directly to ground. This pin is to be connected to V
and V
through a
CCA
CCIOPLL
V
I
SSA
discrete filter circuit. Follow the guidelines for V
(Section 2.5). Refer to the
SSA
appropriate platform design guidelines for complete implementation details.
NOTES:
1. Intel Xeon processors only support BR0# and BR1#. However, the Intel Xeon processors must terminate
BR2# and BR3# to the processor V
.
CC.
§
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
9-27
9-28
Intel® Xeon™ Processor MP with up to 2MB L3 Cache
Working page only. Do not distribute.
1
2
Introduction..........................................................................................................1-1
1.1
Terminology ..................................................................................................1-3
1.1.1 Processor Packaging Terminology ..................................................1-3
References....................................................................................................1-4
1.2
Electrical Specifications .................................................................................2-1
2.1
2.2
2.3
System Bus and GTLREF.............................................................................2-1
Power and Ground Pins................................................................................2-1
Decoupling Guidelines..................................................................................2-1
2.3.1 VCC Decoupling...............................................................................2-2
2.3.2 System Bus AGTL+ Decoupling ......................................................2-2
System Bus Clock (BCLK[1:0]) and Processor Clocking..............................2-2
2.4
2.5
2.6
2.4.1
Bus Clock........................................................................................2-3
PLL Filter.......................................................................................................2-4
2.5.1 Mixing Processors............................................................................2-5
Voltage Identification....................................................................................2-6
2.6.1 Mixing Processors of Different Voltages..........................................2-7
Reserved or Unused Pins.............................................................................2-8
System Bus Signal Groups...........................................................................2-8
Asynchronous GTL+ Signals ........................................................................2-9
Maximum Ratings .......................................................................................2-10
Processor DC Specifications ......................................................................2-10
AGTL+ System Bus Specifications.............................................................2-16
System Bus AC Specifications....................................................................2-17
Processor AC Timing Waveforms...............................................................2-22
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3
System Bus Signal Quality Specifications..............................................3-1
3.1
System Bus Clock (BCLK) Signal Quality Specifications and Measurement
Guidelines.....................................................................................................3-1
System Bus Signal Quality Specifications and Measurement Guidelines ....3-2
System Bus Signal Quality Specifications and Measurement Guidelines ....3-5
3.3.1 Overshoot/Undershoot Guidelines...................................................3-5
3.3.2 Overshoot/Undershoot Magnitude...................................................3-6
3.3.3 Overshoot/Undershoot Pulse Duration ............................................3-6
3.3.4 Activity Factor ..................................................................................3-6
3.3.5 Reading Overshoot/Undershoot Specification Tables .....................3-7
3.3.6 Determining if a System Meets the Overshoot/Undershoot Specifica-
tions .................................................................................................3-7
3.2
3.3
4
5
Mechanical Specifications.............................................................................4-1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Mechanical Specifications.............................................................................4-3
Package Load Specifications........................................................................4-8
Insertion Specifications.................................................................................4-8
Mass Specifications ......................................................................................4-8
Materials .......................................................................................................4-9
Markings .......................................................................................................4-9
Pinout Diagram ...........................................................................................4-10
Thermal Specifications....................................................................................5-1
5.1
5.2
Thermal Specifications..................................................................................5-3
Measurements for Thermal Specifications....................................................5-5
5.2.1 Processor Case Temperature Measurement...................................5-5
29
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6
Features.................................................................................................................6-1
6.1
6.2
Power-On Configuration Options..................................................................6-1
Clock Control and Low Power States ...........................................................6-1
6.2.1 Normal State—State 1.....................................................................6-1
6.2.2 AutoHALT Powerdown State—State 2............................................6-1
6.2.3 Stop-Grant State—State 3...............................................................6-2
6.2.4 HALT/Grant Snoop State—State 4..................................................6-3
6.2.5 Sleep State—State 5 .......................................................................6-3
6.2.6 Bus Response during Low Power States.........................................6-4
Thermal Monitor............................................................................................6-4
6.3.1 Thermal Diode .................................................................................6-4
System Management Bus (SMBus) Interface...............................................6-5
6.4.1 Processor Information ROM (PIROM).............................................6-6
6.4.2 Scratch EEPROM............................................................................6-8
6.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions.....6-8
6.4.4 SMBus Thermal Sensor...................................................................6-8
6.4.5 Thermal Sensor Supported SMBus Transactions............................6-9
6.4.6 SMBus Thermal Sensor Registers.................................................6-11
6.4.6.1 Thermal Reference Registers...........................................6-11
6.4.6.2 Thermal Limit Registers....................................................6-11
6.4.6.3 Status Register .................................................................6-11
6.4.6.4 Configuration Register ......................................................6-12
6.4.6.5 Conversion Rate Registers...............................................6-13
6.4.7 SMBus Thermal Sensor Alert Interrupt..........................................6-13
6.4.8 SMBus Device Addressing ............................................................6-13
6.3
6.4
7
Boxed Processor Specifications.................................................................7-1
7.1
7.2
Introduction...................................................................................................7-1
Mechanical Specifications ............................................................................7-2
7.2.1 Boxed Processor Heatsink Dimensions...........................................7-2
7.2.2 Boxed Processor Heatsink Weight ..................................................7-2
7.2.3 Boxed Processor Retention Mechanism and Heatsink Supports ....7-2
Boxed Processor Requirements...................................................................7-5
7.3.1 Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor ..
.........................................................................................................7-5
7.3
7.4
Thermal Specifications .................................................................................7-5
7.4.1 Boxed Processor Cooling Requirements.........................................7-5
8
9
Debug Tools Specifications..........................................................................8-1
8.1
Logic Analyzer Interface (LAI) ......................................................................8-1
8.1.1 Mechanical Considerations..............................................................8-1
8.1.2 Electrical Considerations .................................................................8-1
Pin Listing and Signal Definitions..............................................................9-1
9.1
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Pin As-
signments .....................................................................................................9-1
9.1.1 Pin Listing by Pin Number .............................................................9-10
Signal Definitions........................................................................................9-19
9.2
30
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2
3
Typical VCCIOPLL, VCCA and VSSA Power Distribution.................................... 2-4
Phase Lock Loop (PLL) Filter Requirements ........................................................... 2-5
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Voltage-Current
Projections............................................................................................................... 2-12
Electrical Test Circuit.............................................................................................. 2-22
TCK Clock Waveform ............................................................................................ 2-23
Differential Clock Waveform.................................................................................. 2-23
Differential Clock Crosspoint Specification ........................................................... 2-24
System Bus Common Clock Valid Delay Timing Waveform ................................ 2-24
System Bus Source Synchronous 2X (Address) Timing Waveform....................... 2-25
System Bus Source Synchronous 4X (Data) Timing Waveform............................ 2-26
System Bus Reset and Configuration Timing Waveform....................................... 2-27
Power-On Reset and Configuration Timing Waveform.......................................... 2-27
TAP Valid Delay Timing Waveform ...................................................................... 2-28
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform............
................................................................................................................................. 2-28
THERMTRIP# to Vcc Timing................................................................................ 2-28
SMBus Timing Waveform ...................................................................................... 2-29
SMBus Valid Delay Timing Waveform.................................................................. 2-29
Example 3.3 Volt/SM_VCC Sequencing................................................................ 2-30
FERR#/PBE# Valid Delay Timing ......................................................................... 2-31
BCLK[1:0] Signal Integrity Waveform..................................................................... 3-2
Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and Asynchro-
nous GTL+ Buffers ................................................................................................... 3-3
High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and Asynchro-
nous GTL+ Buffers ................................................................................................... 3-3
Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers....................................................................................................................... 3-4
High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers....................................................................................................................... 3-5
Maximum Acceptable Overshoot/Undershoot Waveform...................................... 3-10
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™
Processor with 512-KB L2 Cache in INT-mPGA Package - Assembly Drawing (In-
cluding Socket).......................................................................................................... 4-2
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Package Top View
Component Placement Detail.................................................................................... 4-3
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Package Drawing
4-3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Top View - Com-
ponent Keep-In.......................................................................................................... 4-5
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™
Processor with 512-KB L2 Cache in INT-mPGA Package - Cross Section View - Pin
Side Component Keep-In .......................................................................................... 4-5
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™
Processor with 512-KB L2 Cache in INT-mPGA Package - Processor Pin Details. 4-6
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Package IHS Flat-
ness and Tilt Drawing................................................................................................ 4-7
Intel® Xeon™ Processor MP on the 0.13 Micron Process INT-mPGA Package IHS
Flatness and Tilt Drawing ......................................................................................... 4-7
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Top-Side Markings
(Package Example).................................................................................................... 4-9
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Bottom-Side
Markings (Package Example).................................................................................. 4-10
31
32
33
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35
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37
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™
Processor with 512-KB L2 Cache in INT-mPGA Package - Pinout Diagram - Top View
4-11
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor and Intel® Xeon™
Processor with 512-KB L2 Cache in INT-mPGA Package - Pinout Diagram - Bottom
View......................................................................................................................... 4-12
Thermal and Mechanical Components - Exploded View.......................................... 5-1
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Thermal Design
Power vs. Electrical Projections ................................................................................ 5-4
Thermal Measurement Point for Processor TCASE.................................................. 5-5
Stop Clock State Machine ......................................................................................... 6-2
Logical Schematic of SMBus Circuitry..................................................................... 6-5
Mechanical Representation of the Boxed Intel® Xeon™ Processor MP on the 0.13 Mi-
cron Process Processor Passive Heatsink .................................................................. 7-1
Boxed Processor Clip ................................................................................................ 7-3
Boxed Processor Retention Mechanism.................................................................... 7-3
Multiple View Space Requirements for Boxed Processors....................................... 7-4
38
39
40
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1
Feature Table for Intel® Xeon™ Processor MP on the 0.13 Micron Process.................
................................................................................................................................... 1-2
Core Frequency to System Bus Multiplier Configuration......................................... 2-3
System Bus Clock Frequency Select Truth Table for BSEL[1:0]............................. 2-3
Voltage Identification Definition .............................................................................. 2-7
System Bus Signal Groups........................................................................................ 2-9
Processor Absolute Maximum Ratings ................................................................... 2-10
Voltage and Current Specifications......................................................................... 2-11
System Bus Differential BCLK DC Specifications................................................. 2-13
AGTL+ Signal Group DC Specifications ............................................................... 2-14
PWRGOOD and TAP Signal Group DC Specifications......................................... 2-14
Asynchronous GTL+ Signal Group DC Specifications .......................................... 2-15
SMBus Signal Group DC Specifications ................................................................ 2-15
BSEL[1:0] and VID[4:0] DC Specifications........................................................... 2-15
AGTL+ Bus Voltage Definitions ............................................................................ 2-17
System Bus Differential Clock AC Specifications................................................. 2-18
System Bus Common Clock AC Specifications ..................................................... 2-18
System Bus Source Synchronous AC Specifications.............................................. 2-19
Miscellaneous Signals AC Specifications............................................................... 2-20
System Bus AC Specifications (Reset Conditions)................................................. 2-20
TAP Signal Group AC Specifications..................................................................... 2-21
SMBus Signal Group AC Specifications ................................................................ 2-21
BCLK Signal Quality Specifications......................................................................... 3-1
Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers.................. 3-2
Ringback Specifications for PWRGOOD Input and TAP Buffers ........................... 3-3
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Source Synchro-
nous AGTL+ Signal Group (Data) Overshoot/Undershoot Tolerance ...........................
................................................................................................................................... 3-8
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Common Clock
AGTL+ Signal Group Overshoot/Undershoot Tolerance ......................................... 3-8
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Common Clock
AGTL+ Signal Group Overshoot/Undershoot Tolerance ......................................... 3-9
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Asynchronous
GTL+ and TAP Signal Groups Overshoot/Undershoot Tolerance ........................... 3-9
Dimensions for the Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor
Package...................................................................................................................... 4-4
Package Dynamic and Static Load Specifications .................................................... 4-8
Processor Mass.......................................................................................................... 4-8
Processor Material Properties.................................................................................... 4-9
Intel® Xeon™ Processor MP on the 0.13 Micron Process Processor Thermal Design
Power......................................................................................................................... 5-3
Power-On Configuration Option Pins ....................................................................... 6-1
Processor Information ROM Format......................................................................... 6-6
Read Byte SMBus Packet.......................................................................................... 6-8
Write Byte SMBus Packet......................................................................................... 6-8
Write Byte SMBus Packet......................................................................................... 6-9
Read Byte SMBus Packet.......................................................................................... 6-9
Send Byte SMBus Packet........................................................................................ 6-10
Receive Byte SMBus Packet................................................................................... 6-10
ARA SMBus Packet................................................................................................ 6-10
SMBus Thermal Sensor Command Byte Bit Assignments..................................... 6-10
Thermal Reference Register Values........................................................................ 6-11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
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46
47
48
SMBus Thermal Sensor Status Register.................................................................. 6-12
SMBus Thermal Sensor Configuration Register..................................................... 6-12
SMBus Thermal Sensor Conversion Rate Registers ............................................... 6-13
Thermal Sensor SMBus Addressing on the Intel® Xeon™ Processor MP on the 0.13
Micron Process Processor........................................................................................ 6-15
Memory Device SMBus Addressing on the Intel® Xeon™ Processor MP on the 0.13
Micron Process Processor........................................................................................ 6-15
Pin Listing by Pin Name for the INT-mPGA Package.............................................. 9-1
Pin Listing by Pin Number for the INT-mPGA Package ........................................ 9-10
Signal Definitions.................................................................................................... 9-19
49
50
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