PBL38621/2QNT_技术文档

June 1999

PBL 386 21/2

Subscriber Line

Interface Circuit

Description

Key Features

• 24-pin SSOP package

The PBL 386 21/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated

circuit for use in DAML, FITL and other telecommunications equipment. The PBL

386 21/2 has been optimized for low total line interface cost and a high degree of

flexibility in different applications.

The PBL 386 21/2 has constant current feed, programmable to max. 30 mA.

A second lower battery voltage may be connected to the device to reduce short

loop power dissipation. The SLIC automatically switches between the two battery

supply voltages without need for external components or external control.

The SLIC incorporates loop current, ground key and ring trip detection functions.

The PBL 386 21/2 is compatible with loop start signaling.

Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is

accomplished by the SLIC in conjunction with either a conventional CODEC/filter or

with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable

the two-wire impedance, complex or real, is set by a simple external network.

Longitudinal voltages are suppressed by a feedback loop in the SLIC and the

longitudinal balance specifications meet Bellcore TR909 requirements.

The PBL 386 21/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC.

• High and low battery with automatic

switching

• 60 mW on-hook power dissipation in

active state

• On-hook transmission

• Long loop battery feed tracks Vbat for

maximum line voltage

• Only +5 V feed in addition to battery

• Selectable transmit gain (1x or 0.5x)

• No power-up sequence

• 44V open loop voltage @ -48V battery

feed

• Full longitudinal current capability

during on-hook state

• Analog over temperature protection

permits transmission while the

protection circuit is active

• Polarity reversal

• Integrated Ring Relay driver

• Ground key detector

• Programmable signal headroom

• -40 °C to +85 °C ambient temperature

range

Ring Relay

RRLY

Driver

DT

C1

Ring Trip

Comparator

DR

TIPX

RINGX

HP

C2

Input

Decoder

and

C3

Ground Key

Detector

Control

DET

POV

PSG

PLC

Line Feed

Controller

and

Longitudinal

Signal

VCC

Two-wire

Interface

Suppression

LP

PBL

PBL 386 21/2

386 21/2

VBAT2

VBAT

PLD

REF

Off-hook

Detector

PBL 386 21/2

AGND

BGND

VTX

RSN

VF Signal

Transmission

PTG

24-pin SOIC, 24-pin SSOP, 28-pin PLCC

Figure 1. Block diagram.

1

PBL 386 21/2

Maximum Ratings

Parameter

Symbol

Min

Max

Unit

Temperature, Humidity

Storage temperature range

Operating temperature range

Operating junction temperature range, Note 1

T_Stg

T_Amb

T_J

-55

-40

+150

+110

+140

°C

Power supply, -40 °C ≤ T_Amb≤ +85 °C

V

_CCwith respect to A/BGND

V_Bat2with respect to A/BGND

_Batwith respect to A/BGND, continuous

V_CC

V_Bat2

V_Bat

-0.4

V_Bat

-75

-80

6.5

0.4

V

V_Batwith respect to A/BGND, 10 ms

Power dissipation

Continuous power dissipation at T_Amb≤ +85 °C

P_D

V_G

1.5

0,3

W

V

Ground

Voltage between AGND and BGND

Relay Driver

-0,3

Ring relay supply voltage

BGND+14 V

Ring trip comparator

Input voltage

Input current

V_DT, V_DR

I_DT, I_DR

V_Bat

-5

AGND

5

V

mA

Digital inputs, outputs (C1, C2, C3, DET)

Input voltage

V_ID

-0.4

V_CC

V

Output voltage

V_OD

TIPX and RINGX terminals, -40°C < T_Amb< +85°C, V_Bat= -50V

Maximum supplied TIPX or RINGX current

I_TIPX, I_RINGX-100

+100

2

mA

V

TIPX or RINGX voltage, continuous (referenced to AGND), Note 2

TIPX or RINGX, pulse < 10 ms, t_Rep> 10 s, Note 2

TIPX or RINGX, pulse < 1 µs, t_Rep> 10 s, Note 2

V_TA, V_RA

-80

V_Bat-10

V_Bat-25

V_Bat-35

5

V

10

15

V

TIPX or RINGX, pulse < 250 ns, t_Rep> 10 s, Notes 2 & 3

V

Recommended Operating Condition

Parameter

Symbol

Min

Max

Unit

Ambient temperature

T_Amb

V_CC

V_Bat

V_G

-40

4.75

-58

+85

5.25

-8

°C

V

V_CCwith respect to AGND

V_Batwith respect to AGND

AGND with respect to BGND

-100

100

mV

Notes

1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability.

2. With the diodes D_VBand D_VB2included, see figure 12.

3. R_F1and R_F2≥ 20 Ω is also required. Pulse is applied to TIP and RING outside R_F1and R_F2.

2

PBL 386 21/2

Electrical Characteristics

-40 °C ≤ T_Amb≤ +85 °C, PTG = open (see pin description), V_CC= +5V ±5 %, V_Bat= -58V to -40V, V_Bat2= -17V, R_LC=38.3 kΩ,

I_L= 22 mA. R_L= 600 Ω, R_F1= R_F2= R_P1= R_P2=0, R_Ref= 49.9 kΩ, C_HP= 47 nF, C_LP=0.15 µF, R_T= 120 kΩ, R_SG= 0 kΩ, R_RX= 60 kΩ,

R_R= 52.3 kΩ R_OV= ∞ unless otherwise specified. Current definition: current is positive if flowing into a pin.

Ref

Parameter

fig

Conditions

Min

Typ

Max

Unit

Two-wire port

Overload level, V_TRO

2

Active state

1% THD

1.0

V_Peak

On-Hook, I_Ldc< 5mA

Note 1, R_OV= ∞

Input impedance, Z_TR

Longitudinal impedance, Z_LOT, Z_LOR

Longitudinal current limit, I_LOT, I_LOR

Note 2

0 < f < 100 Hz

active state

Z_T/200

20

35

Ω/wire

10

mA_rms/wire

Longitudinal to metallic balance, B_LM

IEEE standard 455-1985, Z_TRX=736Ω

0.2 kHz < f < 1.0 kHz

53

dB

1.0 kHz < f < 3.4 kHz

Reverse polarity 0.2 kHz < f < 3.4 kHz 53

Longitudinal to metallic balance, B_LME

E_Lo

3

4

0.2 kHz < f < 1.0 kHz

1.0 kHz < f < 3.4 kHz

Reverse polarity 0.2 kHz < f < 3.4 kHz 53

53

75

70

68

dB

B_LME=20 • Log

V_TR

Longitudinal to four-wire balance, B_LFE

0.2 kHz < f < 1.0 kHz

1.0 kHz < f < 3.4 kHz

Reverse polarity 0.2 kHz < f < 3.4 kHz 53

53

75

70

68

dB

E_Lo

V_TX

B_LFE= 20 • Log

Metallic to longitudinal balance, B_MLE

V_TR

0.2 kHz < f < 3.4 kHz

40

50

dB

B_MLE= 20 •

; E_RX= 0

Log

V_Lo

C

TIPX

VTX

Figure 2. Overload level, V_TRO, two-wire

port

R_L

V_TRO

I_LDC

R_T

PBL 386 21/2

E_RX

1

<< R_L, R_L= 600 Ω

ωC

RINGX

RSN

R_RX

R_T= 120 kΩ, R_RX= 60 kΩ

VTX

TIPX

Figure 3. Longitudinal to metallic (B_LME

)

and Longitudinal to four-wire (B_LFE

balance

)

E_Lo

R_LT

C

R_T

V_TR

PBL 386 21/2

V_TX

1

ωC

R_LR

<< 150 Ω, R_LR=R_LT=R_L/2=300Ω

RINGX

RSN

R_RX

R_T= 120 kΩ, R_RX= 60 kΩ

3

PBL 386 21/2

Ref

fig

Parameter

Conditions

Min

Typ

Max

Unit

Four-wire to longitudinal balance, B_FLE

4

0.2 kHz < f < 4.0 kHz

40

50

dB

E_RX

B_FLE= 20 • Log

V_Lo

Two-wire return loss, r

|Z_TR+ Z_L|

r = 20 • Log

|Z_TR- Z_L|

0.2 kHz < f < 1.0 kHz

1.0 kHz < f < 3.4 kHz, Note 3

active, I_L= 0 mA

27

20

35

22

- 1.1

V_Bat+2.5

V_Bat+3.6

dB

V

TIPX idle voltage, V_Ti

RINGX idle voltage, V_Ri

V_TR

Four-wire transmit port (VTX)

Overload level, V_TXO

5

Load impedance > 20 kΩ,

1.0

V_Peak

1% THD, Note 4

On-hook, I_L< 5mA

Output offset voltage ∆V_TX

Output impedance, z_TX

1.0

-100

V_Peak

mV

Ω

0

15

100

50

0.2 kHz < f < 3.4 kHz

Four-wire receive port (RSN)

Receive summing node (RSN) DC voltage

Receive summing node (RSN) impedance

Receive summing node (RSN)

current (I_RSN) to metallic loop current (I_L)

gain,α_RSN

I

_RSN= -55 µA

1.15

1.25

8

1.35

20

V

Ω

0.2 kHz < f < 3.4 kHz

0.3 kHz < f < 3.4 kHz

200

ratio

Frequency response

Two-wire to four-wire, g_2-4

6

relative to 0 dBm, 1.0 kHz. E_RX= 0 V

0.3 kHz < f < 3.4 kHz

-0.20

-1.0

0.10

0.1

dB

f = 8.0 kHz, 12 kHz, 16 kHz

Figure 4. Metallic to longitudinal and

four-wire to longitudinal balance

TIPX

VTX

R_LT

C

1

<< 150 Ω, R_LT=R_LR=R_L/2=300Ω

ωC

V_TR

R_T

PBL 386 21/2

E_RX

V_Lo

R_LR

RINGX

RSN

R_T= 120 kΩ, R_RX= 60 kΩ

R_RX

Figure 5. Overload level, V_TXO, four-wire

transmit port

C

TIPX

VTX

R_L

1

<< R_L, R_L= 600 Ω

ωC

I_LDC

R_T

V_TXO

PBL 386 21/2

R_T= 120 kΩ, R_RX= 60 kΩ

E_L

RINGX

RSN

R_RX

4

PBL 386 21/2

Ref

fig

Parameter

Conditions

Min

Typ

Max

Unit

Four-wire to two-wire, g_4-2

6

relative to 0 dBm, 1.0 kHz. E_L=0 V

0.3 kHz < f < 3.4 kHz

f = 8 kHz, 12 kHz,

16 kHz

-0.2

-1.0

-2.0

0.1

0

dB

Four-wire to four-wire, g_4-4

6

relative to 0 dBm, 1.0 kHz, E_L=0 V

0.3 kHz < f < 3.4 kHz

-0.2

0.1

dB

Insertion loss

Two-wire to four-wire, G_2-4

0 dBm, 1.0 kHz, Note 5

V_TX

G_2-4= 20 • Log

; E_RX= 0

-0.2

0.2

dB

V_TR

PTG = AGND

-6.22

-6.02

-5.82

Four-wire to two-wire, G_4-2

6

0 dBm, 1.0 kHz, Note 6

V_TR

G_4-2= 20 • Log

; E_L= 0

-0.2

0.2

dB

E_RX

Gain tracking

Two-wire to four-wire

6

Ref. -10 dBm, 1.0 kHz, Note 7

-40 dBm to +0 dBm

-55 dBm to -40 dBm

Ref. -10 dBm, 1.0 kHz,

-40 dBm to +0 dBm

-0.1

-0.2

0.1

0.2

dB

Four-wire to two-wire

-0.1

-0.2

0.1

0.2

dB

-55 dBm to -40 dBm

Noise

Idle channel noise at two-wire

(TIPX-RINGX) or four-wire (VTX) output

C-message weighting

Psophometrical weighting

Note 8

12

-78

dBrnC

dBmp

Harmonic distortion

Two-wire to four-wire

Four-wire to two-wire

6

0 dBm

0.3 kHz < f < 3.4 kHz

-67

-50

dB

Battery feed characteristics

1 000

R_LC

Constant loop current, I_LProg

12

I_LProg

=

- 4.0 (mA)

- 4.2 (mA)

0.92 I_LProgI_LProg

0.95 I_LProgI_LProg

1.08 I_LProgmA

1.05 I_LProgmA

1 000

R_LC

I_LProg@ 30 mA

I_LProg@ 18 mA

1 000

R_LC

12

I_LProg

=

- 3.9 (mA)

0.94 I_LProgI_LProg

1.06 I_LProgmA

R_LCin kΩ

R_L= 0Ω

Open circuit state loop current, I _LOC

-100

0

100

µA

Figure 6.

Frequency response, insertion loss,

gain tracking.

C

TIPX

VTX

R_L

E_L

1

V_TR

I_LDC

R_T

PBL 386 21/2

<< R_L, R_L= 600 Ω

V_TX

E_RX

ωC

RINGX

RSN

R_T= 120 kΩ, R_RX= 60 kΩ

R_RX

5

PBL 386 21/2

Ref

fig

Parameter

Conditions

Min

Typ

Max

Unit

Loop current detector

Programmable threshold, I_LTh

500

0.85•I_LThI_LTh

1.15•I_LThmA

I_LTh

=

R_LD

R_LDin kΩ, I_LTh≥ 7 mA

Ground key detector

Ground key detector threshold

(I_TIPXand I_RINGXdifference to trigger ground key det.)

Ring trip comparator

10

16

22

20

200

-1

mA

Offset voltage, ∆V_DTDR

Input bias current, I_B

Source resistance, R_S= 0 Ω

I_B= (I_DT+ I_DR)/2

-20

-200

V_Bat+1

0

-20

mV

nA

V

Input common mode range, V_DT, V_DR

Ring relay driver

Saturation voltage, V_OL

Off state leakage current, I_Lk

Digital inputs (C1, C2, C3)

Input low voltage, V_IL

Input high voltage, V_IH

Input low current, I_IL

I_OL= 50 mA

V_OH= 12 V

0.2

0.5

10

V

µA

0

2.5

0.5

V_CC

-50

50

V

µA

V_IL= 0.5

V_IH= 2.5 V

Input high current, I_IH

Detector output (DET)

Output low voltage

I_OL= 0.5 mA

0.7

V

Internal pull-up resistor

Power dissipation (V_Bat= -48V, V_Bat2= -17V)

P₁

15

10

kΩ

Open circuit state, C1, C2, C3 = 0, 0, 0

Active state, C1, C2, C3 = 0, 1, 0

15

80

mW

P₂

Longitudinal current = 0 mA, I _L=0 mA (on-hook) 60

mW

P₃

P₄

R_L= 300 Ω (off-hook)

R_L= 500 Ω (off-hook)

290

145

Power supply currents (V_Bat= -48V)

V

_CCcurrent, I_CC

V_Batcurrent, I_Bat

_CCcurrent, I_CC

Open circuit state

1.2

-0.05

2.8

2.0

4.0

mA

-0.1

-1.5

V

Active state

On-hook, Long Current = 0 mA

V_Batcurrent, I_Bat

-1.0

Power supply rejection ratios

V

_CCto 2- or 4-wire port

_Batto 2- or 4-wire port

Active State

f = 1 kHz, V_n= 100mV

30

36

40

42

45

60

dB

V_Bat2to 2- or 4-wire port

Temperature guard

Junction threshold temperature, T_JG

Thermal resistance

145

°C

28-pin PLCC, θ_JP28plcc

24-pin SOIC, θ_JP24soic

24-pin SSOP, θ_JP24ssop

39

43

55

°C/W

6

PBL 386 21/2

4. The overload level can be adjusted with the resistor R _OV

for higher levels e.g. min 3.1 V_Peakand is specified at the

four-wire transmit port, VTX, with the signal source at the

two-wire port. Note that the gain from the two-wire port to

the four-wire transmit port is G_2-4S= 1 (or 0.5 see pin PTG)

5. Pin PTG = Open sets transmit gain to nom. 0.0dB

Pin PTG = AGND sets transmit gain to nom. -6.02 dB

Secondary protection resistors R _Fand resistors R_Pimpact

the insertion loss as explained in the text, section

Transmission. The specified insertion loss is for R_F= R_P= 0.

6. The specified insertion loss tolerance does not include

errors caused by external components.

Notes

1. The overload level can be adjusted with the resistor R_OVfor

higher levels e.g. min 3.1 V_Peakand is specified at the two-

wire port with the signal source at the four-wire receive

port.

2. The two-wire impedance is programmable by selection of

external component values according to:

Z_TRX= Z_T/|G_2-4Sα _RSN| where:

Z_TRX= impedance between the TIPX and RINGX

terminals

Z_T= programming network between the VTX and RSN

terminals

7. The level is specified at the two-wire port.

G_2-4S= transmit gain, nominally = 1 (or 0.5 see pin PTG)

8. The two-wire idle noise is specified with the port

terminated in 600 Ω (R_L) and with the four-wire receive

port grounded (E_RX= 0; see figure 6).

α

_RSN= receive current gain, nominally = 200 (current

defined as positive flowing into the receivesumm-

ing node, RSN, and when flowing from ring to tip).

The four-wire idle noise at VTX is specified with the two-

wire port terminated in 600 Ω (R _L). The noise

specification is referenced to a 600 Ω programmed two-

wire impedance level at VTX. The four-wire receive port is

grounded (E_RX= 0).

3. Higher return loss values can be achieved by adding a

reactive component to R_T, the two-wire terminating

impedance programming resistance, e.g. by dividing R _T

into two equal halves and connecting a capacitor from the

common point to ground.

7

PBL 386 21/2

1

2

24 VTX

PTG

RRLY

HP

23 AGND

3

22

21

20

19

RSN

REF

PLC

POV

5

6

25

24

23

22

21

20

19

RINGX

BGND

NC

RINGX

BGND

TIPX

4

REF

PLC

POV

PLD

VCC

NC

24-pin SOIC

and

24-pin SSOP

5

7

TIPX

VBAT

6

28-pin PLCC

8

VBAT

VBAT2

PSG

7

18 PLD

17 VCC

16 DET

VBAT2

9

8

10

11

PSG

NC

9

10

15

C1

LP

DT

DR

11

12

14 C2

13

C3

Figure 7. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view.

Pin Description

Refer to figure 7.

PLCC

Symbol

PTG

RRLY

HP

Description

1

2

3

4

5

Prog. Transmit Gain. Left open transmit gain = 0.0 dB, connected to AGND transmit gain = -6.02 dB.

Ring Relay driver output. The relay coil may be connected to maximum +14V.

Connection for High Pass filter capacitor, C_HP. Other end of C_HPconnects to TIPX.

No internal Connection.

NC

RINGX

The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage

protection components and ring relay (and optional test relay).

6

7

BGND

TIPX

Battery Ground, should be tied together with AGND.

The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage

protection components and ring relay (and optional test relay).

8

VBAT

VBAT2

PSG

Battery supply Voltage. Negative with respect to GND.

9

An optional second (2) Battery Voltage connects to this pin via an external diode.

10

Programmable Saturation Guard. The resistive part of the DC feed characteristic is not used for

PBL 386 21/2, RSG = 0 Ω.

11

12

13

NC

LP

DT

No internal Connection.

Connection for Low Pass filter capacitor, C_LP. Other end of C_LPconnects to VBAT.

Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic

level low, indicating off-hook condition. The external ring trip network connects to this input.

14

DR

Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic

level low, indicating off-hook condition. The external ring trip network connects to this input.

8

PBL 386 21/2

15

16

17

C3

C2

C1

C1, C2 and C3 are digital inputs (internal pull-up) controlling the SLIC operating states.

Refer to section "Operating states" for details.

}

18

DET

Detector output. Active low when indicating loop detection and ring trip, active high when indicating

ground key detection.

19

20

21

NC

No internal Connection.

VCC

PLD

+5 V power supply.

Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor

connected from this pin to AGND.

22

23

POV

PLC

Programmable Overhead Voltage. If pin is left open: The overhead voltage is internally set to min 1.0 V in

off-and on-hook. If a resistor is connected between this pin and AGND: the overhead voltage can be set

to higher values.

Prog. Line Current, the constant current part of the DC feed characteristic is programmed by a resistor

connected from this pin to AGND.

24

25

26

REF

NC

A Reference, 49.9 kΩ, resistor should be connected from this pin to AGND.

No internal Connection.

RSN

Receive Summing Node. 200 times the AC-current flowing into this pin equals the metallic (transversal)

AC-current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain

connect to the receive summing node. A resistor should be connected from this pin to AGND.

27

28

AGND

VTX

Analog Ground, should be tied together with BGND.

Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is

reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin

PTG). The two-wire impedance programming network connects between VTX and RSN.

SLIC Operating States

State

C3

C2

C1

SLIC operating state

Active detector

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Open circuit

Ringing state

Active state

Not applicable

Active state

-

Ring trip detector (active low)

Loop detector (active low)

-

Ground key detector (active high)

Loop detector (active low)

Ground key detector (active high)

Active reverse

Table 1. SLIC operating states.

9

PBL 386 21/2

For applications where

Z_T/(α_RSN·G_2-4S) + 2R_F+ 2R_Pis chosen to be

equaltoZ_LtheexpressionforG_4-2simplifies

to:

TIPX

TIP

I

+

L

R

F

P

Z

L

Z

+

TR

VTX

V

TR

R_HP

G

+

2-4S

Z_T

1

-

+

E

-

G₄₋₂= −

L

Z_RX2G_{2− 4S}

V

TX

R

F

P

-

I

L

RING

RINGX

-

Z

T

Four-Wire to Four-Wire Gain

From (1), (2) and (3) with E_L= 0:

Z

RX

RSN

+

V

RX

I

/α

RSN

V_TX

L

-

G₄₋₄

=

PBL 386 21/2

V_RX

Z_T

−

G_{2− 4S}(Z_L+ 2R_F+ 2R_P)

+ G_2−4S(Z_L+ 2R_F+ 2R_P)

Z_T

α_RSN

Z_RX

Figure 8. Simplified ac transmission circuit.

α_RSNis the receive summing node current

Functional Description

andApplicationsInforma-

tion

to metallic loop current gain = 200.

Hybrid Function

Note that the SLICs two-wire to four-wire

gain, G_2-4S, is user programmable between

two fix values. Refer to the datasheets for

The hybrid function can easily be

implemented utilizing the uncommitted

amplifier in conventional CODEC/filter

combinations. Please, refer to figure 9. Via

impedance Z_Ba current proportional to V_RX

is injected into the summing node of the

combination CODEC/filter amplifier. As

can be seen from the expression for the

four-wiretofour-wiregainavoltagepropor-

tional to V_RXis returned to V_TX. This voltage

is converted by R_TXto a current flowing into

the same summing node. These currents

can be made to cancel by letting:

values on G_2-4S

.

Transmission

General

Two-Wire Impedance

A simplified ac model of the transmission

circuitsisshowninfigure8. Circuitanalysis

yields:

To calculate Z_TR, the impedance presented

to the two-wire line by the SLIC including

the fuse and protection resistors R_Fand R_P

let:

V_TX

V_TR

=

+ I_L(2R_F+ 2R_P)

(1)

V_RX= 0.

G_{2− 4S}

From (1) and (2):

V_TXV_RX

I_L

+

=

(2)

(3)

Z_T

Z_RX

α_RSN

V_TXV_RX

Z_T

+

= 0(E_L= 0)

Z_TR

=

+ 2R_F+ 2R_P

R_TX

Z_B

α_RSNG_{2− 4S}

V_TR= E_L- I_L· Z_L

where:

Thefour-wiretofour-wiregain,G_4-4,includes

the required phase shift and thus the

balancenetworkZ_Bcanbecalculatedfrom:

Thus with Z_TR, α_RSN, G_2-4S,R_Pand R_Fknown:

Z_T= α_RSNG_{2− 4S}(Z_TR− 2R_F− 2R_P)

V_TXis a ground referenced version of the

acmetallicvoltagebetweentheTIPX

and RINGX terminals.

G_2-4Sis the programmable SLIC two-wire

to four-wire gain (transmit direction).

See note below.

V

RX

Z

= −R

=

B

TX

V

TX

Two-Wire to Four-Wire Gain

Z

T

From (1) and (2) with V_RX= 0:

+ G

(Z + 2R + 2R )

2−4S L F P

Z

α

RX

RSN

G

R

TX

Z

(Z + 2R + 2R )

L F P

T

2−4S

V_TX

V_TR

Z_T/ α_RSN

G_{2− 4}

=

V_TRis the ac metallic voltage between tip

and ring.

Z_T

α_RSNG_{2− 4S}

+ 2R_F+ 2R_P

When choosing R_TX, make sure the output

load of the VTX terminal is >20 kΩ.

E_L

is the line open circuit ac metallic

voltage.

If calculation of the Z_Bformula above

yields a balance network containing an

inductor, an alternate method is

recommended. Contact Ericsson Micro-

electronics for assistance.

The PBL 386 21/2 SLIC may also be

usedtogetherwithprogrammableCODEC/

filters. The programmable CODEC/filter

allows for system controller adjustment of

Four-Wire to Two-Wire Gain

I_L

is the ac metallic current.

is a fuse resistor.

is part of the SLIC protection.

is the line impedance.

determines the SLIC TIPX to RINGX

impedance at voice frequencies.

From (1), (2) and (3) with E_L= 0:

R_F

R_P

Z_L

Z_T

V_TR

G₄₋₂

=

V_RX

Z_T

−

Z_L

Z_T

α_RSN

Z_RX

+ G_{2− 4S}(Z_L+ 2R_F+ 2R_P)

Z_RXcontrols four- to two-wire gain.

V_RXis the analog ground referenced

receive signal.

10

PBL 386 21/2

hybrid balance to accommodate different

line impedances without change of

hardware. In addition, the transmit and

receivegainmaybeadjusted.Please,refer

to the programmable CODEC/filter data

sheets for design information.

R

FB

R

TX

VTX

Longitudinal Impedance

V

T

PBL

38621/2

A feed back loop counteracts longitudinal

voltages at the two-wire port by injecting

longitudinal currents in opposing phase.

Thus longitudinal disturbances will

appear as longitudinal currents and the

TIPX and RINGX terminals will experience

very small longitudinal voltage excursions,

leaving metallic voltages well within the

SLIC common mode range.

Z

Combination

CODEC/Filter

T

B

Z

RX

V

RX

RSN

Figure 9. Hybrid function.

recommended to position the 3 dB break

The SLIC longitudinal impedance per

wire, Z_LoTand Z_LoR, appears as typically

20Ω to longitudinal disturbances. It should

be noted that longitudinal currents may

exceed the dc loop current without distur-

bing the vf transmission.

point of this filter between 30 and 80 Hz to Battery Feed

get a faster response for the dc steps that

The PBL 386 21/2 SLIC emulate a battery

characteristic with current limitation

adjustable.Theopenloopvoltagemeasured

between the TIPX and RINGX terminals is

tracking the battery voltage V_Bat. The

signalling headroom, or overhead voltage

may occur at DTMF signalling.

Capacitor C_LP

Capacitors C_TCand C_RC

ThecapacitorC_LP,whichconnectsbetween

the terminals CLP and VBAT, positions the

high end frequency break point of the low

pass filter in the dc loop in the SLIC. C_LP

together with C_HPand Z_T(see section Two-

Wire Impedance) forms the total two wire

output impedance of the SLIC. The choise

of these programmable components have

an influence on the power supply rejection

ratio (PSRR) from VBAT to the two wire

side at sub-audio frequencies. At these

frequencies capacitor C_LPalso influences

the transversal to longitudinal balance in

theSLIC.Table1suggestsasuitablevalue

on C_LP. The typical value of the transversal

to longitudinal balance (T-L bal.) at 200Hz

is given in table 1 for the chosen value on

C_LP.

The capacitors designated C_TCand C_RC

in figure 11, connected between TIPX

and ground as well as between RINGX

and ground, can be used for RFI filtering.

The recommended value for C_TCand C_RC

is 2200 pF. Higher capacitance values

may be used, but care must be taken to

prevent degradation of either longitudinal

balance or return loss. C_TCand C_RC

contribute to a metallic impedance of

1/(π·f·C_TC) = 1/(π·f·C_RC), a TIPX to ground

impedance of 1/(2·π·f·C_TC) and a RINGX

to ground impedance of 1/(2·π·f·C_RC).

V_TRO, is programmable with a resistor R_OV

connected between terminal POV on the

SLIC and ground. Please refer to section

“Programmable overhead voltage(POV)”.

Thebatteryvoltageoverhead,V_OH,depends

ontheprogrammedsignaloverheadvoltage

V

_TRO. V_OHdefines the TIP to RING voltage

at open loop conditions according to

V_TR(at I_L= 0 mA) = |V_Bat| - V_OH

Refer to table 2 for the typical value on

V_OH

.

SLIC

V_OH(typ) [V]

AC - DC Separation Capacitor, C_HP

The high pass filter capacitor connected

between terminals HP and TIPX provides

the separation of the ac signal from the

dc part. C_HPpositions the low end

frequency response break point of the ac

loop in the SLIC. Refer to table 1 for a

recommended value of C_HP.

Example: A C_HPvalue of 47 nF will

position the low end frequency response

3dB break point of the ac loop at 5.6 Hz

(f_3dB) according to f_3dB= 1/(2 π R_HPC_HP)

where R_HP= 600 kΩ.

PBL 386 21/2

2.5 +V_TROprog

Table 2. Battery overhead.

T-L bal.

The current limit (reference A - C in figure

12) is adjusted by connecting a resistor,

R_LC, between terminal PLC and ground

according to the equation:

R_FeedR_SG

C_LP@ 200Hz C_HP

[Ω]

[kΩ]

[nF]

[dB]

[nF]

2·25

0

150

-46

47

1000

I_LProg+ 4

Table 1. R_SG, C_LPand C_HPvalues for cons-

tant current feeding characteristics.

R_LC

=

where R_LCis in kΩ for I_LProgin mA.

For values outside table 1, please contact

Ericsson Microelectronics for assistance.

High-Pass Transmit Filter

The capacitor C_TXin figure 11 connected

between the VTX output and the

CODEC/filter forms, together with R_TXand/

or the input impedance of a programmable

CODEC/filter, a high-pass RC filter. It is

A second, lower battery voltage may be

connected to the device at terminal VBAT2

to reduce short loop power dissipation.

The SLIC automatically switches between

the two battery supply voltages without

need for external control. The silent battery

11

PBL 386 21/2

switching occurs when the line voltage

passes the value

Loop Monitoring Functions

Programmable overhead voltage(POV)

The loop current, ground key and ring trip

detectorsreporttheirstatusthroughacom-

mon output, DET. The detector to be

connected to DET is selected via the three

bit wide control interface C1, C2 and C3.

Please refer to section Control Inputs for a

description of the control interface.

With the POV function the overhead

voltage can be increased.

|VB2| - 40 · I_L- V_TRO= 3.6

For correct functionality it is important to

connect the terminal VBAT2 to the second

powersupplyviathediodeD_VB2infigure11.

An optional diode D_BBconnected between

terminalVBandtheVB2powersupply,see

figure 11, will make sure that the SLIC

continues to work on the second battery

even if the first battery voltage disappears.

If a second battery voltage is not used,

VBAT2 is connected to VBAT on the SLIC

and C_VB2, D_BBand D_VB2are removed.

If the POV pin is left open the overhead

voltage is internally set to 1.1 V_Peak.The

overhead voltage is equal in on-hook and

off-hook. If a resistor R_OVis connected

between the POV pin and AGND, the

overhead voltage can be set to higher

values, typical values can be seen in

figure 10. The R_OVand corresponding

V_TRO(signal headroom) are typical values

for THD <1% and the signal frequency

1000Hz.

Observe that the 4-wire output terminal V_TX

cannothandlemorethan3.2V_Peak.Soifthe

gain 2-wire to 4-wire is 0dB, 3.2 V_Peakis

maximum also for the 2-wire side. Signal

levels between 3.2 and 6.4 V_Peakon the

2-wire side can be handled with the PTG

shorted so that the gain G_2-4Sbecome

-6.02dB. Please note that the 2-wire

impedance, R_Rand the 4-wire to 4-wire

gain has to be recalculated if the PTG is

shorted.

Loop Current Detector

The loop current detector is indicating that

the telephone is off hook and that current is

flowing in the loop by putting the output

DET to a logical low level when selected.

The loop current threshold value, I_LTh, at

which the loop current detector changes

state is programmable by selecting the

valueofresistorR_LD.R_LDconnectsbetween

pin PLD and ground and is calculated

according to

CODEC Receive Interface

The PBL 386 21/2 SLIC have got a

completely new receive interface at the

four wire side which makes it possible to

reduce the number of capacitors in the

applications and to fit both single and dual

battery feed CODECs. The RSN terminal,

connecting to the CODEC receive output

viatheresistorR_RX,isdcbiasedwith+1.25V.

This makes it possible to compensate for

currents floating due to dc voltage

differences between RSN and the CODEC

outputwithoutusinganycapacitors. Thisis

done by connecting a resistor R_Rbetween

the RSN terminal and ground. With current

directions defined as in figure 13, current

summation gives:

500

R_LD

=

I_LTh

The current detector is internally filtered

and is not influenced by the ac signal at the

two wire side.

Please note that the maximum signal

current at the 2-wire side can not be

greater than 9 mA.

Ground Key Detector

How to use POV:

The ground key detector is indicating when

thegroundkeyispressed(active)byputting

the output pin DET to a logical high level

when selected. The ground key detector

circuit senses the difference in TIPX and

RINGX currents. When the current at the

RINGX side exceeds the current at the

TIPX side with the threshold value the

detector is triggered. For threshold current

values, please refer to the datasheet.

1.

Decide what overhead

voltage(V_TRO) is needed. The POV

function is only needed if the

overhead voltage exceeds 1.1 V_Peak

In figure 10 the corresponding R_OV

for the decided V_TROcan be found.

If the overhead voltage exceeds

3.2 V_Peak, the G_2-4Sgain has to be

changed to -6.02dB by connecting

the PTG pin to AGND. Please note

that the 2-wire impedance, R_Rand

the 4-wire to 4-wire gain has to be

recalculated.

−I_RSN= I_RT+ I_RRX+ I_RR

=

2.

3.

1,25 1,25 − V_CODEC

1,25

R_R

+

R_T

R_RX

whereV_CODECisthereferencevoltageofthe

CODEC at the receive output.

From this equation the resistor R_Rcan be

calculated as

Ring Trip Detector

Ring trip detection is accomplished by

connecting an external network to a

comparator in the SLIC with inputs DT and

DR. The ringing source can be balanced or

unbalanced superimposed on V_Bor GND.

The unbalanced ringing source may be

applied to either the ring lead or the tip lead

with return via the other wire. A ring relay

drivenbytheSLICringrelaydriverconnects

the ringing source to tip and ring.

The ring trip function is based on a polarity

change at the comparator input when the

line goes off-hook. In the on-hook state no

dc current flows through the loop and the

voltage at comparator input DT is more

positivethanthevoltageatinputDR. When

the line goes off-hook, while the ring relay

1,25

R_R

=

1,25 − V_CODEC

1,25

R_T

Analog Temperature Guard

−I_RSN

−

R_RX

The widely varying environmental

conditions in which SLICs operate may

lead to the chip temperature limitations

being exceeded. The PBL 386 21/2 SLIC

reduce the dc line current when the chip

temperaturereachesapproximately145°C

and increases it again automatically when

the temperature drops. Accordingly trans-

mission is not lost under high ambient

temperature conditions.

For the value on I_RSN, see table 3.

The resistor R_Rhas no influence on the ac

transmission.

SLIC

I_RSN[µA]

PBL 386 21/2

-55

Table3. TheSLICinternalbiascurrentwith

the direction of the current defined as

positivewhenfloatingintotheterminalRSN.

The detector output, DET, is forced to a

logic low level when the temperature guard

is active.

12

PBL 386 21/2

7

6

5

4

3

2

1

0

10

20

30

40

50

60

R_OV(kΩ)

Figure 10. Programmable overhead voltage (POV). R_L= 600 Ω or ∞.

is energized, dc current flows and the

comparator input voltage reverses polar-

ity.

Ringing State

Relay driver

Theringrelaydriverandtheringtripdetector

are activated and the ring trip detector is

indicating off hook with a logic low level at

the detector output.

As the SLIC do not have any stand by state

the SLIC will remain in the active normal

state.

ThePBL38621/2SLIC incorporatesaring

relay driver designed as open collector

(npn) with a current sinking capability of

50 mA. The drive transistor emitter is

connected to BGND. The relay driver has

an internal zener diode clamp for inductive

kick-back voltages.Care must be taken

when using the relay driver together with

relays that have high impedance.

Figure 11 gives an example of a ring trip

detection network. This network is

applicable, when the ring voltage is

superimposed on V_Band is injected on the

ringleadofthetwo-wireport.Thedcvoltage

across sense resistor R_RTis monitored by

the ring trip comparator input DT and DR

via the network R₁, R₂, R₃, R₄, C₁and C₂.

With the line on-hook (no dc current) DT is

more positive than DR and the DET output

will report logic level high, i.e. the detector

is not tripped. When the line goes off-hook,

while ringing, a dc current will flow through

the loop including sense resistor R_RTand

will cause input DT to become more

negative than input DR. This changes out-

put DET to logic level low, i.e. tripped

detector condition. The system controller

(or line card processor) responds by de-

energizing the ring relay, i.e. ring trip.

Complete filtering of the 20 Hz ac

component at terminal DT and DR is not

necessary. A toggling DET output can be

examined by a software routine to deter-

mine the duty cycle. When the DET output

is at logic level low for more than half the

time, off-hook condition is indicated.

Active States

TIPX is the terminal closest to ground and

sources loop current while RINGX is the

more negative terminal and sinks loop

current. Vf signal transmission is normal.

Theloopcurrentorthegroundkeydetector

is activated. The loop current detector is

indicatingoffhookwithalogiclowleveland

the ground key detector is indicating active

groundkeywithalogichighlevelpresentat

the detector output.

Control Inputs

The PBL 386 21/2 SLIC has three digital

control inputs, C1, C2 and C3.

AdecoderintheSLICinterpretsthecontrol

inputconditionandsetsupthecommanded

operating state.

C1 to C3 are internal pull-up inputs.

Open Circuit State

In the Open Circuit State the TIPX and

RINGXlinedriveamplifiersaswellasother

circuit blocks are powered down. This

causes the SLIC to present a high

impedance to the line. Power dissipation is

at a minimum and no detectors are active.

13

PBL 386 21/2

R_FB

PBL 386 21/2

C_TX

R_TX

K_R

-

PTG

VTX

-

0

+

R_T

RRLY

HP

AGND

RSN

NC

R_B

+12 V /+5V

R_RX

0

C_GG

D_HP

C_HP

NC

CODEC/

Filter

R_F2

R_R

R_P2

RING

RINGX

BGND

TIPX

VBAT

VBAT2

PSG

NC

REF

PLC

POV

PLD

VCC

NC

R_REF

R_LC

R_OV

R_LD

C_RC

C_TC

VB

OVP

TIP

R_F1

R_P1

PBL 386 21/2

D_VB2

VB2

VB

VCC

D_BB

D_VB

R_SG

C_VB2

C_VCC

DET

C1

C_LP

E_RG

C_VB

R₁

LP

R_RT

DT

C2

R₂

DR

C3

C₁

C₂

SYSTEM CONTROL

INTERFACE

R₃

R₄

SLIC No. 2 etc.

RESISTORS (Values according to IEC E96 series):

CAPACITORS (Values according to IEC E96 series):

OVP:

R_SG

R_LD

R_OV

R_LC

R_REF

R_R

= 0 Ω

1% 1/10 W

C_VB

= 100 nF

= 150 nF

= 100 nF

= 2.2 nF

= 47 nF

100 V 10%

10 V 10%

100 V 10%

10 V 10%

100 V 10%

63 V 10%

Secondary protection (e. g. Power Innovations

TISPPBL2). The ground terminals of the

secondary protection should be connected to the

common ground on the Printed Board Assembly

with a track as short and wide as possible,

preferable a groundplane.

= 49.9 kΩ 1% 1/10 W

= User programmable

= 38.3 kΩ 1% 1/10 W

= 49.9 kΩ 1% 1/10 W

= 64.9 kΩ 1% 1/10 W

= 105 kΩ 1% 1/10 W

= 24.9 kΩ 1% 1/10 W

= 22.1 kΩ 1% 1/10 W

= 52.3 kΩ 1% 1/10 W

Depending on CODEC/filter

= 604 kΩ 1% 1/10 W

= 249 kΩ 1% 1/10 W

= 280 kΩ 1% 1/10 W

C_VB2

C_VCC

C_TC

C_RC

C_HP

C_LP

R_T

= 150 nF

= 100 nF

= 220 nF

= 330 nF

R_TX

R_B

C_TX

NOTES:

C_GG

C₁

1 R_P1and R_P2may be omitted if D_VBis in place

R_RX

R_FB

R₁

2 It is required to connect D_HPbetween terminal HP

and ground if C_HP> 47 nF

C₂

DIODES:

D_VB

R₂

= 1N4448

R₃

D_VB2

D_BB

R₄

R_RT

= 330 Ω

5% 2 W

D_HP

= 1N4448 (Note 2)

R

, R_P2≥ 10 Ω

1% 1/10 W (Note 1)

R^P_F1¹, R_F2= Line resistor, 40 Ω 1%

Figure 11. single-channel subscriber line interface with PBL 386 21/2 and combination CODEC/filter.

Overvoltage Protection

The PBL 386 21/2 SLIC must be protected As the protection voltage will track the The fuse resistors R_Fserve the dual

against overvoltages on the telephone line negative supply voltage the overvoltage purposes of being non- destructive energy

caused by lightning, ac power contact and

induction.RefertoMaximumRatings,TIPX

and RINGX terminals, for maximum

allowablecontinuousandtransientcurrents

that may be applied to the SLIC.

stress on the SLIC is minimized.

Positive overvoltages are clamped to gro- andofbeingfuses,whenthelineisexposed

und by a diode. Negative overvoltages are to a power cross.

initially clamped close to the SLIC negative If a PTC is choosen for R_F, note that it is

supply rail voltage and the protector will important to always use PTC´s in series

crowbar into a low voltage on-state with resistors not sensitive to temperature,

dissipators, when transients are clamped

Secondary Protection

condition, by firing an internal thyristor.

asthePTCwillactasacapacitanceforfast

Agatedecouplingcapacitor,C_GG,isneeded transients and therefore will not protect the

to carry enough charge to supply a high SLIC.

enough current to quickly turn on the

thyristorintheprotector.C_GGshallbeplaced

close to the overvoltage protection device.

Thecircuitshowninfigure11utilizesseries

resistors together with a programmable

overvoltage protector (e.g Power

Innovations TISPPBL2), serving as a

secondary protection.

Without the capacitor even the low

The TISPPBL2 is a dual forward-conduc-

ting buffered p-gate overvoltage protector. inductanceinthetracktotheV_Batsupplywill

Theprotectorgatereferencestheprotection limit the current and delay the activation of

(clamping) voltage to negative supply

voltage (i.e the battery voltage,V_B).

the thyristor clamp.

14

PBL 386 21/2

DC characteristics

A

B

C

D

E

V_TR[V]

A:

B:

C:

I_L(@V_TR=0V)=I_LProg

Constant current

D:

E:

R_Feed=2·25 Ω

V_TROpen=|V_Bat|-V_OH

10³

R_LC

I

_LConst(typ) = I_LProg

=

- 4·10^-3

V_TR=|V_Bat|-V_OH-50·I_LProg

Figure 12. Battery feed characteristics (without the protection resistors on the line).

VTX

PBL386 21/2

CODEC

DC-GND

R_T

I

I_RT

I_RSN

I_RRX

R_RX

_

+

RSN

I_RR

+1.25 V

U_REFcodec

R_R

Figure 13. CODEC receive interface.

15

PBL 386 21/2

Power-up Sequence

Nospecialpower-upsequenceisnecessary

exceptthatgroundhastobepresentbefore

all other power supply voltages.

Printed Circuit Board Layout

Care in PCB layout is essential for proper

function. The components connecting to

the RSN input should be placed in close

proximity to that pin, such that no

interference is injected into the RSN pin.

Ground plane surrounding the RSN pin is

advisable.

Analog ground (AGND) should be

connected to battery ground (BGND) on

the PCB in one point.The capacitors for the

battery should be connected with short

wide leads of the same length.

Ordering Information

Package

Temp. Range

Part No.

PBL 386 21/2SHT

PBL 386 21/2SOS

PBL 386 21/2SOT

24 pin SSOP Tape & Reel -40° - +85° C

24 pin SOIC Tube

24 pin SOIC Tape & Reel

28 pin PLCC Tube

-40° - +85° C

-40° - +85° C PBL 386 21/2QNS

28 pin PLCC Tape & Reel -40° - +85° C

PBL 386 21/2QNT

Information given in this data sheet is believed to be

accurate and reliable. However no responsibility is

assumed for the consequences of its use nor for any

infringement of patents or other rights of third parties

which may result from its use. No license is granted

by implication or otherwise under any patent or patent

rights of Ericsson Microelectronics AB. These

products are sold only according to Ericsson

Microelectronics AB' general conditions of sale,

unless otherwise confirmed in writing.

Specifications subject to change without

notice.

1522-PBL 386 21/2 Uen Rev. A

This product is an original Ericsson product

protected by US, European and other

patents.

Ericsson Microelectronics AB

SE-164 81 Kista-Stockholm, Sweden

Telephone: +46 8 757 50 00

16


型号：	PBL38621/2QNT
厂家：	Rochester Electronics
描述：	TELECOM-SLIC, PQCC28, PLASTIC, LCC-28 电信电信集成电路
文件：	总17页 (文件大小：813K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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