PBL38621/2SOT [INTEL]
SLIC, Bipolar, PDSO24, SOIC-24;型号: | PBL38621/2SOT |
厂家: | INTEL |
描述: | SLIC, Bipolar, PDSO24, SOIC-24 电信 光电二极管 电信集成电路 |
文件: | 总16页 (文件大小:130K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
June 1999
PBL 386 21/2
Subscriber Line
Interface Circuit
Description
Key Features
• 24-pin SSOP package
The PBL 386 21/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in DAML, FITL and other telecommunications equipment. The PBL
386 21/2 has been optimized for low total line interface cost and a high degree of
flexibility in different applications.
The PBL 386 21/2 has constant current feed, programmable to max. 30 mA.
A second lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 21/2 is compatible with loop start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
the two-wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 386 21/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC.
• High and low battery with automatic
switching
• 60 mW on-hook power dissipation in
active state
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
• Only +5 V feed in addition to battery
• Selectable transmit gain (1x or 0.5x)
• No power-up sequence
• 44V open loop voltage @ -48V battery
feed
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Polarity reversal
• Integrated Ring Relay driver
• Ground key detector
• Programmable signal headroom
• -40 °C to +85 °C ambient temperature
range
Ring Relay
RRLY
Driver
DT
C1
Ring Trip
Comparator
DR
TIPX
RINGX
HP
C2
Input
Decoder
and
C3
Ground Key
Detector
Control
DET
POV
PSG
PLC
Line Feed
Controller
and
Longitudinal
Signal
VCC
Two-wire
Interface
Suppression
LP
PBL
PBL 386 21/2
386 21/2
VBAT2
VBAT
PLD
REF
Off-hook
Detector
PBL 386 21/2
AGND
BGND
VTX
RSN
VF Signal
Transmission
PTG
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
Figure 1. Block diagram.
1
PBL 386 21/2
Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Temperature, Humidity
Storage temperature range
Operating temperature range
Operating junction temperature range, Note 1
TStg
TAmb
TJ
-55
-40
-40
+150
+110
+140
°C
°C
°C
Power supply, -40 °C ≤ TAmb ≤ +85 °C
V
CC with respect to A/BGND
VBat2 with respect to A/BGND
Bat with respect to A/BGND, continuous
VCC
VBat2
VBat
VBat
-0.4
VBat
-75
-80
6.5
0.4
0.4
0.4
V
V
V
V
V
VBat with respect to A/BGND, 10 ms
Power dissipation
Continuous power dissipation at TAmb ≤ +85 °C
PD
VG
1.5
0,3
W
V
Ground
Voltage between AGND and BGND
Relay Driver
-0,3
Ring relay supply voltage
BGND+14 V
Ring trip comparator
Input voltage
Input current
VDT, VDR
IDT, IDR
VBat
-5
AGND
5
V
mA
Digital inputs, outputs (C1, C2, C3, DET)
Input voltage
VID
-0.4
-0.4
VCC
VCC
V
V
Output voltage
VOD
TIPX and RINGX terminals, -40°C < TAmb < +85°C, VBat = -50V
Maximum supplied TIPX or RINGX current
ITIPX, IRINGX -100
+100
2
mA
V
TIPX or RINGX voltage, continuous (referenced to AGND), Note 2
TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2
TIPX or RINGX, pulse < 1 µs, tRep > 10 s, Note 2
VTA, VRA
VTA, VRA
VTA, VRA
VTA, VRA
-80
VBat -10
VBat -25
VBat -35
5
V
10
15
V
TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3
V
Recommended Operating Condition
Parameter
Symbol
Min
Max
Unit
Ambient temperature
TAmb
VCC
VBat
VG
-40
4.75
-58
+85
5.25
-8
°C
V
V
VCC with respect to AGND
VBat with respect to AGND
AGND with respect to BGND
-100
100
mV
Notes
1. The circuit includes thermal protection. Operation at or above 140°C junction temperature may degrade device reliability.
2. With the diodes DVB and DVB2 included, see figure 12.
3. RF1 and RF2 ≥ 20 Ω is also required. Pulse is applied to TIP and RING outside RF1 and RF2.
2
PBL 386 21/2
Electrical Characteristics
-40 °C ≤ TAmb ≤ +85 °C, PTG = open (see pin description), VCC = +5V ±5 %, VBat = -58V to -40V, VBat2 = -17V, RLC=38.3 kΩ,
IL = 22 mA. RL = 600 Ω, RF1= RF2= RP1= RP2=0, RRef = 49.9 kΩ, CHP = 47 nF, CLP=0.15 µF, RT = 120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ,
RR = 52.3 kΩ ROV = ∞ unless otherwise specified. Current definition: current is positive if flowing into a pin.
Ref
Parameter
fig
Conditions
Min
Typ
Max
Unit
Two-wire port
Overload level, VTRO
2
Active state
1% THD
1.0
1.0
VPeak
VPeak
On-Hook, ILdc < 5mA
Note 1, ROV = ∞
Input impedance, ZTR
Longitudinal impedance, ZLOT, ZLOR
Longitudinal current limit, ILOT, ILOR
Note 2
0 < f < 100 Hz
active state
ZT/200
20
35
Ω/wire
10
mArms /wire
Longitudinal to metallic balance, BLM
IEEE standard 455-1985, ZTRX=736Ω
0.2 kHz < f < 1.0 kHz
53
53
dB
dB
dB
1.0 kHz < f < 3.4 kHz
Reverse polarity 0.2 kHz < f < 3.4 kHz 53
Longitudinal to metallic balance, BLME
ELo
3
3
4
0.2 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz
Reverse polarity 0.2 kHz < f < 3.4 kHz 53
53
53
75
70
68
dB
dB
dB
BLME =20 • Log
VTR
Longitudinal to four-wire balance, BLFE
0.2 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz
Reverse polarity 0.2 kHz < f < 3.4 kHz 53
53
53
75
70
68
dB
dB
dB
ELo
VTX
BLFE = 20 • Log
Metallic to longitudinal balance, BMLE
VTR
0.2 kHz < f < 3.4 kHz
40
50
dB
BMLE = 20 •
; ERX = 0
Log
VLo
C
TIPX
VTX
Figure 2. Overload level, VTRO, two-wire
port
RL
VTRO
ILDC
RT
PBL 386 21/2
ERX
1
<< RL, RL= 600 Ω
ωC
RINGX
RSN
RRX
RT = 120 kΩ, RRX = 60 kΩ
VTX
TIPX
Figure 3. Longitudinal to metallic (BLME
)
and Longitudinal to four-wire (BLFE
balance
)
ELo
RLT
C
RT
VTR
PBL 386 21/2
VTX
1
ωC
RLR
<< 150 Ω, RLR =RLT =RL /2=300Ω
RINGX
RSN
RRX
RT = 120 kΩ, RRX = 60 kΩ
3
PBL 386 21/2
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
Four-wire to longitudinal balance, BFLE
4
0.2 kHz < f < 4.0 kHz
40
50
dB
ERX
BFLE = 20 • Log
VLo
Two-wire return loss, r
|ZTR + ZL|
r = 20 • Log
|ZTR - ZL|
0.2 kHz < f < 1.0 kHz
1.0 kHz < f < 3.4 kHz, Note 3
active, IL = 0 mA
active, IL = 0 mA
active, IL = 0 mA
27
20
35
22
- 1.1
VBat +2.5
VBat +3.6
dB
dB
V
V
V
TIPX idle voltage, VTi
RINGX idle voltage, VRi
VTR
Four-wire transmit port (VTX)
Overload level, VTXO
5
Load impedance > 20 kΩ,
1.0
VPeak
1% THD, Note 4
On-hook, IL < 5mA
Output offset voltage ∆VTX
Output impedance, zTX
1.0
-100
VPeak
mV
Ω
0
15
100
50
0.2 kHz < f < 3.4 kHz
Four-wire receive port (RSN)
Receive summing node (RSN) DC voltage
Receive summing node (RSN) impedance
Receive summing node (RSN)
current (IRSN) to metallic loop current (IL)
gain,αRSN
I
RSN = -55 µA
1.15
1.25
8
1.35
20
V
Ω
0.2 kHz < f < 3.4 kHz
0.3 kHz < f < 3.4 kHz
200
ratio
Frequency response
Two-wire to four-wire, g2-4
6
relative to 0 dBm, 1.0 kHz. ERX = 0 V
0.3 kHz < f < 3.4 kHz
-0.20
-1.0
0.10
0.1
dB
dB
f = 8.0 kHz, 12 kHz, 16 kHz
Figure 4. Metallic to longitudinal and
four-wire to longitudinal balance
TIPX
VTX
RLT
C
1
<< 150 Ω, RLT =RLR =RL /2=300Ω
ωC
VTR
RT
PBL 386 21/2
ERX
VLo
RLR
RINGX
RSN
RT = 120 kΩ, RRX = 60 kΩ
RRX
Figure 5. Overload level, VTXO, four-wire
transmit port
C
TIPX
VTX
RL
1
<< RL, RL = 600 Ω
ωC
ILDC
RT
VTXO
PBL 386 21/2
RT = 120 kΩ, RRX = 60 kΩ
EL
RINGX
RSN
RRX
4
PBL 386 21/2
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
Four-wire to two-wire, g4-2
6
relative to 0 dBm, 1.0 kHz. EL=0 V
0.3 kHz < f < 3.4 kHz
f = 8 kHz, 12 kHz,
16 kHz
-0.2
-1.0
-2.0
0.1
0
0
dB
dB
dB
Four-wire to four-wire, g4-4
6
6
relative to 0 dBm, 1.0 kHz, EL=0 V
0.3 kHz < f < 3.4 kHz
-0.2
0.1
dB
Insertion loss
Two-wire to four-wire, G2-4
0 dBm, 1.0 kHz, Note 5
VTX
G2-4 = 20 • Log
; ERX = 0
-0.2
0.2
dB
dB
VTR
PTG = AGND
-6.22
-6.02
-5.82
Four-wire to two-wire, G4-2
6
0 dBm, 1.0 kHz, Note 6
VTR
G4-2 = 20 • Log
; EL = 0
-0.2
0.2
dB
ERX
Gain tracking
Two-wire to four-wire
6
6
Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to +0 dBm
-55 dBm to -40 dBm
Ref. -10 dBm, 1.0 kHz,
-40 dBm to +0 dBm
-0.1
-0.2
0.1
0.2
dB
dB
Four-wire to two-wire
-0.1
-0.2
0.1
0.2
dB
dB
-55 dBm to -40 dBm
Noise
Idle channel noise at two-wire
(TIPX-RINGX) or four-wire (VTX) output
C-message weighting
Psophometrical weighting
Note 8
12
-78
dBrnC
dBmp
Harmonic distortion
Two-wire to four-wire
Four-wire to two-wire
6
0 dBm
0.3 kHz < f < 3.4 kHz
-67
-67
-50
-50
dB
dB
Battery feed characteristics
1 000
RLC
Constant loop current, ILProg
12
12
ILProg
ILProg
=
=
- 4.0 (mA)
- 4.2 (mA)
0.92 ILProg ILProg
0.95 ILProg ILProg
1.08 ILProg mA
1.05 ILProg mA
1 000
RLC
ILProg @ 30 mA
ILProg @ 18 mA
1 000
RLC
12
ILProg
=
- 3.9 (mA)
0.94 ILProg ILProg
1.06 ILProg mA
RLC in kΩ
RL = 0Ω
Open circuit state loop current, I LOC
-100
0
100
µA
Figure 6.
Frequency response, insertion loss,
gain tracking.
C
TIPX
VTX
RL
EL
1
VTR
ILDC
RT
PBL 386 21/2
<< RL, RL = 600 Ω
VTX
ERX
ωC
RINGX
RSN
RT = 120 kΩ, RRX = 60 kΩ
RRX
5
PBL 386 21/2
Ref
fig
Parameter
Conditions
Min
Typ
Max
Unit
Loop current detector
Programmable threshold, ILTh
500
0.85•ILTh ILTh
1.15•ILTh mA
ILTh
=
RLD
RLD in kΩ, ILTh ≥ 7 mA
Ground key detector
Ground key detector threshold
(ITIPX and IRINGX difference to trigger ground key det.)
Ring trip comparator
10
16
22
20
200
-1
mA
Offset voltage, ∆VDTDR
Input bias current, IB
Source resistance, RS = 0 Ω
IB = (IDT + IDR)/2
-20
-200
VBat+1
0
-20
mV
nA
V
Input common mode range, VDT, VDR
Ring relay driver
Saturation voltage, VOL
Off state leakage current, ILk
Digital inputs (C1, C2, C3)
Input low voltage, VIL
Input high voltage, VIH
Input low current, IIL
IOL = 50 mA
VOH = 12 V
0.2
0.5
10
V
µA
0
2.5
0.5
VCC
-50
50
V
V
µA
µA
VIL = 0.5
VIH = 2.5 V
Input high current, IIH
Detector output (DET)
Output low voltage
IOL = 0.5 mA
0.7
V
Internal pull-up resistor
Power dissipation (VBat = -48V, VBat2 = -17V)
P1
15
10
kΩ
Open circuit state, C1, C2, C3 = 0, 0, 0
Active state, C1, C2, C3 = 0, 1, 0
15
80
mW
P2
Longitudinal current = 0 mA, I L=0 mA (on-hook) 60
mW
mW
mW
P3
P4
RL = 300 Ω (off-hook)
RL = 500 Ω (off-hook)
290
145
Power supply currents (VBat = -48V)
V
CC current, ICC
VBat current, IBat
CC current, ICC
Open circuit state
1.2
-0.05
2.8
2.0
4.0
mA
mA
mA
mA
-0.1
-1.5
V
Active state
On-hook, Long Current = 0 mA
VBat current, IBat
-1.0
Power supply rejection ratios
V
V
CC to 2- or 4-wire port
Bat to 2- or 4-wire port
Active State
f = 1 kHz, Vn = 100mV
30
36
40
42
45
60
dB
dB
dB
VBat2 to 2- or 4-wire port
Temperature guard
Junction threshold temperature, TJG
Thermal resistance
145
°C
28-pin PLCC, θJP28plcc
24-pin SOIC, θJP24soic
24-pin SSOP, θJP24ssop
39
43
55
°C/W
°C/W
°C/W
6
PBL 386 21/2
4. The overload level can be adjusted with the resistor R OV
for higher levels e.g. min 3.1 VPeak and is specified at the
four-wire transmit port, VTX, with the signal source at the
two-wire port. Note that the gain from the two-wire port to
the four-wire transmit port is G2-4S = 1 (or 0.5 see pin PTG)
5. Pin PTG = Open sets transmit gain to nom. 0.0dB
Pin PTG = AGND sets transmit gain to nom. -6.02 dB
Secondary protection resistors R F and resistors RP impact
the insertion loss as explained in the text, section
Transmission. The specified insertion loss is for RF = RP = 0.
6. The specified insertion loss tolerance does not include
errors caused by external components.
Notes
1. The overload level can be adjusted with the resistor ROV for
higher levels e.g. min 3.1 VPeak and is specified at the two-
wire port with the signal source at the four-wire receive
port.
2. The two-wire impedance is programmable by selection of
external component values according to:
ZTRX = ZT/|G2-4S α RSN| where:
ZTRX = impedance between the TIPX and RINGX
terminals
ZT = programming network between the VTX and RSN
terminals
7. The level is specified at the two-wire port.
G2-4S = transmit gain, nominally = 1 (or 0.5 see pin PTG)
8. The two-wire idle noise is specified with the port
terminated in 600 Ω (RL) and with the four-wire receive
port grounded (ERX = 0; see figure 6).
α
RSN = receive current gain, nominally = 200 (current
defined as positive flowing into the receivesumm-
ing node, RSN, and when flowing from ring to tip).
The four-wire idle noise at VTX is specified with the two-
wire port terminated in 600 Ω (R L). The noise
specification is referenced to a 600 Ω programmed two-
wire impedance level at VTX. The four-wire receive port is
grounded (ERX = 0).
3. Higher return loss values can be achieved by adding a
reactive component to RT, the two-wire terminating
impedance programming resistance, e.g. by dividing R T
into two equal halves and connecting a capacitor from the
common point to ground.
7
PBL 386 21/2
1
2
24 VTX
PTG
RRLY
HP
23 AGND
3
22
21
20
19
RSN
REF
PLC
POV
5
6
25
24
23
22
21
20
19
RINGX
BGND
NC
RINGX
BGND
TIPX
4
REF
PLC
POV
PLD
VCC
NC
24-pin SOIC
and
24-pin SSOP
5
7
TIPX
VBAT
6
28-pin PLCC
8
VBAT
VBAT2
PSG
7
18 PLD
17 VCC
16 DET
VBAT2
9
8
10
11
PSG
NC
9
10
15
C1
LP
DT
DR
11
12
14 C2
13
C3
Figure 7. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view.
Pin Description
Refer to figure 7.
PLCC
Symbol
PTG
RRLY
HP
Description
1
2
3
4
5
Prog. Transmit Gain. Left open transmit gain = 0.0 dB, connected to AGND transmit gain = -6.02 dB.
Ring Relay driver output. The relay coil may be connected to maximum +14V.
Connection for High Pass filter capacitor, CHP. Other end of CHP connects to TIPX.
No internal Connection.
NC
RINGX
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
6
7
BGND
TIPX
Battery Ground, should be tied together with AGND.
The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage
protection components and ring relay (and optional test relay).
8
VBAT
VBAT2
PSG
Battery supply Voltage. Negative with respect to GND.
9
An optional second (2) Battery Voltage connects to this pin via an external diode.
10
Programmable Saturation Guard. The resistive part of the DC feed characteristic is not used for
PBL 386 21/2, RSG = 0 Ω.
11
12
13
NC
LP
DT
No internal Connection.
Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT.
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The external ring trip network connects to this input.
14
DR
Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic
level low, indicating off-hook condition. The external ring trip network connects to this input.
8
PBL 386 21/2
15
16
17
C3
C2
C1
C1, C2 and C3 are digital inputs (internal pull-up) controlling the SLIC operating states.
Refer to section "Operating states" for details.
}
18
DET
Detector output. Active low when indicating loop detection and ring trip, active high when indicating
ground key detection.
19
20
21
NC
No internal Connection.
VCC
PLD
+5 V power supply.
Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor
connected from this pin to AGND.
22
23
POV
PLC
Programmable Overhead Voltage. If pin is left open: The overhead voltage is internally set to min 1.0 V in
off-and on-hook. If a resistor is connected between this pin and AGND: the overhead voltage can be set
to higher values.
Prog. Line Current, the constant current part of the DC feed characteristic is programmed by a resistor
connected from this pin to AGND.
24
25
26
REF
NC
A Reference, 49.9 kΩ, resistor should be connected from this pin to AGND.
No internal Connection.
RSN
Receive Summing Node. 200 times the AC-current flowing into this pin equals the metallic (transversal)
AC-current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain
connect to the receive summing node. A resistor should be connected from this pin to AGND.
27
28
AGND
VTX
Analog Ground, should be tied together with BGND.
Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is
reproduced as an unbalanced GND referenced signal at VTX with a gain of one (or one half, see pin
PTG). The two-wire impedance programming network connects between VTX and RSN.
SLIC Operating States
State
C3
C2
C1
SLIC operating state
Active detector
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Open circuit
Ringing state
Active state
Not applicable
Not applicable
Active state
-
Ring trip detector (active low)
Loop detector (active low)
-
-
Ground key detector (active high)
Loop detector (active low)
Ground key detector (active high)
Active reverse
Active reverse
Table 1. SLIC operating states.
9
PBL 386 21/2
For applications where
ZT/(αRSN·G2-4S) + 2RF + 2RP is chosen to be
equaltoZL theexpressionforG4-2 simplifies
to:
TIPX
TIP
I
+
L
R
R
F
P
Z
L
Z
+
TR
VTX
V
TR
RHP
G
+
2-4S
ZT
1
-
+
E
-
G4−2 = −
L
ZRX 2G2− 4S
V
TX
R
R
F
P
-
I
L
RING
RINGX
-
Z
T
Four-Wire to Four-Wire Gain
From (1), (2) and (3) with EL = 0:
Z
RX
RSN
+
V
RX
I
/α
RSN
VTX
L
-
G4−4
=
=
PBL 386 21/2
VRX
ZT
−
G2− 4S (ZL + 2RF + 2RP)
+ G2−4S (ZL + 2RF + 2RP )
ZT
αRSN
ZRX
Figure 8. Simplified ac transmission circuit.
αRSN is the receive summing node current
Functional Description
andApplicationsInforma-
tion
to metallic loop current gain = 200.
Hybrid Function
Note that the SLICs two-wire to four-wire
gain, G2-4S, is user programmable between
two fix values. Refer to the datasheets for
The hybrid function can easily be
implemented utilizing the uncommitted
amplifier in conventional CODEC/filter
combinations. Please, refer to figure 9. Via
impedance ZB a current proportional to VRX
is injected into the summing node of the
combination CODEC/filter amplifier. As
can be seen from the expression for the
four-wiretofour-wiregainavoltagepropor-
tional to VRX is returned to VTX. This voltage
is converted by RTX to a current flowing into
the same summing node. These currents
can be made to cancel by letting:
values on G2-4S
.
Transmission
General
Two-Wire Impedance
A simplified ac model of the transmission
circuitsisshowninfigure8. Circuitanalysis
yields:
To calculate ZTR, the impedance presented
to the two-wire line by the SLIC including
the fuse and protection resistors RF and RP
let:
VTX
VTR
=
+ IL (2RF + 2RP )
(1)
VRX = 0.
G2− 4S
From (1) and (2):
VTX VRX
IL
+
=
(2)
(3)
ZT
ZRX
αRSN
VTX VRX
ZT
+
= 0(EL = 0)
ZTR
=
+ 2RF + 2RP
RTX
ZB
αRSN G2− 4S
VTR = EL - IL · ZL
where:
Thefour-wiretofour-wiregain,G4-4,includes
the required phase shift and thus the
balancenetworkZB canbecalculatedfrom:
Thus with ZTR, αRSN, G2-4S, RP and RF known:
ZT = αRSN G2− 4S (ZTR − 2RF − 2RP )
VTX is a ground referenced version of the
acmetallicvoltagebetweentheTIPX
and RINGX terminals.
G2-4S is the programmable SLIC two-wire
to four-wire gain (transmit direction).
See note below.
V
RX
Z
= −R
=
B
TX
V
TX
Two-Wire to Four-Wire Gain
Z
T
From (1) and (2) with VRX = 0:
+ G
(Z + 2R + 2R )
2−4S L F P
Z
α
RX
RSN
G
R
TX
Z
(Z + 2R + 2R )
L F P
T
2−4S
VTX
VTR
ZT / αRSN
G2− 4
=
=
VTR is the ac metallic voltage between tip
and ring.
ZT
αRSN G2− 4S
+ 2RF + 2RP
When choosing RTX, make sure the output
load of the VTX terminal is >20 kΩ.
EL
is the line open circuit ac metallic
voltage.
If calculation of the ZB formula above
yields a balance network containing an
inductor, an alternate method is
recommended. Contact Ericsson Micro-
electronics for assistance.
The PBL 386 21/2 SLIC may also be
usedtogetherwithprogrammableCODEC/
filters. The programmable CODEC/filter
allows for system controller adjustment of
Four-Wire to Two-Wire Gain
IL
is the ac metallic current.
is a fuse resistor.
is part of the SLIC protection.
is the line impedance.
determines the SLIC TIPX to RINGX
impedance at voice frequencies.
From (1), (2) and (3) with EL = 0:
RF
RP
ZL
ZT
VTR
G4−2
=
=
VRX
ZT
−
ZL
ZT
αRSN
ZRX
+ G2− 4S (ZL + 2RF + 2RP)
ZRX controls four- to two-wire gain.
VRX is the analog ground referenced
receive signal.
10
PBL 386 21/2
hybrid balance to accommodate different
line impedances without change of
hardware. In addition, the transmit and
receivegainmaybeadjusted.Please,refer
to the programmable CODEC/filter data
sheets for design information.
R
FB
R
TX
VTX
Longitudinal Impedance
V
T
PBL
38621/2
A feed back loop counteracts longitudinal
voltages at the two-wire port by injecting
longitudinal currents in opposing phase.
Thus longitudinal disturbances will
appear as longitudinal currents and the
TIPX and RINGX terminals will experience
very small longitudinal voltage excursions,
leaving metallic voltages well within the
SLIC common mode range.
Z
Z
Combination
CODEC/Filter
T
B
Z
RX
V
RX
RSN
Figure 9. Hybrid function.
recommended to position the 3 dB break
The SLIC longitudinal impedance per
wire, ZLoT and ZLoR, appears as typically
20Ω to longitudinal disturbances. It should
be noted that longitudinal currents may
exceed the dc loop current without distur-
bing the vf transmission.
point of this filter between 30 and 80 Hz to Battery Feed
get a faster response for the dc steps that
The PBL 386 21/2 SLIC emulate a battery
characteristic with current limitation
adjustable.Theopenloopvoltagemeasured
between the TIPX and RINGX terminals is
tracking the battery voltage VBat. The
signalling headroom, or overhead voltage
may occur at DTMF signalling.
Capacitor CLP
Capacitors CTC and CRC
ThecapacitorCLP,whichconnectsbetween
the terminals CLP and VBAT, positions the
high end frequency break point of the low
pass filter in the dc loop in the SLIC. CLP
together with CHP and ZT (see section Two-
Wire Impedance) forms the total two wire
output impedance of the SLIC. The choise
of these programmable components have
an influence on the power supply rejection
ratio (PSRR) from VBAT to the two wire
side at sub-audio frequencies. At these
frequencies capacitor CLP also influences
the transversal to longitudinal balance in
theSLIC.Table1suggestsasuitablevalue
on CLP. The typical value of the transversal
to longitudinal balance (T-L bal.) at 200Hz
is given in table 1 for the chosen value on
CLP.
The capacitors designated CTC and CRC
in figure 11, connected between TIPX
and ground as well as between RINGX
and ground, can be used for RFI filtering.
The recommended value for CTC and CRC
is 2200 pF. Higher capacitance values
may be used, but care must be taken to
prevent degradation of either longitudinal
balance or return loss. CTC and CRC
contribute to a metallic impedance of
1/(π·f·CTC) = 1/(π·f·CRC), a TIPX to ground
impedance of 1/(2·π·f·CTC) and a RINGX
to ground impedance of 1/(2·π·f·CRC).
VTRO, is programmable with a resistor ROV
connected between terminal POV on the
SLIC and ground. Please refer to section
“Programmable overhead voltage(POV)”.
Thebatteryvoltageoverhead,VOH,depends
ontheprogrammedsignaloverheadvoltage
V
TRO. VOH defines the TIP to RING voltage
at open loop conditions according to
VTR(at IL = 0 mA) = |VBat| - VOH
Refer to table 2 for the typical value on
VOH
.
.
SLIC
VOH(typ) [V]
AC - DC Separation Capacitor, CHP
The high pass filter capacitor connected
between terminals HP and TIPX provides
the separation of the ac signal from the
dc part. CHP positions the low end
frequency response break point of the ac
loop in the SLIC. Refer to table 1 for a
recommended value of CHP.
Example: A CHP value of 47 nF will
position the low end frequency response
3dB break point of the ac loop at 5.6 Hz
(f3dB) according to f3dB = 1/(2 π RHP CHP)
where RHP = 600 kΩ.
PBL 386 21/2
2.5 +VTROprog
Table 2. Battery overhead.
T-L bal.
The current limit (reference A - C in figure
12) is adjusted by connecting a resistor,
RLC, between terminal PLC and ground
according to the equation:
RFeed RSG
CLP @ 200Hz CHP
[Ω]
[kΩ]
[nF]
[dB]
[nF]
2·25
0
150
-46
47
1000
ILProg + 4
Table 1. RSG, CLP and CHP values for cons-
tant current feeding characteristics.
RLC
=
where RLC is in kΩ for ILProg in mA.
For values outside table 1, please contact
Ericsson Microelectronics for assistance.
High-Pass Transmit Filter
The capacitor CTX in figure 11 connected
between the VTX output and the
CODEC/filter forms, together with RTX and/
or the input impedance of a programmable
CODEC/filter, a high-pass RC filter. It is
A second, lower battery voltage may be
connected to the device at terminal VBAT2
to reduce short loop power dissipation.
The SLIC automatically switches between
the two battery supply voltages without
need for external control. The silent battery
11
PBL 386 21/2
switching occurs when the line voltage
passes the value
Loop Monitoring Functions
Programmable overhead voltage(POV)
The loop current, ground key and ring trip
detectorsreporttheirstatusthroughacom-
mon output, DET. The detector to be
connected to DET is selected via the three
bit wide control interface C1, C2 and C3.
Please refer to section Control Inputs for a
description of the control interface.
With the POV function the overhead
voltage can be increased.
|VB2| - 40 · IL - VTRO = 3.6
For correct functionality it is important to
connect the terminal VBAT2 to the second
powersupplyviathediodeDVB2 infigure11.
An optional diode DBB connected between
terminalVBandtheVB2powersupply,see
figure 11, will make sure that the SLIC
continues to work on the second battery
even if the first battery voltage disappears.
If a second battery voltage is not used,
VBAT2 is connected to VBAT on the SLIC
and CVB2, DBB and DVB2 are removed.
If the POV pin is left open the overhead
voltage is internally set to 1.1 VPeak. The
overhead voltage is equal in on-hook and
off-hook. If a resistor ROV is connected
between the POV pin and AGND, the
overhead voltage can be set to higher
values, typical values can be seen in
figure 10. The ROV and corresponding
VTRO (signal headroom) are typical values
for THD <1% and the signal frequency
1000Hz.
Observe that the 4-wire output terminal VTX
cannothandlemorethan3.2VPeak. Soifthe
gain 2-wire to 4-wire is 0dB, 3.2 VPeak is
maximum also for the 2-wire side. Signal
levels between 3.2 and 6.4 VPeak on the
2-wire side can be handled with the PTG
shorted so that the gain G2-4S become
-6.02dB. Please note that the 2-wire
impedance, RR and the 4-wire to 4-wire
gain has to be recalculated if the PTG is
shorted.
Loop Current Detector
The loop current detector is indicating that
the telephone is off hook and that current is
flowing in the loop by putting the output
DET to a logical low level when selected.
The loop current threshold value, ILTh, at
which the loop current detector changes
state is programmable by selecting the
valueofresistorRLD.RLD connectsbetween
pin PLD and ground and is calculated
according to
CODEC Receive Interface
The PBL 386 21/2 SLIC have got a
completely new receive interface at the
four wire side which makes it possible to
reduce the number of capacitors in the
applications and to fit both single and dual
battery feed CODECs. The RSN terminal,
connecting to the CODEC receive output
viatheresistorRRX,isdcbiasedwith+1.25V.
This makes it possible to compensate for
currents floating due to dc voltage
differences between RSN and the CODEC
outputwithoutusinganycapacitors. Thisis
done by connecting a resistor RR between
the RSN terminal and ground. With current
directions defined as in figure 13, current
summation gives:
500
RLD
=
ILTh
The current detector is internally filtered
and is not influenced by the ac signal at the
two wire side.
Please note that the maximum signal
current at the 2-wire side can not be
greater than 9 mA.
Ground Key Detector
How to use POV:
The ground key detector is indicating when
thegroundkeyispressed(active)byputting
the output pin DET to a logical high level
when selected. The ground key detector
circuit senses the difference in TIPX and
RINGX currents. When the current at the
RINGX side exceeds the current at the
TIPX side with the threshold value the
detector is triggered. For threshold current
values, please refer to the datasheet.
1.
Decide what overhead
voltage(VTRO) is needed. The POV
function is only needed if the
overhead voltage exceeds 1.1 VPeak
In figure 10 the corresponding ROV
for the decided VTRO can be found.
If the overhead voltage exceeds
3.2 VPeak, the G2-4S gain has to be
changed to -6.02dB by connecting
the PTG pin to AGND. Please note
that the 2-wire impedance, RR and
the 4-wire to 4-wire gain has to be
recalculated.
−IRSN = IRT + IRRX + IRR
=
2.
3.
1,25 1,25 − VCODEC
1,25
RR
+
+
RT
RRX
whereVCODEC isthereferencevoltageofthe
CODEC at the receive output.
From this equation the resistor RR can be
calculated as
Ring Trip Detector
Ring trip detection is accomplished by
connecting an external network to a
comparator in the SLIC with inputs DT and
DR. The ringing source can be balanced or
unbalanced superimposed on VB or GND.
The unbalanced ringing source may be
applied to either the ring lead or the tip lead
with return via the other wire. A ring relay
drivenbytheSLICringrelaydriverconnects
the ringing source to tip and ring.
The ring trip function is based on a polarity
change at the comparator input when the
line goes off-hook. In the on-hook state no
dc current flows through the loop and the
voltage at comparator input DT is more
positivethanthevoltageatinputDR. When
the line goes off-hook, while the ring relay
1,25
RR
=
1,25 − VCODEC
1,25
RT
Analog Temperature Guard
−IRSN
−
−
RRX
The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 21/2 SLIC
reduce the dc line current when the chip
temperaturereachesapproximately145°C
and increases it again automatically when
the temperature drops. Accordingly trans-
mission is not lost under high ambient
temperature conditions.
For the value on IRSN, see table 3.
The resistor RR has no influence on the ac
transmission.
SLIC
IRSN [µA]
PBL 386 21/2
-55
Table3. TheSLICinternalbiascurrentwith
the direction of the current defined as
positivewhenfloatingintotheterminalRSN.
The detector output, DET, is forced to a
logic low level when the temperature guard
is active.
12
PBL 386 21/2
7
6
5
4
3
2
1
0
0
10
20
30
40
50
60
ROV (kΩ)
Figure 10. Programmable overhead voltage (POV). RL = 600 Ω or ∞.
is energized, dc current flows and the
comparator input voltage reverses polar-
ity.
Ringing State
Relay driver
Theringrelaydriverandtheringtripdetector
are activated and the ring trip detector is
indicating off hook with a logic low level at
the detector output.
As the SLIC do not have any stand by state
the SLIC will remain in the active normal
state.
ThePBL38621/2SLIC incorporatesaring
relay driver designed as open collector
(npn) with a current sinking capability of
50 mA. The drive transistor emitter is
connected to BGND. The relay driver has
an internal zener diode clamp for inductive
kick-back voltages.Care must be taken
when using the relay driver together with
relays that have high impedance.
Figure 11 gives an example of a ring trip
detection network. This network is
applicable, when the ring voltage is
superimposed on VB and is injected on the
ringleadofthetwo-wireport.Thedcvoltage
across sense resistor RRT is monitored by
the ring trip comparator input DT and DR
via the network R1, R2, R3, R4, C1 and C2.
With the line on-hook (no dc current) DT is
more positive than DR and the DET output
will report logic level high, i.e. the detector
is not tripped. When the line goes off-hook,
while ringing, a dc current will flow through
the loop including sense resistor RRT and
will cause input DT to become more
negative than input DR. This changes out-
put DET to logic level low, i.e. tripped
detector condition. The system controller
(or line card processor) responds by de-
energizing the ring relay, i.e. ring trip.
Complete filtering of the 20 Hz ac
component at terminal DT and DR is not
necessary. A toggling DET output can be
examined by a software routine to deter-
mine the duty cycle. When the DET output
is at logic level low for more than half the
time, off-hook condition is indicated.
Active States
TIPX is the terminal closest to ground and
sources loop current while RINGX is the
more negative terminal and sinks loop
current. Vf signal transmission is normal.
Theloopcurrentorthegroundkeydetector
is activated. The loop current detector is
indicatingoffhookwithalogiclowleveland
the ground key detector is indicating active
groundkeywithalogichighlevelpresentat
the detector output.
Control Inputs
The PBL 386 21/2 SLIC has three digital
control inputs, C1, C2 and C3.
AdecoderintheSLICinterpretsthecontrol
inputconditionandsetsupthecommanded
operating state.
C1 to C3 are internal pull-up inputs.
Open Circuit State
In the Open Circuit State the TIPX and
RINGXlinedriveamplifiersaswellasother
circuit blocks are powered down. This
causes the SLIC to present a high
impedance to the line. Power dissipation is
at a minimum and no detectors are active.
13
PBL 386 21/2
RFB
PBL 386 21/2
CTX
RTX
KR
-
PTG
VTX
-
0
+
+
RT
RRLY
HP
AGND
RSN
NC
RB
+12 V /+5V
RRX
0
CGG
DHP
CHP
NC
CODEC/
Filter
RF2
RR
RP2
RING
RINGX
BGND
TIPX
VBAT
VBAT2
PSG
NC
REF
PLC
POV
PLD
VCC
NC
RREF
RLC
ROV
RLD
CRC
CTC
VB
OVP
TIP
RF1
RP1
PBL 386 21/2
DVB2
VB2
VB
VCC
VCC
DBB
DVB
RSG
CVB2
CVCC
DET
C1
CLP
ERG
CVB
R1
LP
RRT
DT
C2
R2
DR
C3
C1
C2
SYSTEM CONTROL
INTERFACE
R3
R4
SLIC No. 2 etc.
RESISTORS (Values according to IEC E96 series):
CAPACITORS (Values according to IEC E96 series):
OVP:
RSG
RLD
ROV
RLC
RREF
RR
= 0 Ω
1% 1/10 W
CVB
= 100 nF
= 150 nF
= 100 nF
= 2.2 nF
= 2.2 nF
= 47 nF
100 V 10%
100 V 10%
10 V 10%
100 V 10%
100 V 10%
100 V 10%
100 V 10%
10 V 10%
100 V 10%
63 V 10%
63 V 10%
Secondary protection (e. g. Power Innovations
TISPPBL2). The ground terminals of the
secondary protection should be connected to the
common ground on the Printed Board Assembly
with a track as short and wide as possible,
preferable a groundplane.
= 49.9 kΩ 1% 1/10 W
= User programmable
= 38.3 kΩ 1% 1/10 W
= 49.9 kΩ 1% 1/10 W
= 64.9 kΩ 1% 1/10 W
= 105 kΩ 1% 1/10 W
= 24.9 kΩ 1% 1/10 W
= 22.1 kΩ 1% 1/10 W
= 52.3 kΩ 1% 1/10 W
Depending on CODEC/filter
= 604 kΩ 1% 1/10 W
= 604 kΩ 1% 1/10 W
= 249 kΩ 1% 1/10 W
= 280 kΩ 1% 1/10 W
CVB2
CVCC
CTC
CRC
CHP
CLP
RT
= 150 nF
= 100 nF
= 220 nF
= 330 nF
= 330 nF
RTX
RB
CTX
NOTES:
CGG
C1
1 RP1 and RP2 may be omitted if DVB is in place
RRX
RFB
R1
2 It is required to connect DHP between terminal HP
and ground if CHP > 47 nF
C2
DIODES:
DVB
R2
= 1N4448
= 1N4448
= 1N4448
R3
DVB2
DBB
R4
RRT
= 330 Ω
5% 2 W
DHP
= 1N4448 (Note 2)
R
, RP2 ≥ 10 Ω
1% 1/10 W (Note 1)
RPF11, RF2 = Line resistor, 40 Ω 1%
Figure 11. single-channel subscriber line interface with PBL 386 21/2 and combination CODEC/filter.
Overvoltage Protection
The PBL 386 21/2 SLIC must be protected As the protection voltage will track the The fuse resistors RF serve the dual
against overvoltages on the telephone line negative supply voltage the overvoltage purposes of being non- destructive energy
caused by lightning, ac power contact and
induction.RefertoMaximumRatings,TIPX
and RINGX terminals, for maximum
allowablecontinuousandtransientcurrents
that may be applied to the SLIC.
stress on the SLIC is minimized.
Positive overvoltages are clamped to gro- andofbeingfuses,whenthelineisexposed
und by a diode. Negative overvoltages are to a power cross.
initially clamped close to the SLIC negative If a PTC is choosen for RF, note that it is
supply rail voltage and the protector will important to always use PTC´s in series
crowbar into a low voltage on-state with resistors not sensitive to temperature,
dissipators, when transients are clamped
Secondary Protection
condition, by firing an internal thyristor.
asthePTCwillactasacapacitanceforfast
Agatedecouplingcapacitor,CGG,isneeded transients and therefore will not protect the
to carry enough charge to supply a high SLIC.
enough current to quickly turn on the
thyristorintheprotector.CGG shallbeplaced
close to the overvoltage protection device.
Thecircuitshowninfigure11utilizesseries
resistors together with a programmable
overvoltage protector (e.g Power
Innovations TISPPBL2), serving as a
secondary protection.
Without the capacitor even the low
The TISPPBL2 is a dual forward-conduc-
ting buffered p-gate overvoltage protector. inductanceinthetracktotheVBatsupplywill
Theprotectorgatereferencestheprotection limit the current and delay the activation of
(clamping) voltage to negative supply
voltage (i.e the battery voltage,VB ).
the thyristor clamp.
14
PBL 386 21/2
DC characteristics
A
B
C
D
E
VTR [V]
A:
B:
C:
IL(@VTR=0V)=ILProg
Constant current
D:
E:
RFeed=2·25 Ω
VTROpen=|VBat|-VOH
103
RLC
I
LConst(typ) = ILProg
=
- 4·10-3
VTR=|VBat|-VOH-50·ILProg
Figure 12. Battery feed characteristics (without the protection resistors on the line).
VTX
PBL386 21/2
CODEC
DC-GND
RT
I
IRT
IRSN
IRRX
RRX
_
+
RSN
IRR
+1.25 V
UREFcodec
RR
Figure 13. CODEC receive interface.
15
PBL 386 21/2
Power-up Sequence
Nospecialpower-upsequenceisnecessary
exceptthatgroundhastobepresentbefore
all other power supply voltages.
Printed Circuit Board Layout
Care in PCB layout is essential for proper
function. The components connecting to
the RSN input should be placed in close
proximity to that pin, such that no
interference is injected into the RSN pin.
Ground plane surrounding the RSN pin is
advisable.
Analog ground (AGND) should be
connected to battery ground (BGND) on
the PCB in one point.The capacitors for the
battery should be connected with short
wide leads of the same length.
Ordering Information
Package
Temp. Range
Part No.
PBL 386 21/2SHT
PBL 386 21/2SOS
PBL 386 21/2SOT
24 pin SSOP Tape & Reel -40° - +85° C
24 pin SOIC Tube
24 pin SOIC Tape & Reel
28 pin PLCC Tube
-40° - +85° C
-40° - +85° C
-40° - +85° C PBL 386 21/2QNS
28 pin PLCC Tape & Reel -40° - +85° C
PBL 386 21/2QNT
Information given in this data sheet is believed to be
accurate and reliable. However no responsibility is
assumed for the consequences of its use nor for any
infringement of patents or other rights of third parties
which may result from its use. No license is granted
by implication or otherwise under any patent or patent
rights of Ericsson Microelectronics AB. These
products are sold only according to Ericsson
Microelectronics AB' general conditions of sale,
unless otherwise confirmed in writing.
Specifications subject to change without
notice.
1522-PBL 386 21/2 Uen Rev. A
© Ericsson Microelectronics AB 1999
This product is an original Ericsson product
protected by US, European and other
patents.
Ericsson Microelectronics AB
SE-164 81 Kista-Stockholm, Sweden
Telephone: +46 8 757 50 00
16
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