PBL38621/2SOS [INFINEON]
SLIC, Bipolar, PDSO24, SOIC-24;
| 型号： | PBL38621/2SOS |
| 厂家： | 
Infineon |
| 描述： | SLIC, Bipolar, PDSO24, SOIC-24 电信 光电二极管 电信集成电路 |
| 文件： | 总46页 (文件大小：861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, DS1, June 2003
FlexiSLICTM
Subscriber Line Interface Circuit
PBL 38621/2, Version 2
Wired Communications
N e v e r s t o p t h i n k i n g .
FlexiSLIC
Revision History:
Previous Version:
2003-06-25
DS1
Page
Subjects (major changes since last revision)
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The information in this document is subject to change without notice.
Edition 2003-06-25
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
FlexiSLIC
PBL 38621/2
Table of Contents
Page
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
1.2
1.3
1.4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Characterictics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Recommended Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Design Supporting Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1
4.2
5
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Two-Wire Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Two-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Four-Wire to Two-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Four-Wire to Four-Wire Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Longitudinal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Capacitors CTC and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AC - DC Separation Capacitor, CHP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
High-pass Transmit Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Capacitor CLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
6
Battery Feed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CODEC Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Programmable Overhead Voltage (POV) . . . . . . . . . . . . . . . . . . . . . . . . . 38
Analog Temperature Guard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1
6.2
6.3
7
Loop Monitoring Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Loop Current Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Ground Key Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Ring Trip Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.1
7.2
7.3
8
Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9
Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Open Circuit (C3, C2, C1 = 0, 0, 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Ringing (C3, C2, C1 = 0, 0, 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Active States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1
9.2
9.3
10
Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Sheet
3
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Table of Contents
Page
10.1
10.2
Overvoltage Protection - General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Secondary Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11
12
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Printed Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
24-pin SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
24-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
28-pin PLCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
13.1
13.2
13.3
Data Sheet
4
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
List of Figures
Page
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration, 24L-SOIC, 24L-SSOP and 28L-PLCC (top view). . 10
Overhead Level, VTRO, Two-Wire Port. . . . . . . . . . . . . . . . . . . . . . . . . 23
Longit. to Metallic, BLME and Longit. to Four-Wire, BLFE Balance. . . . . 24
Metallic to Longit., BMLE and Four-Wire to Longit. Balance, BFLE . . . . . 24
Overhead Level, VTXO, Four-Wire Transmit Port . . . . . . . . . . . . . . . . . 24
Frequency Response, Insertion Loss, Gain Tracking . . . . . . . . . . . . . 25
Application Example of PBL 38621/2 with CODEC/filter . . . . . . . . . . . 26
Simplified AC Model of PBL 38621/2. . . . . . . . . . . . . . . . . . . . . . . . . . 29
Hybrid Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Codec Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Battery Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Programmable Overhead Voltage (POV). RL= 600 Ω or Infinitive . . . . 38
P-SSOP-24-1 (Plastic Shrink Small Outline Package). . . . . . . . . . . . . 43
P-DSO-24-1 (Plastic Dual Small Outline Package) . . . . . . . . . . . . . . . 44
P-LCC-28-2 (Plastic Leaded Chip Carrier Package) . . . . . . . . . . . . . . 45
Data Sheet
5
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
List of Tables
Page
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SLIC Operating States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Resistors (values according to IEC E96 series). . . . . . . . . . . . . . . . . . 27
Capacitors (values according to IEC E96 series) . . . . . . . . . . . . . . . . 27
Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Feeding Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Battery Overhead. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Internal bias current of RSN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Sheet
6
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Subscriber Line Interface Circuit
Version 2
1
Overview
1.1
Features
• 24-pin SSOP package
• High and low battery with automatic switching
• 60 mW on-hook power dissipation in active state
• On-hook transmission
• Long loop battery feed tracks Vbat for maximum line
voltage
• Selectable transmit gain (1x or 0.5x)
• No power-up sequence
• 44 V open loop voltage @ -48 V battery feed
• Full longitudinal current capability during
on-hook state
• Analog overtemperature protection permits transmis-
sion while the protection circuits is active
• Polarity reversal
P-DSO-24-1, -3
• Integrated Ring Relay driver
• Ground key detector
• Programmable signal headroom
• -40 oC to +85 oC ambient temperature range
1.2
Typical Applications
• Basic functionality Central Office Line card
• Private branch exchange (PABX)
• Digital added mainline (DAML)
• Terminal adapters (CPE)
• ISDN terminal adapters
• Other shortloop applications
Type
Package
PBL 38621/2 SH
PBL 38621/2 SO
PBL 38621/2 QN
P-SSOP-24-1
P-DSO-24-1
P-LCC-28-2
Data Sheet
7
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Overview
1.3
Description
The PBL 38621/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in PBX, Terminal adapters and other telecommunications equipment. The
PBL 38621/2 SLIC has been optimized for low total line interface cost and for a high
degree of flexibility in different applications.
The PBL 38621/2 SLIC has constant current feed, programmable to maximum 30 mA.
A second lower battery voltage may be connected to the device to reduce short loop
power dissipation. The SLIC automatically switches between the two battery supply
voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring-trip detection functions. The
PBL 38621/2 is compatible with loop start signalling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with
a programmable CODEC/filter, for example SiCoFi PEB 2466. The programmable two-
wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 38621/2 SLIC package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC.
Data Sheet
8
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Overview
1.4
Block Diagram
VCC
AGND
DT
DR
Ring Trip
Comparator
Ring Relay
Driver
RRLY
C1
C2
C3
Input
Decoder
and
Ground Key
Detector
Control
TIPX
HP
DET
Line Feed
Controller
and
POV
PSG
PLC
LP
Longitudinal
Signal
Two-wire
Interface
Suppression
RINGX
Off - Hook
Detector
PLD
REF
RSN
VTX
VF signal
Transmission
BGND
VBAT
PTG
VBAT2
bl_sch_21
Figure 1
Block Diagram
Data Sheet
9
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Pin Configuration
2
Pin Configuration
PTG 1
RRLY 2
HP 3
24 VTX
23 AGND
22 RSN
21 REF
20 PLC
4
3
2
1 28 27 26
RINGX
4
RINGX
BGND
TIPX
5
6
7
8
9
25 NC
BGND 5
TIPX 6
VBAT 7
VBAT2 8
PSG 9
LP 10
24 REF
PLC
23
24-pin SOIC
and
19 POV
18 PLD
17 VCC
16 DET
15 C1
28-pin PLCC
VBAT
22 POV
21 PLD
20 VCC
19 NC
24- pin SSOP
VBAT2
PSG 10
NC 11
12 13 14 15 16 17 18
DT 11
14 C2
DR 12
13 C3
pinout_21
Figure 2
Table 1
Pin Configuration, 24L-SOIC, 24L-SSOP and 28L-PLCC (top view).
Pin Definition and Functions
P-DSO
P-SSOP
Pin No.
P-LCC
Name
I/O Function
Pin No.
1
1
PTG
–
Programmable transmit gain. Left open
transmit gain = 0.0 dB, connected to AGND
transmit gain = -6.02 dB.
2
3
2
3
RRLY
HP
O
–
Ring relay driver output. The relay coil may
be connected to maximum +14 V.
Connection for high pass filter capacitor, CHP.
Other end of CHP connects to TIPX.
Data Sheet
10
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Pin Configuration
Table 1
Pin Definition and Functions (cont’d)
P-DSO
P-SSOP
Pin No.
P-LCC
Name
I/O Function
Pin No.
4
5
RINGX
–
The RINGX pin connects to the ring lead of
the two-wire interface via over voltage
protection components and ring relay (and
optional test relay).
5
6
6
7
BGND
TIPX
–
–
Battery ground, should be tied together with
AGND.
The TIPX pin connects to the tip lead of the
two-wire interface via over voltage protection
components and ring relay (and optional test
relay).
7
8
9
8
VBAT
VBAT2
PSG
–
–
–
Battery supply voltage. Negative with respect
to GND.
9
An optional second (2) Battery Voltage
connects to this pin via an external diode.
Programmable saturation guard. The
resistive part of the DC feed characteristics is
not used for PBL 38621/2, RSG = 0 Ω
10
10
11
12
13
LP
DT
–
I
Connection for low pass filter capacitor, CLP.
Other end of CLP connects to VBAT.
Input to the ring trip comparator. With DR
more positive than DT the detector output,
DET, is at logic level low, indicating off-hook
condition. The external ring trip network
connects to this input.
12
14
DS
I
Input to the ring trip comparator. With DR
more positive than DT the detector output,
DET, is at logic level low, indicating off-hook
condition. The external ring trip network
connects to this input.
13
14
15
15
16
17
C3
C2
C1
I
I
I
C1, C2, C3 are digital inputs, which control
the SLIC operating states. Refer to Table 2
for details.
Data Sheet
11
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Pin Configuration
Table 1
Pin Definition and Functions (cont’d)
P-DSO
P-SSOP
Pin No.
P-LCC
Name
I/O Function
Pin No.
16
18
DET
O
Detector output. Active low when indicating
loop or ring-trip detection, active high when
indicating ground key detection.
17
18
20
21
VCC
PLD
–
–
+5 V power supply.
Programmable loop detector threshold. The
loop detection threshold is programmed by a
resistor connected from this pin to AGND.
19
22
POV
–
Programmable overhead voltage. If pin is left
open: The overhead voltage is internally set
to min 1.0 V in off- and on-hook. If a resistor
is connected between this pin and AGND:
The overhead voltage can be set to higher
values.
20
23
PLC
–
Programmable line current, the constant part
of the DC feed characteristic is programmed
by a resistor connected from this pin to
AGND.
21
22
24
26
REF
RSN
–
–
A reference, 49.9 kΩ, resistor should be
connected from this pin to AGND.
Receive summing node. 200 times the AC
current flowing into this pin equals the
metallic (transversal) AC current flowing from
RINGX to TIPX. Programming networks for
two-wire impedance and receive gain
connect to the receive node. A resistor should
be connected from this pin to AGND.
23
27
AGND
–
Analog ground, should be tied together with
BGND.
Data Sheet
12
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Pin Configuration
Table 1
Pin Definition and Functions (cont’d)
P-DSO
P-SSOP
Pin No.
P-LCC
Name
I/O Function
Pin No.
24
28
VTX
O
Transmit vf output. The AC voltage difference
between TIPX and RINGX, the AC metallic
voltage, is reproduced as an unbalanced
GND referenced signal at VTX with a gain of
one (or one half, see pin PTG). The two-wire
impedance programming network connects
between VTX and RSN.
-
4, 11, 19, NC
25
–
Not Connected.
Table 2
State
SLIC Operating States
C3
C2
C1
SLIC Operating Active Detector
State
(DET Response)
0
1
2
0
0
0
Open circuit
No active detector
(DET is set high)
0
0
1
Ringing
Active
Ring-trip detector
(DET active low)
0
1
0
Loop detector
(DET active low)
3
4
5
0
1
1
1
0
0
1
0
1
Not applicable
Not applicable
Active
–
–
Ground key detector
(DET active high)
6
7
1
1
1
1
0
1
Active reverse
Active reverse
Loop detector
(DET active low)
Ground key detector
(DET active high)
Data Sheet
13
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
3
Electrical Characteristics
Table 3
Absolute Maximum Ratings
Parameter
Symbol
Values
Min. Typ. Max.
Unit
Note/Test
Condition
Temperature, Humidity
Storage temperature range TStg
-55
-40
–
–
+150 °C
+110 °C
–
–
Operating temperature
TAmb
range
Operating junction
temperature range1)
TJ
-40
–
+140 °C
–
Power Supply (-40 °C ≤TAmb ≤+85 °C)
V
V
CC with respect to A/BGND VCC
BAT2 with respect to
-0.4
VBAT
–
–
6.5
0.4
V
V
–
–
VBAT2
A/BGND
V
BAT with respect to
VBAT
VBAT
-75
-80
–
–
0.4
0.4
V
V
–
–
A/BGND, continuous
VBAT with respect to
A/BGND, 10 ms
Power Dissipation
Continuous power
dissipation
Ground
PD
–
–
–
–
1.5
0.3
W
V
T
–
–
Amb ≤+85 °C
Voltage between AGND and VG
-0.3
–
BGND
Relay Driver
Ring relay supply voltage
–
BGN
V
D+14
Ring Trip Comparator
Input voltage
VDT,
VBAT
–
–
AGN
D
5
V
–
–
VDR
Input current
IDT, IDR -5
mA
Digital Inputs, Outputs (C1, C2, C3, DET)
Input voltage
Output voltage
VID
VOD
-0.4
-0.4
–
–
VCC
VCC
V
V
–
–
Data Sheet
14
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
Table 3
Absolute Maximum Ratings (cont’d)
Symbol Values
Min. Typ. Max.
TIPX and RINGX Terminals (-40 °C ≤TAmb ≤+85 °C, VBAT = -50 V)
Parameter
Unit
Note/Test
Condition
TIPX or RINGX current
ITIPX
,
-100
–
100
mA
–
–
IRINGX
TIPX or RINGX voltage,
continuous (referenced to
AGND)2)
VTA, VRA -80
–
2
V
TIPX or RINGX2)
VTA, VRA VBAT
–
5
V
pulse <
- 10
10 ms,
tRep > 10 s
TIPX or RINGX2)
TIP or RING2)3)
VTA, VRA VBAT
–
–
10
15
V
V
pulse < 1 µs,
- 25
tRep > 10 s
VTA, VRA VBAT
pulse <
- 35
250 ns,
tRep > 10 s
1) The circuit includes thermal protection. Operation above max. junction temperature may degrade device
reliability.
2) With the diodes DVB and DVB2 included, see Figure 8.
3) RF1 and RF2 > 20 Ω is also required. Pulse is supplied to RING and TIP outside RF1 and RF2.
Attention: Stresses above the max. values listed here may cause permanent
damage to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Maximum ratings are absolute ratings; exceeding only one of these
values may cause irreversible damage to the integrated circuit.
Table 4
Operating Range
Parameter
Symbol
Values
Min. Typ. Max.
Unit Note/Test
Condition
Ambient temperature
TAmb
VCC
VBAT
-40
4.75
-58
–
–
–
+85 °C
–
–
–
–
V
V
CC with respect to AGND
BAT with respect to AGND
5.25
-8
V
V
AGND with respect to BGND VG
-100 –
100 mV
Data Sheet
15
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
3.1
Characterictics
The specification is made with following setup: -40 °C ≤TAmb ≤+85 °C, PTG = open (see
pin description), VCC = +5 V ±5%, VBAT = -58 V to -40 V, VBAT2 = -17 V, RLC = 38.3 kΩ,
IL = 22 mA, RL = 600 Ω, RF1 = RF2 = 0, RREF = 49.9 kΩ, CHP = 47 nF, CLP = 0.15 µF, RT =
120 kΩ, RSG = 0 kΩ, RRX = 60 kΩ, RR = 52.3 kΩ, ROV = infinite.
Current definition: current is positive if flowing into a pin unless stated otherwise.
Table 5
Parameter
Characteristics
Symbol
Values
Typ. Max.
Unit
Note/Test
Condition
Min.
Two-Wire Port
Overhead level1) ,
VTRO
1.0
1.0
–
–
–
–
VPeak
VPeak
–
Active, 1% THD
On-Hook,
R
OV = infinite
ILDC ≤5 mA
see Figure 3
Input impedance2)
ZTRX
–
ZT/
200
–
Ω
–
Longitudinal
impedance
ZLOT
,
–
20
35
–
Ω/wire 0 < f < 100 Hz
ZLOR
Longitudinal current
ILOT
,
10
53
–
mArms/ Active
wire
limit
ILOR
Longitudinal to metallic BLM
balance (IEEE
–
–
dB
dB
dB
0.2 kHz ≤f
≤1.0 kHz
1.0 kHz < f
< 3.4 kHz
standard 455-1984)
53
53
–
–
–
–
Reverse polarity
0.2 kHz < f
< 3.4 kHz
Longitudinal to metallic BLME
53
53
53
75
70
68
–
–
–
dB
dB
dB
0.2 kHz ≤f
balance
≤1.0 kHz
BLME = 20 ×
1.0 kHz < f
log|ELO/VTR|,
see Figure 4
< 3.4 kHz
Reverse polarity
0.2 kHz < f
< 3.4 kHz
Data Sheet
16
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Min.
Values
Typ. Max.
Unit
Note/Test
Condition
Longitudinal to four-
wire balance
BLFE
53
53
53
75
70
68
–
–
–
dB
dB
dB
0.2 kHz ≤f
≤1.0 kHz
B
LFE = 20 ×
1.0 kHz < f
log|ELO/VTX|,
see Figure 4
< 3.4 kHz
Reverse polarity
0.2 kHz < f
< 3.4 kHz
Metallic to longitudinal BMLE
40
50
–
dB
0.2 kHz < f
balance
< 3.4 kHz
BMLE = 20 ×
log|VTR/VLO|,
ERX = 0 V, see
Figure 5
Four-wire to
BFLE
40
50
–
dB
0.2 kHz < f
longitudinal balance
< 3.4 kHz
B
FLE = 20 ×
log|ERX/VLO|,
see Figure 5
Two-wire return loss3)
r
27
20
35
–
–
–
dB
dB
0.2 kHz < f
< 1.0kHz
Z
TRX + ZL
TRX – ZL
------------------------
r = 20 × log
22
1.0 kHz < f
Z
< 3.4 kHz
TIPX idle voltage
RINGX idle voltage
VTI
VRI
–
–
-1.1
V
V
Active, IL = 0 mA
Active, IL = 0 mA
V
BAT+ –
2.5
Open loop voltage
VTR
–
V
BAT+ –
V
Active, IL = 0 mA
3.6
Four-Wire Transmit Port (VTX)
Overhead level4),
Load imp. > 20 kΩ
1% THD
VTXO
1.0
1.0
–
–
–
–
VPeak
VPeak
–
On-Hook, IL
≤5 mA
see Figure 6
Output offset voltage
∆VTX
-100
–
100
mV
–
Data Sheet
17
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Min.
Values
Typ. Max.
Unit
Note/Test
Condition
Output impedance
ZTX
–
15
50
Ω
0.2 kHz < f
< 3.4 kHz
Four-Wire Receive Port (receive summing node = RSN)
RSN DC voltage
RSN impedance
VRSNdc 1.15
1.25
8
1.35
20
V
Ω
IRSN = -55 µA
–
0.2 kHz < f
< 3.4 kHz
RSN current (IRSN ) to αRSN
metallic loop current
(IL) gain
–
200
–
ratio
0.3 kHz < f
< 3.4 kHz
Frequency Response
Two-wire to four-wire, g2-4
relative to 0 dBm,
-0.20
-1.0
–
–
–
0.10
0.1
dB
dB
dB
0.3 kHz < f
< 3.4 kHz
1.0 kHz, ERX = 0 V,
see Figure 7
f = 8 kHz, 12 kHz,
16 kHz
Four-wire to two-wire, g4-2
relative to 0 dBm,
1.0 kHz, EL = 0 V,
see Figure 7
-0.2
0.1
0.3 kHz < f
< 3.4 kHz
f = 8 kHz, 12 kHz
f = 16 kHz
0.3 kHz < f
< 3.4 kHz
-1.0
-2.0
-0.2
–
–
–
0
0
0.1
dB
dB
dB
Four-wire to four-wire, g4-4
relative to 0 dBm,
1.0 kHz, EL = 0 V,
see Figure 7
Insertion Loss
Two-wire to four-wire5), G2-4
-0.2
–
0.2
dB
ERX = 0 V,
G
2-4 = 20 ×
PTG = Open
see Figure 7
log|VTX/VTR|
0 dBm, 1.0 kHz
-6.22 -6.02 -5.82 dB
-0.2
PTG = AGND
0 dBm, 1.0 kHz
Four-wire to two-wire6), G4-2
–
0.2
dB
G
4-2 = 20 ×
log|VTR/ERX|,
EL = 0 V, see Figure 7
Data Sheet
18
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Min.
Values
Typ. Max.
Unit
Note/Test
Condition
Gain Tracking
Two-wire to four-wire7),
Ref. -10 dBm, 1.0 kHz,
see Figure 7
-0.1
-0.2
–
–
0.1
0.2
dB
dB
-40 dBm to
+0 dBm
-55 dBm to
-40 dBm
Four-wire to two-wire,
Ref. -10 dBm, 1.0 kHz,
see Figure 7
-0.1
-0.2
–
–
0.1
0.2
dB
dB
-40 dBm to
+0 dBm
-55 dBm to
-40 dBm
Noise
Idle channel noise at
–
–
–
–
12
dBrnC C-message
weighting
two-wire port8)
(TIPX-RINGX) or four-
wire (VTX) output
-78
dBmp Psophometrical
weighting
Harmonic Distortion
Two-wire to four-wire,
–
–
-67
-67
-50
-50
dB
dB
0 dBm
see Figure 7
0.3 kHz < f <
3.4 kHz
Four-wire to two-wire
Battery Feed Characteristics
Constant loop current, ILProg
RLC in kΩ
0.92 × ILProg 1.08 × mA
1000
ILProg
ILProg
ILProg = ----------- – 4, 0
RLC
see Figure 12
I
LProg @ 0.95 × ILProg 1.05 × mA
1000
30 mA ILProg
ILProg
ILProg = ----------- – 4, 2
RLC
I
LProg @ 0.94 × ILProg 1.06 × mA
1000
18 mA ILProg
ILProg
ILProg = ----------- – 3, 9
RLC
RL = 0 Ω
Open circuit loop
current
ILOC
-100
0
100
µA
Loop Detector
Data Sheet
19
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Min.
Values
Typ. Max.
Unit
Note/Test
Condition
Programmable
threshold,
ILTh
0.85 × ILTh
ILTh
1.15 × mA
ILTh
RLD in kΩ,
7 mA ≤ILTh
I
LTh = 500/RLD
Ground Key Detector
Ground key detector
threshold
10
16
22
mA
ITIPX and IRINGX
difference to
trigger ground key
detector.
Ring Trip Comparator
Offset voltage
∆VDTDR -20
0
20
mV
Source resistance,
RS = 0 Ω
Input bias current
IB
-200
-20
–
200
-1
nA
V
IB=(IDT +IDR)/2
–
Input common mode
VDT, VDR VBAT
range
+1
Ring Relay Driver
Saturation voltage
VOL
ILK
–
–
0.2
–
0.5
10
V
µA
IOL = 50 mA
VOH = 12 V
Off state leakage
current
Digital Inputs (C1, C2, C3)
Input low voltage
Input high voltage
Input low current
Input high current
VIL
VIH
IIL
0
2.5
–
–
–
–
–
0.5
VCC
-50
50
V
V
µA
µA
–
–
VIL = 0.5 V
VIH = 2.5 V
IIH
–
Data Sheet
20
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Min.
Values
Typ. Max.
Unit
Note/Test
Condition
Detector Output (DET)
Output low voltage
VOL
–
–
–
15
0.7
–
V
kΩ
IOL = 0.5 mA
–
Internal pull-up resistor
to VCC
Power Dissipation (VBAT -48 V, VBAT2 = -17 V)
Power Dissipation
Power Dissipation
P1
P2
–
–
10
60
15
80
mW
mW
Open circuit
Active (On-hook)
Long current =
0 mA
Power Dissipation
Power Dissipation
P3
P4
–
–
290
145
–
–
mW
mW
Active (Off-hook)
RL = 300 Ω
Active (Off-hook)
RL = 500 Ω
Power Supply Currents (VBAT = -48 V)
VCC current
VBAT current
VCC current
ICC
IBAT
ICC
–
-0.1
–
1.2
-0.05
2.8
2.0
–
4.0
mA
mA
mA
Open circuit
Open circuit
Active, On-hook,
Long current =
0 mA
VBAT current
IBAT
-1.5
-1.0
–
mA
Active, On-hook,
Long current =
0 mA
Power Supply Rejection Ratios
V
CC to 2- or 4-wire port
30
40
36
42
60
45
–
–
–
dB
dB
dB
Active, f = 1 kHz,
Vn = 100 mV
V
BAT2 to 2- or 4-wire
Active, f = 1 kHz,
port
Vn = 100 mV
VBAT to 2- or 4-wire port
Active, f = 1 kHz,
Vn = 100 mV
Data Sheet
21
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
Table 5
Characteristics (cont’d)
Parameter
Symbol
Min.
Values
Typ. Max.
Unit
Note/Test
Condition
Temperature Guard
Junction threshold
temperature
TJG
–
145
–
°C
–
Thermal Resistance
24-pin SSOP
Θ
–
–
55
66.9
–
–
°C/W
–
JP24SSOP
Rth, jA
°C/W P-SSOP-24-1,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
24-pin SOIC
28-pin PLCC
Θ
–
–
43
80.2
–
–
°C/W
–
JP24SOIC
Rth, jA
°C/W P-DSO-24-1-3,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
Θ
–
–
39
50.4
–
–
°C/W
–
JP28PLCC
Rth, jA
°C/W P-LCC-28-2,
4-layer PCB;
Junction to
ambient thermal
resistance in
JEDEC still air
chamber
1) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is
specified at the two-wire port with the signal source at the four-wire receive port.
Data Sheet
22
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
2) The two-wire impedance is programmable by selection of external component values according to:
Z
TRX = ZT/(|G2-4S × αRSN|) where:
Z
TRX = impedance between the TIPX and RINGX terminals
ZT = programming network between the VTX and RSN terminals
G
2-4S = transmit gain, nominally = 1 (or 0.5, see pin PTG)
αRSN = receive current gain, nominally 200 (current defined as positive flowing into the receive summing node,
RSN, and when flowing from ring to tip).
3) Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating
impedance programming resistance, for example by dividing RT into two equal halves and connecting a
capacitor from the common point to ground.
4) The overhead level can be adjusted with the resistor ROV for higher levels, for example min 3.1 VPeak, and is
specified at the four-wire transmit port, (VTX) with the signal source at the two-wire port. Note that the gain
from the two-wire port to the four-wire transmit port is G2-4S = 1 (or 0.5, see pin PTG).
5) Pin PTG = Open sets transmit gain to nom. 0.0 dB.
Pin PTG = AGND sets transmit gain to nom. -6.02 dB
Secondary resistor RF impact the insertion loss as explained in the text, Chapter 5. The specified insertion loss
is for RF = 0.
6) The specified insertion loss tolerance does not include errors caused by external components.
7) The level is specified at the two-wire port.
8) The two-wire idle noise is specified with the port terminated in 600 Ω (RL), and with the four-wire receive port
grounded (ERX = 0; see Figure 7). The four-wire idle noise at VTX is specified with the two-wire port terminated
in 600 Ω (RL). The noise specification is referenced to a 600 Ωtwo-wire impedance level at VTX. The four-wire
receive port is grounded (ERX = 0).
C
TIPX
VTX
RSN
V TRO
ILDC
R L
PBL 38621
R T
ERX
RINGX
R RX
Fig3_21
Figure 3
Overhead Level, VTRO, Two-Wire Port
1/ωC << RL, RL = 600 Ω, RT = 120 kΩ, RRX = 60 kΩ
Data Sheet
23
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
TIPX
VTX
RSN
E LO
C
R LT
R LR
VTR
PBL 38621
R T
VTX
RINGX
R RX
Fig4_21
Figure 4
Longit. to Metallic, BLME and Longit. to Four-Wire, BLFE Balance
1/ωC << 150 Ω, RLT = RLR = RL /2 = 300 Ω, RT = 120 kΩ, RRX = 60 kΩ
TIPX
VTX
RSN
C
R LT
R LR
VTR
PBL 38621
R T
ERX
V LO
RINGX
R RX
Fig5_21
Figure 5
Metallic to Longit., BMLE and Four-Wire to Longit. Balance, BFLE
1/ωC << 150 Ω, RLT = RLR = RL /2 = 300 Ω, RT = 120 kΩ, RRX = 60 kΩ
C
TIPX
VTX
RSN
R L
I LDC
PBL 38621
R T
V TXO
E L
RI NGX
R RX
Fig6_21
Figure 6
Overhead Level, VTXO, Four-Wire Transmit Port
1/ωC << RL, RL = 600 Ω, RT = 120 kΩ, RRX = 60 kΩ
Data Sheet
24
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Electrical Characteristics
C
TIPX
VTX
RSN
R L
V TR
I LDC
PBL 38621
R T
V TX
E RX
E L
RI NGX
R RX
Fig7_21
Figure 7
Frequency Response, Insertion Loss, Gain Tracking
1/ωC << RL, RL = 600 Ω, RT = 120 kΩ, RRX = 60 kΩ
Data Sheet
25
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Application Schematic
4
Application Schematic
sch_21
Figure 8
Application Example of PBL 38621/2 with CODEC/filter
Data Sheet
26
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Application Schematic
4.1
Recommended Components
Table 6
Resistor
RSG
RLD
ROV
RLC
RREF
RR
RT
RRX
RTX
RB
RFB
R1
Resistors (values according to IEC E96 series)
Value
Tolerance Specification
0 Ω
49.9 kΩ
User programmable
38.3 kΩ
49.9 kΩ
64.9 kΩ
105 kΩ
52.3 kΩ
24.9 kΩ
22.1 kΩ
depending on codec
604 kΩ
604 kΩ
249 kΩ
280 kΩ
330 Ω
Line resistor, 40 Ω
1%
1%
–
1/10 W
1/10 W
–
1%
1%
1%
1%
1%
1%
1%
–
1%
1%
1%
1%
5%
1%
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
1/10 W
–
1/10 W
1/10 W
1/10 W
1/10 W
2 W
R2
R3
R4
RRT
RF1, RF2
–
Table 7
Capacitor Value
Capacitors (values according to IEC E96 series)
Tolerance Specification
CVB
CVB2
CTC
CRC
CHP
CVCC
CLP
100 nF
150 nF
2.2 nF
2.2 nF
47 nF
100 nF
150 nF
100 nF
10%
10%
10%
10%
10%
10%
10%
10%
100 V
100 V
100 V
100 V
100 V
10 V
100 V
10 V
CTX
Data Sheet
27
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Application Schematic
Table 7
CGG
C1
Capacitors (values according to IEC E96 series) (cont’d)
220 nF
330 nF
330 nF
10%
10%
10%
100 V
63 V
63 V
C2
Table 8
Diode
DVB
DVB2
DBB
Diodes
Value
1N4448
1N4448
1N4448
1N44481)
Tolerance Specification
DHP
1) It is required to connect DHP beween terminals HP and ground if CHP > 47 nF
OVP
Secondary protection (Bournes TISP PBL2). The ground terminals of the secondary
protection should be connected to the common ground on the Printed Board Assembly
with a track as short and wide as possible, preferably to a ground plane.
4.2
Design Supporting Tools
The following supporting tools are available for the PBL 38621/2:
• Test board TB 208 for PLCC package
• Test board TB 208SSOP for SSOP package
• Pspice model for PBL 38621/2
Data Sheet
28
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Transmission
5
Transmission
5.1
General
A simplified AC model of the transmission circuit is shown in Figure 9.
TIP
RF
TIPX
HP
IL
+
ZL
+
_
VTR
ZTR
VTX
RHP
+
+
VTX
EL
G2-4S
_
_
IL
_
ZT
RING RF
RINGX
IL/
ZRX
RSN
+
RSN
PBL 38621
VRX
_
ac_sch_21
Figure 9
Simplified AC Model of PBL 38621/2
Circuit analysis from the AC model in Figure 9 yields following equations:
VTX
VTR = --------------- + IL × 2RF
G2 – 4S
[1]
IL
VTX VRX
------------ = --------- + ---------
[2]
[3]
αRSN
ZT ZRX
VTR = EL – IL × ZL
Data Sheet
29
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Transmission
where:
VTX
Is the ground referenced version of the AC metallic voltage between the
TIPX and RINGX terminals.
VTR
EL
IL
Is the AC metallic voltage between TIP and RING.
Is the line open circuit AC metallic voltage.
Is the AC metallic current.
RF
Is a fuse resistor.
G2-4S
Is the programmable SLIC two-wire to four-wire gain (transmit
direction)1).
ZL
Is the line impedance.
ZRX
ZT
VRX
αRSN
Controls four- to two-wire gain.
Determines the SLIC TIPX to RINGX impedance at voice frequencies.
Is the analog ground referenced receive signal.
Is the receive summing node current to metallic loop current gain.
αRSN = 200
1) The SLIC two-wire to four-wire gain, G2-4S, is user programmable beween two fixe values. See Table 5.
5.2
Two-Wire Impedance
To calculate ZTR, the impedance presented to the two-wire line by the SLIC including the
fuse resistor RF, let VRX = 0.
From Equation [1] and Equation [2]:
ZT
ZTR = ----------------------------------- + 2RF
αRSN × G2 – 4S
[4]
[5]
Thus with ZTR, G2-4S, αRSN and RF known:
ZT = αRSN × G2 – 4S × (ZTR – 2RF)
5.3
Two-Wire to Four-Wire Gain
From Equation [1] and Equation [2] with VRX = 0:
ZT ⁄ αRSN
----------------------------------------------------
ZT
VTX
---------
G2 – 4
=
=
[6]
VTR
----------------------------------- + 2RF
αRSN × G2 – 4S
Data Sheet
30
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Transmission
5.4
Four-Wire to Two-Wire Gain
From Equation [1] to Equation [3] with EL = 0:
ZT
ZL
VTR
G4 – 2 = --------- = –
VRX
1
--------- --------------- -----------------------------------------------------------------
×
×
[7]
G2 – 4S
ZRX
ZT
----------------------------------- + ZL + 2RF
αRSN × G2 – 4S
For applications where
ZT
----------------------------------- + 2RF = ZL
αRSN × G2 – 4S
[8]
[9]
the expression for G4-2 simplifies to:
ZT
1
--------------------------
G4 – 2 = –
×
---------
ZRX
2 × G2 – 4S
5.5
Four-Wire to Four-Wire Gain
From Equation [1] to Equation [3] with EL = 0:
ZT
ZL + 2RF
VTX
G4 – 4 = --------- = –
VRX
--------- -----------------------------------------------------------------
×
[10]
ZRX
ZT
----------------------------------- + ZL + 2RF
αRSN × G2 – 4S
5.6
Hybrid Function
The hybrid function can easily be implemented utilizing the uncommitted amplifier in
conventional non software programmable codec/filters. Please, refer to Figure 10. Via
impedance ZB a current proportional to VRX is injected into the summing node of the
combination codec/filter amplifier. As can be seen from the expression for the four-wire
to four-wire gain, G4-4, a voltage proportional to VRX is returned to VTX. This voltage is
converted by RTX to a current flowing into the same summing node. These currents can
be made to cancel by letting:
VTX VRX
--------- + --------- = 0
(EL = 0)
RTX ZB
[11]
Data Sheet
31
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Transmission
The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the
balance network ZB can be calculated from:
ZT
----------------------------------- + ZL + 2RF
αRSN × G2 – 4S
VRX
ZRX
×
---------
--------- -----------------------------------------------------------------
ZB = –RTX ×
= RTX ×
[12]
VTX
ZT
ZL + 2RF
When selecting the RTX resistance value, make sure the load resistance on the VTX
terminal is at least 20 kΩ.
If calculation of the ZB formula above yields a balance network containing an inductor,
an alternate method is recommended.
The PBL 38621/2 SLIC may also be used together with programmable CODEC/filters.
The programmable CODEC/filter allows for system controller adjustment of hybrid
balance to accomodate different line impedances without change of hardware. In
addition, the transmit and receive gain may be adjusted. Please, refer to the
programmable CODEC/filter data sheets for design information.
RFB
RTX
VTX
VT
PBL 38621
ZT
ZB
Codec/Filter
ZRX
VRX
RSN
Hybrid_21
Figure 10
Hybrid Function
Data Sheet
32
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Transmission
5.7
Longitudinal Impedance
A feedback loop within the SLIC counteracts longitudinal voltages at the two-wire port by
injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will
appear as longitudinal currents and the TIPX and RINGX terminals will experience very
small longitudinal voltage excursions, leaving metallic voltages well within the SLIC
common mode range.
The SLIC longitudinal impedance per wire, ZLOT and ZLOR, appears as typically 20 Ω to
longitudinal disturbances. It should be noted that longitudinal currents may exceed the
DC loop current without disturbing the VF transmission.
5.8
Capacitors CTC and CRC
The capacitors designated CTC and CRC in Figure 8, connected beween TIPX and
ground as well as beween RINGX and ground, can be used for RFI filtering. The
recommended value for CTC and CRC is 2200 pF. Higher capacitance values may be
used, but care must be taken to prevent degradation of either longitudinal balance or
return loss. CTC and CRC contribute to a metallic impedance of 1/(π × f × CTC) =
1/(π × f × CRC), a TIPX to ground impedance of 1/(2π × f × CTC) and a RINGX to ground
impedance of 1/(2π × f × CRC).
5.9
AC - DC Separation Capacitor, CHP
The high pass filter capacitor connected between terminals HP and TIPX provides the
separation of the AC and DC signals, such that only AC signals are forwarded to the VTX
terminal. CHP positions the low end frequency response break point of the AC feedback
loop in the SLIC. The CHP value of 47 nF will position the low end frequency response
3 dB break point of the AC loop at 5.6 Hz (f3dB) according to f3dB = 1/(2π × RHP × CHP)
where RHP = 600 kΩ.
5.10
High-pass Transmit Filter
The capacitor CTX in Figure 8 connected between the VTX output and the CODEC/filter
forms, together with RTX and/or the input impedance of a programmable CODEC/filter, a
high-pass RC filter. It is recommended to position the 3 dB break point of this filter
between 30 and 80 Hz to get a faster response for the DC steps that may occur at DTMF
signalling.
5.11
Capacitor CLP
The capacitor CLP, which connects between the terminals LP and VBAT, positions the
high end frequency break point of the low pass filter in the DC feedback loop (battery
feed controlling loop) of the SLIC. CLP together with CHP and ZT(see Chapter 5.2) forms
the total two-wire output impedance of the SLIC. The choise of these programmable
Data Sheet
33
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Transmission
components have an influence on the power supply rejection ratio (PSRR) from VBAT
to the two-wire side at sub audio frequencies.At these frequencies CLP also influences
the transversal to longitudinal balance in the SLIC. Table 9 suggests a suitable value on
CLP. The typical value of the transversal to longitudinal balance at 200 Hz is given in the
table below, for the chosen value on CLP.
Table 9
Symbol
RFeed
RSG
CLP
Feeding Setup
Value
2x25
0
150
-46
47
Unit
Ω
Specification
–
–
–
–
–
kΩ
nF
dB
nF
T-L bal. @ 200 Hz
CHP
Data Sheet
34
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Battery Feed
6
Battery Feed
The PBL 38621/2 SLIC emulate a battery characteristic with current limitation
adjustable. The open loop voltage measured between the TIPX and RINGX terminals is
tracking the battery voltage VBAT. The signalling headroom, or overhead voltage VTRO, is
programmable with a resistor ROV connected between terminal POV on the SLIC and
ground. Please refer to Chapter 6.2. The battery voltage overhead,VOH, depends on the
programmed signal overhead voltage VTRO. VOH defines the TIP and RING voltage at
open loop conditions according to
VTR(at IL = 0 mA) = |VBAT| - VOH
Refer to the table below for the typical value on VOH.
Table 10
Symbol
VOH
Battery Overhead
Value (typ)
Unit
V
Specification
–
2.5 + VTRO
The current limit (reference A - C in Figure 12) is adjusted by connecting a resistor, RLC,
between terminal PLC and ground according to the equation:
where RLC is in kΩ for ILProg in mA.
1000
ILProg = ----------- – 4, 0
[13]
RLC
A second lower battery voltage may be connected to the device at terminal VBAT2 to
reduce short loop power dissipation.
The SLIC automatically switches between the two battery supply voltages without need
for external control. The silent battery switching occurs when the line voltage passes the
value
|VB2| - 40 × IL - VTRO = 3.6
For correct functionality it is important to connect the terminal VBAT2 to the second
power supply via the diode DVB2, see Figure 8. An optional diode DBB connected
between terminal VBAT and the VB2 power supply, see Figure 8, will make sure that the
SLIC continues to work on the second battery even if the first battery voltage disappears.
If a second battery voltage is not used, VBAT2 is connected to VBAT on the SLIC and
CVB2, DBB and DVB2 are removed.
6.1
CODEC Receive Interface
The PBL 38621/2 SLIC has got a receive interface at the four- wire side which makes it
possible to reduce the number of capacitors in the applications and to fit both single and
dual battery feed CODECs. The RSN terminal, connecting to the CODEC receive output
via the resistor RRX, is DC biased with +1.25 V. This makes it possible to compensate for
Data Sheet
35
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Battery Feed
currents floating due to DC voltage differences between RSN and the CODEC output
without using any capacitors. This is done by connecting a resistor RR between the RSN
terminal and ground. With current directions defined as in Figure 11, current summation
gives:
1, 25 – VCODEC
1, 25
RT
1, 25
RR
– IRSN = IRT + IRRX + IRR = ------------- + ----------------------------------------- + -------------
[14]
RRX
where VCODEC is the reference voltage of the CODEC at the receive output. From this
equation the resistor RR can be calculated as
1, 25
RR = -------------------------------------------------------------------------------------
[15]
1, 25 – VCODEC
1, 25
– IRSN – ------------- – -----------------------------------------
RT
RRX
For the value on IRSN, see table below. The resistor RR has no influence in the AC
transmission.
Table 11
Symbol
IRSN
Internal bias current of RSN
Value (typ)
-55
Unit
µA
VTX
RT
DC-GND
CODEC
I
IRT
RRX
IRSN
IRX
_
+
RSN
IRR
+1.25
UREFcodec
RR
codecIF
Figure 11
Codec Receive Interface
Data Sheet
36
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Battery Feed
A
B
C
D
E
VTR [V]
batfeed21
Figure 12
Battery Feed Characteristics
A
IL(@VTR = 0) = ILProg
B
C
Constant current
103
RLC
–3
I
LConst(typ) = ILProg =
--------- – 4× 10
VTR = |VBAT| - VOH -50 x ILProg
D
E
R
FEED = 2 × 25 Ω
VTROpen = |VBAT| - VOH
Data Sheet
37
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Battery Feed
6.2
Programmable Overhead Voltage (POV)
With the POV function the overhead voltage can be increased. If the POV pin is left open
the overhead voltage is internally set to 1.1 VPeak. The overhead voltage is equal in on-
hook and off-hook. If a resistor ROV is connected between the POV pin and AGND, the
overhead voltage can be set to higher values, typical values can be seen in Figure 13.
The ROV and corresponding VTRO (signal headroom) are typical values for THD < 1% and
the signal frequency 1000 Hz.
Observe that the four-wire output terminal VTX can not handle more than 3.2 VPeak. So if
the two- to four-wire gain is 0 dB, 3.2 VPeak is maximum also for the two-wire side. Signal
levels between 3.2 and 6.4 VPeak on the two-wire side can be handled with the PTG
shorted so that the gain G2-4S becomes -6.02 dB. Please note that:
• ZT
• RR
• G4 - 4
has to be recalculated if the PTG is shorted.
Please note that the maximum signal current at the two-wire side can not be greater than
9 mA.
How to use POV:
1. Decide what overhead voltage (VTRO) is needed. The POV function is only needed if
the overhead voltage exceeds 1.1 VPeak
.
2. In Figure 13 the corresponding ROV for the decided VTRO can be found.
3. If the overhead voltage exceeds 3.2 VPeak, the G2-4S gain has to be changed to -6.02
dB by connecting PTG pin to AGND
7
6
5
4
3
2
1
0
0
10
20
30
40
50
60
ROV(kohm)
POV
Figure 13
Programmable Overhead Voltage (POV). RL= 600 Ω or Infinitive
Data Sheet
38
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Loop Monitoring Functions
6.3
Analog Temperature Guard
The widely varying environmental conditions in which SLICs operate may lead to the
chip temperature limitations being exceeded The PBL 38621/2 SLIC reduce the DC line
o
current when the chip temperature reaches approximately 145 C and increases line
current again automatically when the temperature drops. Accordingly transmission is not
lost under high ambient temperature conditions.
The detector output, DET, is forced to a logic low level when the temperature guard is
active.
7
Loop Monitoring Functions
The loop current, ground key and ring-trip detectors report their status through a
common output, DET. The particular detector to be connected to the detector pin, DET,
is selected via the three bit control interface C1, C2 and C3. Please refer to Chapter 9
for a description of the control interface.
7.1
Loop Current Detector
The loop current detector indicates that the telephone is off-hook and that DC current is
flowing in the loop by setting the output pin DET to a logic low level when selected. The
loop current detector threshold value, ILTh, where the loop current detector changes
state, is programmable with the RLD resistor. RLD connects between pin PLD and ground
and is calculated according to:
500
RLD = ---------
[16]
ILth
The loop current detector is internally filtered and is not influenced by the AC signal at
the two-wire side.
7.2
Ground Key Detector
The ground key detector is indicating when the ground key is pressed (active) by putting
the output pin DET to a logical high level, when selected. The ground key detector circuit
senses the difference between TIPX and RINGX currents. When the current at the
RINGX side exceeds the current at the TIPX side with the threshold value, the detector
is triggered. For threshold current values, please refer to the datasheet.
Data Sheet
39
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Relay Driver
7.3
Ring Trip Detector
Ring trip detection is accomplished by connecting an external network to a comparator
in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced
superimposed on VB or GND. The unbalanced ringing source may be applied to either
the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC
ring relay driver connects the ringing source to tip and ring.
The ring trip function is based on a polarity change at the comparator input when the line
goes off-hook. In the on-hook state no DC current flows through the loop and the voltage
at comparator input DT is more positive than the voltage at input DR. When the line goes
off-hook, while ring relay is energized, DC current flows and the comparator input voltage
reverses polarity.
Figure 8 gives an example of a ring trip detector network. This network is applicable
when the ring voltage is superimposed on VB and is injected on the ring lead of the two-
wire port. The DC voltage across sense resistor RRT is monitored by the ring trip
comparator input DT and DR via the network R1,R2 ,R3 ,R4 ,C1 and C2.
When the line is on-hook (no DC current), DT is more positive than DR and the DET
output will report logic level high, that is the detector is not tripped. When the line goes
off-hook, while ringing, a DC current will flow through the loop including sense resistor
RRT and will cause input DT to become more negative than input DR. This changes
output DET to logic level low, that is tripped detector conditions. The system controller
(or line card processor) responds by de-energizing the ring relay, that is ring trip.
Complete filtering of the 20 Hz AC component at terminal DT and DR is not necessary.
A toggling DET output can be examined by a software routine to determine the duty
cycle. When the DET output is at logic level low for more than half the time, off-hook
conditions is indicated.
8
Relay Driver
The PBL 38621/2 SLIC incorporates a ring relay driver designed as open collector (npn),
with a current sinking capability of 50 mA. The drive transistor emitter is connected to
BGND. The relay driver has an internal zener diode clamp for inductive kick back
voltages.
Data Sheet
40
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Control Inputs
9
Control Inputs
The SLIC has three digital control inputs, C1, C2 and C3. A decoder in the SLIC
interprets the control input condition and determining the commanded operating state.
C1, C2 and C3 are internally pulled up.
9.1
Open Circuit (C3, C2, C1 = 0, 0, 0)
In the Open Circuit the TIPX and RINGX line drive amplifiers as well as other circuit
blocks are powered down. This causes the SLIC to present a high impedance to the line.
Power dissipation is at a minimum and no detectors are active. DET output is set high.
9.2
Ringing (C3, C2, C1 = 0, 0, 1)
The ring relay driver and the ring trip detector are activated and the ring trip detector is
indicating off-hook with a logic low level at the detector output.
As the SLIC do not have any stand by state the SLIC will remain in the active normal
state.
9.3
Active States
TIPX is the terminal closest to ground and sources loop current while RINGX is the more
negative terminal and sinks loop current. VF signal transmission is normal. The loop
current detector is activated. The loop current detector indicates off-hook with a logic low
level and the ground key detector is indicating active ground key with a logic high level
present at the detector output.
10
Overvoltage Protection
10.1
Overvoltage Protection - General
The SLIC must be protected against foreign voltages on the telephone line.
Overvoltages can result from lightning, AC power contact, induction and other causes.
Refer to Table 3, TIPX and RINGX terminals, for maximum continuous and transient
voltages that may be applied to the SLIC.
10.2
Secondary Protection
The circuit shown in Figure 8 utilizes series resistors (RF1, RF2) together with a
programmable overvoltage protector (OVP, for example Bournes TISP PBL2) as
secondary protection.
The TISP PBL2 is a dual forward-conducting buffered p-gate overvoltage protector. The
protector gate references the protection (clamping) voltage to the negative supply
Data Sheet
41
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Power-Up Sequence
voltage (that is the battery voltage, VB). As the protection voltage will track the negative
supply voltage the overvoltage stress on the SLIC is minimized.
Positive overvoltages are clamped to ground by a diode. Negative overvoltages are
initially clamped close to the SLIC negative supply rail voltage and the protector will
crowbar into a low voltage on-state condition, by firing an internal thyristor.
A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high
enough current to quickly turn on the thyristor in the protector. CGG should be placed
close to the overvoltage protection device. Without the capacitor even the low
inductance in the track to the VB supply will limit the current and delay the activation of
the thyristor clamp.
The fuse resistors RF serve the dual purposes of being non-destructive energy
dissipators when transients are clamped, and of being fuses when the line is exposed to
a power cross. If a PTC is choosen for RF, note that it is important to always use PTC’s
in series with resistors not sensitive to temperature, as the PTC will act as a capacitance
for fast transients and therefore will not protect the SLIC.
11
Power-Up Sequence
No special power-up sequence is necessary, except that ground has to be present
before all other power supply voltages.
12
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout is essential for proper function. The
components connection to the RSN input should be placed in close proximity to that pin,
such that no interference is injected into the receive summing node (RSN). Ground plane
surrounding the RSN pin is advisable.
Analog Ground (AGND) should be connected to Battery Ground (BGND) on the PCB, in
one point. The capacitors for the battery should be connected with short wide leads of
the same length.
Data Sheet
42
DS1, 2003-06-25
FlexiSLIC
PBL 38621/2
Package Outlines
13
Package Outlines
The SLIC is provided in three different packages: 24-pin SSOP, 24-pin SOIC and 28-pin
PLCC.
13.1
24-pin SSOP Package
GPS05388
Figure 14
P-SSOP-24-1 (Plastic Shrink Small Outline Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
DS1, 2003-06-25
SMD = Surface Mounted Device
Data Sheet
43
FlexiSLIC
PBL 38621/2
Package Outlines
13.2
24-pin SOIC Package
0.35 x 45˚
1)
7.6 -0.2
+0.09
0.23
8˚ max
0.4 +0.8
10.3 ±0.3
1.27
0.35 +0.152)
0.1
0.2 24x
24
13
12
1
1)
15.6-0.4
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max rer side
2) Does not include dambar protrusion of 0.05 max per side
GPS05144
GPS05144
Figure 15
P-DSO-24-1 (Plastic Dual Small Outline Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
DS1, 2003-06-25
SMD = Surface Mounted Device
Data Sheet
44
FlexiSLIC
PBL 38621/2
Package Outlines
13.3
28-pin PLCC Package
GPL05039
Figure 16
P-LCC-28-2 (Plastic Leaded Chip Carrier Package)
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Dimensions in mm
DS1, 2003-06-25
SMD = Surface Mounted Device
Data Sheet
45
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