RT8805CPQVA [RICHTEK]
Two Phase General Purpose PWM Controller; 两相通用PWM控制器
| 型号： | RT8805CPQVA |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Two Phase General Purpose PWM Controller |
| 文件： | 总18页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
RT8805C
Two Phase General Purpose PWM Controller
General Description
Features
z 12V Power Supply Voltage
The RT8805C is the most compact dual-phase
synchronous buck controller in the industry specifically
designed for high power density applications. This part is
capable of delivering up to 60A output current due to its
embedded bootstrapped drivers that support 12V + 12V
driving capability.
z 2 Phase Power Conversion
z Embedded 12V Boot Strapped Driver
z Precise Core Voltage Regulation
z Low Side MOSFET RDS(ON) Current Sensing for
Power Stage Current Balance
z External Compensation
The phase currents are sensed by innovative time sharing
z Adjustable Soft-Start
RDS(ON) current sensing technique for current balance and
z Adjustable Frequency and Typical at 300kHz Per
Phase
over current balance. Using one commonGM amplifier to
sense two phase currents eliminates offset and
nonlinearity of the GM amplifier and yields good current
balance. Other features include adjustable operation
frequency from 50kHz to 1MHz, adjustable soft-start,
PGOOD, external compensation, enable/shutdown for
various application and performance consideration.
z Power Good Indication
z Adjustable Over Current Protection
z External Reference Voltage Tracking (RT8805CxQVA)
z Small 16-Lead and 24-Lead VQFN Packages
z RoHS Compliant and 100% Lead (Pb)-Free
The RT8805C comes to a tiny footprint package of
VQFN-16L 3x3 and VQFN-24L 4x4 packages.
Applications
z Middle-High EndGPU Core Power
z High End Desktop PC Memory Core Power
z Low Output Voltage, High PowerDensityDC-DC
Converters
Ordering Information
RT8805C
Package Type
QV : VQFN-16L 3x3 (V-Type)
QVA : VQFN-24L 4x4 (V-Type)
z Voltage Regulator Modules
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area, otherwise visit our website for detail.
Note :
Richtek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
DS8805C-03 August 2007
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1
Preliminary
RT8805C
Pin Configurations
(TOP VIEW)
24 23 22 21 20 19
1
2
3
4
5
6
18
17
16
15
14
13
PHASE1
UGATE1
BOOT1
AGND
IMAX
UGATE2
BOOT2
PGOOD
PI
16 15 14 13
UGATE1
BOOT1
AGND
12 PHASE2
1
2
3
4
UGATE2
BOOT2
PGOOD
11
10
9
GND
GND
17
IMAX
FB
5
6
7
8
25
NC
COMP
7
8
9
10 11 12
VQFN-16L 3x3
VQFN-24L 4x4
Typical Application Circuit
V
IN
RT8805CxQV
C5
R
R8
9
BOOT1
2
1
3.3V
12V
PGOOD
CC
CC
BOOT1
R9
14
C9
VCC
C4
UGATE1
Q1
Q2
R
UGATE1
R1
R2
L1
5
16
15
RT
V
PHASE1
LGATE1
OUT
4
3
R
C
PHASE1
PHASE1
IMAX
AGND
C8
R
8
7
BOOT2
10
11
FB
BOOT2
UGATE2
PHASE2
LGATE2
C1
COMP
C6
C7
L2
C2
Q5
Q3
Q4
R3
R
UGATE2
12
13
6
SS
R
PHASE2
PHASE2
EN
GND
C3
R
C
R4
C
R5
FigureA. Application Circuit for RT8805CxQV (VQFN-16L 3x3)
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DS8805C-03 August 2007
2
Preliminary
RT8805C
V
IN
RT8805CxQVA
C5
R
R8
C9
BOOT1
16
3
2
3.3V
12V
PGOOD
CC
BOOT1
R9
21
22
VCC
CC
C4
UGATE1
Q1
Q2
R
UGATE1
15
7
L1
PI
1
V
PHASE1
LGATE1
OUT
R1
R2
RT
R
C
PHASE1
PHASE1
23
5
4
IMAX
C8
R
AGND
BOOT2
17
18
BOOT2
UGATE2
PHASE2
LGATE2
14
13
FB
C1
C6
C7
L2
Q3
Q4
COMP
R
UGATE2
C2
R3
19
12
11
SS
R
PHASE2
PHASE2
20
EN
GND
Q5
C3
R
C
R4
R5
C
Figure B. Application Circuit for RT8805CxQVA(VQFN-24L 4x4)-Standalone Mode (PIDisabled)
V
IN
RT8805CxQVA
C5
R
R8
C9
BOOT1
16
3
2
3.3V
12V
PGOOD
CC
BOOT1
R9
21
22
VCC
CC
C4
UGATE1
Q1
Q2
R
UGATE1
15
7
L1
R
PI
1
V
PHASE1
LGATE1
OUT
R1
R2
RT
R10
PHASE1
PHASE1
23
5
4
C
IMAX
C8
R
AGND
BOOT2
17
18
BOOT2
UGATE2
PHASE2
LGATE2
14
13
FB
C1
C6
C7
L2
Q3
Q4
COMP
R
UGATE2
C2
R3
19
12
11
SS
R
PHASE2
PHASE2
20
EN
GND
Q5
C3
R
R4
R5
C
C
Figure C. Application Circuit for RT8805CxQVA(VQFN-24L 4x4)-Tracking Mode (PI Enabled)
DS8805C-03 August 2007
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3
Preliminary
RT8805C
Function Block Diagram
RT8805CxQV (VQFN-16L 3x3)
V
BOOT1
CC
PWMCP
-
UGATE1
PHASE1
PGOOD
PWM1
Logic
+
V
CC
0.8V
+
LGATE1
EA
FB
-
BOOT2
V
CC
COMP
UGATE2
PHASE2
PWMCP
+
External
Soft Start
PWM2
Logic
V
CC
-
SS
LGATE2
RAMP1
RAMP2
CLK1
CLK2
AGND
Current
Balance
PHASE2
PHASE1
-
MUX
S/H
GM
+
OCP
OC
IMAX
VCC
To PWM Logic
Reg
V
DD
Central
Logic
PGOOD
CLK1
CLK2
Clock
RT
OC
GND
RT8805CxQVA(VQFN-24L 4x4)
BOOT1
V
CC
PGOOD
0.8V
PWMCP
UGATE1
PHASE1
-
PWM1
Logic
+
V
CC
V
REF_SEL
+
LGATE1
PI
EA
FB
-
BOOT2
V
CC
COMP
UGATE2
PHASE2
PWMCP
External
Soft Start
+
-
PWM2
Logic
V
CC
SS
LGATE2
RAMP1
RAMP2
CLK1
CLK2
S/H
AGND
Current
Balance
PHASE2
PHASE1
-
MUX
GM
+
OCP
OC
IMAX
VCC
To PWM Logic
Reg
V
DD
Central
Logic
PGOOD
CLK1
CLK2
Clock
RT
OC
GND
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4
DS8805C-03 August 2007
Preliminary
RT8805C
Functional Pin Description
Pin No.
Pin Name
Pin Function
VQFN-16L 3x3
16
VQFN-24L 4x4
1
These pins are return nodes of the high-side driver. Connect
These pins to high-side MOSFET sources together with the
low-side MOSFET drains and the inductors.
PHASE1
12
1
19
2
PHASE2
UGATE1
UGATE2
BOOT1
BOOT2
AGND
Upper Gate Drive. These pins drive the gates of the high
side MOSFETs.
11
2
18
3
Bootstrap Power Pin. These pins power the high-side
MOSFET drivers. Connect These pins to the junctions of the
bootstrap capacitors.
10
3
17
4
Chip Analog Ground.
Maximum Current Setting. This pin sets the current limiting
level. Connect this pin with resistor to ground to set the
current limit.
4
5
IMAX
--
5
6, 8, 9, 10, 24 NC
No Internal Connection.
Timing Resistor. Connect a resistor from RT to AGND to set
the clock frequency.
7
RT
11,
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
Soft-Start Pin. This pin provides soft-start function for
controller. The COMP voltage of the converter follows the
ramping voltage on the SS pin.
Exposed Pad (17)
6
GND
Exposed Pad (25)
12
SS
Compensation Pin. This pin is output node of the error
amplifier.
Feedback Pin. This pin is negative input pin of the error
amplifier.
7
8
13
14
COMP
FB
Power Good. PGOOD is an open drain output used to
indicate the status of the voltages on SS pin and FB pin.
PGOOD will go high impedance when SS > 3.7V and FB >
0.6V.
9
16
PGOOD
15
13
23
20
LGATE1
LGATE2
Lower Gate Drive. These pins drive the gate of the lowside
MOSFETs.
The VCC pin is the external 12V power. Internal 5V power
14
--
21, 22
15
VCC
PI
(V ) is regulated from this pin. This pin also powers the low
side MOSFET drivers.
DD
External reference voltage pin. This pin sets the voltage of
FB pin when close loop.
DS8805C-03 August 2007
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5
Preliminary
RT8805C
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VCC -------------------------------------------------------------------------------------------------- −0.3V to 16V
z PHASE to GND
DC------------------------------------------------------------------------------------------------------------------------- −5V to 15V
< 200ns ------------------------------------------------------------------------------------------------------------------ −10V to 30V
z BOOT to PHASE ------------------------------------------------------------------------------------------------------ 15V
z BOOT toGND
DC------------------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V
< 200ns ------------------------------------------------------------------------------------------------------------------ −0.3V to 42V
z Input, Output or I/O Voltage ----------------------------------------------------------------------------------------- GND-0.3V to 7V
z Power Dissipation, PD @ TA = 25°C
VQFN−16L 3x3--------------------------------------------------------------------------------------------------------- 1.47W
VQFN−24L 4x4--------------------------------------------------------------------------------------------------------- 1.923W
z Package Thermal Resistance (Note 4)
VQFN−16L 3x3, θJA --------------------------------------------------------------------------------------------------- 68°C/W
VQFN−24L 4x4, θJA --------------------------------------------------------------------------------------------------- 52°C/W
z Junction Temperature ------------------------------------------------------------------------------------------------- 150°C
z Lead Temperature (Soldering, 10 sec.)--------------------------------------------------------------------------- 260°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 1.5kV
MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Voltage --------------------------------------------------------------------------------------------------------- 9V to 14V
z Junction Temperature Range---------------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range---------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter
Supply Input
Symbol
Test Conditions
Min
Typ
Max Units
Power Supply Voltage
Power On Reset
V
--
5.4
--
12
5.9
0.3
10
15
6.5
--
V
V
CC
V
CC
Power On Reset Hysteresis
Power Supply Current
V
I
V
SS
= 0V
--
--
mA
V
VCC
ON
PI Threshold
VEN
VEN
--
0.3
50
--
Hysteresis
--
--
mV
Soft Start
Soft Start Current
Oscillator
I
8
10
15
μA
SS
Free Running Frequency
Frequency Variation
Frequency Range
Maximum Duty Cycle
f
RT = 33kΩ
255
-15
50
300
--
345
15
kHz
%
OSC
300
75
1000
80
kHz
%
70
To be continued
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6
DS8805C-03 August 2007
Preliminary
RT8805C
Parameter
Ramp Amplitude
Symbol
Test Conditions
Min
Typ
Max Units
--
1.6
0.8
--
V
V
Reference Voltage
Feedback Voltage
Error Amplifier
V
V
FB
= 0.8V
0.792
0.808
FB
DC Gain
60
6
70
10
--
--
--
--
dB
MHz
μA/V
μA
Gain-Bandwidth Product
Trans-conductance
MAX Current (Source & Sink)
Current Sense GM Amplifier
OC
GBW
GM
C
R
= 5pF
LOAD
600
300
660
360
= 20kΩ
= 2.5V
LOAD
I
V
COMP
COMP
--
-220
--
mV
V
R
= 33kΩ
IMAX
PHASE
Gate Driver
Maximum Upper Drive Source
Upper Drive Sink
I
BOOT − PHASE = 12V
1
--
1
--
3.5
--
--
7
A
Ω
A
Ω
UGATE(MAX)
R
V
= 1V
= 12V
= 1V
UGATE
UGATE
Maximum Lower Drive Source
I
PV
V
--
4
LGATE(MAX)
CC
Lower Drive Sink
R
--
2
LGATE
LGATE
Protection
Under Voltage Protection
Power Sequence
0.55
0.6
0.65
V
Power Good Threshold
Power Good Output Low Voltage
Measure SS Voltage
3.4
--
3.8
4.2
0.2
V
V
0.05
I
= 4mA
PGOOD
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard.
DS8805C-03 August 2007
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7
Preliminary
RT8805C
Typical Operating Characteristics
Phase Loading vs. Output Loading
VREF vs. Temperature
30
0.7945
0.794
Low-Side : IPD06N03
High-Side : IPD09N03
25
0.7935
0.793
20
PHASE2
0.7925
0.792
15
PHASE1
0.7915
0.791
10
0.7905
0.79
5
0
0.7895
5
10
15
20
25
30
35
40
45
50
-40 -25 -10
5
20 35 50 65 80 95 110 125
Output Loading (A)
Temperature (°C)
FOSC vs. Temperature
Dead Time
306
304
302
300
298
296
294
Low-Side : IPD06N03
High-Side : IPD09N03
No Load
RRT = 33k
UGATE
PHASE
LGATE
UGATE-PHASE
(5V/Div)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Time (100ns/Div)
(°C)
Temperature
OCP
OCP
Start up then Short, CSS = 0.1μF
VOUT
(1V/Div)
VOUT
(100mV/Div)
SS
(5V/Div)
IL
IL
(20A/Div)
(10A/Div)
SS
UGATE
(2V/Div)
(20V/Div)
Short then Start up, CSS = 0.1μF
Time (25ms/Div)
Time (25ms/Div)
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DS8805C-03 August 2007
Preliminary
RT8805C
Power On
Power Off
No Load
IOUT = 3A
VOUT
VOUT
(1V/Div)
(1V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
IL
LGATE
(10V/Div)
IL
(5A/Div)
(5A/Div)
Time (1ms/Div)
Time (100μs/Div)
Short Pulse
Shutdown by SS Pin
During Soft Start
Low-Side : IPD06N03
High-Side : IPD09N03
No Load
UGATE
UGATE-PHASE
VOUT
(500mV/Div)
PHASE
LGATE
UGATE
(10V/Div)
LGATE
(10V/Div)
(5V/Div)
Time (100μs/Div)
Time (100ns/Div)
UVP
Start Up by SS Pin
VIN = 0V, CSS = 0.1μF
No Load, CSS = 0.1μF
VOUT
(20mV/Div)
VOUT
(1V/Div)
LGATE
(10V/Div)
SS
(2V/Div)
LGATE
(10V/Div)
UGATE
(10V/Div)
UGATE
(1V/Div)
SS
(1V/Div)
Time (50ms/Div)
Time (5ms/Div)
DS8805C-03 August 2007
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9
Preliminary
RT8805C
Applications Information
Power On Reset
Frequency setting
RT8805C operates with input voltage at VCC pin ranging
from 5.9V to 15V. An internal linear regulator regulates
the input voltage to 5V for internal control circuit use. The
POR (power on reset) circuitry monitors the supply voltage
to make sure the supply voltage is high enough for
RT8805C normal work. When the regulated power
exceeds 4.2V typically, the RT8805C releases the reset
state and works according to the setting. Once the
regulated voltage is lower than 4.0V, POR circuitry resets
the chip. Hysteresis between the rising and falling
thresholds assure that once enabled, the RT8805C will
not inadvertently turn off unless the bias voltage drops
substantially (see Electrical Specifications).
The converter switching frequency is programmed by
connecting a resistor from the RT pin to GND. Figure 2
illustrates switching frequency vs. RRT.
Switching Frequency vs. RT Resistance
1200
1000
800
600
400
200
0
Enable, Soft Start and Power Good
Once POR releases, the RT8805C begins its soft start
cycle as shown in Figure 1. A10μAsource current charges
the capacitor CSS connected to SS to control the soft start
behavior of RT8805C. During soft start, SS voltage
increases linearly and clamps the error amplifier output.
Duty cycle and output voltage increase accordingly. The
soft start limits inrush current from input capacitors.
0
20
40
60
80
100
RT Resistance
(kΩ)
Figure 2. Switching Frequency vs. RRT.
Voltage Control
The voltage control loop consists of error amplifier,
multiphase pulse width modulator, drivers and power
components. As conventional voltage mode PWM
controller, the output voltage is locked at the positive input
of error amplifier and the error signal is used as the control
signal of pulse width modulator. The PWM signals of
different channels are generated by comparison of EA
output and split-phase sawtooth wave. Power stage
transforms VIN to output by PWM signal on-time ratio.
The RT8805C regards SS pin voltage higher than 3.7V as
the end of soft start cycle. Then RT8805C trip PGOOD to
high impedance if no fault occurs indicating power good.
The SS pin also act as the timer during OCP and UVP
hiccup as described in the later sections.
VDD
POR
> 3.7V
Current Sensing Setting
SS
RT8805C senses the current of low side MOSFET in each
synchronous rectifier when it is conducting for channel
current balance and OCP detecting. The multiplexer and
sensing GM amplifier converts the voltage on the sense
component (can be a sense resistor or the RDS(ON) of the
low side MOSFET) to current signal into internal circuit
(see Figure 3).
SSH
> 0.6V
FB
PGOOD
Figure 1. Power Sequence
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10
DS8805C-03 August 2007
Preliminary
RT8805C
Current Balance
PHASE1
PHASE2
RT8805C senses the voltage drop of the low-side MOS
and translates this to control the ramp signal. We can see
that the voltage signal finally injected to channel one is
proportional to (IL1 - IL2). Channel two is proportional to
(IL2 - IL1). In steady state and current balance situation,
there is no sensed signal injected into the ramp.
MUX
RAMP1
RAMP2
CLK1
CLK2
Current
Balance
-
S/H
OC
GM
+
OCP
If IL1 > IL2, the ramp bottom of channel 1 will be lifted up
and decreased the duty of UGATE1. On the other hand,
the ramp bottom of channel 2 will be pulled low to increase
the duty of UGATE2. Finally, the loop will be back to the
balance state through above mentioned negative feedback
scheme. Figure 5 shows this scheme.
IMAX
Figure 3. Current Sensing Loop
The sensing circuit gets IX = IL(S/H) x RDS(ON) x GM by
local feedback. IX is sampled and held just before low side
MOSFET turns off (See Figure 4). Therefore,
V
-
+
IN2
COMP
V
REF
Logic
&
Driver
+
-
I
L2
V
RAMP2
OUT
IX(S/H) = IL(S/H) x RDS(ON) x GM
L2
VOUT TOFF
V
IL(S/H) = IL(AVG)
−
×
,
ON2
k2 = k x R
L
2
ON2
CL
V
= k2 x I = k x V
L2
V
IN − VOUT
⎡
⎤
1
2
CSO2
ON2
V
TOFF
=
×5μs,
−
⎢
⎣
⎥
⎦
V
IN
IN1
RL
FSW = 200kHz
Logic
&
Driver
+
-
I
L1
RAMP1
⎡
⎢
⎤
⎥
⎥
⎥
V
IN − VOUT
⎛
⎝
⎞
⎟
⎠
L1
VOUT
×
×5μs
⎜
V
IN
IX(S/H) = IL(AVG)
−
⎢
2L
⎢
k1 = k x R
V
ON1
ON1
V
= k1 x I
L1
⎢
⎥
⎣
⎦
CSO1
= k x V
ON1
×RDS(ON) ×GM
Figure 5. Current Balance
Falling Slope = V
/L
Gate control
OUT
IL
a. Before SS signal reach the valley of the ramp voltage,
UGATE and LGATE will be off.
I
L(AVG)
I
L(S/H)
Inductor Current
b. If SS pin is pulled down 0.4V, UGATE and LGATE will
be off.
c. UV protect function caused by FB < 0.6V and SS >
3.7V, and controller will trigger Always Hiccup Mode.
High Side MOSFET Gate Signal
d. When OC function occurs and SS > 3.7V, a constant
current of 10μA starts to discharge the capacitor
connected to SS pin right away. When OC occurs,
UGATE and LGATE will be off. When the voltage at the
capacitor connected to SS pin pass about 0.4V, a
constant current of 10μAstarts to charge the capacitor.
The PWM signal is enable to pass to UGATE and
Low Side MOSFET Gate Signal
Figure 4. Inductor Current andGate signals
DS8805C-03 August 2007
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11
Preliminary
RT8805C
LGATE. OCP function monitors both channels, either
one can activate OCP. If the OC protection occurs three
times, OCSD(Over Current ShutDown) will be activated
and shut down the chip.
The first step is to calculate the complex conjugate poles
contributed by the LC output filter.
The output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter expressed as follows :
e. When fault conditions occur or SS < 0.4V, the current
sense function will be disabled.
1
F
P(LC)
=
Power Good
2π × L
×C
OUT
OUT
PGOODgoes high when soft-start voltage > 3.7V, and no
fault conditions.
The next step of compensation design is to calculate the
ESR zero. The ESR zero is contributed by the ESR
associated with the output capacitance. Note that this
requires that the output capacitor should have enough ESR
to satisfy stability requirements. The ESR zero of the
output capacitor expressed as follows :
Feedback Loop Compensation
The RT8805C is a voltage mode controller ; the control
loop is a single voltage feedback path including an error
amplifier and PWM comparator. In order to achieve fast
transient response and accurate output regulation, an
adequate compensator design is necessary. The goal of
the compensation network is to provide adequate phase
margin (greater than 45 degrees) and the highest 0dB
crossing frequency. To manipulate loop frequency response
under its gain crosses over 0dB at a slope of -20dB/
decade.
1
FZ(ESR)
=
2π ×COUT ×ESR
2) Compensation Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks as Figure 7 shown.
V
REF
+
R1
V
GM
COMP
V
-
OUT
FB
C2
R2
1) Modulator Frequency Equations
C1
R
RT8805C is a voltage mode buck converter using the high
gain error amplifier with transconductance (OTA,
Operational Transconductance Amplifier), as Figure 6
shown.
F
Figure 7. Compensation Loop
1
FZ1
=
The Transconductance:
2π × R2× C2
P1 = 0
ΔI
ΔV
OUT
GM =
F
M
1
Δ VM = (EA+) - (EA-) ; Δ IOUT = E/A output current.
F
P2
=
C1× C2
⎛
⎜
⎝
⎞
⎟
⎠
V
OUT
2π × R2×
C1+C2
+
EA+
EA-
Figure 8 shows theDC-DC converter's gain vs. frequency.
The compensation gain uses external impedance networks
to provide a stable, high bandwidth loop. High crossover
frequency is desirable for fast transient response, but often
jeopardize the system stability. In order to cancel one of
the LC filter poles, place FZ1 before the LC filter resonant
frequency. In the experience, place FZ1 at 10% LC filter
resonant frequency. Crossover frequency should be higher
than the ESR zero but less than 1/5 of the switching
frequency. The FP2 should be place at half the switching
frequency.
GM
R
OUT
-
Figure 6. OTATopology
This transfer function of OTAis dominated by a higherDC
gain and the output filter (LOUT and COUT) with a double
pole frequency at FLC and a zero at FESR. The DC gain of
the modulator is the input voltage (VIN) divided by the
peak to peak oscillator voltage VRAMP
.
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12
DS8805C-03 August 2007
Preliminary
RT8805C
80
60
Type 3 will induce additional one pole and one zero.
Loop Gain
Zeros :
FZ2
40
20
1
Compensation
Gain
=
2π × (R1+ R3)× C3
0
Poles :
Modulator
Gain
-20
1
F
P3
=
-40
2π × R3 × C3
10
-60
100k
1M
which is in the origin.
100
1k
10k
Frequency (Hz)
We recommend FZ1 placed in 0.5 x FP(LC); FZ2 placed in
Figure 8. Type 2 Bode Plot
FP(LC); FP3 placed in FESR and FP2 placed in 0.5 x FSW
.
Figure 11 shows Type 3 Bode Plot.
There is another type of compensation called Type 3
compensation that adds a pole-zero pair to the Type 2
network. It's used to compensate output capacitor whose
ESR value is much lower (pure MLCC or OSCON
Capacitors).
Loop Gain
60
40
Compensation Gain
20
As shown in Figure 9, to insert a network between VOUT
and FB in the original Type 2 compensation network can
result in Type 3 compensation. Figure 10 shows the
difference of theirAC response. Type 3 compensation has
an additional pole-zero pair that causes a gain boost at
the flat gain region. But the gain boosted is limited by the
ratio (R1+R4)/R4; if R3 << R4.
0
Gain
-20
-40
Modulator Gain
-60
-80
2
3
4
5
6
7
C3
R3
Log Frequency
+
R1
V
Figure 11. Type 3 Bode Plot
GM
FB
COMP
V
-
OUT
C2
R2
C1
R4
Protection
OCP
The RT8805C uses “Cycle by Cycle” current comparison.
The over current level is set by IMAX pin. When OC
function occurs and SS > 3.7V, a constant current of 10μA
starts to discharge the capacitor connected to SS pin
right away. When OC occurs, UGATE and LGATE will be
off.
Figure 9. AdditionalNetwork of Type 3 Compensation
(Add between VOUT and FB)
F
P1
Add Type 3 compensation
Pole
F
P2
F
P3
F
P2
F
F
Z1
Z2
Original Type 2 compensation
Figure 10. AC Response Curves of Type 2 and 3
DS8805C-03 August 2007
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13
Preliminary
RT8805C
When the voltage at the capacitor connected to SS pin
pass about 0.4V, a constant current of 10μA starts to
charge the capacitor. The PWM signal is enabled to pass
to the UGATE and LGATE. OCP function monitors both
channels, either one can activate OCP. If the OC protection
occurs three times, the chip will shut down and the state
will only be released by POR.
UVP
VIN = 0V
VOUT
(20mV/Div)
SS
(2V/Div)
RT8805C uses an external resistor RIMAX to set a
programmable over current trip point. OCP comparator
compares each inductor current with this reference current.
RT8805C uses hiccup mode to eliminate fault detection
of OCP or reduce output current when output is shorted
to ground. The OCP comparator compares the difference
LGATE
(10V/Div)
UGATE
(1V/Div)
Time (50ms/Div)
between IX and IIMAX
.
Figure 12. UVP (Always Hiccup Mode)
OCP Comparator
OTP
I
+
-
IMAX
I
Monitor the temperature near the driver part within the
chip. Shutdown the chip when OTP (Typical trip point :
170°C).
X
For example:
From Electrical Specifications : RIMAX = 33kΩ
General Design Guide
VPHASE = -220mV
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar
with many of the basic skills and techniques referenced
below.
Assume Low side MOSFET RDS(ON) = 3mΩ.
220mV
3mΩ
Get the OCP setting current is
(the valley of inductor's current).
=73A per PHASE
Change the setting current which you want from 73A per
PHASE to 50A per PHASE.
Power Stages
Following below steps:
Designing a multi-phase converter is to determine the
number of phases. This determination depends heavily
on the cost analysis which in turn depends on system
constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted,
the total board space available for power-supply circuitry,
and the maximum amount of load current. Generally
speaking, the most economical solutions are those in
which each phase handles between 20 to 25A(One Upper
and one Lower MOSFET). All surface-mount designs will
tend toward the lower end of this current range.
1. Calculate phase voltage. If Low side MOSFET
RDS(ON) = 3mΩ, VPHASE_new = -150mV.
-220mV
2.RIMAX_new
=
×33kΩ
VPHASE_new
RIMAX_new = 48.4kΩ
UVP
By detecting voltage at FB pin when SS > 3.7V. If
FB < 0.6V, the chip will trigger the always Hiccup mode
and a constant current source 10μA starts to charge
capacitor at SS pin when SS pass 0.4V and discharge
Css when SS > 3.7V. As Figure 12 shown.
If through-hole MOSFETs and inductors can be used,
higher per-phase currents are possible. In cases where
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14
DS8805C-03 August 2007
Preliminary
RT8805C
board space is the limiting constraint, current can be
pushed as high as 40A per phase, but these designs
require heat sinks and forced air to cool the MOSFETs,
inductors and heat dissipating surfaces.
operated under or over maximum (~125°C) operation
rating.
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly, the PCB could
radiate excessive noise and contribute to the converter
instability.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching
frequency, the capability of the MOSFETs to dissipate
heat, and the availability and nature of heat sinking and
air flow.
First, place the PWM power stage components. Mount
all the power components and connections in the top layer
with wide copper areas. The MOSFETs of Buck, inductor,
and output capacitor should be as close to each other as
possible. This can reduce the radiation of EMI due to the
high frequency current loop. If the output capacitors are
placed in parallel to reduce the ESR of capacitor, equal
sharing ripple current should be considered. Place the
input capacitor directly to the drain of high-side MOSFET.
In multi-layer PCB, use one layer as power ground and
have a separate control signal ground as the reference of
the all signal. To avoid the signal ground is effect by noise
and have best load regulation, it should be connected to
the ground terminal of output. Furthermore, follows below
guidelines can get better performance of IC :
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of two
drivers in the controller package, the total power dissipated
by both drivers must be less than the maximum allowable
power dissipation for the VQFNpackage. Calculating the
power dissipation in the drivers for a desired application
is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the
IC beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 3x3 VQFN package is approximately
1.47W at room temperature.
1. A multi-layer printed circuit board is recommended.
2. Use a middle layer of the PC board as a ground plane
and making all critical component ground connections
through vias to this layer.
According below equations at two phases operation, it’ s
clear to describe that the junction temperature of the chip
is directly proportional to the total CISS (including CUGATE
and CLGATE) of all external MOSFETs.
3. Use another solid layer as a power plane and break this
plane into smaller islands of common voltage levels.
PD = ( CUGATE x VBOOT-PHASE2 x f ) + ( CLGATE x VCC2 x f ) +
4. Keep the metal running from the PHASE terminal to
the output inductor short.
χ
TJ = TA + ( θJA x PD )
5. Use copper filled polygons on the top and bottom circuit
layers for the phase node.
(χ is the minor factor and could be ignored)
6. The small signal wiring traces from the LGATE and
UGATE pins to the MOSFET gates should be kept
short and wide enough to easily handle the several
Amperes of drive current.
For example, according to the application we evaluated
on board, the CUGATE = 1nF, CLGATE = 5nF (dual MOSFETs
in parallel), VCC = 12V, VBOOT-PHASE = 12V, and operation
frequency = 300kHz.
2
2
7. The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Position those components close to their
pins with a local GND connection, or via directly to the
ground plane.
≈
PD 1nF x 12 x 300kHz + 2 x 5nF x 12 x 300kHz =
475mW / PHASE
TJ = 30°C+ 68°C/W x 0.475W x 2 = 94.6°C
That means the junction temperature is most likely to be
DS8805C-03 August 2007
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15
Preliminary
RT8805C
8. RT and RIMAX resistors should be near the RT and RIMAX
pin respectively, and theirGNDreturn should be short,
and kept away from the noisy MOSFET GND.
9. Place the compensation components close to the FB
and COMP pins.
10. The feedback resistors for both regulators should also
be located as close as possible to the relevant FB pin
with vias tied straight to the ground plane as required.
11. Minimize the length of the connections between the
input capacitors, CIN and the power switches by placing
them nearby.
12. Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible, and
make the GND returns (From the source of lower
MOSFET to VIN, CVIN, GND) short.
13. Position the output inductor and output capacitors
between the upper MOSFET and lower MOSFET and
the load.
14. AGNDshould be on the clearer plane, and kept away
from the noisy MOSFET GND.
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16
DS8805C-03 August 2007
Preliminary
RT8805C
Outline Dimension
SEE DETAIL A
D
D2
L
1
E
E2
1
2
1
2
e
b
DETAILA
A
A3
Pin #1 ID and Tie Bar Mark Options
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.800
0.000
0.175
0.180
2.950
1.300
2.950
1.300
1.000
0.050
0.250
0.300
3.050
1.750
3.050
1.750
0.031
0.000
0.007
0.007
0.116
0.051
0.116
0.051
0.039
0.002
0.010
0.012
0.120
0.069
0.120
0.069
D
D2
E
E2
e
0.500
0.020
L
0.350
0.450
0.014
0.018
V-Type 16L QFN 3x3 Package
DS8805C-03 August 2007
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17
Preliminary
RT8805C
D2
SEE DETAIL A
D
L
1
E
E2
1
2
1
2
e
b
DETAILA
A
Pin #1 ID and Tie Bar Mark Options
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.800
0.000
0.175
0.180
3.950
2.300
3.950
2.300
1.000
0.050
0.250
0.300
4.050
2.750
4.050
2.750
0.031
0.000
0.007
0.007
0.156
0.091
0.156
0.091
0.039
0.002
0.010
0.012
0.159
0.108
0.159
0.108
D
D2
E
E2
e
0.500
0.020
L
0.350
0.450
0.014
0.018
V-Type 24L QFN 4x4 Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
www.richtek.com
18
DS8805C-03 August 2007
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