RT8803A [RICHTEK]
2/3-Phase PWM Controller for High-Density Power Supply; 三分之二相PWM控制器，用于高密度电源
| 型号： | RT8803A |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 2/3-Phase PWM Controller for High-Density Power Supply |
| 文件： | 总27页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RT8803A
2/3-Phase PWM Controller for High-Density Power Supply
General Description
Features
z 5V Power Supply
The RT8803A is a 2/3-phase synchronous buck controller
specifically designed to power Intel®/AMDnext generation
microprocessors. It implements an internal 8-bitDAC that is
identified by VIDcode of microprocessor directly. RT8803A
generates VID table that conform to Intel® VRD10.x and
VRD11 core power with 6.25mV increments and 0.5%
accuracy.
z 2/3-Phase Power Conversion with Automatic Phase
Selection
z 8-bit VID Interface, Supporting Intel VRD11/VRD10.x
and AMD K8, K8_M2 CPUs
z VR_HOT and VR_FAN Indication
z Precision Core Voltage Regulation
z Power Stage Thermal Balance by DCR Current
Sensing
RT8803Aadoptsinnovativetime-sharingDCRcurrentsensing
technique to sense phase currents for phase current balance,
load line setting and over current protection. Using a common
GM to sense all phase currents eliminates offset and linearity
variation between GMs in conventional current sensing
methods.As sub-milli-ohm-grade inductors are widely used
in modern motherboards, slight offset and linearity mismatch
will cause considerable current shift between phases. This
technique ensures good current balance at mass production.
z Adjustable Soft-start
z Over-Voltage Protection
z Adjustable Frequency and Typical at 300kHz per
Phase
z Power Good Indication
z 32-Lead VQFN Package
z RoHS Compliant and 100% Lead (Pb)-Free
Other features include over current protection, programmable
soft start, over voltage protection, and output offset setting.
RT8803A comes to a small footprint package with
VQFN-32L 5x5.
Applications
z Intel®/AMDNew generation microprocessor forDesktop
PC and Motherboard
z Low Output Voltage, High power density DC-DC
Converters
Ordering Information
RT8803A
z Voltage Regulator Modules
Package Type
QV : VQFN-32L 5x5 (V-Type)
Pin Configurations
(TOP VIEW)
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
32 31 30 29 28 27 26 25
Note :
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
VTT/EN
VR_Ready
FBRTN
FB
VID7
Richtek Pb-free and Green products are :
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
VDD
PWM3
PWM2
PWM1
ISP1
GND
COMP
SS
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
VR_FAN
VR_HOT
33
ISP2
ISP3
9
10 11 12 13 14 15 16
VQFN-32L 5x5
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1
RT8803A
Typical Application Circuit
PWM2
PWM1
FB
TSEN
OFS
FBRTN
COMP
SS
VR_Ready
VR_FAN
VR_HOT
VTT/EN
IMAX
RT
ADJ
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DS8803A-05 August 2007
RT8803A
Functional Pin Description
OFS (Pin 12)
VTT/EN (Pin 1)
The pin is defined for load line offset setting.
The pin is defined as the chip enable, and the VTT is
applied for internal VIDpull high power and power sequence
monitoring.
ADJ (Pin 13)
Current sense output for active droop adjusting. Connect
a resistor from this pin to GND to set the load droop.
VR_Ready (Pin 2)
IMAX (Pin 14)
Power good open-drain output.
The pin is defined to set threshold of over current.
FBRTN (Pin 3)
ISN1 (Pin 15)
Feedback return pin. VIDDAC and error amplifier reference
for remote sensing of the output voltage.
Current sense negative input pin for channel 1 current
sensing.
FB (Pin 4)
ISN23 (Pin 16)
Inverting input pin of the internal error amplifier.
Current sense negative input pins for channel 2 and
channel 4 current sensing.
COMP (Pin 5)
Output pin of the error amplifier and input pin of the PWM
comparator.
ISP1 (Pin 19), ISP2 (Pin 18), ISP3 (Pin 17)
Current sense positive input pins for individual converter
channel current sensing.
SS (Pin 6)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval.
PWM1 (Pin 20), PWM2 (Pin 21), PWM3 (Pin 22)
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which using 2/3/4 channels, pull PWM 3/4/5 pins up to
high.
VR_FAN (Pin 7)
The pin is defined to signal VR thermal information for
external VR thermal dissipation scheme triggering.
VR_HOT (Pin 8)
VDD (Pin 23)
The pin is defined to signal VR thermal information for
external VR thermal dissipation scheme triggering.
IC power supply. Connect this pin to a 5V supply.
VID7 (Pin 24), VID6 (Pin 25), VID5 (Pin 26), VID4 (Pin
27), VID3 (Pin 28), VID2 (Pin 29), VID1 (Pin 30),
VID0 (Pin 31), VID_SEL (32)
TSEN (Pin 9)
Temperature detect pin for VR_HOT and VR_FAN.
DAC voltage identification inputs for VRD10.x / VRD11 /
K8 / K8_M2 . These pins are internally pulled up to VTT.
DVD (Pin 10)
Programmable power UVLO detection input. Trip threshold
is 1V at VDVD rising.
VIDSEL VID [7]
Table
VTT
GND
VDD
VDD
X
X
NC
GND
VR11
VR10.x
K8
RT (Pin 11)
K8_M2
The pin is defined to set internal switching operation
frequency. Connect this pin toGNDwith a resistor RRT to
GND [Exposed pad (33)]
set the frequency FSW
.
4.463 e9
The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
F
SW
=
R
+ 3500
RT
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3
RT8803A
Function Block Diagram
VDD
VTT/EN
DVD
Oscillator
&
Ramp
SS
Power On
Reset
Soft Start
& PGOOD
RT
VR_Ready
Generator
COMP
FB
OFS
Pulse
Width
Modulator
& Output
Buffer
PWM1
PWM2
VID7
VID6
VID5
-
Current
Processing
SUM/N
& OCP
Detection
EA
+
PWM3
VID4
VID3
Clamp
DAC
VID2
VID1
IMAX
VID0
VID_SEL
ISN1
Mux
Mux
FBRTN
-
ISN23
CSA
+
ISP1
ISP2
ISP3
TSEN
Droop Tune
& Hi-I
Detection
Sample
& Hold
Temperature
Processing
Mux
VR_FAN
VR_HOT
ADJ
GND
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DS8803A-05 August 2007
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID2
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
VID1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
VID0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
VID5
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VID6
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.60000V
1.59375V
1.58750V
1.58125V
1.57500V
1.56875V
1.56250V
1.55625V
1.55000V
1.54375V
1.53750V
1.53125V
1.52500V
1.51875V
1.51250V
1.50625V
1.50000V
1.49375V
1.48750V
1.48125V
1.47500V
1.46875V
1.46250V
1.45625V
1.45000V
1.44375V
1.43750V
1.43125V
1.42500V
1.41875V
1.41250V
1.40625V
1.40000V
1.39375V
1.38750V
1.38125V
1.37500V
1.36875V
1.36250V
To be continued
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DS8803A-05 August 2007
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5
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID5
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID6
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.35625V
1.35000V
1.34375V
1.33750V
1.33125V
1.32500V
1.31875V
1.31250V
1.30625V
1.30000V
1.29375V
1.28750V
1.28125V
1.27500V
1.26875V
1.26250V
1.25625V
1.25000V
1.24375V
1.23750V
1.23125V
1.22500V
1.21875V
1.21250V
1.20625V
1.20000V
1.19375V
1.18750V
1.18125V
1.17500V
1.16875V
1.16250V
1,15625V
1.15000V
1.14375V
1.13750V
1.13125V
1.12500V
1.11875V
To be continued
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DS8803A-05 August 2007
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID2
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
VID0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
VID6
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.11250V
1.10625V
1.10000V
1.09375V
OFF
OFF
OFF
OFF
1.08750V
1.08125V
1.07500V
1.06875V
1.06250V
1.05625V
1.05000V
1.04375V
1.03750V
1.03125V
1.02500V
1.01875V
1.01250V
1.00625V
1.00000V
0.99375V
0.98750V
0.98125V
0.97500V
0.96875V
0.96250V
0.95625V
0.95000V
0.94375V
0.93750V
0.93125V
0.92500V
0.91875V
0.91250V
0.90625V
0.90000V
To be continued
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DS8803A-05 August 2007
www.richtek.com
7
RT8803A
Table 1. Output Voltage Program (VRD10.x + VID6)
Pin Name
Nominal Output Voltage DACOUT
VID4
VID3
VID2
VID1
VID0
VID5
VID6
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
0.89375V
0.88750V
0.88125V
0.87500V
0.86875V
0.86250V
0.85625V
0.85000V
0.84375V
0.83750V
0.83125V
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DS8803A-05 August 2007
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Pin Name
Nominal Output Voltage DACOUT
Nominal Output Voltage DACOUT
HEX
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
HEX
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
OFF
1.36875V
1.36250V
1.35625V
1.35000V
1.34375V
1.33750V
1.33125V
1.32500V
1.31875V
1.31250V
1.30625V
1.30000V
1.29375V
1.28750V
1.28125V
1.27500V
1.26875V
1.26250V
1.25625V
1.25000V
1.24375V
1.23750V
1.23125V
1.22500V
1.21875V
1.21250V
1.20625V
1.20000V
1.19375V
1.18750V
1.18125V
1.17500V
1.16875V
1.16250V
1.15625V
1.15000V
1.14375V
1.13750V
1.13125V
OFF
1.60000V
1.59375V
1.58750V
1.58125V
1.57500V
1.56875V
1.56250V
1.55625V
1.55000V
1.54375V
1.53750V
1.53125V
1.52500V
1.51875V
1.51250V
1.50625V
1.50000V
1.49375V
1.48750V
1.48125V
1.47500V
1.46875V
1.46250V
1.45625V
1.45000V
1.44375V
1.43750V
1.43125V
1.42500V
1.41875V
1.41250V
1.40625V
1.40000V
1.39375V
1.38750V
1.38125V
1.37500V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
To be continued
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DS8803A-05 August 2007
www.richtek.com
9
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Pin Name
Nominal Output Voltage DACOUT
Nominal Output Voltage DACOUT
HEX
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
HEX
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
1.12500V
1.11875V
1.11250V
1.10625V
1.10000V
1.09375V
1.08750V
1.08125V
1.07500V
1.06875V
1.06250V
1.05625V
1.05000V
1.04375V
1.03750V
1.03125V
1.02500V
1.01875V
1.01250V
1.00625V
1.00000V
0.99375V
0.98750V
0.98125V
0.97500V
0.96875V
0.96250V
0.95625V
0.95000V
0.94375V
0.93750V
0.93125V
0.92500V
0.91875V
0.91250V
0.90625V
0.90000V
0.89375V
0.88750V
0.88125V
0.87500V
0.86875V
0.86250V
0.85625V
0.85000V
0.84375V
0.83750V
0.83125V
0.82500V
0.81875V
0.81250V
0.80625V
0.80000V
0.79375V
0.78750V
0.78125V
0.77500V
0.76875V
0.76250V
0.75625V
0.75000V
0.74375V
0.73750V
0.73125V
0.72500V
0.71875V
0.71250V
0.70625V
0.70000V
0.69375V
0.68750V
0.68125V
0.67500V
0.66875V
0.66250V
0.65625V
0.65000V
0.64375V
To be continued
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10
DS8803A-05 August 2007
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Pin Name
Nominal Output Voltage DACOUT
Nominal Output Voltage DACOUT
HEX
9C
9D
9E
9F
HEX
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
0.63750V
0.63125V
0.62500V
0.61875V
0.61250V
0.60625V
0.60000V
0.59375V
0.58750V
0.58125V
0.57500V
0.56875V
0.56250V
0.55625V
0.55000V
0.54375V
0.53750V
0.53125V
0.52500V
0.51875V
0.51250V
0.50625V
0.50000V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C0
C1
C2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
To be continued
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11
RT8803A
Table 2. Output Voltage Program (VRD11)
Pin Name
Nominal Output Voltage DACOUT
HEX
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
OFF
OFF
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don't Care
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DS8803A-05 August 2007
RT8803A
Table 3. Output Voltage Program (K8)
Nominal Output Voltage DACOUT
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.200
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
Shutdown
Note: (1) 0 : Connected to GND
(2) 1 : Open
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13
RT8803A
Table 4. Output Voltage Program (K8_M2)
Pin Name
Nominal Output Voltage DACOUT
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
VID4
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
0.7625
0.7500
To be continued
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DS8803A-05 August 2007
RT8803A
Table 4. Output Voltage Program (K8_M2)
Pin Name
Nominal Output Voltage DACOUT
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) The voltage above are load independent for desktop and server platforms. For mobile platforms the voltage above
correspond to zero load current.
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15
RT8803A
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VDD ------------------------------------------------------------------------------------------- 7V
z Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND-0.3V to VDD+0.3V
z Power Dissipation, PD @ TA = 25°C
VQFN−32L 5x5-------------------------------------------------------------------------------------------------- 2.778W
z Package Thermal Resistance (Note 4)
VQFN-32L 5x5, θJA --------------------------------------------------------------------------------------------- 36°C/W
z Junction Temperature ------------------------------------------------------------------------------------------ 150°C
z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------- 260°C
z Storage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 3)
z Supply Voltage, VDD ------------------------------------------------------------------------------------------- 5V 10%
z Junction Temperature Range--------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range--------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VDD = 5V, TA = 25°C, unless otherwise specified)
Parameter
Supply Current
Symbol
Test Conditions
Min
Typ
Max Units
V
DD
Nominal Supply Current
Power-On Reset
POR Threshold
Hysteresis
I
PWM 1,2,3 Open
--
12
16
mA
DD
V
V
V
V
V
V
V
DD
Rising
4.0
0.2
0.9
--
4.2
0.5
1.0
60
4.5
--
V
V
DDRTH
DDHYS
DVDTH
DVDHYS
TTTH
Trip (Low to High)
Hysteresis
Enable
Enable
1.1
--
V
V
DVD
Threshold
mV
Trip (Low to High)
Hysteresis
0.75
--
0.85
0.1
0.95
--
V
TT
Threshold
V
TTHYS
Oscillator
Free Running Frequency
Frequency Adjustable Range
Ramp Amplitude
f
R
R
= 20kΩ
180
50
200
--
220
400
--
kHz
kHz
V
OSC
RT
RT
f
OSC_ADJ
ΔV
= 20kΩ
--
1.9
1.0
67
OSC
Ramp Valley
V
0.7
62
--
V
RV
Maximum On-Time of Each Channel
RT Pin Voltage
Three Phase Operation
= 20kΩ
72
1.1
%
V
R
0.9
1.0
V
RT
RT
To be continued
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DS8803A-05 August 2007
RT8803A
Parameter
Reference and DAC
Symbol
Test Conditions
Min
Typ
Max
Units
V
≥ 1V
−0.5
−5
−8
--
--
--
+0.5
+5
%
mV
mV
V
DAC
1V ≥ V
≥ 0.8V
DACOUT Voltage Accuracy
ΔV
DAC
DAC
V
DAC
< 0.8V
--
+8
DAC (VID0-VID125) Input Low
DAC (VID0-VID125) Input High
--
V
V
1/2V − 0.2
ILDAC
TT
--
--
V
1/2V + 0.2
IHDAC
TT
12
15
1.0
18
1.1
V
Pull-up Resistance
kΩ
V
ID
OFS Pin Voltage
0.9
V
OFS
R
= 100kΩ
OFS
Error Amplifier
DC Gain
--
--
--
65
10
8
--
--
--
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/μs
COMP = 10pF
Current Sense GM Amplifier
CSN Full Scale Source Current
CSN Current for OCP
Protection
100
150
--
--
--
--
I
μA
μA
ISPFSS
Over-Voltage Trip (FB-DACOUT)
IMAX Voltage
100
0.9
150
1.0
200
1.1
mV
V
ΔOVT
V
IMAX
R
= 20k
IMAX
Power Good
Output Low Voltage
--
--
0.2
V
V
I
= 4mA
PGOODL
PGOOD
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
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17
RT8803A
Typical Operating Characteristics
Frequency vs. RRT
GM
700
450
400
350
300
250
200
150
100
50
600
500
400
300
200
100
0
PHASE 3
PHASE 1
PHASE 2
0
0
10 20 30 40 50 60 70 80 90 100
0
25
50
75
100 125 150 175 200
ISN (uA)
(kΩ)
RRT (
Output Voltage vs. Temperature
Frequency vs. Temperature
1.264
1.262
1.26
322
320
318
316
314
312
310
308
306
304
1.258
1.256
1.254
1.252
1.25
1.248
-20
0
20
40
60
80
100
-20
0
20
40
60
80
100
(°C)
Temperature
Temperature
(°C)
Power On from DVD
Power Off from DVD
DVD
(1V/Div)
DVD
(1V/Div)
SS
(1V/Div)
SS
(1V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
PHASE 3
(10V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
Time (1μs/Div)
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DS8803A-05 August 2007
RT8803A
Power On from VCC12
Power Off from VCC12
VCC12
(10V/Div)
SS
VCC12
(10V/Div)
(1V/Div)
SS
(1V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
PHASE 3
(10V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
Time (1ms/Div)
Power On from VCC5
Power Off from VCC5
VCC5
(5V/Div)
SS
VCC5
(5V/Div)
(1V/Div)
SS
(1V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
PHASE 3
(10V/Div)
PHASE 3
(10V/Div)
Time (1ms/Div)
Time (25ms/Div)
Output Short Circuit
Power On with OCP
VR_Ready
(1V/Div)
VR_Ready
(1V/Div)
SS
(2V/Div)
SS
(2V/Div)
VOUT
1V/Div)
VOUT
(1V/Div)
PWM
(5V/Div)
PWM
(5V/Div)
Time (1ms/Div)
Time (500μs/Div)
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RT8803A
VOUT Overshoot
VOUT Droop
VOUT
(20mV/Div)
VOUT
(20mV/Div)
IOUT
(40A/Div)
IOUT
(40A/Div)
Time (2μs/Div)
Time (2μs/Div)
Dynamic VID
Dynamic VID
VOUT
(200mV/Div)
VOUT
(200mV/Div)
VID0
(500mV/Div)
VID0
(500mV/Div)
Time (50μs/Div)
Time (50μs/Div)
OVP
VR_Ready
(1V/Div)
SS
(2V/Div)
FB
(1V/Div)
PWM
(5V/Div)
Time (10μs/Div)
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DS8803A-05 August 2007
RT8803A
Applications Information
with Intel®VRD11 specification as shown in Figure 1. A
time-variant internal current source charges the capacitor
connected to SS pin. SS voltage ramps up piecewise
linearly and locks VID_DAC output with a specified voltage
drop. Consequently, VCORE is built up according to
VID_DAC output and meet Intel® VRD11 requirement.
VR_READY output is pulled high by external resistor when
VCORE reaches VID_DAC output with 1~2ms delay. An
SS capacitor about 47nF is recommend for VRD11
compliance.
RT8803A is a multi-phase DC/DC controller specifically
designed to deliver high quality power for next generation
CPU. RT8803A controls a special power-on sequence &
monitors the thermal condition of VR module to meet the
VRD11 requirement. Phase currents are sensed by
innovative time-sharing DCR current sensing technique
for channel current balance, droop tuning, and over current
protection. Using one common GM amplifier for current
sensing eliminates offset errors and linearity variation
between GMs. As sub-milli-ohm-grade inductors are
widely used in modern mother boards, slight mismatch
ofGM amplifiers offset and linearity results in considerable
current shift between phases. The time-sharing DCR
current sensing technique is extremely important to
guarantee phase current balance in mass production.
VDD POR, DVD, and VTT/EN ready
SS
VCORE
1.1V
VR_Ready
VID on the fly
Converter Initialization, Phase Selection, and
Power Good Function
1~2ms
1~2ms
1~2ms
1~2ms
1~2ms
The RT8803A initiates only after 3 pins are ready: VDD
pin power on reset (POR), VTT/ENpin enabled, andDVD
pin is higher than 1V. VDDPOR is to make sure RT8803A
is powered by a voltage for normal work. The rising
threshold voltage of VDD POR is 4.2V typically. At VDD
POR, RT8803Achecks PWM3, PWM4 and PWM5 status
to determine phase number of operation. Pull high PWM3
for two-phase operation; pull high PWM4 for three-phase
operation; pull high PWM5 for four-phase operation. The
unused current sense pins should be connected to GND
or left floating.
Figure 1. TimmingDiagramDuring Soft Start Interval
Voltage Control
CPU VCORE voltage is Kelvin sensed by FB and FBRTN
pins and precisely regulated to VID_DAC output by internal
high gain Error Amplifier (EA). The sensed signal is also
used for power good and over voltage function. The typical
OVP trip point is 170mV above VID_DAC output. RT8803A
pulls PWM outputs low and latches up upon OVP trip to
prevent damaging the CPU. It can only restart by resetting
one of VDD, DVD, or VTT/EN pin.
VTT/ENacts as a chip enable pin and receives signal from
FSB or other power management IC.
RT8803A supports Intel VRD10.x, VRD11, AMD K8 and
AMD K8_M2 VID specification.
DVD is to make sure that ATX12V is ready for drivers to
work normally. Connect a voltage divider fromATX12V to
DVDpin as shown in the TypicalApplication Circuit. Make
sure that DVD pin voltage is below its threshold voltage
before drivers are ready and above its threshold voltage
for minimumATX12V during normal operation.
The change of VID_DAC output at VID on the fly is also
smoothed by capacitor connected to SS pin.
Consequently, Vcore shifts to its new position smoothly
as shown in Figure 2.
If any one of VDD, VTT/EN, andDVDis not ready, RT8803A
keeps its PWM outputs high impedance and the
companion drivers turn off both upper and lower
MOSFETs. After VDD, VTT/EN, and DVD are ready,
RT8803A initiates its soft start cycle that is compliant
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21
RT8803A
Consequently, the sensing current IX is proportional to
inductor current ILX and is expressed as :
PWM3
VCORE
ILX ×DCRx
RCSNX
IX =
The sensed current IX is used for current balance and droop
tuning as described as followed. Since all phases share
one common GM, GM offset and linearity variation effect
is eliminated in practical applications. As sub-milli-ohm-
grade inductors are widely used in modern mother boards,
slight mismatch ofGM amplifiers offset and linearity results
in considerable current shift between phases. The time-
sharing DCR current sensing technical is extremely
important to guarantee phase current balance in mass
production.
VID7
Figure 2. Vcore Response at VID on the Fly
DCR Current Sensing
Phase Current Balance
RT8803Aadopts an innovative time-sharingDCR current
sensing technique to sense the phase currents for phase
current balance (phase thermal balance) and load line
regulation as shown in Figure 3. Current sensing amplifier
GM samples and holds voltages VCx across the current
sensing capacitor Cx by turns in a switching cycle.
According to the Basic Circuit Theory, if
The sampled and held phase current IX are summed and
averaged to get the averaged current
. Each phase
I
X
current IX then is compared with the averaged current.
The difference between IX and is injected to
I
X
corresponding PWM comparator. If phase current IX is
smaller than the averaged current , RT8803A increases
the duty cycle of corresponding phase to increase the
phase current accordingly and vice versa.
Lx
= Rx×Cx then VCx = I ×DCRx
LX
DCRx
T1
T2
T3
L1
DCR1
R1
C1
+ VC1 -
L3
DCR3
I
I
= I x DCR /R
LX X CSNX
X
ISP1
ISN1
T1
T3
+
CSA
-
S/H CKT
X
R3
C3
+ VC3 -
T1
T3
R
CSN1
ISP3
CSA: Current Sense Amplifier
ISN23
R
CSN3
L2
DCR2
R2
C2
+ VC2 -
ISP2
T2
ISN23
T2
R
CSN2
Figure 3
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DS8803A-05 August 2007
RT8803A
IOFS
4
L
If
X
= (R //R )× Cx then
X
PX
DCRx
R
PX
VCx =
×I ×DCRx
LX
Rx + R
PX
R
FB1
V
-
CORE
EA
COMP
With other phase kept unchanged, this phase would share
(RPX+Rx)/RPX times current than other phases. Figure 6
and 7 show different current ratio setting for the power
stage when Phase 3 is programmed 2 times current than
other phases. Figure 8 and 9 compare the above current
ratio setting results.
+
V
ADJ
4IX
DAC
R
ADJ
Figure 4. Load Line and Offset Function
Output Voltage Offset Function
L
X
I
DCRx
LX
To meet Intel®requirement of initial offset of load line,
RT8803A provides programmable initial offset function.
External resistor ROFS and voltage source at OFS pin
VOFS
VCx
-
Rx
+
Cx
R
PX
generate offset current IOFS
=
ROFS
, where VOFS is 1V typical. One quarter of IOFS flows
through RFB1 as shown in Figure 4. Error amplifier would
hold the inverting pin equal to VDAC - VADJ. Thus output
voltage is subtracted from VDAC - VADJ for a constant offset
V
OUT
T
voltage.
VCORE = VDAC − VADJ
Figure 5
RFB1
4×ROFS
−
A positive output voltage offset is possible by connecting
ROFS to VDD instead of to GND. Please note that when
ROFS is connected to VDD, VOFS is VDD − 2V typically and
half of IOFS flows through RFB1. VCORE is rewritten as :
RFB1
VCORE = VDAC − VADJ
+
ROFS
Current Ratio Setting
Figure 6. GM3 Setting for current ratio function
Current ratio adjustment is possible as described below.
It is important for achieving thermal balance in practical
application where thermal conditions between phases are
not identical. Figure 5 shows the application circuit ofGM
for current ratio requirement. According to Basic Circuit
Theory
RPX
Rx + RPX
SRx ×RPX × Cx
VCx =
×ILX ×DCRx
Figure 7. GM1~2 Setting for current ratio function
+1
Rx + RPX
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23
RT8803A
Current Ratio Function
Load Line without dead zone at light loads
35
30
25
20
15
10
5
1.31
IL3
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
w/o Dead Zone Compensation
RCSN open
IL2
IL1
RCSN2 = 82k
w/i Dead Zone Compensation
0
0
15
30
45
60
75
90
0
5
10
15
20
25
IOUT (A)
IOUT (A)
Figure 8
Figure 10
Current Balance Function
35
Lx
DCRx
I
LX
30
25
20
15
10
5
Cx
Rx
V
OUT
+
-
VCx
+
-
IL3
R
CSN
GMx
Ix
IL2
R
CSN2
IL1
0
Figure 11. Application circuit of GM
0
20
40
60
80
100
120
IOUT (A)
Referring to Figure 11, IX is expressed as :
×DCRx ×DCRx
LX_66%
Figure 9
I
I
V
OUT
LX_66%
I
=
+
+
X
(1)
R
R
R
CSN
CSN2
CSN2
Dead Zone Elimination
RT8803A samples and holds inductor current at 50%
period by time-sharing sourcing a current IX to RCSN. At
light load condition when inductor current is not balance,
voltage VCx across the sensing capacitor would be
negative. It needs a negative IX to sense the voltage.
However, RT8803A CANNOT provide a negative IX and
consequently cannot sense negative inductor current. This
results in dead zone of load line performance as shown in
Figure 10. Therefore a technique as shown in Figure 11 is
required to eliminate the dead zone of load line at light
load condition.
where ILX_50% is the of inductor current at 50% period. To
make sure RT8803A could sense the inductor current,
right hand side of Equation (1) should always be positive:
I
×DCRx
I
×DCRx
R
CSN
V
LX_66%
LX_66%
OUT
+
+
≥ 0 (2)
R
R
CSN2
CSN2
Since RCSN >> DCRx in practical application, Equation (2)
could be simplified as :
I
×DCRx
R
CSN
V
LX_66%
OUT
≥
R
CSN2
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24
DS8803A-05 August 2007
RT8803A
For example, assuming the negative inductor current is
If RADJ is connected as in Figure 14, RADJ = R1 + (R2//
RNTC), which is a negative temperature correlated
resistance. By properly selecting R1 and R2, the positive
temperature coefficient of DCR can be canceled by the
negative temperature coefficient of RADJ. Thus the load
line will be thermally compensated.
ILX_50% = −5A at no load, then for
RCSN 330Ω, RADJ = 160Ω, VOUT = 1.300V
1.3V
− 5A ×1mΩ
330Ω
≥
R
CSN2
RCSN2 ≤ 85.8kΩ
ADJ
Choose RCSN2 = 82kΩ
R1
Figure 10 shows that dead zone of load line at light load
is eliminated by applying this technique.
R
ADJ
R
R2
NTC
VR_HOT & VR_FAN Setting
V
CC
5V
Figure 14. RADJ Connection for Thernal Compensation
+
R1
Q1
Q2
Q3
CMP
-
Over Current Protection
Phase current OCP
0.39 x V
0.33 x V
CC
CC
TSEN
V
TSEN
+
CMP
-
RT8803A uses an external resistor RIMAX connected to
IMAX pin to generate a reference current IIMAX for over
current protection :
R
NTC
+
CMP
-
0.28 x V
CC
V
IMAX
IIMAX
=
Figure 12
RIMAX
where VIMAX is typical 1.0V . OCP comparator compares
each sensed phase current IX with this reference current
as shown in Figure 15. Equivalently, the maximum phase
current ILX(MAX) is calculated as below:
V
TSEN
V
is inversely proportional
TSEN
to Temperature.
0.39 x V
0.33 x V
0.28 x V
CC
CC
CC
1
3
1
2
IX(MAX)
=
IIMAX
V
IMAX
RIMAX
3
2
3
2
×
IX(MAX)
=
IIMAX
=
VR_FAN
VR_HOT
RCSNX
RLX
RCSNX
DCRX
V
IMAX
RIMAX
3
2
×
ILX(MAX) IX
=
×
=
×
Temperature
OCP Comparator
1/3 I
+
-
X
Figure 13. VR_HOT and VR_FANSignal vs TSENVoltage
1/2 I
IMAX
Load Line Setting and Thermal Compensation
Figure 15. Over Current Comparator
VADJ = Sum(IX) x RADJ = (DCR x RADJ / RCSN) x IOUT
= LL x IOUT
VOUT = VDAC − VADJ = VDAC − LL x IOUT
LL = DCR(PTC) x RADJ(NTC) / RCSN
DCR is the inductor DCR which is a PTC resistance.
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25
RT8803A
4.7k
EA
Error Amplifier Characteristic
For fast response of converter to meet stringent output
current transient response, RT8803Aprovides large slew
rate capability and high gain-bandwidth performance.
4.7k
B
-
A
+
V
REF
EA Falling Slew Rate
Figure 18. Gain-Bandwidth Measurement by signalA
divided by signal B
Design Procedure Suggestion
VFB
a. Output filter pole and zero (Inductor, output capacitor
value & ESR).
b. Error amplifier compensation & saw-tooth wave
amplitude (compensation network).
CH1:(500mV/Div)
VCOMP
c. Kelvin sense for VCORE
.
CH2:(2V/Div)
Current Loop Setting
Time (250ns/Div)
a. GM amplifier S/H current (current sense component
DCR, ISPX and ISNX pin external resistor value).
Figure 16. EA Rising Transient with 10pF Loading ;
Slew Rate = 10V/μs
b. Over-current protection trip point (RIMAX resistor).
VRM Load Line Setting
EA Rising Slew Rate
a. Droop amplitude (ADJ pin resistor).
VFB
b. No load offset (RCSN
)
c. DAC offset voltage setting (OFS pin & compensation
network resistor).
d. Temperature coefficient compensation(TSENexternal
resister & thermistor, resistor betweenADJ andGND.)
Power Sequence & SS
CH1:(500mV/Div)
VCOMP
DVD pin external resistor and SS pin capacitor.
CH2:(2V/Div)
PCB Layout
Time (250ns/Div)
a.Kelvin sense for current sense GM amplifier input.
Figure 17. EA Falling Transient with 10pF Loading ;
b.Refer to layout guide for other items.
Slew Rate = 8V/μs
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26
DS8803A-05 August 2007
RT8803A
Outline Dimension
D
D2
SEE DETAIL A
L
1
E
E2
e
b
1
2
1
2
A
A3
DETAILA
A1
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.800
0.000
0.175
0.180
4.950
3.400
4.950
3.400
1.000
0.050
0.250
0.300
5.050
3.750
5.050
3.750
0.031
0.000
0.007
0.007
0.195
0.134
0.195
0.134
0.039
0.002
0.010
0.012
0.199
0.148
0.199
0.148
D
D2
E
E2
e
0.500
0.020
L
0.350
0.450
0.014
0.018
V-Type 32L QFN 5x5 Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
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27
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