X9408YV24IZT1_技术文档

DATASHEET

X9408

FN8191

Rev.4.00

January 15, 2009

Low Noise/Low Power/2-Wire Bus Quad Digitally Controlled (XDCP™)

Potentiometers

Description

Features

The X9408 integrates four digitally controlled potentiometers

(XDCP) on a monolithic CMOS integrated circuit.

• Four Potentiometers in One Package

• 64 Resistor Taps per Potentiometer

• 2-wire Serial Interface

The digital controlled potentiometer is implemented using 63

resistive elements in a series array. Between each element

are tap points connected to the wiper terminal through

switches. The position of the wiper on the array is controlled

by the user through the 2-wire bus interface. Each

potentiometer has associated with it a volatile Wiper Counter

Register (WCR) and four non-volatile Data Registers that

can be directly written to and read by the user. The contents

of the WCR controls the position of the wiper on the resistor

array though the switches. Power-up recalls the contents of

the default data register (DR0) to the WCR.

• Wiper Resistance, 40 Typical at 5V

• Four Nonvolatile Data Registers for Each Pot

• Nonvolatile Storage of Wiper Position

• Standby Current < 1µA max (Total Package)

• V

CC

= 2.7V to 5.5V Operation

V+ = 2.7V to 5.5V

V- = -2.7V to -5.5V

• 10k, 2.5k End to End Resistances

• High reliability

The XDCP can be used as a three-terminal potentiometer or

as a two terminal variable resistor in a wide variety of

applications including control, parameter adjustments, and

signal processing.

• Endurance–100,000 Data Changes Per Bit Per Register

• Register Data Retention–100 years

• 24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP Packages

• Pb-Free (RoHS Compliant)

Block Diagram

V

V+

V-

CC

POT 0

SS

R0 R1

R2 R3

V

/R

H0 H0

R0 R1

R2 R3

WIPER

COUNTER

REGISTER

(WCR)

WIPER

COUNTER

REGISTER

(WCR)

V

/R

H2 H2

RESISTOR

ARRAY

POT 2

V

/R

L0 L0

WP

V

/R

L2 L2

V

/R

SCL

SDA

A0

W0 W0

V

/R

W2 W2

INTERFACE

AND

CONTROL

CIRCUITRY

A1

8

A2

/R

W1 W1

A3

DATA

V

/R

W3 W3

R0 R1

R2 R3

R0 R1

R2 R3

V

/R

H1 H1

WIPER

COUNTER

REGISTER

(WCR)

V

/R

RESISTOR

ARRAY

WIPER

COUNTER

REGISTER

(WCR)

H3 H3

RESISTOR

ARRAY

POT 3

POT 1

V

/R

L1 L1

V

/R

L3 L3

FN8191 Rev.4.00

January 15, 2009

Page 1 of 20

X9408

Ordering Information

POTENTIOMETER

ORGANIZATION

(k)

TEMP RANGE

(°C)

PART NUMBER

X9408YS24*

PART MARKING V

LIMITS (V)

PACKAGE

24 Ld SOIC (300 mil)

CC

X9408YS

5 ±10%

2.5

0 to +70

-40 to +85

0 to +70

X9408YS24I*

X9408YS I

X9408YV

24 Ld SOIC (300 mil)

X9408YV24*

24 Ld TSSOP (4.4mm)

X9408YV24Z* (Note)

X9408YV24I*

X9408YV Z

X9408YV I

X9408YV Z I

X9408WS

0 to +70

24 Ld TSSOP (4.4mm) (Pb-Free)

24 Ld TSSOP (4.4mm)

-40 to +85

0 to +70

X9408YV24IZ* (Note)

X9408WS24*

24 Ld TSSOP (4.4mm) (Pb-Free)

24 Ld SOIC (300 mil)

10

X9408WS24I*

X9408WS I

X9408WV

-40 to +85

0 to +70

24 Ld SOIC (300 mil)

X9408WV24*

24 Ld TSSOP (4.4mm)

X9408WV24Z* (Note)

X9408WV24I*

X9408WV Z

X9408WV I

X9408WV Z I

X9408YS F

X9408YS G

X9408YV F

X9408YV Z F

X9408YV G

0 to +70

24 Ld TSSOP (4.4mm) (Pb-Free)

24 Ld TSSOP (4.4mm)

-40 to +85

0 to +70

X9408WV24IZ* (Note)

X9408YS24-2.7*

X9408YS24I-2.7*

X9408YV24-2.7*

X9408YV24Z-2.7* (Note)

X9408YV24I-2.7*

24 Ld TSSOP (4.4mm) (Pb-Free)

24 Ld SOIC (300 mil)

2.7 to 5.5

2.5

-40 to +85

0 to +70

24 Ld SOIC (300 mil)

24 Ld TSSOP (4.4mm)

0 to +70

24 Ld TSSOP (4.4mm) (Pb-Free)

24 Ld TSSOP (4.4mm)

-40 to +85

X9408YV24IZ-2.7T1 (Note) X9408YV Z G

24 Ld TSSOP (4.4mm) Tape and Reel

(Pb-Free)

X9408WS24-2.7*

X9408WS24I-2.7*

X9408WS F

X9408WS G

10

0 to +70

-40 to +85

0 to +70

24 Ld SOIC (300 mil)

X9408WS24IZ-2.7* (Note) X9408WS Z G

X9408WV24-2.7* X9408WV F

X9408WV24Z-2.7* (Note) X9408WV Z F

X9408WV24I-2.7* X9408WV G

X9408WV24IZ-2.7* (Note) X9408WV Z G

24 Ld SOIC (300 mil) (Pb-Free)

24 Ld TSSOP (4.4mm)

0 to +70

24 Ld TSSOP (4.4mm) (Pb-Free)

24 Ld TSSOP (4.4mm)

-40 to +85

24 Ld TSSOP (4.4mm) (Pb-Free)

*Add "T1" suffix for tape and reel. **Add "T1" suffix for tape and reel.Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8191 Rev.4.00

January 15, 2009

Page 2 of 20

X9408

HARDWARE WRITE PROTECT INPUT (WP)

Pin Descriptions

The WP pin when low prevents nonvolatile writes to the Data

Registers.

Host Interface Pins

SERIAL CLOCK (SCL)

ANALOG SUPPLIES V+, V-

The SCL input is used to clock data into and out of the X9408.

The Analog Supplies V+, V- are the supply voltages for the

XDCP analog section.

SERIAL DATA (SDA)

SDA is a bidirectional pin used to transfer data into and out of

the device. It is an open drain output and may be wire-ORed

with any number of open drain or open collector outputs. An

open drain output requires the use of a pull-up resistor. For

selecting typical values, refer to the guidelines for calculating

typical values on the bus pull-up resistors graph.

Pin Assignments

SYMBOL

DESCRIPTION

Serial Clock

SCL

SDA

A0-A3

Serial Data

DEVICE ADDRESS (A - A )

0

3

Device Address

The address inputs are used to set the least significant 4 bits of

the 8-bit slave address. A match in the slave address serial

data stream must be made with the address input in order to

initiate communication with the X9408. A maximum of 16

devices may occupy the 2-wire serial bus.

V

/R - V /R , V /R

H0 H0 H3 H3 L0 L0

Potentiometer Pins

(terminal equivalent)

- V /R

L3 L3

V

/R

W0 W0

- V /R

Potentiometer Pins

(wiper equivalent)

W3 W3

WP

Hardware Write Protection

Analog Supplies

Potentiometer Pins

V+,V-

V /R (V /R - V /R ), V /R (V /R - V /R

)

H

H0 H0 H3 H3 L0 L0 L3 L3

L

V

System Supply Voltage

System Ground

CC

SS

The V /R and V /R inputs are equivalent to the terminal

H

L

connections on either end of a mechanical potentiometer.

NC

No Connection

V /R (V /R – V /R

)

W

W0 W0 W3 W3

The wiper outputs are equivalent to the wiper output of a

mechanical potentiometer.

Pinouts

X9408

(24 LD DIP/SOIC)

TOP VIEW

(24 LD TSSOP)

TOP VIEW

V

1

2

24

V+

SDA

1

2

24

WP

CC

V

/R

23 V /R

A

23 A

L0 L0

L3 L3

1

2

V

/R

3

22 V /R

V

/R

3

22 V /R

W0 W0

H0 H0

H3 H3

L1 L1

21 V /R/R

W3

V

/R

4

21 V /R

H0 H0

V

/R

4

H1

W0 W0

H1 H1

A

2

5

20 A

0

V

/R

5

20 V /R

L0 L0

W1 W1

WP

6

19 NC

V

6

19 V

CC

SS

V-

SDA

7

18 A

3

7

18 V+

A

1

8

17 SCL

V

/R

8

17 V /R

W2 W2

L3 L3

V

/R

9

16 V /R

L2 L2

V

/R

H2 H2

9

16 V /R

H3 H3

L1 L1

V

/R

10

11

12

15 V /R

H2 H2

V

/R

10

15 V /R

W3 W3

H1 H1

L2 L2

V

/R

14 V /R

SCL 11

12

14 A

0

W1 W1

W2 W2

V

13 V-

A

13 NC

SS

3

FN8191 Rev.4.00

January 15, 2009

Page 3 of 20

X9408

time. These switches are controlled by the Wiper Counter

Register (WCR). The six bits of the WCR are decoded to

select, and enable, one of sixty-four switches.

Principals of Operation

The X9408 is a highly integrated microcircuit incorporating four

resistor arrays and their associated registers and counters and

the serial interface logic providing direct communication

between the host and the XDCP potentiometers.

The WCR may be written directly, or it can be changed by

transferring the contents of one of four associated Data

Registers into the WCR. These Data Registers and the WCR

can be read and written by the host system.

Serial Interface

The X9408 supports a bidirectional bus oriented protocol. The

protocol defines any device that sends data onto the bus as a

transmitter and the receiving device as the receiver. The

device controlling the transfer is a master and the device being

controlled is the slave. The master will always initiate data

transfers and provide the clock for both transmit and receive

operations. Therefore, the X9408 will be considered a slave

device in all applications.

Device Addressing

Following a start condition the master must output the address

of the slave it is accessing. The most significant four bits of the

slave address are the device type identifier (refer to Figure 1

below). For the X9408 this is fixed as 0101[B].

DEVICE TYPE

IDENTIFIER

Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW

0

1

0

1

A3

A2

A1

A0

periods (t

). SDA state changes during SCL HIGH are

LOW

reserved for indicating start and stop conditions.

DEVICE ADDRESS

Start Condition

FIGURE 1. SLAVE ADDRESS

All commands to the X9408 are preceded by the start

condition, which is a HIGH to LOW transition of SDA while SCL

is HIGH (t

). The X9408 continuously monitors the SDA

HIGH

The next four bits of the slave address are the device address.

The physical device address is defined by the state of the A -

and SCL lines for the start condition and will not respond to any

command until this condition is met.

0

A inputs. The X9408 compares the serial data stream with the

3

address input state; a successful compare of all four address

bits is required for the X9408 to respond with an acknowledge.

Stop Condition

All communications must be terminated by a stop condition,

which is a LOW to HIGH transition of SDA while SCL is HIGH.

The A - A inputs can be actively driven by CMOS input

0

3

signals or tied to V

or V

.

SS

CC

Acknowledge

Acknowledge Polling

Acknowledge is a software convention used to provide a

positive handshake between the master and slave devices on

the bus to indicate the successful receipt of data. The

transmitting device, either the master or the slave, will release

the SDA bus after transmitting eight bits. The master generates

a ninth clock cycle and during this period the receiver pulls the

SDA line LOW to acknowledge that it successfully received the

eight bits of data.

The disabling of the inputs, during the internal Nonvolatile write

operation, can be used to take advantage of the typical 5ms

EEPROM write cycle time. Once the stop condition is issued to

indicate the end of the nonvolatile write command the X9408

initiates the internal write cycle. ACK polling can be initiated

immediately. This involves issuing the start condition followed

by the device slave address. If the X9408 is still busy with the

write operation no ACK will be returned. If the X9408 has

completed the write operation an ACK will be returned and the

master can then proceed with the next operation.

The X9408 will respond with an acknowledge after recognition

of a start condition and its slave address and once again after

successful receipt of the command byte. If the command is

followed by a data byte the X9408 will respond with a final

acknowledge.

Array Description

The X9408 is comprised of four resistor arrays. Each array

contains 63 discrete resistive segments that are connected in

series. The physical ends of each array are equivalent to the

fixed terminals of a mechanical potentiometer (R and

H

R inputs).

L

At both ends of each array and between each resistor segment

is a CMOS switch connected to the wiper (R ) output. Within

W

each individual array only one switch may be turned on at a

FN8191 Rev.4.00

January 15, 2009

Page 4 of 20

X9408

Flow 1. ACK Polling Sequence

REGISTER

SELECT

NON-VOLATILE WRITE

COMMAND COMPLETED

ENTER ACK POLLING

I3

I2

I1

I0

R1

R0

P1

P0

WIPER COUNTER

REGISTER SELECT

INSTRUCTIONS

ISSUE

START

FIGURE 2. INSTRUCTION BYTE FORMAT

The four high order bits define the instruction. The next two bits

(R1 and R0) select one of the four registers that is to be acted

upon when a register oriented instruction is issued. The last

bits (P1, P0) select which one of the four potentiometers is to

be affected by the instruction.

ISSUE SLAVE

ADDRESS

ISSUE STOP

ACK

NO

RETURNED?

Four of the nine instructions end with the transmission of the

instruction byte. The basic sequence is illustrated in

YES

Figure 3. These two-byte instructions exchange data between

the Wiper Counter Register and one of the Data Registers. A

transfer from a Data Register to a Wiper Counter Register is

essentially a write to a static RAM. The response of the wiper

NO

FURTHER

OPERATION?

YES

to this action will be delayed t

. A transfer from the Wiper

WRL

Counter Register (current wiper position), to a data register is a

write to nonvolatile memory and takes a minimum of t to

ISSUE

INSTRUCTION

ISSUE STOP

PROCEED

WR

complete. The transfer can occur between one of the four

potentiometers and one of its associated registers; or it may

occur globally, wherein the transfer occurs between all of the

potentiometers and one of their associated registers.

PROCEED

Four instructions require a three-byte sequence to complete.

These instructions transfer data between the host and the

X9408; either between the host and one of the data registers or

directly between the host and the Wiper Counter Register.

These instructions are: Read Wiper Counter Register (read the

current wiper position of the selected pot), Write Wiper Counter

Register (change current wiper position of the selected pot),

Read Data Register (read the contents of the selected

nonvolatile register) and Write Data Register (write a new

value to the selected Data Register). The sequence of

operations is shown in Figure 4.

Instruction Structure

The next byte sent to the X9408 contains the instruction and

register pointer information. The four most significant bits are

the instruction. The next four bits point to one of the two pots

and when applicable they point to one of four associated

registers. The format is shown in Figure 2.

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3

I2

I1 I0

R1 R0 P1 P0

A

C

K

S

T

O

P

FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE

FN8191 Rev.4.00

January 15, 2009

Page 5 of 20

X9408

The Increment/Decrement command is different from the other

commands. Once the command is issued and the X9408 has

responded with an acknowledge, the master can clock the

selected wiper up and/or down in one segment steps; thereby,

providing a fine tuning capability to the host. For each SCL

move one resistor segment towards the R terminal. Similarly,

H

for each SCL clock pulse while SDA is LOW, the selected

wiper will move one resistor segment towards the R terminal.

L

A detailed illustration of the sequence and timing for this

operation are shown in Figures 5 and 6 respectively.

clock pulse (t

) while SDA is HIGH, the selected wiper will

HIGH

TABLE 1. INSTRUCTION SET

INSTRUCTION SET

INSTRUCTION

I

R

P

OPERATION

3

2

1

0

1

0

1

0

Read Wiper CounterRegister

1

0

1

0

P

Read the contents of the Wiper Counter Register pointed to by

1

0

P

- P

1

0

Write Wiper CounterRegister

Read Data Register

1

0

1

0

1

0

P

Write new value to the Wiper Counter Register pointed to by P - P

1 0

1

0

R

Read the contents of the Data Register pointed to by P - P and

1 0

1

0

R

- R

1

0

Write Data Register

1

0

1

0

1

0

1

0

1

0

R

P

Write new value to the Data Register pointed to by

- P and R - R

1

0

P

1

0

1

0

XFR Data Register to Wiper

Counter Register

Transfer the contents of the Data Register pointed to by P - P

1 0

and R - R to its associated Wiper Counter Register

1

0

XFR Wiper Counter Register

to Data Register

Transfer the contents of the Wiper Counter Register pointed to by

- P to the Data Register pointed to by R - R

P

1

0

1

0

Global XFR Data Registers

to Wiper Counter Registers

0

Transfer the contents of the Data Registers pointed to by R - R

1

0

of all four pots to their respective Wiper Counter Registers

Global XFR Wiper Counter

Registers to Data Register

0

Transfer the contents of both Wiper Counter Registers to their

respective Data Registers pointed to by

R

- R of all four pots

0

1

Increment/Decrement Wiper

Counter Register

0

1

0

P

Enable Increment/decrement of the Wiper Counter Register

1

0

pointed to by P - P

1

0

NOTE: (7)1/0 = data is one or zero

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0

R1 R0 P1 P0

A

C

K

0

D5 D4 D3 D2 D1 D0

A

C

K

S

T

O

P

FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3

I2

I1 I0

R1 R0 P1 P0

A

C

K

I

N

C

I

N

C

D

E

C

S

T

O

I

D

N

C

n

E

C

n

1

2

1

P

FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE

FN8191 Rev.4.00

January 15, 2009

Page 6 of 20

X9408

INC/DEC

CMD

ISSUED

t

WRID

SCL

SDA

VOLTAGE OUT

V

/R

W

FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS

SCL FROM

MASTER

1

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

FIGURE 7. ACKNOWLEDGE RESPNSE FROM RECEIVER

FN8191 Rev.4.00

January 15, 2009

Page 7 of 20

X9408

SERIAL DATA PATH

SERIAL

BUS

V /R

H H

FROM INTERFACE

CIRCUITRY

INPUT

C

O

U

N

T

REGISTER 0

REGISTER 1

8

6

PARALLEL

BUS

E

R

INPUT

WIPER

D

E

C

O

D

E

REGISTER 2

REGISTER 3

COUNTER

REGISTER

(WCR)

INC/DEC

LOGIC

IF WCR = 00[H] THEN V /R = V /R

L

W

L

UP/DN

IF WCR = 3F[H] THEN V /R = V /R

H

W

H

V

/R

L

MODIFIED SCL

L

CLK

V

/R

W

FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM

transferred between any of the four Data Registers and the

WCR. It should be noted all operations changing data in one of

these registers is a nonvolatile operation and will take a

maximum of 10ms.

Detailed Operation

All XDCP potentiometers share the serial interface and share a

common architecture. Each potentiometer has a Wiper

Counter Register and four Data Registers. A detailed

discussion of the register organization and array operation

follows.

If the application does not require storage of multiple settings

for the potentiometer, these registers can be used as regular

memory locations that could possibly store system parameters

or user preference data.

Wiper Counter Register

The X9408 contains four Wiper Counter Registers, one for

each XDCP potentiometer. The Wiper Counter Register can be

envisioned as a 6-bit parallel and serial load counter with its

outputs decoded to select one of sixty-four switches along its

resistor array. The contents of the WCR can be altered in four

ways: it may be written directly by the host via the Write Wiper

Counter Register instruction (serial load); it may be written

indirectly by transferring the contents of one of four associated

data registers via the XFR Data Register instruction (parallel

load); it can be modified one step at a time by the Increment/

Decrement instruction. Finally, it is loaded with the contents of

its data register zero (DR0) upon power-up.

Register Descriptions

TABLE 2. DATE REGISTERS, (6-BIT), NONVOLATILE

D5

NV

D4

NV

D3

NV

D2

NV

D1

NV

D0

NV

(MSB)

(LSB)

Four 6-bit Data Registers for each XDCP. (sixteen 6-bit

registers in total). {D5~D0}: These bits are for general purpose

not volatile data storage or for storage of up to four different

wiper values. The contents of Data Register 0 are

The WCR is a volatile register; that is, its contents are lost

when the X9408 is powered-down. Although the register is

automatically loaded with the value in R0 upon power-up, it

should be noted this may be different from the value present at

power-down.

automatically moved to the wiper counter register on power-up.

Data Registers

Each potentiometer has four nonvolatile Data Registers. These

can be read or written directly by the host and data can be

FN8191 Rev.4.00

January 15, 2009

Page 8 of 20

X9408

TABLE 3.

WP5

V

WIPER COUNTER REGISTER, (6-BIT), VOLATILE

One 6-bit Wiper Counter Register for each XDCP. (Four 6-bit

registers in total.)

WP4

V

WP3

V

WP2

V

WP1

V

WP0

V

{D5~D0}: These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is loaded on

power-up by the value in Data Register 0. The contents of the

WCR can be loaded from any of the other Data Register or

directly. The contents of the WCR can be saved in a DR.

(MSB)

(LSB)

Instruction Format

NOTES:

1. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

2. “A3 ~ A0”: stands for the device addresses sent by the master.

3. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.

4. “I”: stands for the increment operation, SDA held high during active

SCL phase (high).

5. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESSES

INSTRUCTION

OPCODE

WCR

ADDRESSES

WIPER POSITION

(SENT BY SLAVE ON SDA)

S

A

C

K

S

A

C

K

M

A

C

K

S

T

O

P

0

1

0

1

A3 A2 A1 A0

1

0

1

0

P1 P0

0

WP WP WP WP WP WP

5

4

3

2

1

0

Write Wiper Counter Register (WCR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESSES

INSTRUCTION

OPCODE

WCR

ADDRESSES

WIPER POSITION

(SENT BY MASTER ON SDA)

S

A

C

K

S

A

C

K

S

A

C

K

S

T

O

P

0

1

0

1

A3 A2 A1 A0

1

0

1

0

P1 P0

0

W

P5 P4 P3 P2 P1 P0

Read Data Register (DR)

S

T

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESSES

INSTRUCTION

OPCODE

DR AND WCR

ADDRESSES

WIPER POSITION/DATA

(SENT BY SLAVE ON SDA)

S

M

S

A

R

T

A

C

K

A

C

K

A

C

K

T

O

P

0

1

0

1

A3 A2 A1 A0

1

0

1

R1 R0 P1 P0

0

W

P5 P4 P3 P2 P1 P0

Write Data Register (DR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESSES

INSTRUCTION

OPCODE

DR AND WCR

ADDRESSES

WIPER POSITION/DATA

(SENT BY MASTER ON SDA)

S

A

C

K

S

A

C

K

S

A

C

K

S

T

O

P

0

1

0

1

A3 A2 A1 A0

1

0

R1 R0 P1 P0

0

W

HIGH-VOLTAGE

WRITE CYCLE

P5 P4 P3 P2 P1 P0

XFR Data Register (DR) to Wiper Counter Register (WCR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESSES

INSTRUCTION

OPCODE

DR AND WCR

ADDRESSES

S

A

C

K

S

T

O

P

A

C

K

0

1

0

1

A3

A2

A1

A0

1

0

1

R1

R0

P1

P0

FN8191 Rev.4.00

January 15, 2009

Page 9 of 20

X9408

Write Wiper Counter Register (WCR) to Data Register (DR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESSES

INSTRUCTION

OPCODE

DR AND WCR

ADDRESSES

S

A

C

K

S

A

C

K

S

T

O

P

0

1

0

1

A3 A2 A1 A0

1

0

R1 R0 P1 P0

HIGH-VOLTAGE

WRITE CYCLE

Increment/Decrement Wiper Counter Register (WCR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESSES

INSTRUCTION

OPCODE

WCR

ADDRESSES

INCREMENT/DECREMENT

(SENT BY MASTER ON SDA)

S

A

C

K

S

A

C

K

S

T

O

P

0

1

0

1

A3 A2 A1 A0

0

1

0

P1 P0

I/D I/D

.

I/D I/D

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESSES

INSTRUCTION

OPCODE

DR

ADDRESSES

S

A

C

K

S

A

C

K

S

T

O

P

0

1

0

1

A3 A2 A1 A0

0

1

R1 R0

0

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

S

T

A

R

T

DEVICE TYPE

IDENTIFIER

DEVICE

ADDRESSES

INSTRUCTION

OPCODE

DR

S

A

C

K

ADDRESSES

S

A

C

K

S

T

O

P

HIGH-VOLTAGE

WRITE CYCLE

0

1

0

1

A3 A2 A1 A0

1

0

R1 R0

0

Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

Symbol Table

WAVEFORM

INPUTS

OUTPUTS

120

V

CC MAX

R

=

=1.8k

MIN

MUST BE

STEADY

WILL BE

STEADY

I

OL MIN

100

80

t

R

=

MAX

MAY CHANGE

FROM LOW TO FROM LWO TO

HIGH

WILL CHANGE

C

BUS

MAX.

RESISTANCE

60

40

20

0

HIGH

MAY CHANGE

FROM HIGH TO FROM HIGH TO

LOW

WILL CHANGE

LOW

Min.

Resistance

DON’T CARE:

CHANGES

ALLOWED

CHANGING:

STATE NOT

KNOWN

0

20 40 60 80 100 120

BUS CAPACITANCE (pF)

N/A

CENTER LINE

IS HIGH

IMPEDANCE

FN8191 Rev.4.00

January 15, 2009

Page 10 of 20

X9408

Absolute Maximum Ratings

Thermal Information

Supply Voltage (V

Limits)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CC

X9408. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

X9408-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Voltage on SDA, SCL any address input

with respect to V : . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V

SS

Voltage on V+ (Referenced to V ). . . . . . . . . . . . . . . . . . . . . . .10V

SS

Operating Conditions

Voltage on V- (Referenced to V ) . . . . . . . . . . . . . . . . . . . . . . -10V

SS

Temperature Range

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

(V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V

I

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

Any VH/RH, VL/RL, VW/RW . . . . . . . . . . . . . . . . . . . . . . . . V- to V+

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

Analog Specifications (Over recommended operating conditions unless otherwise stated.)

LIMITS

MIN

TYP

MAX

SYMBOL

R

PARAMETER

End to end resistance tolerance

Power rating

TEST CONDITION

(Note 6)

(Note 4)

(Note 6)

UNIT

%

-20

+20

50

TOTAL

+25°C, each pot

= (V - V )/R

mW



R

Wiper resistance

I

150

40

250

W

H

L

TOTAL

@ V+, V- = ±3V

I

= (V - V )/R

100



W

H

L

TOTAL

@ V+, V- = ±5V

V +

Voltage on V+ pin

Voltage on V- pin

X9408

+4.5

+2.7

-5.5

V-

+5.5

-4.5

-2.7

V+

V

X9408-2.7

X9408

V -

V

X9408-2.7

V

Voltage on any V /R , V /R or

TERM

H

L

V

/R pin

W

Noise

Ref: 1kHz

(Note 4)

-120

1.6

dBV

%

Resolution

Absolute linearity (Note 1)

Relative linearity (Note 2)

Temperature coefficient of R

V(V /R

)

-

-1

+1

MI

(Note 3)

wn wn (actual)

V(V /R

(Note 4)

wn wn (expected)

V(V

/R ) -

-0.2

+0.2

MI

(Note 3)

w(n+1) w(n+1)

[V(V

/R

) + MI] (Note 4)

w(n) w(n)

(Note 4)

300

20

ppm/°C

pF

TOTAL

Ratiometric Temperature Coefficient

Potentiometer Capacitances

C /C /C

See Macro model

= V- to V+. Device is in Stand-

10/10/25

0.1

H

L

W

I

V /R , V /R , V /R Leakage

V

10

µA

AL

H

L

W

IN

by mode.

Current

FN8191 Rev.4.00

January 15, 2009

Page 11 of 20

X9408

DC Electrical Specifications (Over recommended operating conditions unless otherwise stated.)

LIMITS

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 6)

(Note 4)

(Note 6)

UNIT

I

V

supply current (nonvolatile write)

f = 400kHz, SDA = Open,

SCL

5

mA

CC1

CC

Other Inputs = V

SS

I

supply current (move wiper, write,

f

= 400kHz, SDA = Open,

250

µA

CC2

CC

SCL

Other Inputs = V

read)

SS

SCL = SDA = V , Addr. = V

SS

I

V

current (standby)

3

µA

V

SB

CC

I

Input leakage current

Output leakage current

Input HIGH voltage

Input LOW voltage

Output LOW voltage

10

LI

I

LO

V

x 0.7

V

+0.5

x 0.1

IH

CC

V

–0.5

V

IL

CC

V

I

= 3mA

OL

0.4

V

OL

NOTES:

1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is

a measure of the error in step size.

3. MI = RTOT/63 or [V(V /R ) - V(V /R )]/63, single pot

H

L

ENDURANCE AND DATA RETENTION

PARAMETER

Minimum endurance

Data retention

MIN

100,000

100

UNIT

Data changes per bit per register

years

CAPACITANCE

TYP

SYMBOL

TEST

Input/output capacitance (SDA)

Input capacitance (A0, A1, A2, A3, and SCL)

TEST CONDITION

(Note 4)

UNIT

pF

C

(Note 4)

V

= 0V

8

6

I/O

C

V

pF

IN

POWER-UP TIMING

MIN

MAX

SYMBOL

PARAMETER

(Note 6)

UNIT

ms

t

(Note 5)

Power-up to initiation of read operation

Power-up to initiation of write operation

1

5

PUR

t

ms

PUW

t V

(Note 6)

V Power-up Ramp

CC

0.2

50

V/msec

R

CC

NOTES:

4. Limits should be considered typical and are not production tested.

5. t and t are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific

PUR

PUW CC

instruction can be issued

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

FN8191 Rev.4.00

January 15, 2009

Page 12 of 20

X9408

Power-up Requirements

A.C. Test Conditions

(Power-up sequencing can affect correct recall of the wiper

registers).

Input pulse levels

V

x 0.1 to V

x 0.5

x 0.9

CC

Input rise and fall times

Input and output timing level

10ns

The preferred power-on sequence is as follows: First V-, then

V

CC

V

and V+, and then the potentiometer pins, V /R , V /R ,

H H L L

CC

and V /R . Voltage should not be applied to the

Equivalent A.C. Load Circuit

W

potentiometer pins before V+ or V- is applied. The V

ramp

CC

5V

rate specification should be met, and any glitches or slope

changes in the V line should be held to <100mV if possible.

CC

powers down, it should be held below 0.1V for more

1533

If V

CC

than 1 second before powering up again in order for proper

wiper register recall. Also, V should not reverse polarity by

SDA OUTPUT

CC

more than 0.5V. Recall of wiper position will not be complete

100PF

until V , V+ and V- reach their final value.

CC

Circuit #3 SPICE Macro Model

R

TOTAL

V /R

L L

H

C

L

C

H

C

W

10pF

25pF

V

/R

W

FN8191 Rev.4.00

January 15, 2009

Page 13 of 20

X9408

AC Timing (Over recommended operating condition)

MIN

MAX

SYMBOL

PARAMETER

(Note 5)

UNIT

kHz

ns

f

Clock frequency

400

SCL

t

Clock cycle time

2500

600

1300

600

100

30

CYC

t

Clock high time

ns

HIGH

t

Clock low time

ns

LOW

t

Start setup time

ns

SU:STA

HD:STA

SU:STO

t

Start hold time

ns

t

Stop setup time

ns

t

SDA data input setup time

SDA data input hold time

SCL and SDA rise time

SCL and SDA fall time

ns

SU:DAT

HD:DAT

t

ns

t

300

900

ns

R (Note 7)

t

ns

F (Note 7)

t

SCL low to SDA data output valid time

SDA Data output hold time

ns

AA

t

50

1300

0

ns

DH

T

Noise suppression time constant at SCL and SDA inputs

Bus free time (prior to any transmission)

WP, A0, A1, A2 and A3 setup time

ns

I

t

ns

BUF

t

ns

SU:WPA

t

0

ns

WP, A0, A1, A2 and A3 hold time

HD:WPA

NOTES:

7. This parameter is not production tested. Parameter established by characterization.

HIGH-VOLTAGE WRITE CYCLE TIMING

TYP.

MAX.

SYMBOL

PARAMETER

(Note 4)

(Note 6)

UNIT

t

High-voltage write cycle time (store instructions)

5

10

ms

WR

XDCP TIMING

MIN.

MAX.

SYMBOL

PARAMETER

(Note 5) (Note 6) UNIT

t

Wiper response time after the third (last) power supply is stable

10

µs

WRPO

t

Wiper response time after instruction issued (all load instructions)

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

WRL

t

WRID

FN8191 Rev.4.00

January 15, 2009

Page 14 of 20

X9408

Timing Diagrams

Start and Stop Timing

g

(START)

(STOP)

t

F

R

SCL

t

SU:STO

SU:STA

HD:STA

t

F

R

SDA

Input Timing

t

CYC

HIGH

SCL

SDA

t

LOW

t

BUF

SU:DAT

HD:DAT

Output Timing

SCL

SDA

t

DH

AA

XDCP Timing (for All Load Instructions)

(STOP)

SCL

SDA

VWx

LSB

t

WRL

FN8191 Rev.4.00

January 15, 2009

Page 15 of 20

X9408

XDCP Timing (for Increment/Decrement Instruction)

SCL

WIPER REGISTER ADDRESS

INC/DEC

SDA

VWx

t

WRID

Write Protect and Device Address Pins Timing

(START)

(STOP)

SCL

...

(ANY INSTRUCTION)

...

SDA

...

t

HD:WPA

SU:WPA

WP

A0, A1

A2, A3

Applications information

Basic Configurations of Electronic Potentiometers

+V

R

V

R

I

THREE TERMINAL POTENTIOMETER;

VARIABLE VOLTAGE DIVIDER

TWO TERMINAL VARIABLE RESISTOR;

VARIABLE CURRENT

FN8191 Rev.4.00

January 15, 2009

Page 16 of 20

X9408

Application Circuits

NONINVERTING AMPLIFIER

VOLTAGE REGULATOR

317

V

+

–

S

V

(REG)

IN

O

V

O

R

1

I

adj

R

2

R

2

R

1

V

(REG) = 1.25V (1+R /R )+I R

adj 2

O

2

1

V

= (1+R /R )V

2 1 S

O

OFFSET VOLTAGE ADJUSTMENT

COMPARATOR WITH HYSTERESIS

R

2

1

V

–

+

S

V

S

O

100k

–

+

V

O

TL072

R

1

2

10k

V

= {R /(R +R )} V (max)

1 1 2 O

UL

LL

10k

= {R /(R +R )} V (min)

1

2

O

+12V

-12V

FN8191 Rev.4.00

January 15, 2009

Page 17 of 20

X9408

Application Circuits (continued)

ATTENUATOR

FILTER

C

V

+

–

S

R

V

R

2

O

1

3

–

+

R

V

O

V

S

R

2

R

4

All R = 10k

S

R

1

G

= 1 + R /R

2 1

V

= G V

O

S

fc = 1/(2RC)

-1/2  G  +1/2

INVERTING AMPLIFIER

EQUIVALENT L-R CIRCUIT

R

2

1

V

S

R

2

C

1

–

+

V

+

–

S

V

O

R

1

3

Z

IN

V

= G V

S

O

G = - R /R

2

1

Z

= R + s R (R + R ) C = R + s Leq

2 2 1 3 1 2

IN

(R + R ) >> R

1

3

2

FUNCTION GENERATOR

C

R

1

2

–

+

–

+

R

}

A

B

FREQUENCY µR , R , C

1

2

AMPLITUDE µR , R

A

B

FN8191 Rev.4.00

January 15, 2009

Page 18 of 20

X9408

Thin Shrink Small Outline Package Family (TSSOP)

MDP0044

0.25 M C A B

N

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

D

A

(N/2)+1

MILLIMETERS

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A

A1

A2

b

1.20

0.10

0.90

0.25

0.15

5.00

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

5.00

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

6.50

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

7.80

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

9.70

6.40

4.40

0.65

0.60

1.00

Max

±0.05

PIN #1 I.D.

E

E1

±0.05

+0.05/-0.06

±0.10

0.20 C B A

2X

1

(N/2)

c

N/2 LEAD TIPS

B

D

TOP VIEW

E

Basic

E1

e

±0.10

Basic

0.05

H

e

L

±0.15

C

L1

Reference

Rev. F 2/07

SEATING

PLANE

NOTES:

0.10 M C A B

b

1. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

0.10 C

N LEADS

SIDE VIEW

2. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm per

side.

SEE DETAIL “X”

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

END VIEW

L1

A2

A

GAUGE

PLANE

0.25

L

A1

0° - 8°

DETAIL X

FN8191 Rev.4.00

January 15, 2009

Page 19 of 20

X9408

Small Outline Plastic Packages (SOIC)

M24.3 (JEDEC MS-013-AD ISSUE C)

N

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.33

0.23

MAX

2.65

NOTES

-B-

A

A1

B

C

D

E

e

0.0926

0.0040

0.013

0.1043

0.0118

0.020

-

0.30

-

1

2

3

L

0.51

9

SEATING PLANE

A

0.0091

0.5985

0.2914

0.0125

0.32

-

-A-

0.6141 15.20

15.60

7.60

3

h x 45°

D

0.2992

7.40

4

-C-

0.05 BSC

1.27 BSC

-



H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N



24

7

0°

8°

0°

8°

-

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 4/06

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8191 Rev.4.00

January 15, 2009

Page 20 of 20


型号：	X9408YV24IZT1
厂家：	RENESAS TECHNOLOGY CORP
描述：	QUAD 2.5K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO24, 4.40 MM, GREEN, PLASTIC, TSSOP-24 光电二极管转换器电阻器
文件：	总20页 (文件大小：809K)
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X9408YV24IZT1 [RENESAS]

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X9408YV24T1

X9408YV24T2

X9408YV24T4

X9408YV24T5

X9408YV24T6

X9408YV24Z

X9408YV24Z-2.7

X9408YZ24

X9408YZ24-2.7T3

X9408YZ24-2.7T4

X9408YZ24-2.7T5

X9408YZ24-2.7T7