X9408YZ24-2.7T5_技术文档

APPLICATION NOTES

A V A I L A B L E

AN99 • AN115 • AN124 • AN133 • AN134 • AN135

Low Noise/Low Power/2-Wire Bus

X9408

Quad Digitally Controlled (XDCP^™) Potentiometers

FEATURES

DESCRIPTION

• Four separate XDCP’s in one package

• 64 resistor taps per potentiometer

• 2-wire serial interface

The X9408 integrates four digitally controlled

potentiometers (XDCP) on a monolithic CMOS

integrated circuit.

• Wiper resistance, 150Ω typical

The digital controlled potentiometer is implemented

using 63 resistive elements in a series array. Between

each element are tap points connected to the wiper

terminal through switches. The position of the wiper on

the array is controlled by the user through the SPI bus

interface. Each potentiometer has associated with it a

volatile Wiper Counter Register (WCR) and four non-

volatile Data Registers that can be directly written to

and read by the user. The contents of the WCR

controls the position of the wiper on the resistor array

though the switches. Powerup recalls the contents of

the default data register (DR0) to the WCR.

• Four nonvolatile data registers for each pot

• Nonvolatile storage of wiper position

• Standby current < 1µA max (total package)

• V

= 2.7V to 5.5V operation

CC

V+ = 2.7V to 5.5V

V– = –2.7V to –5.5V

• 10KΩ, 2.5KΩ total pot resistance

• 100 year data retention

• 24-lead SOIC, 24-lead TSSOP, and 24-lead XBGA

packages

The XDCP can be used as a three-terminal

potentiometer or as a two terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

V+

V-

Pot 0

CC

SS

R0 R1

R2 R3

R

R0 R1

R2 R3

H0

Wiper

Counter

Register

(WCR)

Wiper

Counter

Register

(WCR)

R

H2

Resistor

Array

Pot 2

R

L0

WP

R

L2

R

SCL

SDA

A0

W0

R

W2

Interface

and

Control

A1

8

Circuitry

A2

R

A3

W1

Data

R

W3

R0 R1

R2 R3

R0 R1

R2 R3

R

Wiper

Counter

Register

(WCR)

H1

Resistor

Array

Pot 1

Wiper

Counter

Register

(WCR)

H3

Resistor

Array

Pot 3

R

L1

R

L3

Characteristics subject to change without notice. 1 of 20

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X9408

PIN DESCRIPTIONS

R

(R –R

)

W

W0

W3

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

Host Interface Pins

Serial Clock (SCL)

Hardware Write Protect Input (WP)

The SCL input is used to clock data into and out of the

X9408.

The WP pin when low prevents nonvolatile writes to

the wiper counter registers.

Serial Data (SDA)

Analog Supplies V+, V-

SDA is a bidirectional pin used to transfer data into

and out of the device. It is an open drain output and

may be wire-ORed with any number of open drain or

open collector outputs. An open drain output requires

the use of a pull-up resistor. For selecting typical

values, refer to the guidelines for calculating typical

values on the bus pull-up resistors graph.

The Analog Supplies V+, V- are the supply voltages

for the XDCP analog section.

PIN NAMES

Symbol

Description

Serial Clock

SCL

SDA

A0-A3

Serial Data

Device Address (A –A )

0

3

Device Address

The address inputs are used to set the least signiﬁcant

4 bits of the 8-bit slave address. A match in the slave

address serial data stream must be made with the

address input in order to initiate communication with

the X9408. A maximum of 16 devices may occupy the

2-wire serial bus.

R

–R , R –R

Potentiometer Pins

(terminal equivalent)

H0 H3 L0 L3

R

–R

Potentiometer Pins

(wiper equivalent)

W0 W3

WP

Hardware Write Protection

Analog Supplies

V+,V-

Potentiometer Pins

V

System Supply Voltage

System Ground

R (R –R ), R (R –R )

CC

H

H0 H3

L

L0 L3

V

The R and R inputs are equivalent to the terminal

SS

H

L

connections on either end of

a

mechanical

NC

No Connection

potentiometer.

PIN CONFIGURATION

DIP/SOIC

XBGA

TSSOP

1

2

3

4

V+

R

V

WP

SDA

1

2

24

23

22

21

20

19

18

17

16

15

1

2

24

23

22

21

20

19

18

17

16

15

CC

R

A

1

L3

L0

2

R

A

1

A

W0

L1

2

A

R

V

R

A

R

3

R

W0

H0

L0

H3

3

H0

L1

R

SDA

WP

L0

W1

4

H1

W3

4

W0

B

C

D

E

F

R

W1

A

2

5

0

V

R

V

SS

CC

H0

H3

H1

V

NC

SS

V-

WP

6

CC

X9408

SDA

A

3

7

V+

7

V+

R

V-

H2

R

SCL

A

1

R

W2

8

L3

A

R

W2

NC

3

L3

R

H2

R

9

L2

L1

H3

W3

R

10

L2

H2

10

R

H1

R

A

SCL

R

L2

0

W3

R

A

14

13

SCL

14

13

R

W2

11

12

0

11

12

W1

V

A

3

Top View–Bumps Down

V-

SS

NC

Characteristics subject to change without notice. 2 of 20

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X9408

PRINCIPLES OF OPERATION

The X9408 will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9408 will respond with a ﬁnal acknowledge.

The X9408 is

a

highly integrated microcircuit

incorporating four resistor arrays and their associated

registers and counters and the serial interface logic

providing direct communication between the host and

the XDCP potentiometers.

Array Description

The X9408 is comprised of four resistor arrays. Each

array contains 63 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the ﬁxed terminals of a mechanical

Serial Interface

The X9408 supports a bidirectional bus oriented

protocol. The protocol deﬁnes any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9408 will be considered a

slave device in all applications.

potentiometer (R and R inputs).

H

L

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper

(R ) output. Within each individual array only one

W

switch may be turned on at a time. These switches are

controlled by the Wiper Counter Register (WCR). The

six bits of the WCR are decoded to select, and enable,

one of sixty-four switches.

Clock and Data Conventions

Data states on the SDA line can change only during

The WCR may be written directly, or it can be changed

by transferring the contents of one of four associated

Data Registers into the WCR. These Data Registers

and the WCR can be read and written by the host

system.

SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop

conditions.

Start Condition

All commands to the X9408 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most

signiﬁcant four bits of the slave address are the device

type identiﬁer (refer to Figure 1 below). For the X9408

this is ﬁxed as 0101[B].

while SCL is HIGH (t

). The X9408 continuously

HIGH

monitors the SDA and SCL lines for the start condition

and will not respond to any command until this

condition is met.

Stop Condition

Figure 1. Slave Address

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH.

Device Type

Identifier

Acknowledge

0

1

0

1

A3

A2

A1

A0

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

Device Address

The next four bits of the slave address are the device

address. The physical device address is deﬁned by the

state of the A -A inputs. The X9408 compares the

serial data stream with the address input state; a

successful compare of all four address bits is required

for the X9408 to respond with an acknowledge. The

0

3

A –A inputs can be actively driven by CMOS input

0

3

signals or tied to V or V

.

CC

SS

Characteristics subject to change without notice. 3 of 20

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X9408

Acknowledge Polling

point to one of the two pots and when applicable they

point to one of four associated registers. The format is

shown below in Figure 2.

The disabling of the inputs, during the internal

Nonvolatile write operation, can be used to take

advantage of the typical 5ms EEPROM write cycle

time. Once the stop condition is issued to indicate the

end of the nonvolatile write command the X9408

initiates the internal write cycle. ACK polling can be

initiated immediately. This involves issuing the start

condition followed by the device slave address. If the

X9408 is still busy with the write operation no ACK will

be returned. If the X9408 has completed the write

operation an ACK will be returned and the master can

then proceed with the next operation.

Figure 2. Instruction Byte Format

Register

Select

I3

I2

I1

I0

R1 R0

P1 P0

Wiper Counter

Register Select

Instructions

Flow 1. ACK Polling Sequence

The four high order bits deﬁne the instruction. The next

two bits (R1 and R0) select one of the four registers

that is to be acted upon when a register oriented

instruction is issued. The last bits (P1, P0) select which

one of the four potentiometers is to be affected by the

instruction.

Nonvolatile Write

Command Completed

Enter ACK Polling

Four of the nine instructions end with the transmission

of the instruction byte. The basic sequence is

illustrated in Figure 3. These two-byte instructions

exchange data between the Wiper Counter Register

and one of the Data Registers. A transfer from a Data

Register to a Wiper Counter Register is essentially a

write to a static RAM. The response of the wiper to this

Issue

START

Issue Slave

Issue STOP

Address

action will be delayed t

Counter Register (current wiper position), to a data

register is a write to nonvolatile memory and takes a

. A transfer from the Wiper

WRL

NO

ACK

Returned?

minimum of t

to complete. The transfer can occur

YES

WR

between one of the four potentiometers and one of its

associated registers; or it may occur globally, wherein

the transfer occurs between all of the potentiometers

and one of their associated registers.

NO

Further

Operation?

YES

Four instructions require a three-byte sequence to

complete. These instructions transfer data between the

host and the X9408; either between the host and one

of the data registers or directly between the host and

the Wiper Counter Register. These instructions are:

Read Wiper Counter Register (read the current wiper

position of the selected pot), Write Wiper Counter

Register (change current wiper position of the selected

pot), Read Data Register (read the contents of the

selected nonvolatile register) and Write Data Register

(write a new value to the selected Data Register). The

sequence of operations is shown in Figure 4.

Issue

Instruction

Issue STOP

Proceed

Instruction Structure

The next byte sent to the X9408 contains the instruction

and register pointer information. The four most

signiﬁcant bits are the instruction. The next four bits

Characteristics subject to change without notice. 4 of 20

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X9408

Figure 3. Two-Byte Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 P1 P0

A

C

K

S

T

O

P

The Increment/Decrement command is different from

the other commands. Once the command is issued and

the X9408 has responded with an acknowledge, the

master can clock the selected wiper up and/or down in

one segment steps; thereby, providing a ﬁne tuning

resistor segment towards the V terminal. Similarly, for

each SCL clock pulse while SDA is LOW, the selected

H

wiper will move one resistor segment towards the V

L

terminal. A detailed illustration of the sequence and

timing for this operation are shown in Figures 5 and 6

respectively.

capability to the host. For each SCL clock pulse (t

)

HIGH

while SDA is HIGH, the selected wiper will move one

Table 1. Instruction Set

Instruction Set

Instruction

I

R

P

Operation

1/0 1/0 Read the contents of the Wiper Counter Register

pointed to by P –P

3

2

1

0

1

0

1

0

Read Wiper Counter

Register

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Write Wiper Counter

Register

0

1/0 1/0 Write new value to the Wiper Counter Register pointed

to by P –P

1

0

Read Data Register

1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by

P –P and R –R

1

0

1

0

Write Data Register

1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to by

P –P and R –R

1

0

1

0

XFR Data Register to

Wiper Counter Register

1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed to

by P –P and R –R to its associated Wiper Counter

1

0

1

0

Register

XFR Wiper Counter

Register to Data

Register

1

0

1

0

1

0

1

0

1

0

1

0

1/0 1/0

0

1/0 Transfer the contents of the Wiper Counter Register

pointed to by P –P to the Data Register pointed to

1

0

by R –R

1

0

Global XFR Data Reg-

isters to Wiper Counter

Registers

0

Transfer the contents of the Data Registers pointed to

by R –R of all four pots to their respective Wiper

Counter Registers

1

0

Global XFR Wiper

Counter Registers to

Data Register

Transfer the contents of both Wiper Counter Regis-

ters to their respective Data Registers pointed to by

R –R of all four pots

1

0

Increment/Decrement

Wiper Counter Register

0

1/0 1/0 Enable Increment/decrement of the Wiper Counter

Register pointed to by P –P

1

0

Note: (7) 1/0 = data is one or zero

Characteristics subject to change without notice. 5 of 20

REV 1.0 6/20/00

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X9408

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 P1 P0

A

C

K

0

D5 D4 D3 D2 D1 D0

A

C

K

S

T

O

P

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 P1 P0

A

C

K

I

D

E

C

1

S

T

O

P

I

D

N

C

1

N

C

2

N

C

n

E

C

n

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

t

WRID

SCL

SDA

Voltage Out

V

/R

W

Characteristics subject to change without notice. 6 of 20

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X9408

Figure 7. Acknowledge Response from Receiver

SCL from

Master

1

8

9

Data Output

from Transmitter

Data Output

from Receiver

START

Acknowledge

Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path

Serial

Bus

Input

R

H

From Interface

Circuitry

C

o

u

n

t

Register 0

Register 2

Register 1

8

6

Parallel

Bus

Input

e

r

Wiper

D

e

c

o

d

e

Register 3

Counter

Register

(WCR)

INC/DEC

Logic

If WCR = 00[H] then R = R

W

L

UP/DN

If WCR = 3F[H] then R = R

W

H

R

Modified SCL

L

CLK

R

W

Characteristics subject to change without notice. 7 of 20

REV 1.0 6/20/00

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X9408

DETAILED OPERATION

If the application does not require storage of multiple

settings for the potentiometer, these registers can be

used as regular memory locations that could possibly

store system parameters or user preference data.

All XDCP potentiometers share the serial interface

and share a common architecture. Each potentiometer

has a Wiper Counter Register and four Data Registers.

A detailed discussion of the register organization and

array operation follows.

Register Descriptions

Data Registers, (6-Bit), Nonvolatile

Wiper Counter Register

D5

NV

D4

NV

D3

NV

D2

NV

D1

NV

D0

NV

The X9408 contains four Wiper Counter Registers,

one for each XDCP potentiometer. The Wiper Counter

Register can be envisioned as a 6-bit parallel and

serial load counter with its outputs decoded to select

one of sixty-four switches along its resistor array. The

contents of the WCR can be altered in four ways: it

may be written directly by the host via the Write Wiper

Counter Register instruction (serial load); it may be

written indirectly by transferring the contents of one of

four associated data registers via the XFR Data

Register instruction (parallel load); it can be modiﬁed

one step at a time by the Increment/ Decrement

instruction. Finally, it is loaded with the contents of its

data register zero (DR0) upon power-up.

(MSB)

(LSB)

Four 6-bit Data Registers for each XDCP. (sixteen 6-bit

registers in total).

– {D5~D0}: These bits are for general purpose not vol-

atile data storage or for storage of up to four different

wiper values. The contents of Data Register 0 are

automatically moved to the wiper counter register on

power-up.

Wiper Counter Register, (6-Bit), Volatile

WP5

V

WP4

V

WP3

V

WP2

V

WP1

V

WP0

V

The WCR is a volatile register; that is, its contents are

lost when the X9408 is powered-down. Although the

register is automatically loaded with the value in R0

upon power-up, it should be noted this may be

different from the value present at power-down.

(MSB)

(LSB)

One 6-bit Wiper Counter Register for each XDCP.

(Four 6-bit registers in total.)

Data Registers

– {D5~D0}:These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is

loaded on power-up by the value in Data Register 0.

The contents of the WCR can be loaded from any of

the other Data Register or directly. The contents of

the WCR can be saved in a DR.

Each potentiometer has four nonvolatile Data

Registers. These can be read or written directly by the

host and data can be transferred between any of the

four data registers and the WCR. It should be noted all

operations changing data in one of these registers is a

nonvolatile operation and will take a maximum of

10ms.

Characteristics subject to change without notice. 8 of 20

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X9408

Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.

(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.

(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).

(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register

S device type

device

addresses

instruction

opcode

wiper

addresses

wiper position

(sent by slave on SDA)

S

A

C

K

S

A

C

K

M S

A T

C O

K P

T

A

R

T

identifier

W W W W W W

0 0 P P P P P P

A A A A

P P

1 0

0

1

0

1

0

1

0

3

2

1

0

5

4 3 2 1 0

Write Wiper Counter Register

S device type

device

addresses

instruction

opcode

wiper

addresses

wiper position

(sent by master on SDA)

S

A

C

K

S

A

C

K

S S

A T

C O

K P

T

A

R

T

identifier

W W W W W W

0 0 P P P P P P

A A A A

P P

1 0

0

1

0

1

0

1

0

3

2

1

0

5

4 3 2 1 0

Read Data Register

S device type device

instruction

opcode

wiper

addresses

wiper position

(sent by slave on SDA)

S

A

C

K

S

A

C

K

M S

A T

C O

K P

T

A

R

T

identifier

addresses

W W W W W W

0 0 P P P P P P

A A A A

R R P P

0

1

0

1

0

1

3

2

1

0

1

0

1 0

5

4 3 2 1 0

Write Data Register

S device type

device

addresses

instruction

opcode

wiper

addresses

wiper position

(sent by master on SDA)

S

A

C

K

S S

T

A

R

T

identifier

A

C

K

A T HIGH-VOLTAGE

C O WRITE CYCLE

K P

W W W W W W

0 0 P P P P P P

5 4 3 2 1 0

A A A A

3 2 1 0

R R P P

1 0 1 0

0 1 0 1

1 1 0 0

XFR Data Register to Wiper Counter Register

S device type

device

addresses

instruction

opcode

wiper

addresses

S

A

C

K

S S

T

A

R

T

identifier

A T

C O

K P

A A A A

3 2 1 0

R R P P

1 0 1 0

0 1 0 1

1 1 0 1

Write Wiper Counter Register to Data Register

S device type

device

addresses

instruction

opcode

wiper

addresses

S

A

C

K

S S

T

A

R

T

identifier

A T HIGH-VOLTAGE

C O WRITE CYCLE

K P

A A A A

3 2 1 0

R R P P

1 0 1 0

0 1 0 1

1 1 1 0

Characteristics subject to change without notice. 9 of 20

REV 1.0 6/20/00

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X9408

Increment/Decrement Wiper Counter Register

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

wiper

addresses

increment/decrement

(sent by master on SDA)

S

A

C

K

S

A

C

K

S

T

O

P

A A A A

P P

1 0

I/ I/

D D

I/ I/

D D

0

1

0

1

0

1

0

.

3

2

1

0

Global XFR Data Register to Wiper Counter Register

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

wiper

addresses

S

A

C

K

S S

A T

C O

K P

A A A A

R R

1 0

0

1

0

1

0

1

0 0

3

2

1

0

Global XFR Wiper Counter Register to Data Register

S device type

device

addresses

instruction

opcode

wiper

addresses

S

A

C

K

S S

A T

C O

K P

T

A

R

T

identifier

HIGH-VOLTAGE

WRITE CYCLE

A A A A

3 2 1 0

R R

0 0

1 0

0 1 0 1

1 0 0 0

SYMBOL TABLE

Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

WAVEFORM

INPUTS

OUTPUTS

120

V

CC MAX

OL MIN

R

=

=1.8KΩ

Must be

steady

Will be

steady

MIN

I

100

80

t

R

=

MAX

May change

from Low to

High

Will change

from Low to

High

C

BUS

Max.

Resistance

60

40

20

0

May change

from High to

Low

Will change

from High to

Low

Min.

Resistance

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

0

20 40 60 80 100 120

N/A

Center Line

is High

Impedance

Bus Capacitance (pF)

Characteristics subject to change without notice. 10 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias....................–65°C to +135°C

Storage temperature.........................–65°C to +150°C

Voltage on SDA, SCL or any address

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; the functional operation of

the device (at these or any other conditions above

those listed in the operational sections of this

speciﬁcation) is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect device reliability.

input with respect to V ......................... –1V to +7V

SS

Voltage on V+ (referenced to V ) ........................ 10V

SS

Voltage on V- (referenced to V ) ........................ -10V

SS

(V+) – (V-) ............................................................. 12V

Any V .................................................................... V+

H

Any V ...................................................................... V-

L

Lead temperature (soldering, 10 seconds) ........300°C

I

(10 seconds) ............................................... ±12mA

W

RECOMMENDED OPERATING CONDITIONS

Temperature

Commercial

Industrial

Min.

0°C

Max.

+70°C

+85°C

Device

X9408

Supply Voltage (V ) Limits

CC

5V ±10%

–40°C

X9408-2.7

2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol

Parameter

End to end resistance tolerance

Power rating

Min.

Typ.

Max.

±20

50

Unit

%

Test Condition

mW

mA

Ω

25°C, each pot

I

Wiper current

±6

W

R

Wiper resistance

150

500

+5.5

-4.5

-2.7

V+

Wiper Current = ± 3mA

X9118

W

V +

Voltage on V+ pin

+4.5

+2.7

-5.5

V-

V

X9118-2.7

X9118

V -

V

Voltage on V- pin

V

X9118-2.7

V

Voltage on any R or R pin

V

= 0V

SS

TERM

H

L

Noise

Resolution ⁽⁴⁾

-120

0.1

dBV/√Hz Ref: 1V

%

(5)

Absolute linearity ⁽¹⁾

Relative linearity ⁽²⁾

±1

MI⁽³⁾

R

–R

w(n)(actual) w(n)(expected)

(5)

±0.2

–[R

]

w(n + 1)

w(n) + MI

Temperature coefficient of R

±300

ppm/°C

pF

TOTAL

Ratiometric Temperature Coefficient

Potentiometer Capacitances

20

C /C /C

W

10/10/25

See Macro model

H

L

Characteristics subject to change without notice. 11 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

I

V

write)

supply current (nonvolatile

1

mA

f = 400kHz, SDA = Open,

SCL

CC1

CC

Other Inputs = V

SS

I

V

supplycurrent(movewiper,

100

µA

f

= 400kHz, SDA = Open,

SCL

CC2

CC

write, read)

Other Inputs = V

SS

I

V

current (standby)

1

µA

V

SCL = SDA = V , Addr. = V

CC SS

SB

CC

I

Input leakage current

Output leakage current

Input HIGH voltage

Input LOW voltage

Output LOW voltage

10

V

= V to V

SS CC

LI

IN

I

= V to V

SS CC

LO

OUT

V

x 0.7

V

x 0.5

IH

CC

V

–0.5

x 0.1

V

IL

CC

V

0.4

V

I

= 3mA

OL

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used

as a potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (V –V )/63, single pot

H

L

(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.

ENDURANCE AND DATA RETENTION

Parameter

Minimum endurance

Data retention

Min.

100,000

100

Unit

Data changes per bit per register

years

CAPACITANCE

Symbol

Test

Max.

Unit

pF

Test Condition

(5)

I/O

C

Input/output capacitance (SDA)

8

6

V

= 0V

I/O

(5)

IN

C

Input capacitance (A0, A1, A2, A3, and SCL)

pF

V

IN

POWER-UP TIMING

Symbol

Parameter

Min.

Max.

1

Unit

ms

(6)

PUR

t

Power-up to initiation of read operation

Power-up to initiation of write operation

(6)

PUW

t

5

ms

(7)

CC

t V

V Power Up Ramp

CC

0.2

50

V/msec

R

POWER-UP AND POWER-DOWN

There are no restrictions on the power-up or power-down sequencing of the bias supplies V , V+, and V- provided

CC

that all three supplies reach their ﬁnal values within 1msec of each other. However, at all times, the voltages on the

potentiometer pins must be less than V+ and more than V–. The recall of the wiper position from nonvolatile

memory is not in effect until all supplies reach their ﬁnal value.

Notes: (5) This parameter is periodically sampled and not 100% tested

(6) t

and t

are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the speciﬁc

PUR

PUW CC

instruction can be issued.These parameters are periodically sampled and not 100% tested.

(7) This is not a tested or guaranteed parameter and should only be used as a guidance.

Characteristics subject to change without notice. 12 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

A.C. TEST CONDITIONS

Test Circuit #3 SPICE Macro Model

Input pulse levels

V

x 0.1 to V x 0.9

CC

R

TOTAL

Input rise and fall times

Input and output timing level

10ns

R

L

H

C

V

x 0.5

L

CC

C

H

C

W

10pF

EQUIVALENT A.C. LOAD CIRCUIT

10pF

25pF

5V

2.7V

R

W

1533Ω

SDA Output

100pF

AC TIMING (over recommended operating condition)

Symbol Parameter

Min.

Max.

Unit

kHz

ns

f

Clock frequency

400

SCL

t

Clock cycle time

2500

600

1300

600

100

30

CYC

t

Clock high time

HIGH

t

Clock low time

LOW

t

Start setup time

SU:STA

HD:STA

SU:STO

t

Start hold time

t

Stop setup time

t

SDA data input setup time

SDA data input hold time

SCL and SDA rise time

SCL and SDA fall time

SCL low to SDA data output valid time

SDA Data output hold time

SU:DAT

HD:DAT

t

300

900

R

t

F

t

AA

DH

t

50

1300

0

T

Noise suppression time constant at SCL and SDA inputs

Bus free time (prior to any transmission)

WP, A0, A1, A2 and A3 setup time

I

t

BUF

t

SU:WPA

t

WP, A0, A1, A2 and A3 hold time

0

HD:WPA

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol

Parameter

Typ.

Max.

Unit

t

High-voltage write cycle time (store instructions)

5

10

ms

WR

Characteristics subject to change without notice. 13 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

XDCP TIMING

Symbol

Parameter

Min. Max. Unit

t

Wiper response time after the third (last) power supply is stable

10

µs

WRPO

t

Wiper response time after instruction issued (all load instructions)

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

WRL

t

WRID

Notes: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undeﬁned region of the falling

edge of SCL.

TIMING DIAGRAMS

START and STOP Timing

g

(START)

(STOP)

t

F

R

SCL

SDA

t

SU:STO

SU:STA

HD:STA

t

F

R

Input Timing

t

CYC

HIGH

SCL

SDA

t

LOW

t

BUF

SU:DAT

HD:DAT

Output Timing

SCL

SDA

t

DH

AA

Characteristics subject to change without notice. 14 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

XDCP Timing (for All Load Instructions)

(STOP)

SCL

SDA

VWx

LSB

t

WRL

XDCP Timing (for Increment/Decrement Instruction)

SCL

Wiper Register Address

Inc/Dec

SDA

VWx

t

WRID

Write Protect and Device Address Pins Timing

(START)

(STOP)

SCL

...

(Any Instruction)

...

SDA

...

t

SU:WPA

HD:WPA

WP

A0, A1

A2, A3

Characteristics subject to change without notice. 15 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

PACKAGING INFORMATION

24-Lead Plastic Dual In-Line Package Type P

1.265 (32.13)

1.230 (31.24)

0.557 (14.15)

0.530 (13.46)

Pin 1 Index

Pin 1

0.080 (2.03)

0.065 (1.65)

1.100 (27.94)

Ref.

0.162 (4.11)

0.140 (3.56)

Seating

Plane

0.030 (0.76)

0.015 (0.38)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.065 (1.65)

0.040 (1.02)

0.022 (0.56)

0.014 (0.36)

0.625 (15.87)

0.600 (15.24)

0°

Typ. 0.010 (0.25)

15°

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

Characteristics subject to change without notice. 16 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

PACKAGING INFORMATION

24-Lead Plastic Small Outline Gull Wing Package Type S

0.393 (10.00)

0.290 (7.37)

0.299 (7.60)

0.420 (10.65)

Pin 1 Index

Pin 1

0.014 (0.35)

0.020 (0.50)

0.598 (15.20)

0.610 (15.49)

(4X) 7°

0.092 (2.35)

0.105 (2.65)

0.003 (0.10)

0.012 (0.30)

0.050 (1.27)

0.050"Typical

0.010 (0.25)

0.020 (0.50)

X 45°

0.050"

Typical

0° – 8°

0.009 (0.22)

0.013 (0.33)

0.420"

0.015 (0.40)

0.050 (1.27)

0.030" Typical

24 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 17 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

PACKAGING INFORMATION

24-Lead Plastic, TSSOP Package Type V

.026 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.303 (7.70)

.311 (7.90)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.06)

.005 (.15)

.010 (.25)

Gage Plane

(7.72)

(4.16)

0°–8°

Seating Plane

.020 (.50)

.030 (.75)

(1.78)

(0.42)

Detail A (20X)

(0.65)

ALL MEASUREMENTS ARE TYPICAL

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 18 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

PACKAGING INFORMATION

24-Ball BGA (X9408WC)

a

l

j

m

1

2

3

4

3

2

1

A

B

C

D

E

F

A

B

C

D

E

F

k

b

f

Top View (Bump Side Down)

Bottom View (Bump Side Up)

Note: Drawing not to scale

d

= Die Orientation mark

c

e

Side View (Bump Side Down)

Millimeters

Inches

Symbol Min

Nom.

Max

Min

Nom

Max

Package Body Dimension X

Package Body Dimension Y

Package Height

a

b

c

d

e

f

2.575 2.605 2.635 0.10138 0.10258 0.10374

3.794 3.824 3.854 0.14937 0.15055 0.15173

0.697 0.750 0.763 0.02744 0.02874 0.03004

Package Body Thickness

Ball Height

0.444 0.457 0.470 0.01748 0.01799 0.01850

0.253 0.273 0.293 0.00996 0.01075 0.01154

Ball Diameter

0.360 0.374 0.388 0.01417 0.01472 0.01528

Total Ball Count

g

h

i

24

Ball Count X Axis

Ball Count Y Axis

Pins Pitch XAxis

4

6

j

0.5

Pins Pitch Y Axis

k

l

0.5

Edge to Ball Center (Corner) Distance Along X

Edge to Ball Center (Corner) Distance Along Y

0.523 0.553 0.583 0.02057 0.02175 0.02293

0.632 0.662 0.692 0.02488 0.02606 0.02724

m

Characteristics subject to change without notice. 19 of 20

REV 1.0 6/20/00

www.xicor.com

X9408

Ordering Information

X9408

Y

P

T

V

Limits

CC

Device

Blank = 5V ±10%

–2.7 = 2.7 to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C

I = Industrial = –40°C to +85°C

Package

S24 = 24-Lead SOIC

V24 = 24-Lead TSSOP

Z24 = 24-Lead XBGA

Potentiometer Organization

Pot 0 Pot 1 Pot 3 Pot 4

W =

Y =

10KΩ 10KΩ 10KΩ 10KΩ

2.5KΩ 2.5KΩ 2.5KΩ 2.5KΩ

Part Mark Convention

24 Lead XBGA

X9408WZ24I-2.7

X9408WZ24

Top Mark

XABO

XABP

XACB

XACA

X9408YZ24

X9408YZ24I-2.7

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,

express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.

Xicor, Inc. makes no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices

at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All

others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;

4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;

5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection

and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

Characteristics subject to change without notice. 20 of 20

REV 1.0 6/20/00

www.xicor.com

Xicor Product Change Notice 02/04/00

Page 1 of 9

Product Change Notice : PCN February 4, 2000

February 4, 2000

Ref: PCN-00-01

Dear Xicor Customer,

At Xicor, we continuously strive to improve the performance and efficiency of our operations, and

the quality of our products. Consistent with this effort, we are currently adding additional wafer

fabrication capacity for various IIC and SPI serial products.

This added wafer fabrication capacity will complement current operations and will expand Xicor’s

capabilities to accommodate future growth.

In addition, several of the IIC and SPI serial products are undergoing a die revision change. The

new die revision is functionally and pin to pin compatable with the existing die revision.

See the detailed product number list below for the implementation date and description of the

change. Samples for qualification will be available approximately 4 weeks before the

implementation date. Qualification data is available upon request.

If you have any further questions, please contact your regional Xicor sales office.

Sincerely,

Xicor Marketing Department

Xicor Part Number

IIC Serial Products

X24164P

Implement Date

Description of Change

2/28/00

5/31/00

Foundry Change

X24164P-3

Foundry Change

X24164PI

Foundry Change

X24164PI-3

X24164S

Foundry Change

X24164S-2.7

X24164S-3

Foundry Change

X24164SI

Foundry Change

X24164SI-2.7

X24C04P

Foundry Change

Die Rev / Foundry Change

X24C04P-2.7

X24C04P-3

X24C04P-3.5

X24C04PI

X24C04PI-2.7

file://F:\export\projects\bitting2\imaging\BITTING\mail_pdf\recode\pcn_000204.html

1/15/01

Xicor Product Change Notice 02/04/00

Page 2 of 9

X24C04PI-3

5/31/00

8/31/00

Die Rev / Foundry Change

X24C04PI-3.5

X24C04PM

X24C04PM-3

X24C04PM-3.5

X24C04S14

X24C04S14-3

X24C04S14-3.5

X24C04S14I

X24C04S14I-3

X24C04S14I-3.5

X24C04S14M

X24C04S14M-3

X24C04S14M-3.5

X24C04S8

X24C04S8-2.7

X24C04S8-3

X24C04S8-3.5

X24C04S8I

X24C04S8I-2.7

X24C04S8I-3

X24C04S8I-3.5

X24C04S8M

X24C04S8M-3

X24C04S8M-3.5

X24C08P

X24C08P-2.7

X24C08P-3

X24C08P-3.5

X24C08PI

X24C08PI-2.7

X24C08PI-3

X24C08PI-3.5

X24C08PM

X24C08PM-3

X24C08PM-3.5

X24C08S

X24C08S-3

X24C08S-3.5

X24C08S8

X24C08S8-2.7

X24C08S8-3

X24C08S8I

X24C08S8I-2.7

file://F:\export\projects\bitting2\imaging\BITTING\mail_pdf\recode\pcn_000204.html

1/15/01

Xicor Product Change Notice 02/04/00

Page 3 of 9

X24C08S8I-3

X24C08S8M

X24C08SI

8/31/00

Die Rev / Foundry Change

X24C08SI-3

X24C08SI-3.5

X24C08SM

X24C08SM-3

X24C08SM-3.5

SPI Serial Products

X25020P

7/31/00

8/31/00

Die Rev / Foundry Change

Foundry Change

X25020P-2.7

X25020PI

X25020PI-2.7

X25020S

X25020S-2.7

X25020S-3

X25020SI

X25020SI-2.7

X25020SI-3

X25040P

X25040P-2.7

X25040PI

X25040PI-2.7

X25040S

X25040S-2.7

X25040SI

X25040SI-2.7

X25040SM

X25160S

X25160S-2.7

X25160SI

Foundry Change

X25160SI-2.7

X25320P

Foundry Change

X25320S

Foundry Change

X25320S-2.7

X25320SI

Foundry Change

X25320SI-2.7

Foundry Change

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1/15/01

Xicor Product Change Notice 02/04/00

Page 4 of 9

February 4, 2000

Dear Xicor Customer,

At Xicor, we continuously strive to improve the performance and efficiency of our operations, and

the quality of our products. Consistent with this effort, we are revising the tape and reel "T" codes

to eliminate partial reel quantities.

See the detailed tape and reel "T" codes definitions list and definitions matrix below . The

implementation date for the new tape and reel "T" codes is March 1, 2000. All existing orders with

shipment dates on or after March 1, 2000 will be converted to the new tape and reel "T" codes. All

new orders on or after March 1, 2000 must use the new tape and reel "T" codes.

If you have any further questions, please contact your regional Xicor sales office.

Sincerely,

Xicor Marketing Department

Tape and Reel "T" Code Definitions

CODE

T1

PACKAGE

QTY

REQUIREMENTS

Tape and Reel

REEL SIZE

13"

SOIC (150 MIL SOIC) "S"

SOIC (300 MIL SOIC) "S"

EIAJ (WIDE SOIC) "A"

TSOP (THIN SOIC) "T"

PLCC "J"

=2500

=1000

=2000

=1000

=750

13"

T1

13"

T1

13"

T1

13"

T1

MSOP "M"

=2500

=500

13"

T1

GULL WING "R"

TSSOP "V"

13"

T1

=2500

=10000

13"

T1

XBGA "B" or "Z"

13"

T1

SOIC (150 MIL SOIC) "S"

SOIC (300 MIL SOIC) "S"

EIAJ (WIDE SOIC) "A"

=1000

=500

Tape and Reel

7"

T2

13"

7"

T2

=1000

T2

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1/15/01

Xicor Product Change Notice 02/04/00

Page 5 of 9

TSOP (THIN SOIC) "T"

PLCC "J"

=500

Tape and Reel

13"

7"

T2

T3

T4

T5

T6

=500

Tape and Reel

MSOP "M"

=1000

=250

Tape and Reel

GULL WING "R"

TSSOP "V"

Tape and Reel

13"

7"

=1000

=5000

=2500

=1000

=2000

=1000

=750

Tape and Reel

XBGA "B" or "Z"

SOIC (150 MIL SOIC) "S"

SOIC (300 MIL SOIC) "S"

EIAJ (WIDE SOIC) "A"

TSOP (THIN SOIC) "T"

PLCC "J"

Tape and Reel

13"

7"

Tape and Reel & Dry Pack

Tape and Reel

MSOP "M"

=2500

=500

GULL WING "R"

TSSOP "V"

=2500

=10000

=1000

=500

XBGA "B" or "Z"

SOIC (150 MIL SOIC) "S"

SOIC (300 MIL SOIC) "S"

EIAJ (WIDE SOIC) "A"

TSOP (THIN SOIC) "T"

PLCC "J"

13"

7"

=1000

=500

13"

7"

=500

MSOP "M"

=1000

=250

GULL WING "R"

TSSOP "V"

13"

7"

=1000

=5000

=3500

=2500

=3500

=2500

XBGA "B" or "Z"

MSOP "M"

13"

TSSOP "V"

Tape and Reel

XBGA "B" or "Z"

MSOP "M"

Tape and Reel

Tape and Reel & Dry Pack

TSSOP "V"

XBGA "B" or "Z"

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Xicor Product Change Notice 02/04/00

Page 6 of 9

XBGA "B" or "Z"

ALL PACKAGES

=2500

Tape and Reel & Dry Pack

Dry Pack

13"

T6

T7

ALL QTYS.

N/A

Tape and Reel "T" Code Definition Matrix

150 MIL SOIC "S" (8L, 14L,16L)

Code

T1

2500

1000

Dry Pack

x

T2

x

T3

T4

x

T7*

x

*NOTE: DRY PACK ONLY

TSOP THIN SOIC "T"

1000

500

Dry Pack

Code

T1

x

T2

x

T3

x

T4

x

T7*

*NOTE: DRY PACK ONLY

GULL WING "R"

Code

T1

500

x

250

Dry Pack

x

T2

x

T3

x

X

x

T4

x

T7*

file://F:\export\projects\bitting2\imaging\BITTING\mail_pdf\recode\pcn_000204.html

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Xicor Product Change Notice 02/04/00

Page 7 of 9

*NOTE: DRY PACK ONLY

300 MIL SOIC "S" (20L, 24L, 28L)

Code 1000 500

Dry Pack

T1

T2

T3

T4

T7*

X

x

X

x

X

x

X

x

X

*NOTE: DRY PACK ONLY

XBGA "B" or "Z"

Code

T1

10000

5000 2500

Dry Pack

x

T2

x

T3

x

T4

x

T5

x

T6

x

T7*

*NOTE: DRY PACK ONLY

EIAJ "A"

Code

T1

2000

1000

Dry Pack

x

T2

x

T3

x

T4

x

T7*

*NOTE: DRY PACK ONLY

file://F:\export\projects\bitting2\imaging\BITTING\mail_pdf\recode\pcn_000204.html

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Xicor Product Change Notice 02/04/00

Page 8 of 9

PLCC "J"

Code

T1

750

x

500

x

Dry Pack

x

T2

x

T3

x

X

x

T4

x

T7*

x

*NOTE: DRY PACK ONLY

TSSOP "V"

Code

T1

2500

1000

3500

Dry Pack

x

T2

x

T3

x

T4

x

T5

x

T6

x

T7*

*NOTE: DRY PACK ONLY

MSOP "M"

Code

T1

2500

1000

3500

Dry Pack

x

T2

x

T3

x

T4

x

T5

x

T6

x

file://F:\export\projects\bitting2\imaging\BITTING\mail_pdf\recode\pcn_000204.html

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Xicor Product Change Notice 02/04/00

Page 9 of 9

x

T7*

x

*NOTE: DRY PACK ONLY

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file://F:\export\projects\bitting2\imaging\BITTING\mail_pdf\recode\pcn_000204.html

1/15/01


型号：	X9408YZ24-2.7T5
厂家：	XICOR INC.
描述：	Digital Potentiometer, 4 Func, 2500ohm, 2-wire Serial Control Interface, 64 Positions, CMOS, PBGA24, XBGA-24
文件：	总29页 (文件大小：175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X9408YZ24-2.7T5 [XICOR]

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