X9408YV24Z_技术文档

X9408

®

Low Noise/Low Power/2-Wire Bus

Data Sheet

September 19, 2005

FN8191.2

DESCRIPTION

Quad Digitally Controlled (XDCP™)

Potentiometers

The X9408 integrates four digitally controlled

potentiometers (XDCP) on a monolithic CMOS

integrated circuit.

FEATURES

• Four potentiometers in one package

• 64 resistor taps per potentiometer

• 2-wire serial interface

• Wiper resistance, 40Ω typical at 5V

• Four nonvolatile data registers for each pot

• Nonvolatile storage of wiper position

• Standby current < 1µA max (total package)

The digital controlled potentiometer is implemented

using 63 resistive elements in a series array. Between

each element are tap points connected to the wiper

terminal through switches. The position of the wiper on

the array is controlled by the user through the 2-wire

bus interface. Each potentiometer has associated with

it a volatile Wiper Counter Register (WCR) and four

non-volatile Data Registers that can be directly written

to and read by the user. The contents of the WCR

controls the position of the wiper on the resistor array

though the switches. Powerup recalls the contents of

the default data register (DR0) to the WCR.

• V

= 2.7V to 5.5V operation

CC

V+ = 2.7V to 5.5V

V- = –2.7V to -5.5V

• 10kΩ, 2.5kΩ end to end resistances

• High reliability

—Endurance–100,000 data changes per bit per

register

The XDCP can be used as

a three-terminal

—Register data retention–100 years

• 24 Ld SOIC, 24 Ld TSSOP, 24 Ld PDIP packages

• Pb-free plus anneal available (RoHS compliant)

potentiometer or as a two terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

V+

V-

Pot 0

CC

SS

R0 R1

R2 R3

V

/R

R0 R1

R2 R3

H0 H0

Wiper

Counter

Register

(WCR)

Wiper

Counter

Register

(WCR)

V

/R

H2 H2

Resistor

Array

Pot 2

V

/R

L0 L0

WP

V

/R

L2 L2

V

/R

SCL

SDA

A0

W0 W0

V

/R

W2 W2

Interface

and

Control

A1

8

Circuitry

A2

V

/

R

A3

W1 W1

Data

V

/R

W3 W3

R0 R1

R2 R3

R0 R1

R2 R3

V

/R

Wiper

Counter

Register

(WCR)

H1 H1

/

R

Resistor

Array

Pot 1

Wiper

Counter

Register

(WCR)

H3 H3

Resistor

Array

Pot 3

V

/R

L1 L1

V

/R

L3 L3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

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All other trademarks mentioned are the property of their respective owners.

X9408

Ordering Information

POTENTIOMETER

ORGANIZATION

(kΩ)

TEMP RANGE

(°C)

PART NUMBER

X9408YP24

PART MARKING V

LIMITS (V)

PACKAGE

CC

5 ±10%

2.5

0 to 70

24 Ld PDIP

X9408YS24*

24 Ld SOIC (300 mil)

24 Ld TSSOP (4.4mm)

24 Ld TSSOP (4.4mm) (Pb-free)

24 Ld TSSOP (4.4mm)

24 Ld TSSOP (4.4mm) (Pb-free)

24 Ld PDIP

X9408YS24I*

-40 to 85

0 to 70

X9408YV24*

X9408YV

X9408YV24Z* (Note)

X9408YV24I*

X9408YV Z

X9408YV I

X9408YV Z I

0 to 70

-40 to 85

0 to 70

X9408YV24IZ* (Note)

X9408WP24

10

X9408WP24I

-40 to 85

0 to 70

24 Ld PDIP

X9408WS24*

X9408WS

24 Ld SOIC (300 mil)

24 Ld TSSOP (4.4mm)

24 Ld TSSOP (4.4mm) (Pb-free)

24 Ld TSSOP (4.4mm)

24 Ld TSSOP (4.4mm) (Pb-free)

24 Ld PDIP

X9408WS24I*

X9408WS I

X9408WV

-40 to 85

0 to 70

X9408WV24*

X9408WV24Z* (Note)

X9408WV24I*

X9408WV Z

X9408WV I

X9408WV Z I

0 to 70

-40 to 85

0 to 70

X9408WV24IZ* (Note)

X9408YP24I-2.7

X9408YS24-2.7*

X9408YS24I-2.7*

X9408YV24-2.7*

X9408YV24Z-2.7* (Note)

X9408YV24I-2.7*

2.7 to 5.5

2.5

24 Ld SOIC (300 mil)

24 Ld TSSOP (4.4mm)

24 Ld TSSOP (4.4mm) (Pb-free)

24 Ld TSSOP (4.4mm)

-40 to 85

0 to 70

X9408YV F

X9408YV Z F

X9408YV G

0 to 70

-40 to 85

X9408YV24IZ-2.7T1 (Note) X9408YV Z G

24 Ld TSSOP (4.4mm) Tape and Reel

(Pb-free)

X9408WP24-2.7

X9408WP24I-2.7

10

0 to 70

-40 to 85

0 to 70

24 Ld PDIP

X9408WS24-2.7*

X9408WS24I-2.7*

X9408WSI-2.7

X9408WS F

X9408WS G

24 Ld SOIC (300 mil)

24 Ld TSSOP (4.4mm)

24 Ld TSSOP (4.4mm) (Pb-free)

24 Ld TSSOP (4.4mm)

24 Ld TSSOP (4.4mm) (Pb-free)

-40 to 85

0 to 70

X9408WV24-2.7*

X9408WV F

X9408WV24Z-2.7* (Note) X9408WV Z F

X9408WV24I-2.7* X9408WV G

0 to 70

-40 to 85

X9408WV24IZ-2.7* (Note) X9408WV Z G

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8191.2

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September 19, 2005

X9408

PIN DESCRIPTIONS

V /R (V /R

W0 W0

– V /R )

W3 W3

W

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

Hos t Interface Pins

Serial Clock (SCL)

Hardware Write Protect Input (WP)

The SCL input is used to clock data into and out of the

X9408.

The WP pin when low prevents nonvolatile writes to

the Data Registers.

Serial Data (SDA)

Analog Supplies V+, V-

SDA is a bidirectional pin used to transfer data into

and out of the device. It is an open drain output and

may be wire-ORed with any number of open drain or

open collector outputs. An open drain output requires

the use of a pull-up resistor. For selecting typical

values, refer to the guidelines for calculating typical

values on the bus pull-up resistors graph.

The Analog Supplies V+, V- are the supply voltages

for the XDCP analog section.

PIN NAMES

Symbol

Description

Serial Clock

SCL

SDA

A0-A3

Serial Data

Device Address (A - A )

0

3

Device Address

The address inputs are used to set the least significant

4 bits of the 8-bit slave address. A match in the slave

address serial data stream must be made with the

address input in order to initiate communication with

the X9408. A maximum of 16 devices may occupy the

2-wire serial bus.

V

/R - V /R

H0 H0 H3 H3

/R - V /R

L0 L0 L3 L3

,

Potentiometer Pins

(terminal equivalent)

V

/R

- V /R

Potentiometer Pins

(wiper equivalent)

W0 W0 W3 W3

WP

Hardware Write Protection

Analog Supplies

V+,V-

Potentiometer Pins

V

System Supply Voltage

System Ground

V /R (V /R - V /R ), V /R (V /R - V /R

)

CC

H

H0 H0 H3 H3 L0 L0 L3 L3

L

V

The V /R and V /R inputs are equivalent to the

SS

H

L

terminal connections on either end of a mechanical

potentiometer.

NC

No Connection

PIN CONFIGURATION

DIP/SOIC

TSSOP

V+

V

WP

SDA

1

2

24

23

22

21

20

19

18

17

16

15

1

2

24

23

22

21

20

19

18

17

16

15

CC

/R

V

/R

A

2

A

L3 L3

L0 L0

1

V

/R

V

A

/R

V

/R

3

V

/R

W0 W0

H3 H3

3

H0 H0

L1 L1

/R

V

/R

V

/R

4

H1 H1

H0 H0

W3 W3

4

W0 W0

V

/R

W1 W1

/R

A

2

5

L0 L0

0

V

NC

SS

WP

6

CC

X9408

SDA

V-

A

3

7

V+

V

7

V

/R

SCL

A

1

/R

W2 W2

8

L3 L3

V

/R

V

/R

V

/R

9

V

/R

9

L2 L2

H2 H2

L1 L1

H3 H3

V

/R

10

L2 L2

H2 H2

10

V

/R

W3 W3

H1 H1

V

/R

A

14

13

SCL

14

13

V

/R

W2 W2

11

12

0

11

12

W1 W1

V

A

3

V-

SS

NC

FN8191.2

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September 19, 2005

X9408

PRINCIPLES OF OPERATION

The X9408 is highly integrated microcircuit

incorporating four resistor arrays and their associated

registers and counters and the serial interface logic

providing direct communication between the host and

the XDCP potentiometers.

The X9408 will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9408 will respond with a final acknowledge.

a

Array Description

The X9408 is comprised of four resistor arrays. Each

array contains 63 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the fixed terminals of a mechanical

Serial Interface

The X9408 supports a bidirectional bus oriented

protocol. The protocol defines any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9408 will be considered a

slave device in all applications.

potentiometer (R and R inputs).

H

L

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper

(R ) output. Within each individual array only one

W

switch may be turned on at a time. These switches are

controlled by the Wiper Counter Register (WCR). The

six bits of the WCR are decoded to select, and enable,

one of sixty-four switches.

Clock and Data Conventions

Data states on the SDA line can change only during

The WCR may be written directly, or it can be changed

by transferring the contents of one of four associated

Data Registers into the WCR. These Data Registers

and the WCR can be read and written by the host

system.

SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop

conditions.

Start Condition

All commands to the X9408 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most

significant four bits of the slave address are the device

type identifier (refer to Figure 1 below). For the X9408

this is fixed as 0101[B].

while SCL is HIGH (t

). The X9408 continuously

HIGH

monitors the SDA and SCL lines for the start condition

and will not respond to any command until this

condition is met.

Stop Condition

Figure 1. Slave Address

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH.

Device Type

Identifier

Acknowledge

0

1

0

1

A3

A2

A1

A0

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

Device Address

The next four bits of the slave address are the device

address. The physical device address is defined by

the state of the A - A inputs. The X9408 compares

the serial data stream with the address input state; a

successful compare of all four address bits is required

for the X9408 to respond with an acknowledge. The

0

3

A - A inputs can be actively driven by CMOS input

0

3

signals or tied to V

or V

.

CC

SS

FN8191.2

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September 19, 2005

X9408

Acknowledge Polling

Figure 2. Instruction Byte Format

The disabling of the inputs, during the internal

Nonvolatile write operation, can be used to take

advantage of the typical 5ms EEPROM write cycle

time. Once the stop condition is issued to indicate the

end of the nonvolatile write command the X9408

initiates the internal write cycle. ACK polling can be

initiated immediately. This involves issuing the start

condition followed by the device slave address. If the

X9408 is still busy with the write operation no ACK will

be returned. If the X9408 has completed the write

operation an ACK will be returned and the master can

then proceed with the next operation.

Register

Select

I3

I2

I1

I0

R1 R0

P1 P0

Wiper Counter

Register Select

Instructions

The four high order bits define the instruction. The

next two bits (R1 and R0) select one of the four

registers that is to be acted upon when a register

oriented instruction is issued. The last bits (P1, P0)

select which one of the four potentiometers is to be

affected by the instruction.

Flow 1. ACK Polling Sequence

Nonvolatile Write

Command Completed

Enter ACK Polling

Four of the nine instructions end with the transmission

of the instruction byte. The basic sequence is

illustrated in Figure 3. These two-byte instructions

exchange data between the Wiper Counter Register

and one of the Data Registers. A transfer from a Data

Register to a Wiper Counter Register is essentially a

write to a static RAM. The response of the wiper to this

Issue

START

action will be delayed t

. A transfer from the Wiper

WRL

Counter Register (current wiper position), to a data

register is a write to nonvolatile memory and takes a

Issue Slave

Issue STOP

Address

minimum of t

to complete. The transfer can occur

WR

between one of the four potentiometers and one of its

associated registers; or it may occur globally, wherein

the transfer occurs between all of the potentiometers

and one of their associated registers.

NO

ACK

Returned?

YES

Four instructions require a three-byte sequence to

complete. These instructions transfer data between

the host and the X9408; either between the host and

one of the data registers or directly between the host

and the Wiper Counter Register. These instructions

are: Read Wiper Counter Register (read the current

wiper position of the selected pot), Write Wiper

Counter Register (change current wiper position of the

selected pot), Read Data Register (read the contents

of the selected nonvolatile register) and Write Data

Register (write a new value to the selected Data

Register). The sequence of operations is shown in

Figure 4.

NO

Further

Operation?

YES

Issue

Instruction

Issue STOP

Proceed

Instruction Structure

The next byte sent to the X9408 contains the instruction

and register pointer information. The four most

significant bits are the instruction. The next four bits

point to one of the two pots and when applicable they

point to one of four associated registers. The format is

shown below in Figure 2.

FN8191.2

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September 19, 2005

X9408

Figure 3. Two-Byte Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 P1 P0

A

C

K

S

T

O

P

The Increment/Decrement command is different from

the other commands. Once the command is issued

and the X9408 has responded with an acknowledge,

the master can clock the selected wiper up and/or

down in one segment steps; thereby, providing a fine

tuning capability to the host. For each SCL clock pulse

move one resistor segment towards the R terminal.

H

Similarly, for each SCL clock pulse while SDA is LOW,

the selected wiper will move one resistor segment

towards the R terminal. A detailed illustration of the

L

sequence and timing for this operation are shown in

Figures 5 and 6 respectively.

(t

) while SDA is HIGH, the selected wiper will

HIGH

Table 1. Instruction Set

Instruction Set

Instruction

I

R

P

Operation

3

2

1

0

1

0

1

0

Read Wiper Counter

Register

1

0

1

0

1

0

1

0

1

0

P

Read the contents of the Wiper Counter Register

1

0

pointed to by P - P

1

0

Write Wiper Counter

Register

0

1

0

P

Write new value to the Wiper Counter Register pointed

to by P - P

1

0

1

0

Read Data Register

R

Read the contents of the Data Register pointed to by

P - P and R - R

1

0

1

0

1

0

Write Data Register

R

Write new value to the Data Register pointed to by

P - P and R - R

1

0

1

0

XFR Data Register to

Wiper Counter Register

Transfer the contents of the Data Register pointed to

by P - P and R - R to its associated Wiper Counter

1

0

1

0

Register

XFR Wiper Counter

Register to Data

Register

1

0

1

0

1

0

1

0

1

0

1

0

R

P

Transfer the contents of the Wiper Counter Register

pointed to by P - P to the Data Register pointed to

1

0

1

0

1

0

by R - R

1

0

Global XFR Data Regis-

ters to Wiper Counter

Registers

0

Transfer the contents of the Data Registers pointed to by

R - R of all four pots to their respective Wiper Counter

1

0

Registers

Global XFR Wiper

Counter Registers to

Data Register

0

Transfer the contents of both Wiper Counter Registers

to their respective Data Registers pointed to by

R - R of all four pots

1

0

Increment/Decrement

Wiper Counter Register

0

P

Enable Increment/decrement of the Wiper Counter

Register pointed to by P - P

1

0

1

0

Note: (7) 1/0 = data is one or zero

FN8191.2

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September 19, 2005

X9408

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 P1 P0

A

C

K

0

D5 D4 D3 D2 D1 D0

A

C

K

S

T

O

P

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 P1 P0

A

C

K

I

D

E

C

1

S

T

O

P

I

D

N

C

1

N

C

2

N

C

n

E

C

n

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

t

WRID

SCL

SDA

Voltage Out

V

/R

W

FN8191.2

September 19, 2005

7

X9408

Figure 7. Acknowledge Response from Receiver

SCL from

Master

1

8

9

Data Output

from Transmitter

Data Output

from Receiver

START

Acknowledge

Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path

Serial

Bus

Input

V /R

H H

From Interface

Circuitry

C

o

u

n

t

Register 0

Register 2

Register 1

8

6

Parallel

Bus

Input

e

r

Wiper

D

e

c

o

d

e

Register 3

Counter

Register

(WCR)

INC/DEC

Logic

If WCR = 00[H] then V /R = V /R

W

L

UP/DN

If WCR = 3F[H] then V /R = V /R

H

W

H

V /R

Modified SCL

L

CLK

V

/R

W

FN8191.2

September 19, 2005

8

X9408

DETAILED OPERATION

If the application does not require storage of multiple

settings for the potentiometer, these registers can be

used as regular memory locations that could possibly

store system parameters or user preference data.

All XDCP potentiometers share the serial interface

and share a common architecture. Each potentiometer

has a Wiper Counter Register and four Data

Registers. A detailed discussion of the register

organization and array operation follows.

Register Descriptions

Data Registers, (6-Bit), Nonvolatile

Wiper Counter Register

D5

NV

D4

NV

D3

NV

D2

NV

D1

NV

D0

NV

The X9408 contains four Wiper Counter Registers,

one for each XDCP potentiometer. The Wiper Counter

Register can be envisioned as a 6-bit parallel and

serial load counter with its outputs decoded to select

one of sixty-four switches along its resistor array. The

contents of the WCR can be altered in four ways: it

may be written directly by the host via the Write Wiper

Counter Register instruction (serial load); it may be

written indirectly by transferring the contents of one of

four associated data registers via the XFR Data

Register instruction (parallel load); it can be modified

one step at a time by the Increment/ Decrement

instruction. Finally, it is loaded with the contents of its

data register zero (DR0) upon power-up.

(MSB)

(LSB)

Four 6-bit Data Registers for each XDCP. (sixteen 6-

bit registers in total).

– {D5~D0}: These bits are for general purpose not vol-

atile data storage or for storage of up to four differ-

ent wiper values. The contents of Data Register 0

are automatically moved to the wiper counter regis-

ter on power-up.

Wiper Counter Register, (6-Bit), Volatile

WP5

V

WP4

V

WP3

V

WP2

V

WP1

V

WP0

V

The WCR is a volatile register; that is, its contents are

lost when the X9408 is powered-down. Although the

register is automatically loaded with the value in R0

upon power-up, it should be noted this may be

different from the value present at power-down.

(MSB)

(LSB)

One 6-bit Wiper Counter Register for each XDCP.

(Four 6-bit registers in total.)

Data Registers

– {D5~D0}: These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is

loaded on power-up by the value in Data Register 0.

The contents of the WCR can be loaded from any of

the other Data Register or directly. The contents of

the WCR can be saved in a DR.

Each potentiometer has four nonvolatile Data

Registers. These can be read or written directly by the

host and data can be transferred between any of the

four Data Registers and the WCR. It should be noted

all operations changing data in one of these registers

is a nonvolatile operation and will take a maximum of

10ms.

FN8191.2

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September 19, 2005

X9408

Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.

(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.

(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).

(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

wiper position

(sent by slave on SDA)

S

A

C

K

S

A

C

K

M S

A T

C O

K P

W W W W W W

0 0 P P P P P P

A A A A

P P

1 0

0

1

0

1

0

1

0

3

2

1

0

5

4 3 2 1 0

Write Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

wiper position

(sent by master on SDA)

S

A

C

K

S

A

C

K

S S

A T

C O

K P

W W W W W W

0 0 P P P P P P

A A A A

P P

1 0

0

1

0

1

0

1

0

3

2

1

0

5

4 3 2 1 0

Read Data Register (DR)

S device type device

instruction DR and WCR

wiper position/data

(sent by slave on SDA)

S

A

C

K

S

M S

T

A

R

T

identifier

addresses

opcode

addresses

A

C

K

A T

C O

K P

W W W W W W

0 0 P P P P P P

A A A A

R

1

R

0

P

1

P

0

1

0

1

0

1

3

2 1 0

5

4 3 2 1 0

Write Data Register (DR)

S device type

device

addresses

instruction DR and WCR

wiper position/data

(sent by master on SDA)

S

S S

T

A

R

T

identifier

opcode

addresses

A

C

K

A

C

K

A T HIGH-VOLTAGE

C O WRITE CYCLE

K P

W W W W W W

0 P P P P P P

A A A A

R

1

R

0

P

1

P

0

1

0

1

0

3

2 1 0

5

4 3 2 1 0

XFR Data Register (DR) to Wiper Counter Register (WCR)

S device type

device

addresses

instruction DR and WCR

S

A

C

K

S S

A T

C O

K P

T

A

R

T

identifier

opcode

addresses

A A A A

R

1

R

0

P

1

P

0

1

0

1

1 1 0 1

3

2 1 0

Write Wiper Counter Register (WCR) to Data Register (DR)

S device type

device

addresses

instruction DR and WCR

S

A

C

K

S S

T

A

R

T

identifier

opcode

addresses

A T HIGH-VOLTAGE

C O WRITE CYCLE

K P

A A A A

R

1

R

0

P

1

P

0

1

0

1

1 1 1 0

3

2

1

0

FN8191.2

September 19, 2005

10

X9408

Increment/Decrement Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

increment/decrement

(sent by master on SDA)

S

A

C

K

S

A

C

K

S

T

O

P

A A A A

P P

1 0

I/ I/

D D

I/ I/

D D

0

1

0

1

0

1

0

.

3

2

1

0

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

DR

addresses

S

A

C

K

S

A

C O

S

T

A A A A

R R

1 0

0

1

0

1

0

1

0 0

K

P

3

2

1

0

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

S device type

device

addresses

instruction

opcode

DR

addresses

S

A

C

K

S S

A T

C O

K P

T

A

R

T

identifier

HIGH-VOLTAGE

WRITE CYCLE

A A A A

R R

1 0

0

1

0

1

0

0 0

3

2

1

0

SYMBOL TABLE

Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

WAVEFORM

INPUTS

OUTPUTS

120

V

CC MAX

OL MIN

R

=

=1.8kΩ

Must be

steady

Will be

steady

MIN

I

100

80

t

R

=

MAX

May change

from Low to

High

Will change

from Low to

High

C

BUS

Max.

Resistance

60

40

20

0

May change

from High to

Low

Will change

from High to

Low

Min.

Resistance

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

0

20 40 60 80 100 120

N/A

Center Line

is High

Impedance

Bus Capacitance (pF)

FN8191.2

September 19, 2005

11

X9408

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias.................... -65°C to +135°C

Storage temperature ......................... -65°C to +150°C

Voltage on SDA, SCL or any address

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; the functional operation of

the device (at these or any other conditions above

those listed in the operational sections of this

specification) is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect device reliability.

input with respect to V ......................... -1V to +7V

SS

Voltage on V+ (referenced to V )........................10V

SS

Voltage on V- (referenced to V )........................-10V

SS

(V+) - (V-) ..............................................................12V

Any V /R , V /R , V /R ............................ V- to V+

H

L

W

Lead temperature (soldering, 10s) .................... 300°C

(10s)..............................................................±6mA

I

W

RECOMMENDED OPERATING CONDITIONS

Temp

Min.

0°C

Max.

+70°C

+85°C

Device

X9408

Supply Voltage (V ) Limits

CC

Commercial

Industrial

5V ± 10%

-40°C

X9408-2.7

2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol

R

Parameter

End to end resistance tolerance

Power rating

Min.

Typ.

Max.

+20

50

Unit

%

Test Condition

25°C, each pot

-20

TOTAL

mW

mA

Ω

I

Wiper current

-3

+3

W

R

Wiper resistance

150

40

250

100

+5.5

-4.5

-2.7

V+

I

= ± 1mA @ V+, V- = ±3V

= ± 1mA @ V+, V- = ±5V

W

Ω

V +

Voltage on V+ pin

Voltage on V- pin

X9408

+4.5

+2.7

-5.5

V-

V

X9408-2.7

X9408

V -

V

X9408-2.7

V

Voltage on any V /R , V /R or

TERM

H

L

V /R pin

W

Noise

-120

1.6

dBV

%

Ref: 1kHz

Resolution

See Note 4

(1)

(3)

Absolute linearity

-1

+1

MI

V(V /R -

)

wn wn (actual)

(4)

V(V /R

)

wn wn (expected)

(2)

(3)

MI

Relative linearity

-0.2

+0.2

V(V

[V(V

/R

) -

) + MI]

w(n+1) w(n+1)

/R

w(n) w(n)

Temperature coefficient of R

±300

ppm/°C See Note 4

TOTAL

Ratiometric Temperature Coefficient

Potentiometer Capacitances

20

10

C /C /C

10/10/25

0.1

pF

µA

See Macro model

V = V- to V+. Device is in

H

L

W

I

V /R , V /R , V /R Leakage

AL

H

L

W

IN

Stand-by mode.

Current

FN8191.2

12

September 19, 2005

X9408

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

I

V

supply current (nonvolatile

1

mA

f = 400kHz, SDA = Open,

SCL

CC1

CC

write)

Other Inputs = V

SS

I

V

supply current (move wiper,

100

µA

f

= 400kHz, SDA = Open,

CC2

CC

write, read)

SCL

Other Inputs = V

SS

I

V

current (standby)

1

µA

V

SCL = SDA = V , Addr. = V

CC SS

SB

CC

I

Input leakage current

Output leakage current

Input HIGH voltage

Input LOW voltage

Output LOW voltage

10

V

= V to V

SS CC

LI

IN

I

= V to V

SS CC

LO

OUT

V

x 0.7

V

+0.5

IH

CC

–0.5

CC

V

x 0.1

V

IL

CC

V

0.4

V

I

= 3mA

OL

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiom-

eter. It is a measure of the error in step size.

(3) MI = RTOT/63 or [V(V /R )–V(V /R )]/63, single pot

H

L

ENDURANCE AND DATA RETENTION

Parameter

Minimum endurance

Data retention

Min.

100,000

100

Unit

Data changes per bit per register

years

CAPACITANCE

Symbol

Test

Max.

Unit

pF

Test Condition

(4)

C

Input/output capacitance (SDA)

8

6

V

= 0V

I/O

(4)

C

Input capacitance (A0, A1, A2, A3, and SCL)

pF

V

IN

POWER-UP TIMING

Symbol

Parameter

Min.

Max.

1

Unit

ms

(5)

t

Power-up to initiation of read operation

Power-up to initiation of write operation

PUR

(5)

(6)

t

5

ms

PUW

t V

V

Power-up Ramp

0.2

50

V/msec

R CC

CC

Power-up Requirements (Power-up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First V-, then V

and V+, and then the potentiometer pins, V /R ,

CC

H

V /R , and V /R . Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The V

L

W

CC

ramp rate specification should be met, and any glitches or slope changes in the V

line should be held to <100mV if

CC

possible. If V

powers down, it should be held below 0.1V for more than 1 second before powering up again in order

CC

for proper wiper register recall. Also, V

should not reverse polarity by more than 0.5V. Recall of wiper position will

CC

not be complete until V , V+ and V- reach their final value.

CC

Notes: (4) This parameter is periodically sampled and not 100% tested

(5) t

and t

are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific

PUR

PUW CC

instruction can be issued. These parameters are periodically sampled and not 100% tested.

(6) This is not a tested or guaranteed parameter and should only be used as a guidance.

FN8191.2

13

September 19, 2005

X9408

A.C. TEST CONDITIONS

Circuit #3 SPICE Macro Model

Input pulse levels

V

x 0.1 to V

x 0.5

x 0.9

CC

R

TOTAL

Input rise and fall times

Input and output timing level

10ns

V /R

L L

H

C

V

L

CC

C

H

C

W

10pF

EQUIVALENT A.C. LOAD CIRCUIT

10pF

25pF

W

5V

V

/R

W

1533Ω

SDA Output

100pF

AC TIMING (over recommended operating condition)

Symbol Parameter

Min.

Max.

Unit

kHz

ns

f

Clock frequency

400

SCL

t

Clock cycle time

2500

600

1300

600

100

30

CYC

t

Clock high time

HIGH

t

Clock low time

LOW

t

Start setup time

SU:STA

HD:STA

SU:STO

t

Start hold time

t

Stop setup time

t

SDA data input setup time

SDA data input hold time

SCL and SDA rise time

SCL and SDA fall time

SU:DAT

t

HD:DAT

t

300

900

R

t

F

t

SCL low to SDA data output valid time

SDA Data output hold time

AA

DH

t

50

T

Noise suppression time constant at SCL and SDA inputs

Bus free time (prior to any transmission)

WP, A0, A1, A2 and A3 setup time

I

t

1300

0

BUF

t

SU:WPA

HD:WPA

t

WP, A0, A1, A2 and A3 hold time

0

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol

Parameter

Typ.

Max.

Unit

t

High-voltage write cycle time (store instructions)

5

10

ms

WR

FN8191.2

14

September 19, 2005

X9408

XDCP TIMING

Symbol

Parameter

Min. Max. Unit

t

Wiper response time after the third (last) power supply is stable

10

µs

WRPO

t

Wiper response time after instruction issued (all load instructions)

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

WRL

t

WRID

Notes: (9) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling

edge of SCL.

TIMING DIAGRAMS

START and STOP Timing

g

(START)

(STOP)

t

F

R

SCL

SDA

t

SU:STO

SU:STA

HD:STA

t

F

R

Input Timing

t

CYC

HIGH

SCL

SDA

t

LOW

t

BUF

SU:DAT

HD:DAT

Output Timing

SCL

SDA

t

DH

AA

FN8191.2

15

September 19, 2005

X9408

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

+V

R

V

R

I

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Application Circuits

Noninverting Amplifier

Voltage Regulator

V

+

–

S

V

V (REG)

O

317

O

IN

R

1

R

2

I

adj

R

1

2

V

= (1+R /R )V

V

(REG) = 1.25V (1+R /R )+I

R

adj 2

O

2

1

S

O

2

1

Offset Voltage Adjustment

Comparator with Hysteresis

R

2

1

V

–

+

S

V

S

O

100kΩ

–

+

V

O

TL072

R

1

2

10kΩ

+12V

V

= {R /(R +R )} V (max)

1 1 2 O

UL

LL

10kΩ

-12V

= {R /(R +R )} V (min)

1

2

O

FN8191.2

16

September 19, 2005

X9408

Application Circuits (continued)

Attenuator

Filter

C

V

+

–

S

R

V

R

1

2

O

–

R

V

O

V

+

S

R

3

R

2

R

4

All R = 10kΩ

S

R

1

G

= 1 + R /R

2 1

V

= G V

S

O

fc = 1/(2πRC)

-1/2 ≤ G ≤ +1/2

Inverting Amplifier

Equivalent L-R Circuit

R

2

1

V

S

R

2

C

1

–

+

V

+

–

S

V

O

R

1

Z

IN

V

= G V

S

O

G = - R /R

2

1

3

Z

= R + s R (R + R ) C = R + s Leq

2 2 1 3 1 2

IN

(R + R ) >> R

1

3

2

Function Generator

C

R

1

2

–

+

–

+

R

}

A

B

frequency ∝ R , R , C

1

2

amplitude ∝ R , R

A

B

FN8191.2

September 19, 2005

17

X9408

XDCP Timing (for All Load Instructions)

(STOP)

SCL

SDA

VWx

LSB

t

WRL

XDCP Timing (for Increment/Decrement Instruction)

SCL

Wiper Register Address

Inc/Dec

SDA

VWx

t

WRID

Write Protect and Device Address Pins Timing

(START)

(STOP)

SCL

...

(Any Instruction)

...

SDA

...

t

SU:WPA

HD:WPA

WP

A0, A1

A2, A3

FN8191.2

18

September 19, 2005

X9408

PACKAGING INFORMATION

24-Lead Plastic Dual In-Line Package Type P

1.265 (32.13)

1.230 (31.24)

0.557 (14.15)

0.530 (13.46)

Pin 1 Index

Pin 1

0.080 (2.03)

0.065 (1.65)

1.100 (27.94)

Ref.

0.162 (4.11)

0.140 (3.56)

Seating

Plane

0.030 (0.76)

0.015 (0.38)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.065 (1.65)

0.040 (1.02)

0.022 (0.56)

0.014 (0.36)

0.625 (15.87)

0.600 (15.24)

0°

Typ. 0.010 (0.25)

15°

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

FN8191.2

19

September 19, 2005

X9408

PACKAGING INFORMATION

24-Lead Plastic Small Outline Gull Wing Package Type S

0.393 (10.00)

0.290 (7.37)

0.299 (7.60)

0.420 (10.65)

Pin 1 Index

Pin 1

0.014 (0.35)

0.020 (0.50)

0.598 (15.20)

0.610 (15.49)

(4X) 7°

0.092 (2.35)

0.105 (2.65)

0.003 (0.10)

0.012 (0.30)

0.050 (1.27)

0.050"Typical

0.010 (0.25)

0.020 (0.50)

X 45°

0.050"

Typical

0° - 8°

0.009 (0.22)

0.013 (0.33)

0.420"

0.015 (0.40)

0.050 (1.27)

0.030" Typical

24 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

FN8191.2

September 19, 2005

20

X9408

PACKAGING INFORMATION

24-Lead Plastic, TSSOP Package Type V

.026 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.303 (7.70)

.311 (7.90)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.06)

.005 (.15)

.010 (.25)

Gage Plane

(7.72)

(4.16)

0° - 8°

Seating Plane

.020 (.50)

.030 (.75)

(1.78)

(0.42)

Detail A (20X)

(0.65)

ALL MEASUREMENTS ARE TYPICAL

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8191.2

21

September 19, 2005


型号：	X9408YV24Z
厂家：	Intersil
描述：	Low Noise/Low Power/2-Wire Bus 低噪音/低功耗/ 2 - Wire总线转换器电阻器光电二极管
文件：	总21页 (文件大小：372K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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