X9119TV14I [RENESAS]
100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO14, 4.40 MM, PLASTIC, TSSOP-14;
| 型号： | X9119TV14I |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO14, 4.40 MM, PLASTIC, TSSOP-14 光电二极管 转换器 电阻器 |
| 文件： | 总18页 (文件大小：757K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X9119
FN8162
Rev 5.00
July 5, 2016
1024 Tap, Low Power, 2-Wire Interface, Digitally Controlled (XDCP™)
Potentiometer
The X9119 integrates a single digitally controlled
Features
potentiometer (XDCP™) on a monolithic CMOS integrated
circuit.
• 1024 resistor taps – 10-bit resolution
• 2-Wire serial interface for write, read, and
transfer operations of the potentiometer
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four nonvolatile data registers that can be
directly written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of the
default data register (DR0) to the WCR.
• Wiper resistance, 40Ω typical at V = 5V
CC
• Four nonvolatile data registers
• Nonvolatile storage of multiple wiper positions
• Power-on recall, loads saved wiper position on power-up.
• Standby current <3µA maximum
• V : 2.7V to 5.5V operation
CC
• 100kΩ end-to-end resistance
• 100 yr. data retention
The XDCP™ can be used as a 3-terminal potentiometer or as a
2-terminal variable resistor in a wide variety of applications
including control, parameter adjustments and signal
processing.
• Endurance: 100,000 data changes per bit per register
• 14 Ld TSSOP
• Low power CMOS
• Single supply version of the X9118
• Pb-free available (RoHS compliant)
V
R
H
CC
WRITE
READ
TRANSFER
ADDRESS
DATA
STATUS
POWER-ON RECALL
100kΩ
1024-TAPS
POT
BUS
INTERFACE
AND
WIPER COUNTER
REGISTER (WCR)
2-WIRE
BUS
INTERFACE
WIPER
DATA REGISTERS
CONTROL
(DR0-DR3)
CONTROL
R
R
V
NC
NC
W
L
SS
FIGURE 1. FUNCTIONAL DIAGRAM
FN8162 Rev 5.00
July 5, 2016
Page 1 of 18
X9119
System Level
• Adjust the contrast in LCD displays
Applications
Circuit Level
• Control the power level of LED transmitters in communication
systems
• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for comparators
and detectors
• Set and regulate the DC biasing point in an RF power amplifier
in wireless systems
• Control the volume in audio circuits
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter
circuits
• Trim offset and gain errors in artificial intelligent
systems
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
Ordering Information
POTENTIOMETER
ORGANIZATION
TEMP
RANGE
(°C)
PART NUMBER
(Notes 2, 3)
V
LIMITS
(V)
PACKAGE
RoHS COMPLIANT
CC
PART MARKING
X9119 TVZI
X9119 TVZ
(kΩ)
PKG. DWG.#
M14.173
M14.173
M14.173
M14.173
X9119TV14IZ
5 ±10%
100
-40 to +85 14 Ld TSSOP (4.4mm)
0 to +70 14 Ld TSSOP (4.4mm)
0 to +70 14 Ld TSSOP (4.4mm)
-40 to +85 14 Ld TSSOP (4.4mm)
X9119TV14Z
X9119TV14Z-2.7
X9119TV14IZ-2.7 (Note 1)
NOTES:
X9119 TVZF
X9119 TVZG
2.7 to 5.5
1. Add “T1” suffix for 2.5k unit tape and reel option.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for X9119. For more information on MSL, please see tech brief TB363.
V
CC
POWER ON
RECALL
DR0 DR1
R
H
SCL
SDA
A2
WIPER
COUNTER
REGISTER
(WCR)
INTERFACE
AND
CONTROL
CIRCUITRY
100kΩ
1024-TAPS
DATA
R
DR2 DR3
L
A1
CONTROL
A0
R
W
WP
V
SS
FIGURE 2. DETAILED FUNCTIONAL DIAGRAM
FN8162 Rev 5.00
July 5, 2016
Page 2 of 18
X9119
DEVICE ADDRESS (A –A )
2
0
Pin Configuration
The Address inputs are used to set the least significant 3 bits of
the 8-bit slave address. A match in the slave address serial data
stream must be made with the Address input in order to initiate
communication with the X9119. A maximum of 8 devices may
occupy the 2-wire serial bus.
X9119
(14 LD TSSOP)
TOP VIEW
NC
14
1
2
3
4
5
6
7
V
CC
R
R
R
A0
13
12
11
10
L
HARDWARE WRITE PROTECT INPUT (WP)
NC
H
The WP pin when LOW, prevents nonvolatile writes to the Data
Registers.
A2
SCL
SDA
W
NC
A1
9
8
V
Potentiometer Pins
SS
WP
R , R
H
L
The R and R pins are equivalent to the terminal connections on
H
L
a mechanical potentiometer.
Pin Assignments
R
W
PIN
NUMBER
PIN NAME
NC
FUNCTION
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
1, 3, 10
No connect
2
4
A0
Device address for 2-wire bus
Device address for 2-wire bus
Serial clock for 2-wire bus
Bias Supply Pins
A2
SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY
CC
5
SCL
GROUND (V
)
SS
The V pin is the system supply voltage. The V pin is the
system ground.
6
SDA
Serial data input/output for 2-wire bus
System ground
CC
SS
7
V
SS
Other Pins
8
WP
A1
Hardware write protect
9
Device address for 2-wire bus
Wiper terminal of the potentiometer
High terminal of the potentiometer
Low terminal of the potentiometer
System supply voltage
NO CONNECT
11
12
13
14
R
W
No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.
R
H
R
L
Principals of Operation
V
CC
The X9119 is an integrated microcircuit incorporating a resistor
array and its associated registers and counters and the serial
interface logic providing direct communication between the host
and the digitally controlled potentiometer. This section provides
detail description of the following:
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a
2-wire slave device and is used to transfer data into and out of
the device. It receives device address, opcode, wiper register
address and data sent from a 2-wire master at the rising edge of
the serial clock SCL, and it shifts out data after each falling edge
of the serial clock SCL.
• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description
Resistor Array Description
It is an open-drain output and may be wire-ORed with any
number of open-drain or open collector outputs. An open-drain
output requires the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical values on the
bus pull-up resistors graph.
The X9119 is comprised of a resistor array. The array contains, in
effect, 1023 discrete resistive segments that are connected in
series (Figure 3 on page 4). The physical ends of each array are
equivalent to the fixed terminals of a mechanical potentiometer
(R and R inputs).
H
L
SERIAL CLOCK (SCL)
At both ends of each array and between each resistor segment is
This input is used by a 2-wire master to supply a 2-wire serial
clock to the X9119.
a CMOS switch connected to the wiper (R ) output. Within each
W
individual array only one switch may be turned on at a time.
These switches are controlled by the Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.
FN8162 Rev 5.00
July 5, 2016
Page 3 of 18
X9119
The WCR may be written directly. The data registers and the WCR
can be read and written by the host system.
ACKNOWLEDGE
Acknowledge is a software convention used to provide a positive
handshake between the master and slave devices on the bus to
indicate the successful receipt of data. The transmitting device,
either the master or the slave, will release the SDA bus after
transmitting eight bits. The master generates a ninth clock cycle
and during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits of data.
Serial Interface Description
SERIAL INTERFACE
The X9119 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9119 will be considered a slave
device in all applications.
The X9119 will respond with an acknowledge after recognition of
a start condition and its slave address and once again after
successful receipt of the command byte. If the command is
followed by a data byte the X9119 will respond with a final
acknowledge (see Figure 4).
ACKNOWLEDGE POLLING
CLOCK AND DATA CONVENTIONS
The disabling of the inputs, during the internal nonvolatile write
operation, can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9119
initiates the internal write cycle. ACK polling, Flow 1 (see
Figure 5 on page 5), can be initiated immediately. This involves
issuing the start condition followed by the device slave address. If
the X9119 is still busy with the write operation, no ACK will be
returned. If the X9119 has completed the write operation, an
ACK will be returned and the master can then proceed with the
next operation.
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (Figure 6 on page 8).
START CONDITION
All commands to the X9119 are preceded by the start condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
X9119 continuously monitors the SDA and SCL lines for the start
condition and will not respond to any command until this
condition is met (Figure 6).
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH (see
Figure 6).
SERIAL DATA PATH
R
SERIAL
BUS
INPUT
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
(DR0)
REGISTER 1
(DR1)
10
10
PARALLEL
BUS
INPUT
E
R
REGISTER 2
(DR2)
REGISTER 3
(DR3)
WIPER
D
E
C
O
D
E
R
COUNTER
REGISTER
(WCR)
IF WCR = 000[HEX] THEN R = R
W
L
IF WCR = 3FF[HEX] THEN R = R
W
H
R
R
L
W
FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM SERIAL INTERFACE DESCRIPTION
FN8162 Rev 5.00
July 5, 2016
Page 4 of 18
X9119
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ISSUE STOP
ADDRESS
ACK
NO
RETURNED?
YES
NO
FURTHER
OPERATION?
YES
ISSUE
ISSUE STOP
PROCEED
INSTRUCTION
PROCEED
FIGURE 5. FLOW 1. ACK POLLING SEQUENCE
FN8162 Rev 5.00
July 5, 2016
Page 5 of 18
X9119
Only the device which slave address matches the incoming
device address sent by the master executes the instruction. The
A2–A0 inputs can be actively driven by CMOS input signals or
Instruction and Register
Description
Device Addressing: Identification Byte
(ID and A)
Following a start condition, the master must output the address
of the slave it is accessing. The most significant four bits of the
slave address are the device type identifier. The ID[3:0] bits is the
device ID for the X9119; this is fixed as 0101[B] (refer to Table 1).
tied to V or V . The R/W bit is the LSB and is be used to
CC SS
program the device for read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
The next byte sent to the X9119 contains the instruction and
register pointer information. The three most significant bits are
used provide the instruction opcode (IOP[2:0]). The RB and RA
bits point to one of the four registers. The format is shown in
Table 2.
The A2–A0 bits in the ID byte is the internal slave address. The
physical device address is defined by the state of the A2–A0
input pins. The slave address is externally specified by the user.
The X9119 compares the serial data stream with the address
input state; a successful compare of both address bits is required
for the X9119 to successfully continue the command sequence.
Table 3 provides a complete summary of the instruction set
opcodes.
TABLE 1. IDENTIFICATION BYTE FORMAT
INTERNAL SLAVE
ADDRESS
READ OR
WRITE BIT
DEVICE TYPE
IDENTIFIES
ID3
0
ID2
1
ID1
0
ID0
1
A2
A1
A0
R/W
(MSB)
(LSB)
TABLE 2. INSTRUCTION BYTE FORMAT
INSTRUCTION
OPCODE
REGISTER
SELECTION
I2
I1
I0
0
RB
RA
0
0
(MSB)
(LSB)
REGISTER SELECTED
RB
0
RA
0
DR0
DR1
DR2
DR3
0
1
1
0
1
1
TABLE 3. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
R/W
I
I
I
0
0
0
0
0
RB
0
RA
0
0
0
0
0
0
0
0
0
OPERATION
2
1
Read Wiper Counter Register
Write Wiper Counter Register
Read Data Register
1
0
1
1
1
1
0
0
0
0
1
1
Read the contents of the wiper counter register.
Write new value to the wiper counter register.
0
0
1/0 1/0
Read the contents of the data register pointed to
RB-RA.
Write Data Register
0
1
1
1
1
1
0
0
0
0
1/0 1/0
1/0 1/0
0
0
0
0
Write new value to the data register pointed to RB-RA.
XFR Data Register to Wiper
Counter Register
Transfer the contents of the data register pointed to by
RB-RA to the wiper counter register.
XFR Wiper Counter Register to
Data Register
0
1
1
1
0
1/0 1/0
0
0
Transfer the contents of the wiper counter register to
the data register pointed to by RB-RA.
NOTE: 1/0 = data is one or zero.
FN8162 Rev 5.00
July 5, 2016
Page 6 of 18
X9119
Four of the six instructions are four bytes in length. These
instructions are:
Instruction and Register
Description
• Read Wiper Counter Register – Reads the current wiper
position of the selected potentiometer.
Device Addressing
• Write Wiper Counter Register – Changes current wiper position
of the selected potentiometer.
WIPER COUNTER REGISTER (WCR)
The X9119 contains a wiper counter register (refer to Table 4) for
the XDCP potentiometer. The WCR is equivalent to a serial-in,
parallel-out register/counter with its outputs decoded to select
one of 1024 switches along its resistor array. The contents of the
WCR can be altered in one of three ways:
• Read Data Register – Reads the contents of the selected Data
Register.
• Write Data Register – Writes a new value to the selected Data
Register.
The basic sequence of the four byte instructions is illustrated in
Figure 6 on page 8. These 4-byte instructions exchange data
between the WCR and one of the data registers. A transfer from
a data register to a WCR is essentially a write to a static RAM,
with the static RAM controlling the wiper position. The response
1. It may be written directly by the host via the write wiper
counter register instruction (serial load).
2. It may be written indirectly by transferring the contents of one
of four associated data registers via the XFR data register.
3. It is loaded with the contents of its data register zero (R0)
upon power-up.
of the wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a data register is a
write-to-nonvolatile memory and takes a minimum of t to
The wiper counter register is a volatile register; that is, its
contents are lost when the X9119 is powered-down. Although the
register is automatically loaded with the value in DR0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.
WR
complete. The transfer can occur between one of the four
potentiometers and one of its associated registers.
Two instructions (Figure 7 on page 8) require a 2-byte sequence
to complete. These instructions transfer data between the host
and the X9119; either between the host and one of the data
registers or directly between the host and the wiper counter
register. These instructions are:
DATA REGISTERS (DR0 TO DR3)
The potentiometer has four 10-bit nonvolatile data registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four data registers and the
wiper counter register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
• XFR Data Register to Wiper Counter Register – This transfers
the contents of one specified data register to the wiper counter
register.
• XFR Wiper Counter Register to Data Register – This transfers
the contents of the wiper counter register to the specified data
register.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference
data.
See “Instruction Format” on page 8 for more details.
POWER-UP AND POWER-DOWN REQUIREMENTS
There are no restrictions on the power-up condition of V and
CC
the voltages applied to the potentiometer pins provided that the
Bit 9 to Bit 0 are used to store one of the 1024 wiper position (0
~1023).
V
is always more positive than or equal to the voltages at R ,
CC
H
R , and R , i.e., V ≥ R , R , R . There are no restrictions on
L
W
CC
H
L
W
the power-down condition. However, the datasheet parameters
for the DCP do not apply until 1ms after V reaches its final
CC
value.
TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9
V
WCR8
V
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(MSB)
(LSB)
TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE, NV)
BIT 9
NV
BIT 8
NV
BIT 7
NV
BIT 6
NV
BIT 5
NV
BIT 4
NV
BIT 3
NV
BIT 2
NV
BIT 1
NV
BIT 0
NV
MSB
LSB
FN8162 Rev 5.00
July 5, 2016
Page 7 of 18
X9119
SCL
SDA
0
1
0
1
0
0
0
0
0
S
T
A
R
T
ID3 ID2 ID1 ID0
DEVICE ID
I2
I0
A2 A1 A0 R/W
A
C
K
RB RA
A
C
K
I1
S
T
O
P
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
FIGURE 6. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
0
1
0
1
0
0
X
X
0
0
X
X
X
X
X X
S
A0
ID3 ID2ID1ID0 A2 A1
R/W
0 RB RA 0
A
C
K
W W
A
C
K
W W W W W W W W A
I0
I2 I1
S
T
A
C
K
C
R
9
C
R
8
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
T
O
P
C
K
A
R
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
DEVICE ID
T
WIPER OR DATA
POSITION
FIGURE 7. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
Instruction Format
READ WIPER COUNTER REGISTER (WCR)
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
WIPER POSITION
(SENT BY SLAVE ON SDA)
WIPER POSITION
(SENT BY SLAVE ON SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
W W
M
A
C
W W W W W W W W
M
A
C
S
T
O
P
0
1
0
1
A2 A1 A0
1
0
0
0
0
0
0
0
X
X
X
X
X
X
C
R
9
C
R
8
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
K
K
WRITE WIPER COUNTER REGISTER (WCR)
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
WIPER POSITION
(SENT BY MASTER ON SDA)
WIPER POSITION
(SENT BY MASTER ON SDA)
S
T
A
R
T
S
A
C
K
S
W
C
W
C
S
W
C
W
C
W
C
W
C
W
C
W
C
W
C
W
C
S
A
C
K
S
T
O
P
0
1
0
1
A2 A1 A0
1
0
1
0
0
0
0
0
A
C
K
X
X
X
X
X
X
A
C
K
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
READ DATA REGISTER (DR)
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
WIPER POSITION
(SENT BY SLAVE ON SDA)
WIPER POSITION OR DATA
(SENT BY SLAVE ON SDA)
S
T
A
R
T
S
S
A
C
K
M
M
S
T
O
P
W
W
W W W W W W W W
CR CR CR CR CR CR CR CR
A
C
K
A
C
K
A
C
K
0
1
0
1
A2 A1 A0
1
0
1
0
RB RA
0
0
X
X
X
X
X
X
CR CR
9
8
7
6
5
4
3
2
1
0
WRITE DATA REGISTER (DR)
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
WIPER POSITION OR DATA
(SENT BY MASTER ON SDA)
WIPER POSITION OR DATA
(SENT BY MASTER ON SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
W
C
R
9
W
C
R
8
S
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
S
S
0
1
0
1
A2 A1 A0
1
1
0
0
RB RA
0
0
X
X
X
X
X
X
A
C
K
A
C
K
T
O
P
FN8162 Rev 5.00
July 5, 2016
Page 8 of 18
X9119
TRANSFER WIPER COUNTER REGISTER (WCR) TO DATA REGISTER (DR)
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
S
T
A
R
T
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
A2
1
A0
1
1
1
0
RB RA
0
0
HIGH-VOLTAGE
WRITE CYCLE
TRANSFER DATA REGISTER (DR) TO WIPER COUNTER REGISTER (WCR)
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
S
T
A
R
T
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
A2 A1 A0
1
1
0
0
RB RA
0
0
NOTES:
4. A2 ~ A0”: stand for the device addresses sent by the master.
5. WCRx refers to wiper position data in the wiper counter register.
FN8162 Rev 5.00
July 5, 2016
Page 9 of 18
X9119
Absolute Maximum Ratings
Thermal Information
Voltage on SCL, SDA, or any address input
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
with respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +7V
SS
V = | (VH–VL) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
Operating Conditions
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40° to +85°C
Supply Voltage (V ) Limits (Note 9)
CC
X9119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9119-2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Analog Specifications (Over recommended operation conditions unless otherwise stated.)
MIN
MAX
PARAMETER
End-to-End Resistance
SYMBOL
R
TEST CONDITIONS
(Note 13)
TYP
100
(Note 13)
UNIT
kΩ
%
TOTAL
End-to-End Resistance Tolerance
Power Rating
±20
50
+25°C, each pot
mW
mA
Ω
Wiper Current
I
±3
W
Wiper Resistance
R
Wiper Current = ± 50µA,
= 5V
40
110
W
V
CC
Wiper Current = ± 50µA,
150
300
5
Ω
V
V
= 3V
= 0V
CC
Voltage on any R or R Pin
V
V
SS
V
dBV
%
H
L
TERM
SS
Noise
Ref: 1V
-120
0.1
Resolution
Absolute Linearity (Note 6)
Relative Linearity (Note 7)
Temperature Coefficient of R
R
– R
, where n = 8 to
(Note 9)
w(n)(expected)
±1.5
±2.0
±0.5
±1.0
MI
(Note 8)
w(n)(actual)
1006
w(n)(expected)
R
– R
±1.5
MI
(Note 8)
w(n)(actual)
R
1006
– [R
+ MI], where m = 8 to
+ MI] (Note 9)
w(m)
MI
(Note 8)
w(m + 1)
w(m)
R
– [R
±0.5
MI
(Note 8)
w(m + 1)
±300
20
ppm/°C
ppm/°C
pF
TOTAL
Ratiometric Temperature Coefficient
Potentiometer Capacitances
NOTES:
C /C /C
W
See Macro model
10/10/25
H
L
6. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage as determined by wiper position when used as a potentiometer.
7. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
8. MI = R /1023 or (R – R )/1023, single potentiometer
TOT
H
L
9. n = 0, 1, 2, …,1023; m = 0, 1, 2, …, 1022.
10. ESD Rating on R , R , R pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.
H
L
W
FN8162 Rev 5.00
July 5, 2016
Page 10 of 18
X9119
Operating Specifications (Over the recommended operating conditions unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
3
UNIT
mA
V
V
Supply Current (Active)
I
f
= 400kHz; V = +5.5V;
SCL
CC
CC1
CC
SDA = Open; (for 2-wire, active, read and volatile write states only)
Supply Current
I
f
= 400kHz; V = +5.5V;
CC
5
3
mA
µA
CC
CC2
SCL
(Nonvolatile Write)
SDA = Open; (for 2-wire, active, non-volatile write state only)
V
Current (Standby)
I
I
V
= +5.5V; V = V or V ; SDA = V
;
CC
SB
CC
(for 2-wire, standby state only)
IN SS CC CC
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
I
V
V
= V to V
SS CC
10
10
µA
µA
V
LI
IN
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 1
IH
CC
CC
V
-1
V
x 0.3
V
IL
CC
Output LOW Voltage
Output HIGH Voltage
V
I
= 3mA
OL
0.4
V
OL
V
OH
Endurance and Data Retention
PARAMETER
Minimum Endurance
Data Retention
MIN
UNITS
100,000
100
Data changes per bit per register
years
Capacitance
TEST
SYMBOL
TEST CONDITIONS
= 0V
MAX
8
UNIT
Input/Output Capacitance (SI)
Input Capacitance (SCL, WP, A1 and A0)
C
C
(Note 11)
V
pF
pF
IN/OUT
OUT
(Note 11)
V
= 0V
6
IN
IN
Power-Up Timing
PARAMETER
SYMBOL
MIN
0.2
MAX
50
1
UNIT
V
Power-Up Rate
t V (Note 11)
CC
V/ms
ms
CC
r
Power-Up to Initiation Of Read Operation
Power-Up to Initiation Of Write Operation
NOTES:
t
t
(Note 12)
(Note 12)
PUR
50
ms
PUW
11. Limits should be considered typical and are not production tested.
12. t and t are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued. These
PUR
PUW
parameters are not 100% tested.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
AC Test Conditions
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
10ns
x 0.5
Input Rise and Fall Times
Input and Output Timing Level
V
CC
FN8162 Rev 5.00
July 5, 2016
Page 11 of 18
X9119
Equivalent A.C. Load Circuit
5V
3V
SPICE MACROMODEL
1533Ω
867Ω
R
TOTAL
R
L
R
H
SDA OUTPUT
SDA OUTPUT
C
C
C
L
W
L
10pF
10pF
100pF
25pF
100pF
R
W
AC Timing High-Voltage Write Cycle Timing
PARAMETER
SYMBOL
MIN
MAX
UNIT
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Frequency
f
400
SCL
CYC
Clock Cycle Time
t
2500
600
1300
600
600
600
100
0
Clock High Time
t
HIGH
Clock Low Time
t
LOW
Start Set-Up Time
t
SU:STA
HD:STA
Start Hold Time
t
Stop Set-Up Time
t
t
SU:STO
SU:DAT
HD:DAT
SDA Data Input Set-Up Time
SDA Data Input Hold Time
SCL and SDA Rise Time
t
t
300
300
R
SCL and SDA Fall Time
t
F
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Noise Suppression Time Constant at SCL and SDA Inputs
Bus Free Time (Prior to Any Transmission)
A0, A1, A2 Set-Up Time
t
250
0
AA
DH
t
T
50
1300
0
I
t
BUF
t
SU:WPA
A0, A1, A2 Hold Time
t
0
HD:WPA
High-Voltage Write Cycle Timing
PARAMETER
SYMBOL
TYP
5
MAX
10
UNIT
ms
High-Voltage Write Cycle Time (Store Instructions)
t
WR
XDCP Timing
PARAMETER
SYMBOL
MIN
5
MAX
10
UNIT
µs
Wiper Response Time After the Third (Last) Power Supply is Stable
Wiper Response Time After Instruction Issued (All Load Instructions)
t
WRPO
t
5
10
µs
WRL
FN8162 Rev 5.00
July 5, 2016
Page 12 of 18
X9119
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW to
HIGH
Will change
from LOW to
HIGH
May change
from HIGH to
LOW
Will change
from HIGH to
LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is HIGH
Impedance
Timing Diagrams
( START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
SDA
FIGURE 8. START AND STOP TIMING
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
FIGURE 9. INPUT TIMING
SCL
SDA
t
t
DH
AA
FIGURE 10. OUTPUT TIMING
FN8162 Rev 5.00
July 5, 2016
Page 13 of 18
X9119
Timing Diagrams
(STOP)
SCL
SDA
LSB
t
WRL
R
W
FIGURE 11. XDCP TIMING (FOR ALL LOAD INSTRUCTIONS)
(START)
(STOP)
SCL
SDA
...
(ANY INSTRUCTION)
...
...
T
T
SU:WPA
HD:WPA
WP
A0, A1, A2
FIGURE 12. WRITE PROTECT AND DEVICE ADDRESS PINS TIMING
FN8162 Rev 5.00
July 5, 2016
Page 14 of 18
X9119
Applications information
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
FIGURE 13. THREE-TERMINAL POTENTIOMETER; VARIABLE VOLTAGE
DIVIDER
FIGURE 14. TWO-TERMINAL VARIABLE RESISTOR; VARIABLE
CURRENT
Application Circuits
V
+
–
S
V
V (REG)
O
317
IN
V
O
R
1
R
I
2
ADJ
R
R
2
1
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
V
= (1+R /R )V
2 1 S
O
FIGURE 15. NONINVERTING AMPLIFIER
FIGURE 16. VOLTAGE REGULATOR
R
R
2
1
V
V
–
S
S
V
O
100kΩ
+
–
+
V
O
TL072
R
R
2
10kΩ
10kΩ
1
10kΩ
V
= {R /(R +R )} V (max)
1 1 2 O
RL = {R /(R +R )} V (min)
UL
L
1
1
2
O
+12V
-12V
FIGURE 18. COMPARATOR WITH HYSTERESIS
FIGURE 17. OFFSET VOLTAGE ADJUSTMENT
FN8162 Rev 5.00
July 5, 2016
Page 15 of 18
X9119
Application Circuits(Continued)
C
V
+
–
S
V
O
R
R
R
2
1
3
–
+
R
V
O
V
S
R
2
R
4
R
= R = R = R = 10kΩ
2 3 4
R
1
1
G
= 1 + R /R
2 1
O
V
= G V
S
O
fc = 1/(2pRC)
-1/2 £ G £ +1/2
FIGURE 19. ATTENUATOR
FIGURE 20. FILTER
R
2
C
1
V
+
–
S
R
R
2
1
V
S
R
R
1
3
Z
IN
–
+
V
O
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
V
= G V
S
IN
O
(R + R ) >> R
G = - R /R
1
3
2
2
1
FIGURE 21. INVERTING AMPLIFIER
FIGURE 22. EQUIVALENT L-R CIRCUIT
C
R
R
1
2
–
+
–
+
R
R
}
A
B
}
FREQUENCY µ R , R , C
1
2
AMPLITUDE µ R , R
A
B
FIGURE 23. FUNCTION GENERATOR
FN8162 Rev 5.00
July 5, 2016
Page 16 of 18
X9119
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
FN8162.5
CHANGE
July 5, 2016
Updated entire datasheet applying Intersil’s new standards.
Updated title.
Updated Ordering Information table by removing obsolete parts, updating Note 1 and adding Note 3.
Removed Lead temperature (soldering, 10s) from the Thermal Information section on page 10.
Updated Absolute Linearity maximum specification from “±1” to “±1.5”.
Added Revision History and About Intersil sections.
Updated POD to the latest revision changes are as follows:
Updated drawing to remove table and added land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2005-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8162 Rev 5.00
July 5, 2016
Page 17 of 18
X9119
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
FN8162 Rev 5.00
July 5, 2016
Page 18 of 18
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