X9119TV14Z-2.7 [INTERSIL]
Single Digitally-Controlled (XDCP?) Potentiometer; 单数字控制（ XDCP⑩ ）电位计
| 型号： | X9119TV14Z-2.7 |
| 厂家： | 
Intersil |
| 描述： | Single Digitally-Controlled (XDCP?) Potentiometer |
| 文件： | 总17页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9119
®
Single Supply/Low Power/1024-Tap/2-Wire Bus
Data Sheet
July 9, 2008
FN8162.4
Single Digitally-Controlled (XDCP™)
Potentiometer
Features
• 1024 Resistor Taps – 10-Bit Resolution
The X9119 integrates a single digitally controlled
potentiometer (XDCP™) on a monolithic CMOS integrated
circuit.
• 2-Wire Serial Interface for Write, Read, and
Transfer Operations of the Potentiometer
• Wiper Resistance, 40Ω Typical @ V
= 5V
CC
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the contents of
the default data register (DR0) to the WCR.
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 3µA Max
• V : 2.7V to 5.5V Operation
CC
• 100kΩ End-to-End Resistance
• 100 yr. Data Retention
The XDCP™ can be used as a three-terminal potentiometer
or as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• Endurance: 100,000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Low Power CMOS
• Single Supply Version of the X9118
• Pb-Free available (RoHS compliant)
Functional Diagram
V
R
H
CC
WRITE
READ
TRANSFER
ADDRESS
DATA
STATUS
POWER-ON RECALL
100kΩ
1024-TAPS
BUS
INTERFACE
AND
WIPER COUNTER
REGISTER (WCR)
2-WIRE
POT
BUS
INTERFACE
WIPER
DATA REGISTERS
(DR0-DR3)
CONTROL
CONTROL
R
R
V
NC
NC
W
L
SS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners
X9119
Ordering Information
POTENTIOMETER
ORGANIZATION
(kΩ)
TEMP
RANGE
(°C)
PART
MARKING
V
LIMITS
(V)
PKG. DWG.#
CC
PART NUMBER
X9119TV14I
PACKAGE
X9119 TVI
5 ±10%
100
-40 to +85 14 Ld TSSOP (4.4mm)
M14.173
X9119TV14IZ (Note)
X9119TV14
X9119 TVZI
X9119 TV
-40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
0 to +70 14 Ld TSSOP (4.4mm) M14.173
0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
0 to +70 14 Ld TSSOP (4.4mm) M14.173
0 to +70 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
-40 to +85 14 Ld TSSOP (4.4mm) M14.173
-40 to +85 14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9119TV14Z (Note)
X9119TV14-2.7*
X9119 TVZ
X9119 TVF
X9119 TVZF
X9119 TVG
X9119 TVZG
2.7 to 5.5
X9119TV14Z-2.7* (Note)
X9119TV14I-2.7
X9119TV14IZ-2.7* (Note)
*Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Detailed Functional Diagram
V
CC
POWER ON
RECALL
DR0 DR1
R
H
SCL
SDA
A2
WIPER
COUNTER
REGISTER
(WCR)
INTERFACE
AND
CONTROL
100KΩ
1024-TAPS
DATA
R
DR2 DR3
L
CIRCUITRY
A1
CONTROL
A0
R
W
WP
V
SS
FN8162.4
July 9, 2008
2
X9119
Applications
Pin Assignments
Circuit Level
PIN
• Vary the gain of a voltage amplifier
NUMBER PIN NAME
FUNCTION
• Provide programmable DC reference voltages for
comparators and detectors
1, 3, 10
NC
A0
No Connect
2
4
Device Address for 2-wire bus
Device Address for 2-wire bus
Serial Clock for 2-wire bus
• Control the volume in audio circuits
A2
• Trim out the offset voltage error in a voltage amplifier
circuit
5
SCL
SDA
6
Serial Data Input/Output for 2-wire bus
System Ground
• Set the output voltage of a voltage regulator
7
V
SS
• Trim the resistance in Wheatstone bridge circuits
8
WP
A1
Hardware Write Protect
• Control the gain, characteristic frequency and Q-factor in
filter circuits
9
Device Address for 2-wire bus
Wiper terminal of the Potentiometer
High terminal of the Potentiometer
Low terminal of the Potentiometer
System Supply Voltage
• Set the scale factor and zero point in sensor signal
conditioning circuits
11
12
13
14
R
W
R
H
• Vary the frequency and duty cycle of timer ICs
R
L
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
V
CC
Bus Interface Pins
System Level
SERIAL DATA INPUT/OUTPUT (SDA)
• Adjust the contrast in LCD displays
The SDA is a bidirectional serial data input/output pin for a
2-wire slave device and is used to transfer data into and out
of the device. It receives device address, opcode, wiper
register address and data sent from an 2-wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial
systems
SERIAL CLOCK (SCL)
• Trim offset and gain errors in artificial intelligent
systems
This input is used by 2-wire master to supply 2-wire serial
clock to the X9119.
Pinout
DEVICE ADDRESS (A –A )
2
0
X9119
(14 LD TSSOP)
TOP VIEW
The Address inputs are used to set the least significant 3 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9119. A maximum
of 8 devices may occupy the 2-wire serial bus.
NC
14
13
12
11
10
1
2
3
4
5
6
7
V
CC
R
R
R
A0
L
HARDWARE WRITE PROTECT INPUT (WP)
NC
H
The WP pin when LOW prevents nonvolatile writes to the
Data Registers.
A2
SCL
SDA
W
NC
A1
9
8
V
Potentiometer Pins
SS
WP
R , R
H
L
The R and R pins are equivalent to the terminal
H
L
connections on a mechanical potentiometer.
FN8162.4
July 9, 2008
3
X9119
R
At both ends of each array and between each resistor
W
segment is a CMOS switch connected to the wiper (R )
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 10-bits of the WCR
(WCR[9:0]) are decoded to select, and enable, one of 1024
switches.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY
CC
GROUND (V
)
SS
The WCR may be written directly. The Data Registers and
the WCR can be read and written by the host system.
The V
CC
pin is the system supply voltage. The V pin is
SS
the system ground.
Serial Interface Description
Other Pins
SERIAL INTERFACE
NO CONNECT
The X9119 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9119 will be
considered a slave device in all applications.
No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.
Principals of Operation
The X9119 is an integrated microcircuit incorporating a
resistor array and its associated registers and counters and
the serial interface logic providing direct communication
between the host and the digitally controlled potentiometer.
This section provides detail description of the following:
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Figure 3).
• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description
Resistor Array Description
START CONDITION
All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9119 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met (Figure 3).
The X9119 is comprised of a resistor array. The array
contains, in effect, 1023 discrete resistive segments that are
connected in series (Figure 1). The physical ends of each
array are equivalent to the fixed terminals of a mechanical
potentiometer (R and R inputs).
H
L
SERIAL DATA PATH
R
SERIAL
BUS
INPUT
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
(DR0)
REGISTER 1
(DR1)
10
10
PARALLEL
BUS
INPUT
E
R
REGISTER 2
(DR2)
REGISTER 3
(DR3)
WIPER
COUNTER
REGISTER
(WCR)
D
E
C
O
D
E
R
IF WCR = 000[HEX] THEN R = R
W
L
H
IF WCR = 3FF[HEX] THEN R = R
W
R
R
L
W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM SERIAL INTERFACE DESCRIPTION
FN8162.4
July 9, 2008
4
X9119
STOP CONDITION
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 3).
The X9119 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9119 will
respond with a final acknowledge (see Figure 2).
ACKNOWLEDGE
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACKNOWLEDGE POLLING
FLOW 1. ACK Polling Sequence
The disabling of the inputs, during the internal nonvolatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the nonvolatile write command
the X9119 initiates the internal write cycle. ACK polling,
Flow 1, can be initiated immediately. This involves issuing
the start condition followed by the device slave address. If
the X9119 is still busy with the write operation, no ACK will
be returned. If the X9119 has completed the write operation,
an ACK will be returned and the master can then proceed
with the next operation.
NONVOLATILE WRITE
COMMAND COMPLETED
ENTERACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ISSUE STOP
ACK
NO
RETURNED?
YES
NO
FURTHER
OPERATION?
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
FN8162.4
July 9, 2008
5
X9119
slave address matches the incoming device address sent by
the master executes the instruction. The A2–A0 inputs can
Instruction and Register Description
Device Addressing: Identification Byte (ID and A)
be actively driven by CMOS input signals or tied to V
or
CC
Following a start condition, the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier. The
ID[3:0] bits is the device id for the X9119; this is fixed as
0101[B] (refer to Table 1).
V
. The R/W bit is the LSB and is be used to program the
SS
device for read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
The next byte sent to the X9119 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (IOP[2:0]). The RB
and RA bits point to one of the four registers. The format is
shown below in Table 2.
The A2–A0 bits in the ID byte is the internal slave address.
The physical device address is defined by the state of the
A2–A0 input pins. The slave address is externally specified
by the user. The X9119 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9119 to successfully
continue the command sequence. Only the device which
Table 3 provides a complete summary of the instruction set
opcodes.
TABLE 1. IDENTIFICATION BYTE FORMAT
INTERNAL SLAVE
ADDRESS
DEVICE TYPE
IDENTIFIES
READ OR
WRITE BIT
ID3
0
ID2
1
ID1
0
ID0
1
A2
A1
A0
R/W
(MSB)
(LSB)
TABLE 2. INSTRUCTION BYTE FORMAT
REGISTER
SELECTION
INSTRUCTION
OPCODE
I2
I1
I0
0
RB
RA
0
0
(MSB)
(LSB)
REGISTER SELECTED
RB
0
RA
DR0
DR1
DR2
DR3
0
1
0
1
0
1
1
TABLE 3. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
R/W
I
I
I
0
0
RB
RA
0
0
OPERATION
2
1
Read Wiper Counter
Register
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register
0
0
0
0
0
0
Write new value to the Wiper Counter
Register
Read Data Register
1/0
1/0
1/0
1/0
1/0
1/0
Read the contents of the Data Register pointed to
RB-RA.
Write Data Register
Write new value to the Data Register
pointed to RB-RA.
XFR Data Register to
Wiper Counter Register
Transfer the contents of the Data Register
pointed to by RB-RA.to the Wiper Counter
Register
XFR Wiper Counter Register
to Data Register
0
1
1
1
0
1/0
1/0
0
0
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by
RB-RA.
NOTE: 1/0 = data is one or zero.
FN8162.4
July 9, 2008
6
X9119
Although the register is automatically loaded with the value
in DR0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR0 value
into the WCR.
Instruction and Register Description
Device Addressing
WIPER COUNTER REGISTER (WCR)
The X9119 contains a Wiper Counter Registers (refer to
Table 4) for the XDCP potentiometer. The WCR is equivalent
to a serial-in, parallel-out register/counter with its outputs
decoded to select one of 1024 switches along its resistor
array. The contents of the WCR can be altered in one of
three ways:
DATA REGISTERS (DR0 TO DR3)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the Wiper Counter Register. All operations
changing data in one of the data registers is a nonvolatile
operation and will take a maximum of 10ms.
1. it may be written directly by the host via the write wiper
counter register instruction (serial load)
2. it may be written indirectly by transferring the contents of
one of four associated data registers via the XFR data
register
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
3. it is loaded with the contents of its data register zero (R0)
upon power-up.
Bit 9–Bit 0 are used to store one of the 1024 wiper position
(0 ~1023).
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9119 is powered-down.
TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used to store the current wiper position (Volatile, V)
WCR9
V
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Non-Volatile, NV)
Bit 9
NV
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
Four of the six instructions are four bytes in length. These
instructions are:
Two instructions (Figure 4) require a two-byte sequence to
complete. These instructions transfer data between the host
and the X9119; either between the host and one of the data
registers or directly between the host and the Wiper Counter
Register. These instructions are:
• Read Wiper Counter Register – read the current wiper
position of the selected potentiometer,
• Write Wiper Counter Register – change current wiper
position of the selected potentiometer,
• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the Wiper Counter Register.
• Read Data Register – read the contents of the selected
Data Register;
• XFR Wiper Counter Register to Data Register – This
transfers the contents of the Wiper Counter Register to the
specified Data Register.
• Write Data Register – write a new value to the selected
Data Register.
The basic sequence of the four byte instructions is illustrated
in Figure 3. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer
from a data register to a WCR is essentially a write to a static
RAM, with the static RAM controlling the wiper position. The
See “Instruction Format” on page 8 for more details.
POWER-UP AND DOWN REQUIREMENTS
There are no restrictions on the power-up condition of V
CC
and the voltages applied to the potentiometer pins provided
that the V
is always more positive than or equal to the
response of the wiper to this action will be delayed by t
A transfer from the WCR (current wiper position), to a data
.
CC
voltages at R , R , and R , i.e. V
WRL
≥ R , R , R . There
H
L
W
CC
H
L
W
are no restrictions on the power-down condition. However,
register is a write-to-nonvolatile memory and takes a
the datasheet parameters for the DCP do not apply until 1ms
minimum of t
to complete. The transfer can occur
WR
after V
CC
reaches its final value.
between one of the four potentiometers and one of its
associated registers.
FN8162.4
July 9, 2008
7
X9119
SCL
SDA
0
1
0
1
0
0
0
0
S
T
A
R
T
ID3 ID2 ID1 ID0
DEVICE ID
I2
I0
A2 A1 A0 R/W
A
C
K
I1
0
RB RA
A
C
K
S
T
O
P
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
0
1
0
1
0
0
X
0
0
X
X
X X
X
X
X
S
T
A0
ID3 ID2ID1ID0 A2 A1
R/W
0 RB RA 0
A
C
K
W W
A
C
K
W W W W W W W W A
I0
I2 I1
S
T
A
C
K
C
R
9
C
R
8
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
C
K
O
P
A
R
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
DEVICE ID
T
WIPER OR DATA
POSITION
FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
Instruction Format
READ WIPER COUNTER REGISTER (WCR)
DEVICE
TYPE
DEVICE
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
WIPER POSITION
(SENT BY SLAVE ON SDA)
WIPER POSITION
(SENT BY SLAVE ON SDA)
IDENTIFIER ADDRESSES
S
T
A
R
T
S
A
C
K
S
A
C
K
W W M W W W W W W W W M
S
T
O
P
0
1
0
1
A2 A1 A0
1
0
0
0
0
0
0
0
X
X
X
X
X
X
C
R
9
C
R
8
A
C
K
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
A
C
K
WRITE WIPER COUNTER REGISTER (WCR)
DEVICE
WIPER POSITION
WIPER POSITION
TYPE
DEVICE
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
(SENT BY MASTER ON
SDA)
(SENT BY MASTER ON
SDA)
IDENTIFIER ADDRESSES
S
T
A
R
T
S
A
C
K
S
W W
S
W W W W W W W W
S
A
C
K
S
T
O
P
0
1
0
1
A2 A1 A0
1
0
1
0
0
0
0
0
A
C
K
X
X
X
X
X
X
C
R
9
C
R
8
A
C
K
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
READ DATA REGISTER (DR)
DEVICE
TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION REGISTER
OPCODE ADDRESSES
WIPER POSITION
(SENT BY SLAVE ON SDA)
WIPER POSITION OR DATA
(SENT BY SLAVE ON SDA)
S
T
A
R
T
S
S
W
C
R
9
W
C
R
8
M
A
C
K
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
M
S
T
O
P
0
1
0
1
A2 A1 A0
A
C
K
1
0
1
0
RB RA
0
0
A
C
K
X
X
X
X
X
X
A
C
K
FN8162.4
July 9, 2008
8
X9119
WRITE DATA REGISTER (DR)
DEVICE
WIPER POSITION OR
DATA
WIPER POSITION OR
DATA
TYPE
DEVICE
INSTRUCTION REGISTER
OPCODE ADDRESSES
(SENT BY MASTER ON
SDA)
(SENT BY MASTER ON
SDA)
IDENTIFIER ADDRESSES
S
T
A
R
T
S
A
C
K
S
A
C
K
W W
S
A
C
K
W W W W W W W W
S
A
C
K
S
T
O
P
0
1
0
1
A2 A1 A0
1
1
0
0
RB RA
0
0
X
X
X
X
X
X
C
R
9
C
R
8
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
TRANSFER WIPER COUNTER REGISTER (WCR) TO DATA REGISTER (DR)
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
S
T
A
R
T
S
A
C
K
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
A2
1
A0
1
1
1
0
RB RA
0
0
TRANSFER DATA REGISTER (DR) TO WIPER COUNTER REGISTER (WCR)
DEVICE
TYPE
DEVICE
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
S
T
A
R
T
IDENTIFIER ADDRESSES
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
A2 A1 A0
1
1
0
0
RB RA
0
0
NOTES:
1. A2 ~ A0”: stand for the device addresses sent by the master.
2. WCRx refers to wiper position data in the Wiper Counter Register
FN8162.4
July 9, 2008
9
X9119
Absolute Maximum Ratings
Thermal Information
Voltage on SCL, SDA, or any address input
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
with respect to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
SS
ΔV = | (VH–VL) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
I
W
Operating Conditions
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40° to +85°C
Supply Voltage (VCC) Limits (Note 4)
X9119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
X9119-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Analog Specifications (Over recommended operation conditions unless otherwise stated.)
MIN
MAX
PARAMETER
End-to-End Resistance
End-to-End Resistance Tolerance
Power Rating
SYMBOL
R
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
kΩ
100
TOTAL
±20
50
%
+25°C, each pot
mW
mA
Ω
Wiper Current
I
±3
W
Wiper Resistance
R
Wiper Current = ± 50µA,
= 5V
40
110
W
V
CC
Wiper Current = ± 50µA,
150
300
5
Ω
V
V
= 3V
= 0V
CC
SS
Voltage on any R or R Pin
V
V
SS
V
dBV
%
H
L
TERM
Noise
Ref: 1V
-120
0.1
Resolution
Absolute Linearity (Note 1)
Relative Linearity (Note 2)
Temperature Coefficient of R
R
– R
, where n = 8
(Note 4)
±1
MI
(Note 3)
w(n)(actual)
to 1006
w(n)(expected)
R
R
– R
w(n)(expected)
±1.5
±2.0
±0.5
±1.0
MI
(Note 3)
w(n)(actual)
– [R
w(m)
+ MI], where m = 8 to
+ MI] (Note 4)
MI
(Note 3)
w(m + 1)
1006
R
– [R
w(m)
±0.5
MI
(Note 3)
w(m + 1)
±300
20
ppm/°C
ppm/°C
pF
TOTAL
Ratiometric Temp. Coefficient
Potentiometer Capacitancies
C /C /C
W
See Macro model
10/10/25
H
L
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage as determined by wiper position when used as a potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = R
/1023 or (R – R )/1023, single pot
H L
TOT
4. n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
5. ESD Rating on R , R , R pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.
H
L
W
FN8162.4
July 9, 2008
10
X9119
Operating Specifications (Over the recommended operating conditions unless otherwise specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNITS
V
supply current
I
f
= 400kHz; V = +5.5V;
3
mA
CC
CC1
CC2
SCL
CC
(active)
SDA = Open; (for 2-wire, Active, Read and
Volatile Write States only)
V
supply current
I
f
= 400kHz; V = +5.5V;
CC
5
3
mA
µA
CC
(nonvolatile write)
SCL
SDA = Open; (for 2-wire, Active,
Non-volatile Write State only)
V
current (standby)
I
V
= +5.5V; V = V or V
;
CC
SB
CC
IN SS CC
SDA = V
;
CC
(for 2-wire, Standby State only)
Input leakage current
I
V
V
= V to V
SS CC
10
10
µA
µA
LI
IN
Output leakage
current
I
= V to V
SS CC
LO
OUT
Input HIGH voltage
Input LOW voltage
Output LOW voltage
Output HIGH voltage
V
V
x 0.7
V
+ 1
V
V
V
IH
CC
CC
V
-1
V
x 0.3
IL
CC
0.4
V
I
= 3mA
OL
OL
OH
V
Endurance and Data Retention
PARAMETER
MIN
100,000
100
UNITS
Minimum Endurance
Data Retention
Data changes per bit per register
years
Capacitance
TEST
Input/Output capacitance (SI)
SYMBOL
MAX
UNITS
pF
TEST CONDITIONS
= 0V
C
C
(Note 6)
8
6
V
IN/OUT
(Note 6)
OUT
V = 0V
IN
Input capacitance (SCL, WP, A1 and A0)
pF
IN
Power-Up Timing
PARAMETER
SYMBOL
(Note 6)
MIN
MAX
50
UNITS
V/ms
ms
V
Power-up Rate
t V
CC
0.2
CC
r
Power-up to Initiation of read operation
Power-up to Initiation of write operation
t
t
(Note 7)
(Note 7)
1
PUR
50
ms
PUW
NOTES:
6. Limits should be considered typical and are not production tested.
7. t and t are the delays required from the time the (last) power supply (Vcc-) is stable until the specific instruction can be issued. These
PUR
PUW
parameters are not 100% tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
AC Test Conditions
Input Pulse Levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
Input Rise and Fall Times
Input and Output Timing Level
10ns
V
CC
FN8162.4
July 9, 2008
11
X9119
Equivalent A.C. Load Circuit
5V
3V
SPICE MACROMODEL
1533Ω
867Ω
R
TOTAL
C
R
L
R
H
SDA OUTPUT
SDA OUTPUT
C
C
L
W
L
10pF
10pF
100pF
25pF
100pF
R
W
AC Timing High-Voltage Write Cycle Timing
PARAMETER
SYMBOL
MIN
MAX
UNITS
kHz
ns
Clock Frequency
f
400
SCL
Clock Cycle Time
t
2500
600
1300
600
600
600
100
0
CYC
Clock High Time
t
ns
HIGH
Clock Low Time
t
ns
LOW
Start Setup Time
t
ns
SU:STA
HD:STA
SU:STO
Start Hold Time
t
ns
Stop Setup Time
t
ns
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
t
ns
SU:DAT
HD:DAT
t
ns
t
300
300
ns
R
t
ns
F
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Noise Suppression Time Constant at SCL and SDA Inputs
Bus Free Time (Prior to Any Transmission)
A0, A1, A2 Setup Time
t
250
0
ns
AA
DH
t
ns
T
50
1300
0
ns
I
t
ns
BUF
t
ns
SU:WPA
A0, A1, A2 Hold Time
t
0
ns
HD:WPA
High-Voltage Write Cycle Timing
PARAMETER
SYMBOL
TYP
MAX
UNITS
High-Voltage Write CycleTime (Store Instructions)
t
5
10
ms
WR
XDCP Timing
PARAMETER
SYMBOL
WRPO
WRL
MIN
5
MAX
10
UNITS
µs
Wiper Response Time After theThird (Last) Power Supply is Stable
t
t
WiperResponse Time After Instruction Issued (All Load
Instructions)
5
10
µs
FN8162.4
July 9, 2008
12
X9119
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Timing Diagrams
Start and Stop Timing
( START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
SDA
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
FN8162.4
July 9, 2008
13
X9119
XDCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
LSB
t
WRL
R
W
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(ANY INSTRUCTION)
...
SDA
...
T
T
SU:WPA
HD:WPA
WP
A0, A1, A2
FN8162.4
July 9, 2008
14
X9119
Applications information
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Application Circuits
NONINVERTING AMPLIFIER
VOLTAGE REGULATOR
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
ADJ
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
OFFSET VOLTAGE ADJUSTMENT
COMPARATOR WITH HYSTERESIS
R
R
2
1
V
–
+
S
V
V
S
O
100kΩ
–
+
V
O
TL072
R
R
1
2
10kΩ
10kΩ
V
= {R /(R +R )} V (max)
1 1 2 O
UL
RL = {R /(R +R )} V (min)
10kΩ
L
1
1
2
O
+12V
-12V
FN8162.4
July 9, 2008
15
X9119
Application Circuits (Continued)
ATTENUATOR
FILTER
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
R
= R = R = R = 10kΩ
1
2
3
4
R
1
G
= 1 + R /R
2 1
O
V
= G V
S
O
fc = 1/(2pRC)
-1/2 £ G £ +1/2
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
FUNCTION GENERATOR
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
FREQUENCY µ R , R , C
1
2
AMPLITUDE µ R , R
A
B
FN8162.4
July 9, 2008
16
X9119
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
M14.173
INDEX
AREA
0.25(0.010)
M
B M
E
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
E1
-B-
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
1
2
3
A
A1
A2
b
-
-
L
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
0.25
0.010
0.05(0.002)
SEATING PLANE
A
-
-A-
D
9
c
-
-C-
α
D
3
A2
e
A1
E1
e
4
c
b
0.10(0.004)
0.026 BSC
0.65 BSC
-
0.10(0.004) M
C
A M B S
E
0.246
0.256
6.25
0.45
6.50
0.75
-
L
0.0177
0.0295
6
NOTES:
N
14
14
7
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
o
o
o
o
0
8
0
8
-
α
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8162.4
July 9, 2008
17
相关型号：
X9119TV14Z-2.7T1
100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-14
RENESAS
X9119TV14ZT1
100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO14, 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-14
RENESAS
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