MR82C59A-12/B [RENESAS]
80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CQCC28, CERAMIC, LCC-28;
| 型号： | MR82C59A-12/B |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CQCC28, CERAMIC, LCC-28 时钟 外围集成电路 装置 |
| 文件： | 总20页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
82C59A
CMOS Priority Interrupt Controller
March 1997
Features
Description
• 12.5MHz, 8MHz and 5MHz Versions Available
The Intersil 82C59A is a high performance CMOS Priority
Interrupt Controller manufactured using an advanced 2µm
CMOS process. The 82C59A is designed to relieve the sys-
- 12.5MHz Operation. . . . . . . . . . . . . . . . . . . 82C59A-12
- 8MHz Operation . . . . . . . . . . . . . . . . . . . . . . . 82C59A
- 5MHz Operation . . . . . . . . . . . . . . . . . . . . . . 82C59A-5
tem CPU from the task of polling in
a multilevel
priority system. The high speed and industry standard
configuration of the 82C59A make it compatible with micro-
processors such as 80C286, 80286, 80C86/88, 8086/88,
8080/85 and NSC800.
• High Speed, “No Wait-State” Operation with 12.5MHz
80C286 and 8MHz 80C86/88
• Pin Compatible with NMOS 8259A
The 82C59A can handle up to eight vectored priority inter-
rupting sources and is cascadable to 64 without additional
circuitry. Individual interrupting sources can be masked or
prioritized to allow custom system configuration. Two modes
of operation make the 82C59A compatible with both 8080/85
and 80C86/88/286 formats.
• 80C86/88/286 and 8080/85/86/88/286 Compatible
• Eight-Level Priority Controller, Expandable to
64 Levels
• Programmable Interrupt Modes
• Individual Request Mask Capability
• Fully Static Design
Static CMOS circuit design ensures low operating power.
The Intersil advanced CMOS process results in performance
equal to or greater than existing equivalent products at a
fraction of the power.
• Fully TTL Compatible
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum
- ICCOP . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum
• Single 5V Power Supply
• Operating Temperature Ranges
o
o
- C82C59A . . . . . . . . . . . . . . . . . . . . . . . . .0 C to +70 C
o
o
- I82C59A . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
o
o
- M82C59A. . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Ordering Information
PART NUMBER
TEMPERATURE
5MHz
8MHz
CP82C59A
12.5MHz
PACKAGE
28 Ld PDIP
RANGE
PKG. NO.
E28.6
o
o
CP82C59A-5
IP82C59A-5
CP82C59A-12
IP82C59A-12
CS82C59A-12
IS82C59A-12
CD82C59A-12
ID82C59A-12
MD82C59A-12/B
-
0 C to +70 C
o
o
IP82C59A
-40 C to +85 C
E28.6
N28.45
N28.45
F28.6
F28.6
F28.6
F28.6
J28.A
J28.A
M28.3
o
o
CS82C59A-5
IS82C59A-5
CS82C59A
28 Ld PLCC
CERDIP
0 C to +70 C
o
o
IS82C59A
-40 C to +85 C
o
o
CD82C59A-5
ID82C59A-5
CD82C59A
0 C to +70 C
o
o
ID82C59A
-40 C to +85 C
o
o
MD82C59A-5/B
5962-8501601YA
MR82C59A-5/B
5962-85016013A
CM82C59A-5
MD82C59A/B
5962-8501602YA
MR82C59A/B
5962-85016023A
CM82C59A
-55 C to +125 C
SMD#
o
o
MR82C59A-12/B
-
28 Pad CLCC
SMD#
-55 C to +125 C
o
o
CM82C59A-12
28 Ld SOIC
0 C to +70 C
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 2784.2
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
82C59A
Pinouts
82C59A (PDIP, CERDIP, SOIC)
82C59A (PLCC, CLCC)
TOP VIEW
TOP VIEW
1
2
3
4
28 V
CS
WR
RD
CC
27
26
25
24
23
22
21
20
19
18
17
16
15
A0
1
4
3
2
28 27 26
INTA
IR7
25
24
23
22
21
20
19
D6
D5
D4
D3
D2
D1
D0
IR7
IR6
IR5
5
6
D7
IR6
D6
5
6
7
8
IR5
D5
IR4
IR3
7
8
IR4
D4
IR3
D3
9
9
IR2
D2
10
11
IR2
IR1
10
11
12
13
14
IR1
D1
IR0
D0
12
13 14 15 16 17 18
INT
CAS 0
CAS 1
GND
SP/EN
CAS 2
PIN
DESCRIPTION
Data Bus (Bidirectional)
Read Input
D7 - D0
RD
WR
Write Input
A0
Command Select Address
Chip Select
CS
CAS 2 - CAS 0
SP/EN
INT
Cascade Lines
Slave Program Input Enable
Interrupt Output
INTA
Interrupt Acknowledge Input
Interrupt Request Inputs
IR0 - IR7
Functional Diagram
INTA
INT
DATA
BUS
BUFFER
D -D
7
0
CONTROL LOGIC
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
RD
WR
READ/
WRITE
LOGIC
IN -
SERVICE
REG
INTERRUPT
REQUEST
REG
PRIORITY
RESOLVER
A
0
(ISR)
(IRR)
CS
CAS 0
CAS 1
CAS 2
CASCADE
BUFFER
COMPARATOR
INTERRUPT MASK REG
(IMR)
SP/EN
INTERNAL BUS
FIGURE 1.
2
82C59A
Pin Description
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
: The +5V power supply pin. A 0.1µF capacitor between pins 28 and 14 is recommended for
V
28
I
V
CC
CC
decoupling.
GND
CS
14
1
I
I
GROUND
CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the
82C59A. INTA functions are independent of CS.
WR
RD
2
3
I
WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from
the CPU.
I
READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus
for the CPU.
D7 - D0
CAS0 - CAS2
SP/EN
4 - 11
12, 13, 15
16
I/O
I/O
I/O
BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via
this bus.
CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A struc-
ture. These pins are outputs for a master 82C59A and inputs for a slave 82C59A.
SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it
can be used as an output to control buffer transceivers (EN). When not in the Buffered Mode it is
used as an input to designate a master (SP = 1) or slave (SP = 0).
INT
17
O
I
INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to inter-
rupt the CPU, thus, it is connected to the CPU's interrupt pin.
IR0 - IR7
18 - 25
INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an
IR input (low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just
by a high level on an IR input (Level Triggered Mode). Internal pull-up resistors are implemented
on IR0 - 7.
INTA
A0
26
27
I
I
INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the
data bus by a sequence of interrupt acknowledge pulses issued by the CPU.
ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the
82C59A to decipher various Command Words the CPU writes and status the CPU wishes to read.
It is typically connected to the CPU A0 address line (A1 for 80C86/88/286).
Functional Description
CPU - DRIVEN
MULTIPLEXER
Interrupts in Microcomputer Systems
CPU
Microcomputer system design requires that I/O devices such
as keyboards, displays, sensors and other components
receive servicing in an efficient manner so that large
amounts of the total system tasks can be assumed by the
microcomputer with little or no effect on throughput.
RAM
ROM
I/O (1)
I/O (2)
The most common method of servicing such devices is the
Polled approach. This is where the processor must test each
device in sequence and in effect “ask” each one if it needs
servicing. It is easy to see that a large portion of the main
program is looping through this continuous polling cycle and
that such a method would have a serious, detrimental effect
on system throughput, thus, limiting the tasks that could be
assumed by the microcomputer and reducing the cost effec-
tiveness of using such devices.
I/O (N)
FIGURE 2. POLLED METHOD
3
82C59A
A more desirable method would be one that would allow the The Programmable Interrupt Controller (PlC) functions as an
microprocessor to be executing its main program and only overall manager in an Interrupt-Driven system. It accepts
stop to service peripheral devices when it is told to do so by requests from the peripheral equipment, determines which of
the device itself. In effect, the method would provide an the incoming requests is of the highest importance (priority),
external asynchronous input that would inform the processor ascertains whether the incoming request has a higher prior-
that it should complete whatever instruction that is currently ity value than the level currently being serviced, and issues
being executed and fetch a new routine that will service the an interrupt to the CPU based on this determination.
requesting device. Once this servicing is complete, however,
Each peripheral device or structure usually has a special
the processor would resume exactly where it left off.
program or “routine” that is associated with its specific func-
This is the Interrupt-driven method. It is easy to see that sys- tional or operational requirements; this is referred to as a
tem throughput would drastically increase, and thus, more “service routine”. The PlC, after issuing an interrupt to the
tasks could be assumed by the microcomputer to further CPU, must somehow input information into the CPU that can
enhance its cost effectiveness.
“point” the Program Counter to the service routine associ-
ated with the requesting device. This “pointer” is an address
in a vectoring table and will often be referred to, in this docu-
ment, as vectoring data.
INT
CPU
82C59A Functional Description
PIC
The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for expand-
ability to other 82C59As (up to 64 levels). It is programmed
by system software as an I/O peripheral. A selection of prior-
ity modes is available to the programmer so that the manner
in which the requests are processed by the 82C59A can be
configured to match system requirements. The priority
modes can be changed or reconfigured dynamically at any
time during main program operation. This means that the
complete interrupt structure can be defined as required,
based on the total system environment.
I/O (1)
RAM
ROM
I/O (2)
I/O (N)
Interrupt Request Register (IRR) and In-Service Register
(ISR)
The interrupts at the IR input lines are handled by two registers
in cascade, the Interrupt Request Register (lRR) and the In-
Service Register (lSR). The IRR is used to indicate all the inter-
rupt levels which are requesting service, and the ISR is used to
store all the interrupt levels which are currently being serviced.
FIGURE 3. INTERRUPT METHOD
INTA
INT
DATA
BUS
BUFFER
D
- D
0
7
CONTROL LOGIC
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
RD
READ/
WRITE
LOGIC
WR
IN
INTERRUPT
REQUEST
REG
A
SERVICE
REG
PRIORITY
RESOLVER
0
(ISR)
(IRR)
CS
CASCADE
BUFFER
COMPARATOR
CAS 0
CAS 1
CAS 2
INTERRUPT MASK REG
(IMR)
SP/EN
INTERNAL BUS
FIGURE 4. 82C59A FUNCTIONAL DIAGRAM
4
82C59A
Priority Resolver
The Cascade Buffer/Comparator
This logic block determines the priorities of the bits set in the This function block stores and compares the IDs of all
lRR. The highest priority is selected and strobed into the cor- 82C59As used in the system. The associated three I/O pins
responding bit of the lSR during the INTA sequence.
(CAS0 - 2) are outputs when the 82C59A is used as a mas-
ter and are inputs when the 82C59A is used as a slave. As a
master, the 82C59A sends the ID of the interrupting slave
device onto the CAS0 - 2 lines. The slave, thus selected will
send its preprogrammed subroutine address onto the Data
Bus during the next one or two consecutive INTA pulses.
(See section “Cascading the 82C59A”.)
Interrupt Mask Register (IMR)
The lMR stores the bits which disable the interrupt lines to be
masked. The IMR operates on the output of the IRR. Mask-
ing of a higher priority input will not affect the interrupt
request lines of lower priority.
Interrupt Sequence
Interrupt (INT)
The powerful features of the 82C59A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specified interrupt routine requested without
any polling of the interrupting devices. The normal sequence
of events during an interrupt depends on the type of CPU
being used.
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible with
the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286
input levels.
Interrupt Acknowledge (INTA)
INTA pulses will cause the 82C59A to release vectoring
information onto the data bus. The format of this data
depends on the system mode (µPM) of the 82C59A.
These events occur in an 8080/8085 system:
1. One or more of the INTERRUPT REQUEST lines
(IR0 - IR7) are raised high, setting the corresponding IRR
bit(s).
Data Bus Buffer
This 3-state, bidirectional 8-bit buffer is used to interface the
82C59A to the System Data Bus. Control words and status
information are transferred through the Data Bus Buffer.
2. The 82C59A evaluates those requests in the priority
resolver and sends an interrupt (INT) to the CPU, if
appropriate.
Read/Write Control Logic
3. The CPU acknowledges the lNT and responds with an
INTA pulse.
The function of this block is to accept output commands from
the CPU. It contains the Initialization Command Word (lCW)
registers and Operation Command Word (OCW) registers
which store the various control formats for device operation.
This function block also allows the status of the 82C59A to
be transferred onto the Data Bus.
4. Upon receiving an lNTA from the CPU group, the highest
priority lSR bit is set, and the corresponding lRR bit is
reset. The 82C59A will also release a CALL instruction
code (11001101) onto the 8-bit data bus through D0 - D7.
5. This CALL instruction will initiate two additional INTA
pulses to be sent to 82C59A from the CPU group.
Chip Select (CS)
A LOW on this input enables the 82C59A. No reading or 6. These two INTA pulses allow the 82C59A to release its
writing of the device will occur unless the device is selected.
preprogrammed subroutine address onto the data bus.
The lower 8-bit address is released at the first INTA pulse
and the higher 8-bit address is released at the second
INTA pulse.
Write (WR)
A LOW on this input enables the CPU to write control words
(lCWs and OCWs) to the 82C59A.
7. This completes the 3-byte CALL instruction released by
the 82C59A. In the AEOI mode, the lSR bit is reset at the
end of the third INTA pulse. Otherwise, the lSR bit
remains set until an appropriate EOI command is issued
at the end of the interrupt sequence.
Read (RD)
A LOW on this input enables the 82C59A to send the status
of the Interrupt Request Register (lRR), In-Service Register
(lSR), the Interrupt Mask Register (lMR), or the interrupt
level (in the poll mode) onto the Data Bus.
The events occurring in an 80C86/88/286 system are the
same until step 4.
A0
4. The 82C59A does not drive the data bus during the first
INTA pulse.
This input signal is used in conjunction with WR and RD sig-
nals to write commands into the various command registers,
as well as to read the various status registers of the chip.
This line can be tied directly to one of the system address
lines.
5. The 80C86/88/286 CPU will initiate a second INTA pulse.
During this INTA pulse, the appropriate ISR bit is set and
the corresponding bit in the IRR is reset. The 82C59A
outputs the 8-bit pointer onto the data bus to be read by
the CPU.
5
82C59A
ADDRESS BUS (16)
CONTROL BUS
I/OR
I/OW
INT
INTA
DATA BUS (8)
CS
A
D
- D
0
RD
WR
INT
INTA
0
7
CAS 0
CASCADE
LINES
82C59A
CAS 1
CAS 2
IRQ
7
IRQ
6
IRQ
5
IRQ
4
IRQ
3
IRQ
2
IRQ
1
IRQ
0
SP/EN
INTERRUPT
REQUESTS
SLAVE PROGRAM/
ENABLE BUFFER
FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE
6. This completes the interrupt cycle. In the AEOI mode, the
ISR bit is reset at the end of the second INTA pulse. Oth-
erwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt subroutine.
CONTENT OF SECOND INTERRUPT VECTOR BYTE
INTERVAL = 4
IR
D7
A7
A7
A7
A7
A7
A7
A7
A7
D6
A6
A6
A6
A6
A6
A6
A6
A6
D5
A5
A5
A5
A5
A5
A5
A5
A5
D4
1
D3
1
D2
1
D1
0
D0
0
7
6
5
4
3
2
1
0
If no interrupt request is present at step 4 of either sequence
(i.e., the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.
1
1
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
Interrupt Sequence Outputs
0
0
1
0
0
8080, 8085 Interrupt Response Mode
0
0
0
0
0
This sequence is timed by three INTA pulses. During the first
lNTA pulse, the CALL opcode is enabled onto the data bus.
IR
INTERVAL = 8
D7
A7
A7
A7
A7
A7
A7
A7
A7
D6
A6
A6
A6
A6
A6
A6
A6
A6
DS
1
D4
1
D3
1
D2
0
D1
0
D0
0
First Interrupt Vector Byte Data: Hex CD
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
0
0
Call Code
1
1
0
0
1
1
0
1
1
0
1
0
0
0
During the second INTA pulse, the lower address of the
appropriate service routine is enabled onto the data bus.
When interval = 4 bits, A5 - A7 are programmed, while
A0 - A4 are automatically inserted by the 82C59A. When
interval = 8, only A6 and A7 are programmed, while A0 - A5
are automatically inserted.
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
During the third INTA pulse, the higher address of the appro-
priate service routine, which was programmed as byte 2 of the
initialization sequence (A8 - A15), is enabled onto the bus.
6
82C59A
Initialization Command Words (lCWs)
CONTENT OF THIRD INTERRUPT VECTOR BYTE
D7
D6
D5
D4
D3
D2
D1
D0
General
A15
A14
A13
A12
A11
A10
A9
A8
Whenever a command is issued with A0 = 0 and D4 = 1, this
is interpreted as Initialization Command Word 1 (lCW1).
lCW1 starts the initialization sequence during which the fol-
lowing automatically occur:
80C86, 8OC88, 80C286 Interrupt Response Mode
80C86/88/286 mode is similar to 8080/85 mode except that
only two Interrupt Acknowledge cycles are issued by the pro-
cessor and no CALL opcode is sent to the processor. The a. The edge sense circuit is reset, which means that follow-
first interrupt acknowledge cycle is similar to that of 8080/85
systems in that the 82C59A uses it to internally freeze the
state of the interrupts for priority resolution and, as a master,
it issues the interrupt code on the cascade lines. On this first
cycle, it does not issue any data to the processor and leaves
its data bus buffers disabled. On the second interrupt
acknowledge cycle in the 86/88/286 mode, the master (or
slave if so programmed) will send a byte of data to the pro-
cessor with the acknowledged interrupt code composed as
follows (note the state of the ADI mode control is ignored
and A5 - A11 are unused in the 86/88/286 mode).
ing initialization, an interrupt request (IR) input must make
a low-to-high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. lR7 input is assigned priority 7.
d. Special Mask Mode is cleared and Status Read is set to
lRR.
e. If lC4 = 0, then all functions selected in lCW4 are set to
zero. (Non-Buffered mode (see note), no Auto-EOI,
8080/85 system).
NOTE: Master/Slave in ICW4 is only used in the buffered mode.
CONTENT OF INTERRUPT VECTOR BYTE FOR
80C86/88/286 SYSTEM MODE
ICW1
D7
T7
T7
T7
T7
T7
T7
T7
T7
D6
T6
T6
T6
T6
T6
T6
T6
T6
D5
T5
T5
T5
T5
T5
T5
T5
T5
D4
T4
T4
T4
T4
T4
T4
T4
T4
D3
T3
T3
T3
T3
T3
T3
T3
T3
D2
1
D1
1
D0
1
lR7
lR6
IR5
IR4
IR3
IR2
IR1
IR0
1
1
0
ICW2
1
0
1
1
0
0
0
1
1
IN
NO (SNGL = 1)
0
1
0
CASCADE
MODE
0
0
1
0
0
0
YES (SNGL = 0))
Programming the 82C59A
ICW3
The 82C59A accepts two types of command words gener-
ated by the CPU:
NO (IC4 = 0)
1. Initialization Command Words (ICWs): Before normal
operation can begin, each 82C59A in the system must be
brought to a starting point - by a sequence of 2 to 4 bytes
timed by WR pulses.
IS ICW4
NEEDED
YES (IC4 = 1)
2. Operation Command Words (OCWs): These are the
command words which command the 82C59A to operate
in various interrupt modes. Among these modes are:
ICW4
a. Fully nested mode.
b. Rotating priority mode.
c. Special mask mode.
d. Polled mode.
READY TO ACCEPT
INTERRUPT REQUESTS
FIGURE 6. 82C59A INITIALIZATION SEQUENCE
Initialization Command Words 1 and 2 (ICW1, lCW2)
The OCWs can be written into the 82C59A anytime after ini-
tialization.
A5 - A15: Page starting address of service routines. In an
8080/85 system the 8 request levels will generate CALLS to
8 locations equally spaced in memory. These can be pro-
grammed to be spaced at intervals of 4 or 8 memory loca-
tions, thus, the 8 routines will occupy a page of 32 or 64
bytes, respectively.
7
82C59A
ICW1
A
0
D
D
D
D
D
2
D
D
0
D
6
5
4
3
1
7
1
LTIM
ADI
SNGL
IC4
A
A
A
0
5
7
6
1 = ICW4 needed
0 = No ICW4 needed
1 = Single
0 = Cascade Mode
CALL address interval
1 = Interval of 4
0 = Interval of 8
1 = Level triggered mode
0 = Edge triggered mode
A
- A of Interrupt vector address
5
7
(MCS-80/85 mode only)
ICW2
A
0
D
D
D
D
3
D
2
D
1
D
0
D
6
5
4
7
A
A
A
A
A
A
A
A
8
15
14
13
12
11
10
9
1
T
T
T
T
T
3
7
6
5
4
A
- A of interrupt vector address
8
15
(MCS80/85 mode)
T
- T of interrupt vector address
3
7
(8086/8088 mode)
ICW3 (MASTER DEVICE)
A
D
D
D
D
D
D
D
D
0
6
5
4
3
2
1
0
7
1
S
S
S
S
S
S
S
S
0
7
6
5
4
3
2
1
1 = IR input has a slave
0 = IR input does not have a slave
ICW3 (SLAVE DEVICE)
A
D
D
D
D
D
D
D
D
0
6
5
4
3
2
1
0
7
1
0
0
0
0
0
ID
ID
ID
2
1
0
SLAVE ID (NOTE)
0
0
0
0
1
1
0
0
2
0
1
0
3
1
1
0
4
0
0
1
5
1
0
1
6
0
1
1
7
1
1
1
ICW4
A
0
D
D
D
D
D
D
D
D
6
5
4
3
2
1
0
7
1
0
0
0
SFNM
BUF
M/S
AEOI
µPM
1 = 8086/8088 mode
0 = MCS-80/85 mode
1 = Auto EOI
0 = Normal EOI
0
1
1
X
0
1
- Non buffered mode
- Buffered mode slave
- Buffered mode master
1 = Special fully nested moded
0 = Not special fully nested mode
NOTE: Slave ID is equal to the corresponding master IR input.
FIGURE 7. 82C59A INITIALIZATION COMMAND WORD FORMAT
8
82C59A
The address format is 2 bytes long (A0 - A15). When the AEOI: If AEOI = 1, the automatic end of interrupt mode is
routine interval is 4, A0 - A4 are automatically inserted by the
82C59A, while A5 - A15 are programmed externally. When
the routine interval is 8, A0 - A5 are automatically inserted by
the 82C59A while A6 - A15 are programmed externally.
programmed.
µPM: Microprocessor mode: µPM = 0 sets the 82C59A for
8080/85 system operation, µPM = 1 sets the
82C59A for 80C86/88/286 system operation.
The 8-byte interval will maintain compatibility with current
software, while the 4-byte interval is best for a compact jump
table.
Operation Command Words (OCWs)
After the Initialization Command Words (lCWs) are pro-
grammed into the 82C59A, the device is ready to accept
interrupt requests at its input lines. However, during the
82C59A operation, a selection of algorithms can command
the 82C59A to operate in various modes through the Opera-
tion Command Words (OCWs).
In an 80C86/88/286 system, A15 - A11 are inserted in the
five most significant bits of the vectoring byte and the
82C59A sets the three least significant bits according to the
interrupt level. A10 - A5 are ignored and ADI (Address inter-
val) has no effect.
LTlM: If LTlM = 1, then the 82C59A will operate in the level
interrupt mode. Edge detect logic on the interrupt
inputs will be disabled.
OPERATION COMMAND WORDS (OCWs)
A0
1
D7
M7
R
D6
M6
SL
D5
D4
OCW1
M4
D3
M3
0
D2
M2
L2
P
D1
M1
L1
D0
M0
L0
ADI:
ALL address interval. ADI = 1 then interval = 4; ADI
= 0 then interval = 8.
M5
SNGL: Single. Means that this is the only 82C59A in the
system. If SNGL = 1, no ICW3 will be issued.
OCW2
0
0
EOI
IC4:
If this bit is set - lCW4 has to be issued. If lCW4 is
not needed, set lC4 = 0.
OCW3
0
0
0
ESMM SMM
1
RR
RIS
Initialization Command Word 3 (ICW3)
Operation Command Word 1 (OCW1)
OCW1 sets and clears the mask bits in the Interrupt Mask
This word is read only when there is more than one 82C59A
in the system and cascading is used, in which case
SNGL = 0. It will load the 8-bit slave register. The functions of Register (lMR) M7 - M0 represent the eight mask bits. M = 1
this register are:
indicates the channel is masked (inhibited), M = 0 indicates
the channel is enabled.
a. In the master mode (either when SP = 1, or in buffered
mode when M/S = 1 in lCW4) a “1” is set for each slave in
the bit corresponding to the appropriate IR line for the
slave. The master then will release byte 1 of the call
sequence (for 8080/85 system) and will enable the corre-
sponding slave to release bytes 2 and 3 (for 80C86/88/
286, only byte 2) through the cascade lines.
Operation Command Word 2 (OCW2)
R, SL, EOI - These three bits control the Rotate and End of
Interrupt modes and combinations of the two. A chart of
these combinations can be found on the Operation Com-
mand Word Format.
b. In the slave mode (either when SP = 0, or if BUF = 1 and L2, L1, L0 - These bits determine the interrupt level acted
M/S = 0 in lCW4), bits 2 - 0 identify the slave. The slave upon when the SL bit is active.
compares its cascade input with these bits and if they are
Operation Command Word 3 (OCW3)
equal, bytes 2 and 3 of the call sequence (or just byte 2 for
80C86/88/286) are released by it on the Data Bus.
ESMM - Enable Special Mask Mode. When this bit is set to 1
it enables the SMM bit to set or reset the Special Mask
Mode. When ESMM = 0, the SMM bit becomes a “don’t
care”.
NOTE: (The slave address must correspond to the IR line it is con-
nected to in the master ID).
Initialization Command Word 4 (ICW4)
SMM - Special Mask Mode. If ESMM = 1 and SMM = 1, the
82C59A will enter Special Mask Mode. If ESMM = 1 and
SMM = 0, the 82C59A will revert to normal mask mode.
When ESMM = 0, SMM has no effect.
SFNM: If SFNM = 1, the special fully nested mode is pro-
grammed.
BUF: If BUF = 1, the buffered mode is programmed. In
buffered mode, SP/EN becomes an enable output
and the master/slave determination is by M/S.
Fully Nested Mode
This mode is entered after initialization unless another mode
is programmed. The interrupt requests are ordered in priority
from 0 through 7 (0 highest). When an interrupt is acknowl-
edged the highest priority request is determined and its vec-
tor placed on the bus. Additionally, a bit of the Interrupt
Service register (IS0 - 7) is set. This bit remains set until the
microprocessor issues an End of Interrupt (EOI) command
M/S:
If buffered mode is selected: M/S = 1 means the
82C59A is programmed to be a master, M/S = 0
means the 82C59A is programmed to be a slave. If
BUF = 0, M/S has no function.
9
82C59A
immediately before returning from the service routine, or if After the initialization sequence, IR0 has the highest priority
the AEOI (Automatic End of Interrupt) bit is set, until the trail- and IR7 the lowest. Priorities can be changed, as will be
ing edge of the last INTA. While the IS bit is set, all further explained in the rotating priority mode or via the set priority
interrupts of the same or lower priority are inhibited, while command.
higher levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal interrupt
enable flip-flop has been re-enabled through software).
OCW1
A
D
D
D
D
D
D
D
D
0
6
5
4
3
2
1
0
7
1
M
M
M
M
M
M
M
M
7
6
5
4
3
2
1
0
Interrupt Mask
1 = Mask set
0 = Mask reset
OCW2
A
0
D
D
D
D
D
D
D
0
D
6
5
4
3
2
1
7
0
R
SL
EOI
0
0
L
L
L
0
2
1
IR LEVEL TO BE
ACTED UPON
0
0
0
1
1
0
2
0
1
3
1
1
4
0
0
5
1
0
6
0
1
7
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
1
1
0
Non-specific EOI command
† Specific EOI command
End of interrupt
Rotate on non-specific EOI command
Rotate in automatic EOI mode (set)
Rotate in automatic EOI mode (clear)
Automatic rotation
Specific rotation
0
1
1
0
0
1
1
1
0
1
0
0
†
†
Rotate on specific EOI command
Set priority command
No operation
† L - L are used
0
2
OCW3
A
0
D
D
D
D
D
D
D
D
6
5
4
3
2
1
0
7
0
0
ESMM
SMM
0
1
P
RR
RIS
READ REGISTER COMMAND
0
0
1
0
0
1
1
1
Read IS reg on
next RD pulse
Read IR reg on
next RD pulse
No Action
1 = Poll command
0 = No poll command
SPECIAL MASK MODE
0
0
1
0
0
1
1
1
Set special
mask
Reset special
mask
No Action
FIGURE 8. 82C59A OPERATION COMMAND WORD FORMAT
10
82C59A
End of Interrupt (EOI)
After Rotate (lR4 was serviced, all other priorities rotated
correspondingly)
The In-Service (IS) bit can be reset either automatically fol-
lowing the trailing edge of the last in sequence INTA pulse
(when AEOI bit in lCW1 is set) or by a command word that
must be issued to the 82C59A before returning from a ser-
vice routine (EOI Command). An EOI command must be
issued twice if servicing a slave in the Cascade mode, once
for the master and once for the corresponding slave.
IS7
IS6
1
IS5
0
IS4
0
IS3
0
IS2
0
IS1
0
IS0
0
“IS” Status
0
2
Priority
Status
1
0
7
6
5
4
3
highest
lowest
There are two forms of EOl command: Specific and Non-
Specific. When the 82C59A is operated in modes which pre-
serve the fully nested structure, it can determine which IS bit
to reset on EOI. When a Non-Specific command is issued
the 82C59A will automatically reset the highest IS bit of
those that are set, since in the fully nested mode the highest
IS level was necessarily the last level acknowledged and
serviced. A non-specific EOI can be issued with OCW2
(EOl = 1, SL = 0, R = 0).
There are two ways to accomplish Automatic Rotation using
OCW2, the Rotation on Non-Specific EOI Command (R = 1,
SL = 0, EOI = 1) and the Rotate in Automatic EOI Mode
which is set by (R = 1, SL = 0, EOI = 0) and cleared by
(R = 0, SL = 0, EOl = 0).
Specific Rotation (Specific Priority)
The programmer can change priorities by programming the
lowest priority and thus, fixing all other priorities; i.e., if IR5 is
programmed as the lowest priority device, then IR6 will have
the highest one.
When a mode is used which may disturb the fully nested
structure, the 82C59A may no longer be able to determine
the last level acknowledged. In this case a Specific End of
Interrupt must be issued which includes as part of the com-
mand the IS level to be reset. A specific EOl can be issued
with OCW2 (EOI = 1, SL = 1, R = 0, and L0 - L2 is the binary
level of the IS bit to be reset).
The Set Priority command is issued in OCW2 where: R = 1,
SL = 1, L0 - L2 is the binary priority level code of the lowest
priority device.
Observe that in this mode internal status is updated by soft-
ware control during OCW2. However, it is independent of the
End of Interrupt (EOI) command (also executed by OCW2).
Priority changes can be executed during an EOI command
by using the Rotate on Specific EOl command in OCW2
(R = 1, SL = 1, EOI = 1, and L0 - L2 = IR level to receive low-
est priority).
An lRR bit that is masked by an lMR bit will not be cleared by
a non-specific EOI if the 82C59A is in the Special Mask
Mode.
Automatic End of Interrupt (AEOI) Mode
If AEOI = 1 in lCW4, then the 82C59A will operate in AEOl
mode continuously until reprogrammed by lCW4. In this
mode the 82C59A will automatically perform a non-specific
EOI operation at the trailing edge of the last interrupt
acknowledge pulse (third pulse in 8080/85, second in
80C86/88/286). Note that from a system standpoint, this
mode should be used only when a nested multilevel interrupt
structure is not required within a single 82C59A.
Interrupt Masks
Each Interrupt Request input can be masked individually by
the Interrupt Mask Register (IMR) programmed through
OCW1. Each bit in the lMR masks one interrupt channel if it
is set (1). Bit 0 masks IR0, Bit 1 masks IR1 and so forth.
Masking an IR channel does not affect the operation of other
channels.
Automatic Rotation (Equal Priority Devices)
Special Mask Mode
In some applications there are a number of interrupting
devices of equal priority. In this mode a device, after being
serviced, receives the lowest priority, so a device requesting
an interrupt will have to wait, in the worst case until each of 7
other devices are serviced at most once. For example, if the
priority and “in service” status is:
Some applications may require an interrupt service routine
to dynamically alter the system priority structure during its
execution under software control. For example, the routine
may wish to inhibit lower priority requests for a portion of its
execution but enable some of them for another portion.
The difficulty here is that if an Interrupt Request is acknowl-
edged and an End of Interrupt command did not reset its IS
bit (i.e., while executing a service routine), the 82C59A
would have inhibited all lower priority requests with no easy
way for the routine to enable them.
Before Rotate (lR4 the highest priority requiring service)
IS7
0
IS6
1
IS5
0
IS4
1
IS3
0
IS2
0
IS1
0
IS0
0
“IS” Status
Priority
Status
7
6
5
4
3
2
1
0
That is where the Special Mask Mode comes in. In the Spe-
cial Mask Mode, when a mask bit is set in OCW1, it inhibits
further interrupts at that level and enables interrupts from all
other levels (lower as well as higher) that are not masked.
lowest
highest
Thus, any interrupts may be selectively enabled by loading
the mask register.
11
82C59A
The Special Mask Mode is set by OCW3 where: ESMM = 1, The word enabled onto the data bus during RD is:
SMM = 1, and cleared where ESMM = 1, SMM = 0.
D7
D6
D5
D4
D3
D2
D1
D0
Poll Command
I
-
-
-
-
W2
W1
W0
In this mode, the INT output is not used or the microproces-
sor internal Interrupt Enable flip flop is reset, disabling its
interrupt input. Service to devices is achieved by software
using a Poll command.
W0 - W2: Binary code of the highest priority level request-
ing service.
I:
Equal to a “1” if there is an interrupt.
The Poll command is issued by setting P = 1 in OCW3. The
82C59A treats the next RD pulse to the 82C59A (i.e., RD =
0, CS = 0) as an interrupt acknowledge, sets the appropriate
IS bit if there is a request, and reads the priority level. Inter-
rupt is frozen from WR to RD.
This mode is useful if there is a routine command common to
several levels so that the INTA sequence is not needed
(saves ROM space). Another application is to use the poll
mode to expand the number of priority levels to more than 64.
LTIM BIT
0 = EDGE
1 = LEVEL
TO OTHER PRIORITY CELLS
CLR ISR
CLR
EDGE
SENSE
LATCH
Q
ISR BIT
PRIORITY
RESOLVER
SET
CLR
Q
SET ISR
V
CC
IN - SERVICE
LATCH
SET
CONTROL
LOGIC
REQUEST
LATCH
D
C
Q
Q
NON-
MASKED
REQ
IR
MASK LATCH
D
C
Q
INTA
8080/85
MODE
CLR
FREEZE
INTA
READ IMR
80C86/
88/286
MODE
READ ISR
FREEZE
READ WRITE
IRR MASK
MASTER CLEAR
FREEZE
NOTES:
1. Master clear active only during ICW1.
2. FREEZE is active during INTA and poll sequence only.
3. Truth Table for D-latch.
C
1
0
D
D1
X
Q
Operation
Follow
Hold
D1
Qn-1
FIGURE 9. PRIORITY CELL - SIMPLIFIED LOGIC DIAGRAM
Reading the 82C59A Status
The input status of several internal registers can be read to Interrupt Mask Register: 8-bit register which contains the
update the user information on the system. The following interrupt request lines which are masked.
registers can be read via OCW3 (lRR and ISR) or OCW1
The lRR can be read when, prior to the RD pulse, a Read
(lMR).
Register Command is issued with OCW3 (RR = 1, RIS = 0).
Interrupt Request Register (IRR): 8-bit register which con-
The ISR can be read when, prior to the RD pulse, a Read
tains the levels requesting an interrupt to be acknowledged.
Register Command is issued with OCW3 (RR = 1, RIS = 1).
The highest request level is reset from the lRR when an
interrupt is acknowledged. lRR is not affected by lMR.
There is no need to write an OCW3 before every status read
operation, as long as the status read corresponds with the
previous one: i.e., the 82C59A “remembers” whether the lRR
or ISR has been previously selected by the OCW3. This is
not true when poll is used. In the poll mode, the 82C59A
In-Service Register (ISR): 8-bit register which contains the
priority levels that are being serviced. The ISR is updated
when an End of Interrupt Command is issued.
12
82C59A
treats the RD following a “poll write” operation as an INTA. In both the edge and level triggered modes the IR inputs
After initialization, the 82C59A is set to lRR.
must remain high until after the falling edge of the first INTA.
If the IR input goes low before this time a DEFAULT lR7 will
occur when the CPU acknowledges the interrupt. This can
be a useful safeguard for detecting interrupts caused by spu-
rious noise glitches on the IR inputs. To implement this fea-
ture the lR7 routine is used for “clean up” simply executing a
return instruction, thus, ignoring the interrupt. If lR7 is
needed for other purposes a default lR7 can still be detected
by reading the ISR. A normal lR7 interrupt will set the corre-
sponding ISR bit, a default IR7 won’t. If a default IR7 routine
occurs during a normal lR7 routine, however, the ISR will
remain set. In this case it is necessary to keep track of
whether or not the IR7 routine was previously entered. If
another lR7 occurs it is a default.
For reading the lMR, no OCW3 is needed. The output data bus
will contain the lMR whenever RD is active and A0 = 1 (OCW1).
Polling overrides status read when P = 1, RR = 1 in OCW3.
Edge and Level Triggered Modes
This mode is programmed using bit 3 in lCW1.
If LTlM = “0”, an interrupt request will be recognized by a low to
high transition on an IR input. The IR input can remain high
without generating another interrupt.
If LTIM = “1”, an interrupt request will be recognized by a “high”
level on an IR input, and there is no need for an edge detection.
The interrupt request must be removed before the EOI com-
mand is issued or the CPU interrupt is enabled to prevent a
second interrupt from occurring.
In power sensitive applications, it is advisable to place the
82C59A in the edge-triggered mode with the IR lines nor-
mally high. This will minimize the current through the internal
pull-up resistors on the IR pins.
The priority cell diagram shows a conceptual circuit of the level
sensitive and edge sensitive input circuitry of the 82C59A. Be
sure to note that the request latch is a transparent D type latch.
80C86/88/286
8080/85
IR
INT
80C86/88/286
INTA
LATCH
ARM
(NOTE 1)
8080/85
LATCH
ARM
LATCH
ARM
(NOTE 1)
(NOTE 1)
EARLIEST IR
CAN BE
REMOVED
NOTE:
1. Edge triggered mode only.
FIGURE 10. IR TRIGGERING TIMING REQUIREMENTS
The Special Fully Nested Mode
This mode will be used in the case of a big system where
cascading is used, and the priority has to be conserved
within each slave. In this case the special fully nested mode
will be programmed to the master (using lCW4). This mode
is similar to the normal nested mode with the following
exceptions:
one from that slave. This is done by sending a non-spe-
cific End of Interrupt (EOI) command to the slave and
then reading its In-Service register and checking for zero.
If it is empty, a non-specified EOI can be sent to the mas-
ter, too. If not, no EOI should be sent.
Buffered Mode
a. When an interrupt request from a certain slave is in ser-
vice, this slave is not locked out from the master’s priority
logic and further interrupt requests from higher priority
IRs within the slave will be recognized by the master and
will initiate interrupts to the processor. (In the normal
nested mode a slave is masked out when its request is in
service and no higher requests from the same slave can
be serviced.
When the 82C59A is used in a large system where bus driv-
ing buffers are required on the data bus and the cascading
mode is used, there exists the problem of enabling buffers
The buffered mode will structure the 82C59A to send an
enable signal on SP/EN to enable the buffers. In this mode,
whenever the 82C59A’s data bus outputs are enabled, the
SP/EN output becomes active.
b. When exiting the Interrupt Service routine the software
has to check whether the interrupt serviced was the only
13
82C59A
This modification forces the use of software programming to device routine address during bytes 2 and 3 of INTA. (Byte 2
determine whether the 82C59A is a master or a slave. Bit 3 only for 80C86/88/286).
in ICW4 programs the buffered mode, and bit 2 in lCW4
The cascade bus lines are normally low and will contain the
determines whether it is a master or a slave.
slave address code from the leading edge of the first INTA
pulse to the trailing edge of the last INTA pulse. Each
82C59A in the system must follow a separate initialization
Cascade Mode
The 82C59A can be easily interconnected in a system of one
master with up to eight slaves to handle up to 64 priority lev-
els.
sequence and can be programmed to work in a different
mode. An EOI command must be issued twice: once for the
master and once for the corresponding slave. Chip select
decoding is required to activate each 82C59A.
The master controls the slaves through the 3 line cascade
bus (CAS2 - 0). The cascade bus acts like chip selects to the
slaves during the INTA sequence.
NOTE: Auto EOI is supported in the slave mode for the 82C59A.
The cascade lines of the Master 82C59A are activated only
for slave inputs, non-slave inputs leave the cascade line
inactive (low). Therefore, it is necessary to use a slave
address of 0 (zero) only after all other addresses are used.
In a cascade configuration, the slave interrupt outputs (INT)
are connected to the master interrupt request inputs. When a
slave request line is activated and afterwards acknowledged,
the master will enable the corresponding slave to release the
ADDRESS BUS (16)
CONTROL BUS
DATA BUS (8)
INT REQ
CS
A
D
- D INTA
INT
CS
A
D
- D INTA
INT
CAS 0
CAS 1
CAS 2
CS
A
D
- D INTA
INT
CAS 0
CAS 1
CAS 2
0
7
0
0
7
0
0
7
0
CAS 0
CAS 1
CAS 2
SLAVE A
SLAVE B
MASTER 82C59A
82C59A
SP/EN
82C59A
SP/EN
SP/EN
7
6
5
4
3
2
1
1
0
0
7
6
5
5
4
4
3
3
2
2
1
0
7
6
5
5
4
4
3
3
2
2
1
0
7
6
5
4
3
2
7
6
1
0
7
6
1
0
V
GND
GND
CC
INTERRUPT REQUESTS
FIGURE 11. CASCADING THE 82C59A
14
82C59A
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Thermal Resistance (Typical)
θJA ( C/W) θJC ( C/W)
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class I
CC
CERDIP Package . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
PLCC Package . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature Ceramic Package . . . . . . . +175 C
Maximum Junction Temperature Plastic Package . . . . . . . . +150 C
Maximum Lead Temperature Package (Soldering 10s) . . . . +300 C
55
65
55
65
75
12
14
N/A
N/A
N/A
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
o
o
o
(PLCC and SOIC - Lead Tips Only)
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
o
o
o
o
DC Electrical Specifications
V
= +5.0V ±10%, T = 0 C to +70 C (C82C59A), T = -40 C to +85 C (I82C59A), T = -55 C to
o
CC A A A
+125 C (M82C59A)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
V
Logical One Input Voltage
2.0
2.2
-
V
V
C82C59A, I82C59A
M82C59A
lH
V
Logical Zero Input Voltage
Output HIGH Voltage
-
0.8
-
V
IL
V
3.0
VCC -0.4
V
V
I
l
= -2.5mA
= -100µA
OH
OH
OH
V
Output LOW Voltage
Input Leakage Current
Output Leakage Current
IR Input Load Current
-
0.4
V
l
= +2.5mA
OL
II
OL
-1.0
-10.0
+1.0
+10.0
µA
µA
V
V
= GND or V , Pins 1-3, 26-27
CC
IN
IO
= GND or V , Pins 4-13, 15-16
CC
OUT
ILIR
-
-
-200
10
µA
µA
V
V
= 0V
IN
IN
= V
CC
lCCSB
ICCOP
Standby Power Supply Current
Operating Power Supply Current
-
10
µA
V
= 5.5V, V = V
or GND Outputs
CC
IN
CC
CC
Open, (Note 1)
-
1
mA/MHz
V
= 5.0V, V = V
IN
or GND, Outputs Open,
CC
o
T
= 25 C, (Note 2)
A
NOTES:
1. Except for IR0 - lR7 where V = V
or open.
IN CC
2. ICCOP = 1mA/MHz of peripheral read/write cycle time. (ex: 1.0µs I/O read/write cycle time = 1mA).
o
Capacitance T = +25 C
A
SYMBOL
CIN
PARAMETER
Input Capacitance
TYP
15
UNITS
pF
TEST CONDITIONS
FREQ = 1MHz, all measurements reference to
device GND.
COUT
CI/O
Output Capacitance
I/O Capacitance
15
pF
15
pF
o
o
o
o
AC Electrical Specifications
V
= +5.0V ±10%, GND = 0V, T = 0 C to +70 C (C82C59A), T -40 C to +85 C (l82C59A),
CC
A
A
o
o
T
= -55 C to +125 C (M82C59A)
A
82C59A-5
82C59A
82C59A-12
TEST
SYMBOL
PARAMETER
MIN MAX MIN MAX MIN MAX UNITS CONDITIONS
TIMING REQUIREMENTS
(1) TAHRL
(2) TRHAX
(3) TRLRH
(4) TAHWL
A0/CS Setup to RD/INTA
10
5
-
-
-
-
10
5
-
-
-
-
5
0
-
-
-
-
ns
ns
ns
ns
A0/CS Hold after RD/INTA
RD/lNTA Pulse Width
A0/CS Setup to WR
235
0
160
0
60
0
15
82C59A
o
o
o
o
AC Electrical Specifications
V
= +5.0V ±10%, GND = 0V, T = 0 C to +70 C (C82C59A), T -40 C to +85 C (l82C59A),
CC A A
o
o
T
= -55 C to +125 C (M82C59A)
A
82C59A-5
82C59A
82C59A-12
TEST
SYMBOL
(5) TWHAX
(6) TWLWH
(7) TDVWH
(8) TWHDX
(9) TJLJH
PARAMETER
A0/CS Hold after WR
MIN MAX MIN MAX MIN MAX UNITS CONDITIONS
5
-
-
-
-
-
-
5
95
160
5
-
-
-
-
-
-
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
WR Pulse Width
165
240
5
60
70
0
Data Setup to WR
Data Hold after WR
Interrupt Request Width Low
100
55
100
40
40
30
(10) TCVlAL
Cascade Setup to Second or Third INTA
(Slave Only)
(11) TRHRL
End of RD to next RD, End of INTA (within
an INTA sequence only)
160
-
160
-
90
-
ns
(12) TWHWL End of WR to next WR
190
500
-
-
190
400
-
-
60
90
-
-
ns
ns
(13) TCHCL
(Note 1)
End of Command to next command (not
same command type), End of INTA
sequence to next INTA sequence
TIMING RESPONSES
(14) TRLDV
(15) TRHDZ
(16) TJHlH
(17) TlALCV
Data Valid from RD/INTA
-
5
-
160
100
350
565
-
5
-
120
85
-
5
-
40
22
90
50
ns
ns
ns
ns
1
2
1
1
Data Float after RD/INTA
Interrupt Output Delay
300
360
Cascade Valid from First INTA
(Master Only)
-
-
-
(18) TRLEL
(19) TRHEH
(20) TAHDV
(21) TCVDV
Enable Active from RD or INTA
Enable Inactive from RD or INTA
Data Valid from Stable Address
Cascade Valid to Valid Data
-
-
-
-
125
60
-
-
-
-
100
50
-
-
-
-
40
22
60
70
ns
ns
ns
ns
1
1
1
1
210
300
200
200
NOTE:
1. Worst case timing for TCHCL in an actual microprocessor system is typically greater than the values specified for the 82C59A,
(i.e. 8085A = 1.6µs, 8085A -2 = 1µs, 80C86 = 1µs, 80C286 -10 = 131ns, 80C286 -12 = 98ns).
AC Test Circuit
V
1
R
R
1
2
OUTPUT FROM
DEVICE UNDER
TEST
TEST
POINT
C
1
(NOTE)
NOTE: Includes stray and jig capacitance.
TEST CONDITION DEFINITION TABLE
TEST
CONDITION
V
R
R
C
1
1
1
2
1
2
1.7V
523Ω
1.8kΩ
Open
100pF
50pF
V
1.8kΩ
CC
16
82C59A
AC Testing Input, Output Waveform
INPUT
OUTPUT
V
+0.4V
V
OH
IH
1.5V
1.5V
V
- 0.4V
V
IL
OL
NOTE: AC Testing: All input signals must switch between V - 0.4V and V + 0.4V. Input rise and fall times are driven at 1ns/V.
IL IH
Timing Waveforms
(6)
TWLWH
WR
(5)
(4)
TWHAX
TAHWL
CS
ADDRESS BUS
A
0
(8)
TWHDX
(7)
TDVWH
DATA BUS
FIGURE 12. WRITE
(3)
TRLRH
RD/INTA
EN
(18)
TRLEL
(19)
TRHEH
(2)
TRHAX
(1)
TAHRL
CS
ADDRESS BUS
A
0
(14)
TRLDV
(15)
TRHDZ
DATA BUS
(20)
TAHDV
FIGURE 13. READ/INTA
RD
INTA
(11)
TRHRL
WR
(12)
TWHWL
RD
INTA
WR
(13)
TCHCL
RD
INTA
WR
FIGURE 14. OTHER TIMING
17
82C59A
Timing Waveforms (Continued)
(16)
TJHIH
IR
SEE NOTE 3
SEE NOTE 4
(9)
TJLJH
INT
INTA
SEE NOTE 1
SEE
NOTE 2
DB
(10)
(10)
TCVIAL
TCVIAL
CAS 0 - 2
(17)
TIALCV
(21)
TCVDV
NOTES:
1. Interrupt Request (IR) must remain HIGH until leading edge of first INTA.
2. During first INTA the Data Bus is not active in 80C86/88/286 mode.
3. 80C86/88/286 mode.
4. 8080/8085 mode.
FIGURE 15. INTA SEQUENCE
Burn-In Circuits
MD82C59A CERDIP
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R3
R3
GND
WR
RD
28
1
2
V
CC
R1
27
26
25
24
23
22
21
20
19
18
17
16
15
A0
C1
R1
R2
R2
R2
R2
R2
R2
R2
R2
3
INTA
IR7
D7
4
D6
V
CC
5
IR6
D5
6
IR5
D4
7
IR4
R3
R3
D3
8
IR3
A
D2
9
IR2
D1
10
11
12
13
14
IR1
D0
IR0
CAS 0
CAS 1
A
R3
R3
SP/EN
CAS 2
GND
18
82C59A
Burn-In Circuits
MR82C59A CLCC
V
C1
CC
D7 RD WR GND
R1 R1 R1 R1
A0 INTA
R1 R1
4
3
2
1
28 27 26
R1
R1
R1
R1
R1
R1
R1
R2
R2
R2
R2
R2
R2
R2
25
24
23
22
21
20
19
D6
IR7
5
6
D5
D4
IR6
IR5
7
8
D3
D2
D1
IR4
IR3
IR2
9
10
11
D0
IR1
12 13 14 15 16 17 18
R1 R1 R1 R1 R4 R2
NOTES:
1. V
= 5.5V ±0.5V.
7. R3 = 10kΩ ±5%.
8. R4 = 1.2kΩ ±5%.
9. C1 = 0.01µF min.
CC
2. V = 4.5V ±10%.
IH
3. V = -0.2V to 0.4V.
IL
4. GND = 0V.
10. F0 = 100kHz ±10%.
11. F1 = F0/2, F2 = F1/2, ...F8 = F7/2.
5. R1 = 47kΩ ±5%.
6. R2 = 510Ω ±5%.
19
82C59A
Die Characteristics
DIE DIMENSIONS:
143 x 130 x 19 ±1mils
(3630 x 3310 x 525µm)
METALLIZATION:
Type: Si-Al-Cu
Thickness: Metal 1: 8kÅ ± 0.75kÅ
Metal 2: 12kÅ ± 1.0kÅ
GLASSIVATION:
Type: Nitrox
Thickness: 10kÅ ± 3.0kÅ
Metallization Mask Layout
82C59A
D3
D0
D1
D2
D4
D5
D6
CAS0
CAS1
D7
RD
WR
GND
CS
CAS2
V
CC
SP/EN
A0
INT
IR0
INTA
IR1
IR2
IR3
IR4
IR5
IR6
IR7
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
相关型号：
MR82C59A-5/B
80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CQCC28, CERAMIC, LCC-28
RENESAS
MR82C59A/B
80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CQCC28
RENESAS
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