MR82C83H [INTERSIL]
CMOS Octal Latching Inverting Bus Driver; CMOS八进制锁存反相总线驱动程序
| 型号： | MR82C83H |
| 厂家： | 
Intersil |
| 描述： | CMOS Octal Latching Inverting Bus Driver |
| 文件： | 总6页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82C83H
CMOS Octal Latching Inverting Bus Driver
March 1997
Features
Description
• Full 8-Bit Parallel Latching Buffer
• Bipolar 8283 Compatible
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
• Three-State Inverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
Ordering Information
• Low Power Operation
PART NO.
CP82C83H
IP82C83H
PACKAGE
TEMP RANGE
PKG. NO
E20.3
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Operating Temperature Ranges
o
o
20 Ld PDIP
0 C to +70 C
o
o
-40 C to +85 C
E20.3
o
o
o
o
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0 C to +70 C
CS82C83H
IS82C83H
20 Ld PLCC
0 C to +70 C
N20.35
N20.35
F20.3
o
o
o
o
- I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
-40 C to +85 C
o
o
o
o
CD82C83H
ID82C83H
20 Ld CERDIP
0 C to +70 C
- M82C83H . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
o
o
-40 C to +85 C
F20.3
o
o
MD82C83H/B
8406702RA
0 C to +70 C
F20.3
o
o
SMD#
-55 C to +125 C F20.3
o
o
MR82C83H/B 20 Pad CLCC
-55 C to +125 C J20.A
o
o
84067022A
SMD#
-55 C to +125 C J20.A
Pinouts
82C83H (PDIP, CERDIP)
82C83H (PLCC, CLCC)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
V
CC
DI
DI
DI
DI
DI
DI
DI
DI
20
19
0
1
2
3
4
5
3
2
1
20
19
DO
0
1
2
3
4
5
6
18 DO
17 DO
16 DO
15 DO
14 DO
13 DO
4
5
6
7
8
18 DO
DI
DI
DI
DI
DI
3
4
5
6
7
1
2
3
4
5
17
16
15
DO
DO
DO
6
7
14 DO
12
OE
DO
7
GND 10
11 STB
9
10
11 12 13
TRUTH TABLE
PIN NAMES
DESCRIPTION
STB
X
OE
DI
X
L
DO
HI-Z
H
PIN
H
L
L
L
DI - DI
Data Input Pins
0
7
H
DO - DO
0
Data Output Pins
7
H
H
X
L
STB
OE
Active High Strobe
↓
†
Active Low Output Enable
H = Logic One
L = Logic Zero
X = Don‘t Care
HI-Z = High Impedance
↓
†
= Negative Transition
= Latched to Value of Last
Data
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2971.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19949-281
82C83H
state). The 82C8X series gated inputs mean that this condi-
Functional Diagram
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
D Q
DO0
DI0
CLK
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DI1
DI2
DI3
DI4
DI5
DI6
DI7
V
CC
P
OE
P
INTERNAL
DATA
DATA IN
V
CC
N
N
P
N
STB
OE
FIGURE 2. 82C86H/87H GATED INPUTS
Gated Inputs
Decoupling Capacitors
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C83H data sheet
is determined by
and typically cause an increase in power dissipation in I = C (dv/dt)
L
CMOS devices by creating a low resistance path between
Assuming that all outputs change state at the same time and
that dv/dt is constant;
V
and GND when the signal is at or near the input switch-
CC
ing threshold. Additionally, if the driving signal becomes high
impedance (``float'' condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
(V
× 80 percent)
(EQ. 1)
CC
--------------------------------------------------------
I = C
L
t
⁄ t
F
R
where t = 20ns, V
R
= 5.0V, C = 300pF on each eight out-
L
CC
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the V
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
puts.
-12
-9
I = (8 x 300 x 10 ) x (5.0V x 0.8)/(20 x 10 ) = 480mA
This current spike may cause a large negative voltage spike on
and
CC
V
which could cause improper operation of the device. To fil-
CC
ter out this noise, it is recommended that a 0.1µF ceramic disc
capacitor be placed between V and GND at each device,
CC
from V
to GND occurs during input transitions and invalid
CC
with placement being as near to the device as possible.
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
ALE
MULTI-
PLEXED
BUS
V
V
CC
ADDRESS
ADDRESS
CC
P
ICC
P
V
V
CC
CC
N
STB
P
P
INTERNAL
DATA
DATA IN
P
N
N
N
STB
DATA IN
P
INTERNAL
DATA
N
N
FIGURE 1. 82C82/83H
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V or maximum
IH
conditions. This is due to the operation of the input cir-
V
IL
cuitry in its linear operating region (partially conducting
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
4-282
82C83H
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical)
θ
C/W
θ
C/W
JC
JA
Input, Output or I/O Voltage . . . . . . . . . . . . GND 0.5V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
+0.5V
CC
CERDIP Package . . . . . . . . . . . . . . . .
CLCC Package . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
PLCC Package . . . . . . . . . . . . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65 C to +150 C
Max Junction Temperature Ceramic Package . . . . . . . . . . . . . . +175 C
70
80
75
75
16
20
N/A
N/A
Operating Conditions
o
o
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
o
o
Max Junction Temperature Plastic Package. . . . . . . . . . . . . . . . +150 C
Lead Temperature (Soldering 10s) (PLCC - Lead Tips Only) . . +300 C
o
o
C82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C
o
o
o
I82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
o
o
M82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
o
DC Electrical Specifications V = 5.0V ± 10%; T = 0 C to +70 C (C82C83H);
CC
A
o
o
T = -40 C to +85 C (I82C83H);
A
o
o
T = -55 C to +125 C (M82C83H)
A
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
V
Logical One Input Voltage
2.0
2.2
-
V
C82C83H, I82C83H,
M82C83H, (Note 1)
IH
V
Logical Zero Input Voltage
Logical One Output Voltage
0.8
-
V
V
IL
V
3.0
I
I
= -8mA,
= -100mA, OE = GND
OH
OH
OH
V
-0.4V
CC
V
Logical Zero Output Voltage
Input Leakage Current
0.45
10
V
I
= 20mA, OE = GND
OL
OL
I
-10
-10
-
µA
V
= GND or V ,
CC
I
IN
DIP Pins 1-9,11
I
Output Leakage Current
10
10
1
µA
µA
V
= GND or OE ≥ V -0.5V
CC
O
O
DIP Pins 12-19
lCCSB
Standby Power Supply Current
Operating Power Supply Current
V
V
= V or GND
CC
IN
= 5.5V Outputs Open
CC
o
IC COP
-
mA/
T = +25 C, V
A
= 5V, Typical
CC
MHz
(See Note 2)
NOTES:
1. V is measured by applying a pulse of magnitude = V
to one data Input at a time and checking the corresponding device output for
IH
lHMIN
a valid logical 1 - during valid input high time. Control pins (STB, CE) are tested separately with all device data input pins at V
-0.4V.
CC
2. Typical ICCOP = 1 mA/MHz of STB cycle time. (Example: 5MHz µP, ALE = 1.25MHz, ICCOP = 1.25mA).
o
Capacitance T = +25 C
A
SYMBOL
PARAMETER
Input Capacitance
Output Capacitance
TYPICAL
UNITS
pF
TEST CONDITIONS
C
13
20
FREQ = 1MHz, all measure-
ments are referenced to device
GND
IN
C
pF
OUT
4-283
82C83H
AC Electrical Specifications V = 5.0V ±10%; C = 300pF (Note 1), FREQ = 1MHz
CC
L
o
o
T = 0 C to +70 C (C82C83H);
A
o
o
T = -40 C to +85 C (l82C83H);
A
o
o
T = -55 C to +125 C (M82C83H)
A
LIMITS
SYMBOL
(1) TlVOV
PARAMETER
Propagation Delay Input to Output
Propagation Delay STB to Output
Output Disable Time
MIN
5
MAX
25
50
22
45
-
UNITS
ns
TEST CONDITIONS
See Notes 2, 3
(2) TSHOV
(3) TEHOZ
(4) TELOV
(5) TlVSL
(6) TSLIX
(7) TSHSL
(8) TR, TF
NOTES:
10
5
ns
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
See Notes 2, 3
ns
Output Enable Time
10
0
ns
Input to STB Set Up Time
Input to STB Hold Time
STB High Time
ns
30
15
-
-
ns
-
ns
Input Rise/Fall Times
20
ns
1. Output load capacitance is rated 300pF for both ceramic and plastic packages.
2. All AC Parameters tested as per test load circuits. Input rise and tall times are driven at 1ns/V.
3. Input test signals must switch between V -0.4V and V +0.4V.
IL lH
Timing Waveforms
TR, TF (8)
2.0V
0.8V
INPUTS
STB
TIVSL (5)
TSLIX
(6)
TSHSL (7)
OE
TIVOV
(1)
TELOV (4)
TEHOZ (3)
VOH -0.1V
VOL +0.1V
3.0V
OUTPUTS
0.45V
TSHOV (2)
All Timing measurements are made at 1.5V unless otherwise noted.
FIGURE 4. TIMING WAVEFORMS
Test Load Circuits
2.27V
1.5V
91Ω
180Ω
TEST
POINT
TEST
POINT
OUTPUT
OUTPUT
300pF
300pF
(SEE NOTE)
(SEE NOTE)
FIGURE 5. TIVOV, TSHOV
FIGURE 6. TELOV OUTPUT HIGH ENABLE
4-284
82C83H
Test Load Circuits (Continued)
1.5V
2.27V
51Ω
91Ω
TEST
POINT
TEST
POINT
OUTPUT
OUTPUT
300pF
(SEE NOTE)
50pF
(SEE NOTE)
NOTE: Includes jig and stray capacitance.
FIGURE 7. TELOV OUTPUT LOW ENABLE
FIGURE 8. TEHOZ OUTPUT LOW/HIGH DISABLE
Burn-In Circuits
V
CC
C1
V
CC
C1
R1
F2
F2
F2
F2
F2
F2
F2
F2
F0
1
2
20
19
18
17
16
15
14
13
12
11
R1
R1
R1
R1
R1
R1
R1
R1
A
3
2
1
20 19
3
A
A
A
R4
R4
R4
R4
4
18
F2
F2
4
5
6
7
8
5
17
16
V
CC
6
A
A
A
A
R4
R4
R4
R4
F2
F2
F2
V
CC
7
R2
R2
15
14
2
8
R4
R4
A
9
R1
9
10 11 12 13
10
F1
FIGURE 9. MD82C83H CERDIP
FIGURE 10. MR82C83H CLCC
NOTES:
1. V
= 5.5V ± 0.5V GND = 0V
CC
2. V = 4.5V ± 10%
IH
3. V = -0.2 to 0.4V
IL
4. R1 = 47kW ± 5%
5. R2 = 2.0kW ± 5%
6. R3 = 1.0kW ± 5%
7. R4 = 5.0kW ± 5%
8. C1 = 0.01µF Minimum
9. F0 = 100kHz ± 10%
10. F1 = F0/2, F2 = F1/2, F3 = F2/2
4-285
82C83H
Die Characteristics
DIE DIMENSIONS:
138.6 x 155.5 x 19 ± 1 mils
GLASSIVATION:
Type: SiO
2
Thickness: 8kÅ ± 1kÅ
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11kÅ ± 2kÅ
WORST CASE CURRENT DENSITY:
2.0 x 10 A/cm
5
2
Metallization Mask Layout
82C83H
DI2
DI1
DI2
VCC
DO0
DO1
DO2
DO3
DO4
DO5
DI3
DI4
DI5
DI6
DI7
OE GND
STB
DO7 DO6
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-286
相关型号：
MR82C83H/B
Bus Driver, CMOS Series, 1-Func, 8-Bit, Inverted Output, CMOS, CQCC20, CERAMIC, LCC-20
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