MR82C82 [INTERSIL]
CMOS Octal Latching Bus Driver; CMOS八进制锁存总线驱动程序
| 型号： | MR82C82 |
| 厂家： | 
Intersil |
| 描述： | CMOS Octal Latching Bus Driver |
| 文件： | 总7页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
82C82
CMOS Octal Latching Bus Driver
March 1997
Features
Description
• Full Eight-Bit Parallel Latching Buffer
• Bipolar 8282 Compatible
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this sig-
nal. The active low output enable (OE) permits simple inter-
face to state-of-the-art microprocessor systems.
• Three-State Noninverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
Ordering Information
• Single 5V Power Supply
PART NUMBER TEMP. RANGE
PACKAGE
PKG. NO.
o
o
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA
CP82C82
IP82C82
0 C to +70 C 20 Ld PDIP
E20.3
o
o
-40 C to +85 C
• Operating Temperature Ranges
o
o
o
o
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to +70 C
CS82C82
IS82C82
0 C to +70 C 20 Ld PLCC
N20.35
o
o
o
o
-40 C to +85 C
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
o
o
CD82C82
ID82C82
0 C to +70 C 20 Ld CERDIP F20.3
o
o
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
o
o
-40 C to +85 C
o
o
MD82C82/B
8406701RA
MR82C82/B
84067012A
-55 C to +125 C
SMD #
o
o
-55 C to +125 C 20 Pad CLCC J20.A
SMD #
Pinouts
82C82 (PDIP, CERDIP)
82C82 (PLCC, CLCC)
TOP VIEW
TOP VIEW
TRUTH TABLE
STB
X
OE
H
L
DI
X
L
DO
Hi-Z
L
3
2
1
20 19
H
1
2
3
4
5
6
7
8
9
V
CC
20
19
DI
DI
DI
DI
DI
DI
0
1
2
3
4
5
H
L
H
X
H
DO
0
1
2
3
4
5
6
4
5
6
7
8
18 DO
DI
DI
DI
DI
DI
3
4
5
6
7
1
2
3
4
5
↓
L
†
18 DO
17 DO
16 DO
15 DO
14 DO
13 DO
H
L
X
†
= Logic One
= Logic Zero
= Don’t Care
= Latched to Value of Last
Data
17
16
15
DO
DO
DO
Hi-Z = High Impedance
DI
DI
6
7
14 DO
↓
= Neg. Transition
PIN NAMES
12
OE
DO
7
9
10 11 12 13
PIN
DESCRIPTION
GND 10
11 STB
DI -DI
Data Input Pins
0
7
DO -DO
0
Data Output Pins
Active High Strobe
7
STB
OE
Active Low Output
Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2975.1
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19949-274
82C82
Functional Diagram
D Q
CLK
DI
DO
O
0
1
DI
DI
DI
DI
DI
DI
DI
DO
DO
DO
DO
DO
DO
DO
1
2
3
2
3
4
5
6
7
4
5
6
7
OE
STB
Gated Inputs
During normal system operation of a latch, signals on the bus DC input voltage levels can also cause an increase in ICC if
at the device inputs will become high impedance or make these input levels approach the minimum V or maximum
IH
conditions. This is due to the operation of the input cir-
transitions unrelated to the operation of the latch. These unre-
V
IL
lated input transitions switch the input circuitry and typically cuitry in its linear operating region (partially conducting
cause an increase in power dissipation in CMOS devices by state). The 82C8X series gated inputs mean that this condi-
creating a low resistance path between V
and GND when tion will occur only during the time the device is in the trans
CC
the signal is at or near the input switching threshold. Addition- parent mode (STB = logic one). ICC remains below the max-
ally, if the driving signal becomes high impedance (“float” con- imum ICC standby specification of l0mA during the time
dition), it could create an indeterminate logic state at the input inputs are disabled, thereby, greatly reducing the average
and cause a disruption in device operation.
power dissipation of the 82C8X series devices
The Intersil 82C8X Series of bus drivers eliminates these con-
ditions by turning off data inputs when data is latched (STB =
logic zero for the 82C82/83H) and when the device is disabled
(OE = logic one for 82C86H/87H). These gated inputs dis-
Typical 82C82 System Example
In a typical 80C86/88 system, the 82C82 is used to latch
multiplexed addresses and the STB input is driven by ALE
(Address Latch Enable) (see Figure 3). The high pulse width
of ALE is approximately 100ns with a bus cycle time of
800ns (80C86/88 at 5MHz). The 82C82 inputs are active
only 12.5% of the bus cycle time. Average power dissipation
related to input transitioning is reduced by this factor also.
connect the input circuitry from the V
and ground power
CC
supply pins by turning off the upper P-channel and lower N-
channel (see Figures 1, 2). No new current flow from V to
CC
GND occurs during input transitions and invalid logic states
from floating inputs are not transmitted. The next stage is held
to a valid logic level internal to the device.
V
CC
V
V
CC
CC
P
P
P
P
OE
N
INTERNAL
DATA
STB
P
DATA IN
V
CC
INTERNAL
DATA
DATA IN
N
N
P
N
N
N
FIGURE 16. 82C82/83H
FIGURE 17. 82C86H/87H GATED INPUTS
4-275
82C82
Application Information
Decoupling Capacitors
The transient current required to charge and discharge the where tR = 20ns, V
300pF load capacitance specified in the 82C82 data sheet is outputs.
= 5.0V, C = 300pF on each of eight
L
CC
determined by:
-12
–9
(EQ. 4)
I = (8 x 300 x 10 )x (5.0V x 0.8)/(20 x 10 ) = 480mA
I = C (dv/dt)
(EQ. 1)
L
This current spike may cause a large negative voltage spike
Assuming that all outputs change state at the same time and
that dv/dt is constant;
on V , which could cause improper operation of the device.
CC
To filter out this noise, it is recommended that a 0.1µF
I = C
(EQ. 2)
ceramic disc decoupling capacitor be placed between V
L
CC
and GND at each device, with placement being as near to
the device as possible.
(V
x 80%)
CC
(EQ. 3)
-----------------------------------
tR/tF
V
V
CC
CC
P
N
P
ALE
STB
P
MULTIPLEXED
BUS
ADDRESS
ADDRESS
INTERNAL
DATA
DATA IN
N
N
ICC
FIGURE 18. SYSTEM EFFECTS OF GATED INPUTS
4-276
82C82
Thermal Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V Thermal Resistance (Typical)
θ
o
θ
JC
JA
o
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
+0.5V
CC
CERDIP. . . . . . . . . . . . . . . . . . . . . . . . 75 C/W
18 C/W
o
o
CLCC. . . . . . . . . . . . . . . . . . . . . . . . . . 85 C/W
22 C/W
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . .
PLCC. . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65 C to +150 C
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
75
75
N/A
N/A
Operating Conditions
o
o
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C
I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
M82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
o
o
o
o
o
o
o
Minimum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300 C
(PLCC Lead Tips Only)
o
o
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
o
DC Electrical Specifications V = 5.0V ±10%;
T = 0 C to +70 C (C82C82);
A
CC
o
o
T = -40 C to +85 C (I82C82);
T = -55 C to +125 C (M82C82)
A
o
o
A
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
C82C82, I82C82 (Note 1)
M82C82 (Note 1)
V
Logical One Input Voltage
2.0
2.2
-
-
-
V
V
IH
V
Logical Zero Input Voltage
Logical One Output Voltage
0.8
-
V
IL
V
2.9
V
I
I
I
= -8mA, OE = GND
= -100µA, OE = GND
= 8mA, OE = GND
OH
OH
OH
OL
V
-0.4V
-
V
CC
V
Logical Zero Output Voltage
Input Leakage Current
-
0.4
1.0
10.0
V
OL
II
-1.0
-10.0
µA
µA
V
= GND or V , DIP Pins 1-9, 11
CC
IN
IO
Output Leakage Current
V
= GND or V , OE ≥ V -0.5V
CC CC
O
DIP Pins 12-19
ICCSB
ICCOP
NOTES:
Standby Power Supply Cur-
rent
-
-
10
1
µA
V
= V
or GND, V
= 5.5V, Outputs Open
CC
IN
CC
o
Operating Power Supply
Current
mA/MHz
T = +25 C, V
= 5V, Typical (See Note 2)
CC
A
1. V is measured by applying a pulse of magnitude = V min to one data input at a time and checking the corresponding device output
IH IH
for a valid logical “1” during valid input high time. Control pins (STB, OE) are tested separately with all device data input pins at V
-0.4.
CC
2. Typical ICCOP = 1mA/MHz of STB cycle time. (Example: 5MHz µP, ALE = 1.25MHz, ICCOP = 1.25mA).
o
Capacitance T = +25 C
A
SYMBOL
PARAMETER
Input Capacitance
Output Capacitance
TYPICAL
UNITS
TEST CONDITIONS
C
C
13
20
pF
pF
Freq = 1MHz, all measurements are
referenced to device GND
IN
OUT
4-277
82C82
o
o
AC Electrical Specifications
V
C
= 5.0V ±10%;
T = 0 C to +70 C (C82C82);
A
CC
o
o
= 300pF (Note 1), Freq = 1MHz T = -40 C to +85 C (I82C82);
L
A
o
o
T = -55 C to +125 C (M82C82)
A
SYMBOL
PARAMETER
MIN
MAX
35
55
35
50
-
UNITS
ns
TEST CONDITIONS
Notes 2, 3
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
TIVOV
TSHOV
TEHOZ
TELOV
TIVSL
Propagation Delay Input to Output
Propagation Delay STB to Output
Output Disable Time
-
-
ns
Notes 2, 3
-
ns
Notes 2, 3
Output Enable Time
-
ns
Notes 2, 3
Input to STB Setup Time
Input to STB Hold Time
STB High Time
0
25
25
-
ns
Notes 2, 3
TSLIX
-
ns
Notes 2, 3
TSHSL
TR, TF
-
ns
Notes 2, 3
Input Rise/Fall Times
20
ns
Notes 2, 3
NOTES:
1. Output load capacitance is rated at 300pF for ceramic and plastic packages.
2. All AC parameters tested as per test circuits and definitions below. Input rise and fall times are driven at 1ns/V.
3. Input test signals must switch between V - 0.4V and V +0.4V.
IL
IH
Timing Waveforms
TR, TF (8)
2.0V
0.8V
INPUTS
STB
TIVSL (5)
TSLIX
(6)
TSHSL (7)
OE
TIVOV
(1)
TEHOZ (3)
TELOV (4)
2.4V
VOH -0.1V
VOL +0.1V
OUTPUTS
0.8V
TSHOV (2)
Test Load Circuits
1.7V
0.6V
3.3V
150Ω
300Ω
300Ω
TEST
POINT
TEST
POINT
TEST
POINT
OUTPUT
OUTPUT
OUTPUT
300pF
(NOTE)
50pF
(NOTE)
50pF
(NOTE)
TIVOV, TSHOV, TELOV
TEHOZ OUTPUT HIGH DISABLE
TEHOZ OUTPUT LOW DISABLE
NOTE: Includes stray and jig capacitance.
4-278
82C82
Burn-In Circuits
MD82C82 CERDIP
V
CC
C1
R
R
R
R
R
R
R
R
R
1
1
1
1
1
1
1
1
1
1
2
20
19
18
17
16
15
14
13
12
11
F2
F2
F2
F2
F2
F2
F2
F2
F0
A
A
A
A
A
A
A
A
F1
3
4
5
V
CC
6
R
R
7
2
8
A
9
R
1
2
10
MR82C82 CLCC
V
C1
CC
V
/2
R
F2 F2
F2
1
CC
R
3
R
3
R
3
3
3
2
20 19
R
R
R
R
R
R
R
R
R
R
3
3
3
3
3
3
3
3
3
3
F2
V
V
V
V
V
/2
/2
/2
/2
/2
18
17
16
15
14
4
CC
CC
CC
CC
CC
F2
F2
F2
F2
5
6
7
8
9
10 11 12 13
R
R
R
3
R
3
3
3
F0
F1 V /2 V /2
CC CC
NOTES:
1. V
= 5.5 ± 0.5V, GND = 0V.
CC
2. V = 4.5V ±10%.
IH
3. V = -0.2V to 0.4V.
IL
4. R = 47kΩ ±5%.
1
5. R = 2.0kΩ ±5%.
2
6. R = 4.2kΩ ±5%.
3
7. R = 470kΩ ±5%.
4
8. C = 0.01µF minimum.
1
9. F = 100kHz ±10%.
0
10. F = F / , F = F / .
0 2 1 2
1
2
4-279
82C82
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
Type: SiO
118.1 x 92.1 x 19 ±1mils
2
Thickness: 8kÅ ±1kÅ
METALLIZATION:
Type: Si - Al
WORST CASE CURRENT DENSITY:
5
2
Thickness: 11kÅ ±1kÅ
2.00 x 10 A/cm
Metallization Mask Layout
82C82
D11
2
D10
1
V
DO0
19
D01
18
CC
20
3
D12
17
16
15
DO2
DO3
DO4
4
5
D13
D14
14
13
DO5
DO6
6
7
D15
D16
8
9
10
11
12
D17
OE
GND
STB
DO7
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-280
相关型号：
MR82C83H/B
Bus Driver, CMOS Series, 1-Func, 8-Bit, Inverted Output, CMOS, CQCC20, CERAMIC, LCC-20
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